ADSP-21369KSWZ-6A_技术文档

SHARC Processor

ADSP-21367/ADSP-21368/ADSP-21369

SUMMARY

DEDICATED AUDIO COMPONENTS

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—2M bits of on-chip SRAM and 6M bits of

on-chip mask programmable ROM

S/PDIF-compatible digital audio receiver/transmitter

4 independent asynchronous sample rate converters (SRC)

16 PWM outputs configured as four groups of four outputs

ROM-based security features include

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

Code compatible with all other members of the SHARC family

The ADSP-21367/ADSP-21368/ADSP-21369 are available

with a 400 MHz core instruction rate with unique audiocen-

tric peripherals such as the digital applications interface,

S/PDIF transceiver, serial ports, 8-channel asynchronous

sample rate converter, precision clock generators, and

more. For complete ordering information, see Ordering

Guide.

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Available in 256-ball BGA_ED and 208-lead LQFP_EP

packages

Internal Memory

SIMD Core

Block 0

RAM/ROM

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

Instruction

Cache

5 stage

Sequencer

B2D

64-BIT

B0D

64-BIT

B3D

64-BIT

B1D

64-BIT

S

DAG1/2

PEx

Timer

PEy

DMD

64-BIT

DMD 64-BIT

Core Bus

Cross Bar

Internal Memory I/F

PMD 64-BIT

PMD

64-BIT

IOD0 32-BIT

FLAGx/IRQx/

TMREXP

EPD BUS 32-BIT

JTAG

PERIPHERAL BUS

32-BIT

IOD1

32-BIT

IOD0 BUS

MTM

PERIPHERAL BUS

EP

IDP/

PDAP

7-0

S/PDIF PCG ASRC

SPORT

7-0

CORE PCG

FLAGS

TIMER

UART

CORE PWM

TWI

SPI/B

AMI

SDRAM

Tx/Rx

A

-D

3

-

0

C

-

D

2

-0

1-

0

FLAGS

3-0

DPI Routing/Pins

DAI Routing/Pins

External Port Pin MUX

External

Port

DPI Peripherals

DAI Peripherals

Peripherals

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. G Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-21367/ADSP-21368/ADSP-21369

TABLE OF CONTENTS

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 7

I/O Processor Features ......................................... 10

System Design .................................................... 10

Development Tools ............................................. 11

Additional Information ........................................ 12

Related Signal Chains .......................................... 12

Pin Function Descriptions ....................................... 13

Specifications ........................................................ 16

Operating Conditions .......................................... 16

Electrical Characteristics ....................................... 17

Package Information ........................................... 18

ESD Caution ...................................................... 18

Maximum Power Dissipation ................................. 18

Absolute Maximum Ratings ................................... 18

Timing Specifications ........................................... 18

Output Drive Currents ......................................... 51

Test Conditions .................................................. 51

Capacitive Loading .............................................. 51

Thermal Characteristics ........................................ 53

256-Ball BGA_ED Pinout ......................................... 54

208-Lead LQFP_EP Pinout ....................................... 57

Package Dimensions ............................................... 59

Surface-Mount Design .......................................... 60

Automotive Products .............................................. 61

Ordering Guide ..................................................... 61

REVISION HISTORY

9/2017—Rev. F to Rev. G

Changes to Middleware Packages ................................ 12

Change to SDCLK1 Pin Description, Table 8 in Pin Function

Descriptions .......................................................... 13

Changes to Table 24, Memory Read ............................. 30

Change to Endnote 1, Table 45 in

256-Ball BGA_ED Pinout ......................................... 54

Changes to Figure 52, Package Dimensions ................... 59

Change to Table 47, Surface-Mount Design ................... 60

Changes to Ordering Guide ....................................... 61

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ADSP-21367/ADSP-21368/ADSP-21369

GENERAL DESCRIPTION

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC^®proces-

sors are members of the SIMD SHARC family of DSPs that

feature Analog Devices’ Super Harvard Architecture. These pro-

cessors are source code-compatible with the ADSP-2126x and

ADSP-2116x DSPs as well as with first generation ADSP-2106x

SHARC processors in SISD (single-instruction, single-data)

mode. The processors are 32-bit/40-bit floating-point proces-

sors optimized for high performance automotive audio

applications with its large on-chip SRAM, mask programmable

ROM, multiple internal buses to eliminate I/O bottlenecks, and

an innovative digital applications interface (DAI).

Table 2. ADSP-2136x Family Features¹(Continued)

Feature

Serial Ports

8

IDP

Yes

DAI

Yes

As shown in the functional block diagram on Page 1, the

processors use two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. Fabricated in a state-of-the-art, high

speed, CMOS process, the ADSP-21367/ADSP-21368/

ADSP-21369 processors achieve an instruction cycle time of up

to 2.5 ns at 400 MHz. With its SIMD computational hardware,

the processors can perform 2.4 GFLOPS running at 400 MHz.

UART

2

DAI

Yes

DPI

Yes

S/PDIF Transceiver

AMI Interface Bus Width

SPI

1

32/16/8 bits

Table 1 shows performance benchmarks for these devices.

2

TWI

Yes

128 dB

Table 1. Processor Benchmarks (at 400 MHz)

SRC Performance

Package

Speed

(at 400 MHz)

256 Ball- 256 Ball- 256 Ball-

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with reversal) 23.2 s

FIR Filter (per tap)¹

IIR Filter (per biquad)¹

Matrix Multiply (pipelined)

[3×3] × [3×1]

BGA,

208-Lead

LQFP_EP

BGA

BGA,

208-Lead

LQFP_EP

1.25 ns

5.0 ns

¹W = Automotive grade product. See Automotive Products for more information.

²Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,

DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass

management, delay, speaker equalization, graphic equalization, and more.

Decoder/post-processoralgorithmcombinationsupportvariesdependingupon

the chip version and the system configurations. Please visit www.analog.com for

complete information.

11.25 ns

20.0 ns

8.75 ns

13.5 ns

[4×4] × [4×1]

Divide (y/x)

Inverse Square Root

¹Assumes two files in multichannel SIMD mode.

The diagram on Page 1 shows the two clock domains that make

up the ADSP-21367/ADSP-21368/ADSP-21369 processors. The

core clock domain contains the following features.

Table 2. ADSP-2136x Family Features¹

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting 2x64-bit data

transfers between memory and the core at every core pro-

cessor cycle

• One periodic interval timer with pinout

• On-chip SRAM (2M bit)

Feature

Frequency

400 MHz

RAM

ROM²

2M bits

6M bits

Yes

Audio Decoders in ROM

Pulse-Width Modulation

S/PDIF

• On-chip mask-programmable ROM (6M bit)

Yes

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allows flexible exception handling.

Yes

SDRAM Memory Bus Width

32/16 bits

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ADSP-21367/ADSP-21368/ADSP-21369

The block diagram of the ADSP-21368 on Page 1 also shows the

peripheral clock domain (also known as the I/O processor) and

contains the following features:

• IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an AMI and SDRAM controller

• 4 units for PWM control

• Digital peripheral interface that includes three timers, a 2-

wire interface, two UARTs, two serial peripheral interfaces

(SPI), 2 precision clock generators (PCG) and a flexible sig-

nal routing unit (DPI SRU).

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-

ble at the assembly level with the ADSP-2126x, ADSP-21160,

and ADSP-21161, and with the first generation ADSP-2106x

SHARC processors. The ADSP-21367/ADSP-21368/

ADSP-21369 processors share architectural features with the

ADSP-2126x and ADSP-2116x SIMD SHARC processors, as

shown in Figure 2 and detailed in the following sections.

• 1 MTM unit for internal-to-internal memory transfers

• Digital applications interface that includes four precision

clock generators (PCG), a input data port (IDP) for serial

and parallel interconnect, an S/PDIF receiver/transmitter,

four asynchronous sample rate converters, eight serial

ports, a flexible signal routing unit (DAI SRU).

S

SIMD Core

JTAG

FLAG TIMER INTERRUPT CACHE

PM ADDRESS 24

DMD/PMD 64

5 STAGE

PROGRAM SEQUENCER

PM DATA 48

DAG2

16x32

DAG1

16x32

PM ADDRESS 32

SYSTEM

I/F

DM ADDRESS 32

PM DATA 64

USTAT

4x32-BIT

PX

64-BIT

DM DATA 64

DATA

SWAP

RF

Rx/Fx

PEx

RF

Sx/SFx

PEy

ALU

SHIFTER

MULTIPLIER

ALU

SHIFTER MULTIPLIER

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MRF

80-BIT

MSF

80-BIT

ASTATy

STYKy

ASTATx

STYKx

Figure 2. SHARC Core Block Diagram

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ADSP-21367/ADSP-21368/ADSP-21369

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

SIMD Computational Engine

The processors contain two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

between the 40-bit register file and the PM data bus. These reg-

isters contain hardware to handle the data width difference.

Timer

A core timer that can generate periodic software Interrupts. The

core timer can be configured to use FLAG3 as a timer expired

signal.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21367/ADSP-21368/ADSP-21369 feature an

enhanced Harvard architecture in which the data memory

(DM) bus transfers data and the program memory (PM) bus

transfers both instructions and data (see Figure 2). With sepa-

rate program and data memory buses and on-chip instruction

cache, the processors can simultaneously fetch four operands

(two over each data bus) and one instruction (from the cache),

all in a single cycle.

Instruction Cache

Independent, Parallel Computation Units

The processors include an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing

elements. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21367/ADSP-21368/ADSP-21369 have two data

address generators (DAGs). The DAGs are used for indirect

addressing and implementing circular data buffers in hardware.

Circular buffers allow efficient programming of delay lines and

other data structures required in digital signal processing, and

are commonly used in digital filters and Fourier transforms.

The two DAGs contain sufficient registers to allow the creation

of up to 32 circular buffers (16 primary register sets, 16 second-

ary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the ADSP-2136x enhanced Har-

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

Context Switch

Flexible Instruction Set

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

The 48-bit instruction word accommodates a variety of parallel

operations for concise programming. For example, the

ADSP-21367/ADSP-21368/ADSP-21369 can conditionally exe-

cute a multiply, an add, and a subtract in both processing

elements while branching and fetching up to four 32-bit values

from memory—all in a single instruction.

Universal Registers

On-Chip Memory

These registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all system registers (control/status) of

the core.

The processors contain two megabits of internal RAM and six

megabits of internal mask-programmable ROM. Each block can

be configured for different combinations of code and data stor-

age (see Table 3). Each memory block supports single-cycle,

independent accesses by the core processor and I/O processor.

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ADSP-21367/ADSP-21368/ADSP-21369

The memory architecture, in combination with its separate on-

chip buses, allows two data transfers from the core and one

from the I/O processor, in a single cycle.

Table 3. Internal Memory Space ¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Instruction Word (48 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 BFFF

0x0008 0000–0x0008 FFFF

0x0008 0000–0x0009 7FFF

0x0010 0000–0x0012 FFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

Block 0 SRAM

0x0004 C000–0x0004 EFFF

0x0009 0000–0x0009 3FFF

0x0009 8000–0x0009 DFFF

0x0013 0000–0x0013 BFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 BFFF

0x000A 0000–0x000A FFFF

0x000A 0000–0x000B 7FFF

0x0014 0000–0x0016 FFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

Block 1 SRAM

0x0005 C000–0x0005 EFFF

0x000B 0000–0x000B 3FFF

0x000B 8000–0x000B DFFF

0x0017 0000–0x0017 BFFF

Block 2 SRAM

0x0006 0000–0x0006 0FFF

0x000C 0000–0x000C 1554

0x000C 0000–0x000C 1FFF

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000– 0x0006 FFFF

0x000C 1555–0x000C 3FFF

0x000C 2000–0x000D FFFF

0x0018 4000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 0FFF

0x000E 0000–0x000E 1554

0x000E 0000–0x000E 1FFF

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

0x000E 1555–0x000F FFFF

0x000E 2000–0x000F FFFF

0x001C 4000–0x001F FFFF

¹The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

The SRAM can be configured as a maximum of 64k words of

32-bit data, 128k words of 16-bit data, 42k words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to two megabits. All of the memory can be accessed as

16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the amount

of data that can be stored on-chip. Conversion between the

32-bit floating-point and 16-bit floating-point formats is per-

formed in a single instruction. While each memory block can

store combinations of code and data, accesses are most efficient

when one block stores data using the DM bus for transfers, and

the other block stores instructions and data using the PM bus

for transfers.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2x64-bits, core CLK) and the

IOD0/1 buses (2x32-bit, PCLK).

ROM-Based Security

The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu-

rity feature that provides hardware support for securing user

software code by preventing unauthorized reading from the

internal code when enabled. When using this feature, the pro-

cessor does not boot-load any external code, executing

exclusively from internal ROM. Additionally, the processor is

not freely accessible via the JTAG port. Instead, a unique 64-bit

key, which must be scanned in through the JTAG or test access

port will be assigned to each customer. The device will ignore a

wrong key. Emulation features and external boot modes are

only available after the correct key is scanned.

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

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ADSP-21367/ADSP-21368/ADSP-21369

Table 4. External Memory for SDRAM Addresses

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-21367/ADSP-21368/ADSP-21369 family contains a

rich set of peripherals that support a wide variety of applications

including high quality audio, medical imaging, communica-

tions, military, test equipment, 3D graphics, speech recognition,

motor control, imaging, and other applications.

Size in

Words

Bank

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

62M

64M

0x0020 0000–0x03FF FFFF

0x0400 0000–0x07FF FFFF

0x0800 0000–0x0BFF FFFF

0x0C00 0000–0x0FFF FFFF

External Port

The external port interface supports access to the external mem-

ory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports of the ADSP-21367/8/9 processors are comprised

of the following modules.

• An Asynchronous Memory Interface which communicates

with SRAM, FLASH, and other devices that meet the stan-

dard asynchronous SRAM access protocol. The AMI

supports 14M words of external memory in bank 0 and

16M words of external memory in bank 1, bank 2, and

bank 3.

• An SDRAM controller that supports a glueless interface

with any of the standard SDRAMs. The SDC supports 62M

words of external memory in bank 0, and 64M words of

external memory in bank 1, bank 2, and bank 3.

• Arbitration Logic to coordinate core and DMA transfers

between internal and external memory over the external

port.

for connection of industry-standard synchronous DRAM

devices and DIMMs (dual inline memory module), while the

second is an asynchronous memory controller intended to

interface to a variety of memory devices. Four memory select

pins enable up to four separate devices to coexist, supporting

any desired combination of synchronous and asynchronous

device types. Non-SDRAM external memory address space is

shown in Table 5.

Table 5. External Memory for Non-SDRAM Addresses

Size in

Words

Bank

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

14M

0x0020 0000–0x00FF FFFF

0x0400 0000–0x04FF FFFF

0x0800 0000–0x08FF FFFF

0x0C00 0000–0x0CFF FFFF

16M

• A Shared Memory Interface that allows the connection of

up to four ADSP-21368 processors to create shared exter-

nal bus systems (ADSP-21368 only).

16M

Shared External Memory

SDRAM Controller

The ADSP-21368 processor supports connecting to common

shared external memory with other ADSP-21368 processors to

create shared external bus processor systems. This support

includes:

• Distributed, on-chip arbitration for the shared external bus

• Fixed and rotating priority bus arbitration

• Bus time-out logic

The SDRAM controller provides an interface of up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs, at

speeds up to f_SCLK. Fully compliant with the SDRAM standard,

each bank has its own memory select line (MS0–MS3), and can

be configured to contain between 16M bytes and 128M bytes of

memory. SDRAM external memory address space is shown in

Table 4.

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as either 32 bits wide for max-

imum performance and bandwidth or 16 bits wide for

minimum device count and lower system cost.

The SDRAM controller address, data, clock, and control pins

can drive loads up to distributed 30 pF loads. For larger memory

systems, the SDRAM controller external buffer timing should

be selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

• Bus lock

Multiple processors can share the external bus with no addi-

tional arbitration logic. Arbitration logic is included on-chip to

allow the connection of up to four processors.

Bus arbitration is accomplished through the BR1–4 signals and

the priority scheme for bus arbitration is determined by the set-

ting of the RPBA pin. Table 8 provides descriptions of the pins

used in multiprocessor systems.

External Port Throughput

The throughput for the external port, based on 166 MHz clock

and 32-bit data bus, is 221M bytes/s for the AMI and 664M

bytes/s for SDRAM.

External Memory

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

32-bit wide bus can be used to interface to synchronous and/or

asynchronous memory devices through the use of its separate

internal memory controllers. The first is an SDRAM controller

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ADSP-21367/ADSP-21368/ADSP-21369

processor core, configurable as either eight channels of I²S serial

Asynchronous Memory Controller

data or as seven channels plus a single 20-bit wide synchronous

parallel data acquisition port. Each data channel has its own

DMA channel that is independent from the processor’s serial

ports.

For complete information on using the DAI, see the

ADSP-21368 SHARC Processor Hardware Reference.

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory

control lines. Bank 0 occupies a 14M word window and Banks 1,

2, and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of

interfacing to a range of memories and I/O devices tailored

either to high performance or to low cost and power.

Serial Ports

The processors feature eight synchronous serial ports (SPORTs)

that provide an inexpensive interface to a wide variety of digital

and mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Pulse-Width Modulation

Serial ports are enabled via 16 programmable and simultaneous

receive or transmit pins that support up to 32 transmit or 32

receive channels of audio data when all eight SPORTs are

enabled, or eight full duplex TDM streams of 128 channels

per frame.

The serial ports operate at a maximum data rate of 50 Mbps.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for packed I²S

mode

• I²S mode

• Packed I²S mode

• Left-justified sample pair mode

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode,

the duty cycle values are programmable only once per PWM

period. This results in PWM patterns that are symmetrical

about the midpoint of the PWM period. In double update

mode, a second updating of the PWM registers is implemented

at the midpoint of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce lower

harmonic distortion in 2-phase PWM inverters.

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Digital Applications Interface (DAI)

The digital applications interface (DAI ) provide the ability to

connect various peripherals to any of the DSP’s DAI pins

(DAI_P20–1). Programs make these connections using the sig-

nal routing unit (SRU1), shown in Figure 1.

The SRU is amatrix routing unit (or group of multiplexers) that

enable the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

Each of the serial ports supports the left-justified sample pair

and I²S protocols (I²S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I²S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I²S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I²S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional -law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

The DAI include eight serial ports, an S/PDIF receiver/trans-

mitter, four precision clock generators (PCG), eight channels of

synchronous sample rate converters, and an input data port

(IDP). The IDP provides an additional input path to the

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ADSP-21367/ADSP-21368/ADSP-21369

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports

example, frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

(SPIs). The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI-compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex

synchronous serial interface, supporting both master and slave

modes. The SPI port can operate in a multimaster environment

by interfacing with up to four other SPI-compatible devices,

either acting as a master or slave device. The ADSP-21367/

ADSP-21368/ADSP-21369 SPI-compatible peripheral imple-

mentation also features programmable baud rate and clock

phase and polarities. The SPI-compatible port uses open-drain

drivers to support a multimaster configuration and to avoid

data contention.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left-justified, I²S, or

right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources such as the

SPORTs, external pins, the precision clock generators (PCGs),

or the sample rate converters (SRC) and are controlled by the

SRU control registers.

UART Port

The processors provide a full-duplex universal asynchronous

receiver/transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

standard. The UART port also includes support for five data bits

to eight data bits, one stop bit or two stop bits, and none, even,

or odd parity. The UART port supports two modes of

operation:

Synchronous/Asynchronous Sample Rate Converter

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter and provides up to 128 dB

SNR. The SRC block is used to perform synchronous or asyn-

chronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the SRC can be used to clean up audio data from jittery

clock sources such as the S/PDIF receiver.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

Input Data Port

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I2S, left-justified sample pair, or right-justi-

fied mode. One frame sync cycle indicates one 64-bit left/right

pair, but data is sent to the FIFO as 32-bit words (that is, one-

half of a frame at a time). The processor supports 24- and 32-bit

I²S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit

right-justified formats.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/1,048,576) to

(f_SCLK/16) bits per second.

Precision Clock Generators

• Supporting data formats from 7 bits to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

Where the 16-bit UART_Divisor comes from the DLH register

(most significant eight bits) and DLL register (least significant

eight bits).

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

Digital Peripheral Interface (DPI)

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), two universal asynchro-

nous receiver-transmitters (UARTs), a 2-wire interface (TWI),

12 flags, and three general-purpose timers.

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ADSP-21367/ADSP-21368/ADSP-21369

Peripheral Timers

Delay Line DMA

Three general-purpose timers can generate periodic interrupts

and be independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The ADSP-21367/ADSP-21368/ADSP-21369 processors pro-

vide delay line DMA functionality. This allows processor reads

and writes to external delay line buffers (in external memory,

SRAM, or SDRAM) with limited core interaction.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Each general-purpose timer has one bidirectional pin and four

registers that implement its mode of operation: a 6-bit configu-

ration register, a 32-bit count register, a 32-bit period register,

and a 32-bit pulse width register. A single control and status

register enables or disables all three general-purpose timers

independently.

Program Booting

The internal memory of the processors can be booted up at sys-

tem power-up from an 8-bit EPROM via the external port, an

SPI master or slave, or an internal boot. Booting is determined

by the boot configuration (BOOT_CFG1–0) pins (see Table 7

and the processor hardware reference). Selection of the boot

source is controlled via the SPI as either a master or slave device,

or it can immediately begin executing from ROM.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

• Simultaneous master and slave operation on multiple

device systems with support for multimaster data

arbitration

• Digital filtering and timed event processing

• 7-bit and 10-bit addressing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

Table 7. Boot Mode Selection

BOOT_CFG1–0

Booting Mode

SPI Slave Boot

00

01

10

11

SPI Master Boot

EPROM/FLASH Boot

No boot (processor executes from

internal ROM after reset)

I/O PROCESSOR FEATURES

Power Supplies

The I/O processor provides many channels of DMA, and con-

trols the extensive set of peripherals described in the previous

sections.

The processors have separate power supply connections for the

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS) power

supplies. The internal and analog supplies must meet the 1.3 V

requirement for the 400 MHz device and 1.2 V for the

333 MHz and 266 MHz devices. The external supply must meet

the 3.3 V requirement. All external supply pins must be con-

nected to the same power supply.

DMA Controller

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the processor’s internal memory and its serial ports, the

SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the parallel data acquisition port (PDAP), or

the UART.

Note that the analog supply pin (A_VDD) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

A

_VDDpin. Place the filter components as close as possible to the

_VDD/A_VSSpins. For an example circuit, see Figure 3. (A recom-

A

mended ferrite chip is the muRata BLM18AG102SN1D). To

reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V_DDINTand GND. Use wide traces

to connect the bypass capacitors to the analog power (A_VDD) and

ground (A_VSS) pins. Note that the A_VDDand A_VSSpins specified in

Figure 3 are inputs to the processor and not the analog ground

plane on the board—the A_VSSpin should connect directly to dig-

ital ground (GND) at the chip.

Thirty four channels of DMA are available on the ADSP-2136x

processors as shown in Table 6.

Table 6. DMA Channels

Peripheral

SPORTs

DMA Channels

16

8

PDAP

SPI

2

UART

4

External Port

Memory-to-Memory

2

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ADSP-21367/ADSP-21368/ADSP-21369

EZ-KIT Lite Evaluation Board

ADSP-213xx

100nF

10nF

1nF

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

A

V

VDD

DDINT

HI-Z FERRITE

BEAD CHIP

A

VSS

LOCATE ALL COMPONENTS

CLOSE TO A AND A PINS

VDD

VSS

EZ-KIT Lite Evaluation Kits

Figure 3. Analog Power (A_VDD) Filter Circuit

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21367/

ADSP-21368/ADSP-21369 processors to monitor and control

the target board processor during emulation. Analog Devices

DSP Tools product line of JTAG emulators provides emulation

at full processor speed, allowing inspection and modification of

memory, registers, and processor stacks. The processor’s JTAG

interface ensures that the emulator will not affect target system

loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User’s Guide.”

DEVELOPMENT TOOLS

Software Add-Ins for CrossCore Embedded Studio

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore^®Embed-

ded Studio and/or VisualDSP++^®), evaluation products,

emulators, and a wide variety of software add-ins.

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

The newest IDE, CrossCore Embedded Studio, is based on the

Board Support Packages for Evaluation Hardware

TM

Eclipse framework. Supporting most Analog Devices proces-

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

www.analog.com/cces.

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

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ADSP-21367/ADSP-21368/ADSP-21369

Middleware Packages

RELATED SIGNAL CHAINS

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

• www.analog.com/ucos2

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/ucusbh

• www.analog.com/lwip

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The application signal chains page in the Circuits from the Lab^®

site (http:\\www.analog.com\circuits) provides:

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see “Analog Devices JTAG

Emulation Technical Reference” (EE-68). This document is

updated regularly to keep pace with improvements to emulator

support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-21367/ADSP-21368/ADSP-21369 architecture and func-

tionality. For detailed information on the ADSP-2136x family

core architecture and instruction set, refer to the ADSP-21368

SHARC Processor Hardware Reference and the SHARC Processor

Programming Reference.

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ADSP-21367/ADSP-21368/ADSP-21369

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 8:

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-

sors use extensive pin multiplexing to achieve a lower pin count.

For complete information on the multiplexing scheme, see the

ADSP-21368 SHARC Processor Hardware Reference, “System

Design” chapter.

A = asynchronous, G = ground, I = input, O = output,

O/T = output three-state, P = power supply, S = synchronous,

(A/D) = active drive, (O/D) = open-drain, (pd) = pull-down

resistor, (pu) = pull-up resistor.

Table 8. Pin Descriptions

State During/

After Reset

(ID = 00x)

Name

Type

Description

ADDR_23–0

O/T (pu)¹

Pulled high/

driven low

External Address. The processors output addresses for external memory and peripher-

als on these pins.

DATA_31–0

I/O (pu)¹

Pulled high/

pulled high

External Data. Data pins can be multiplexed to support external memory interface data

(I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode

and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_P-

DAP_CTL register, IDP Channel 0 scans the external port data pins for parallel input data.

ACK

I (pu)¹

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an

external memory access. ACK is used by I/O devices, memory controllers, or other periph-

erals to hold off completion of an external memory access.

MS_0–1

O/T (pu)¹

Pulled high/

driven high

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

sponding banks of external memory. The MS_3-0lines are decoded memory address lines

that change at the same time as the other address lines. When no external memory access

is occurring, the MS_3-0lines are inactive; they are active, however, when a conditional

memory access instruction is executed, whether or not the condition is true.

The MS₁pin can be used in EPORT/FLASH boot mode. See the processor hardware

reference for more information.

RD

O/T (pu)¹

Pulled high/

driven high

External Port Read Enable. RD is asserted whenever the processors read a word from

external memory.

WR

Pulled high/

driven high

External Port Write Enable. WR is asserted when the processors write a word to external

memory.

FLAG[0]/IRQ0

FLAG[1]/IRQ1

I/O

FLAG[0] INPUT

FLAG[1] INPUT

FLAG[2] INPUT

FLAG0/Interrupt Request 0.

FLAG1/Interrupt Request 1.

FLAG[2]/IRQ2/

MS₂

I/O with pro-

grammablepu

(for MS mode)

FLAG2/Interrupt Request 2/Memory Select 2.

FLAG[3]/

TMREXP/MS₃

I/O with pro-

grammablepu

(for MS mode)

FLAG[3] INPUT

FLAG3/Timer Expired/Memory Select 3.

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Table 8. Pin Descriptions (Continued)

State During/

After Reset

(ID = 00x)

Name

Type

Description

SDRAS

O/T (pu)¹

Pulled high/

driven high

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS

SDWE

O/T (pu)¹

O/T

Pulled high/

driven high

SDRAMColumnAddressSelect. ConnecttoSDRAM’sCASpin.Inconjunctionwithother

SDRAM command pins, defines the operation for the SDRAM to perform.

Pulled high/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

SDCKE

SDA10

SDCLK0

SDCLK1

Pulled high/

driven high

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal.

For details, see the data sheet supplied with the SDRAM device.

Pulled high/

driven low

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

High-Z/driving

SDRAM Clock Output 0. Clock driver for this pin differs from all other clock drivers. See

Figure 40.

O/T

SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple

SDRAM devices, handles the increased clock load requirements, eliminating need of off-

chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. Clock driver

for this pin differs from all other clock drivers. See Figure 40.

The SDCLK1 signal is only available on the FCBGA package. SDCLK1 is not available on

the LQFP_EP package.

DAI _P_20–1

I/O with pro-

grammable

pu²

Pulled high/

pulled high

Digital Applications Interface. These pins provide the physical interface to the DAI SRU.

The DAI SRU configuration registers define the combination of on-chip audiocentric

peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The

configuration registers then determines the exact behavior of the pin. Any input or

output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU

provides the connection from the serial ports (8), the SRC module, the S/PDIF module,

input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pull-

ups can be disabled via the DAI_PIN_PULLUP register.

DPI _P_14–1

I/O with pro-

grammable

pu²

Pulled high/

pulled high

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU

provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and

general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output—

so the pins used for I²C data and clock should be connected to logic level 0. Pull-ups can

be disabled via the DPI_PIN_PULLUP register.

TDI

I (pu)

O/T

I (pu)

I

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO

TMS

TCK

Test Clock (JTAG). ProvidesaclockforJTAGboundaryscan. TCKmustbeasserted(pulsed

low) after power-up, or held low for proper operation of the processor

TRST

I (pu)

TestReset(JTAG). Resetstheteststatemachine. TRSTmustbeasserted(pulsedlow)after

power-up or held low for proper operation of the processor.

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ADSP-21367/ADSP-21368/ADSP-21369

Table 8. Pin Descriptions (Continued)

State During/

After Reset

(ID = 00x)

Name

Type

Description

EMU

O (O/D, pu)

Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/

ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board con-

nectors only.

CLK_CFG_1–0

CLKIN

I

Core/CLKINRatioControl. Thesepinssetthestart-upclockfrequency.Seetheprocessor

hardware reference for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the

processors to use either its internal clock generator or an external clock source. Connect-

ing the necessary components to CLKIN and XTAL enables the internal clock generator.

Connecting the external clock to CLKIN while leaving XTAL unconnected configures the

processor to use an external clock such as an external clock oscillator. CLKIN may not be

halted, changed, or operated below the specified frequency.

XTAL

O

I

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

RESET

ProcessorReset. Resetstheprocessortoaknownstate. Upondeassertion,thereisa4096

CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution

from the hardware reset vector address. The RESET input must be asserted (low) at power-

up.

RESETOUT

O

I

Driven low/

driven high

Reset Out. Drives out the core reset signal to an external device.

BOOT_CFG_1–0

Boot Configuration Select. These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before reset is asserted. See the processor hardware

reference for a description of the boot modes.

BR_4–1

I/O (pu)¹

Pulled high/

pulled high

External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus master-

ship. A processor only drives its own BR_xline (corresponding to the value of its ID2-0

inputs) and monitors all others. In a system with less than four processors, the unused BR_x

pins should be tied high; the processor’s own BR_xline must not be tied high or low

because it is an output.

ID_2–0

I (pd)

Processor ID. Determineswhichbusrequest(BR_4–1)isusedbytheADSP-21368processor.

ID = 001 corresponds to BR_1,ID = 010 corresponds to BR₂, and so on. Use ID = 000 or 001

in single-processor systems. These lines are a system configuration selection that should

be hardwired or only changed at reset. ID = 101,110, and 111 are reserved.

RPBA

I (pu)¹

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for the

ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is

selected. This signal is a system configuration selection which must be set to the same

value on every processor in the system.

¹The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID_2–0= 00x

²Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

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ADSP-21367/ADSP-21368/ADSP-21369

SPECIFICATIONS

OPERATING CONDITIONS

366 MHz

350 MHz

333 MHz

266 MHz

400 MHz

Parameter¹Description

Min

Max

Min

Max

Min

Max

Unit

V_DDINT

A_VDD

Internal (Core) Supply Voltage

1.25

3.13

2.0

1.35

3.47

1.235

3.13

1.365

3.47

1.14

3.13

1.26

3.47

V

Analog (PLL) Supply Voltage

V_DDEXT

External (I/O) Supply Voltage

2

V_IH

High Level Input Voltage @ V_DDEXT= Max

Low Level Input Voltage @ V_DDEXT= Min

High Level Input Voltage @ V_DDEXT= Max

Low Level Input Voltage @ V_DDEXT= Min

V_DDEXT+ 0.5 2.0

V_DDEXT+ 0.5

2

V_IL

–0.5

1.74

–0.5

+0.8

–0.5

+0.8

–0.5

+0.8

3

V_IH

V_DDEXT+ 0.5 1.74

V_DDEXT+ 0.5

+1.1

_

CLKIN

3

V_IL

T_J

+1.1

–0.5

+1.1

110

N/A

–0.5

_CLKIN

Junction Temperature 208-Lead LQFP_EP @

T_AMBIENT0C to 70C

0

95

0

110

C

T_J

Junction Temperature 208-Lead LQFP_EP @

T_AMBIENT–40C to +85C

N/A

0

N/A

95

N/A

–40

0

+120

105

Junction Temperature 256-Ball BGA_ED @

T_AMBIENT0C to 70C

Junction Temperature 256-Ball BGA_ED @

T_AMBIENT–40C to +85C

N/A

–40

+105

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

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ADSP-21367/ADSP-21368/ADSP-21369

ELECTRICAL CHARACTERISTICS

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

1

V_OH

High Level Output Voltage

Low Level Output Voltage

@ V_DDEXT= Min, I_OH= –1.0 mA²

@ V_DDEXT= Min, I_OL= 1.0 mA²

@ V_DDEXT= Max, V_IN= V_DDEXTMax

@ V_DDEXT= Max, V_IN= 0 V

2.4

V

1

V_OL

0.4

10

V

3, 4

I_IH

High Level Input Current

μA

3, 5, 6

I_IL

Low Level Input Current

10

5

I_IHPD

High Level Input Current Pull-Down

Low Level Input Current Pull-Up

Three-State Leakage Current

Three-State Leakage Current Pull-Up

Supply Current (Internal)

@ V_DDEXT= Max, V_IN= 0 V

250

200

10

4

I_ILPU

@ V_DDEXT= Max, V_IN= 0 V

7, 8

I_OZH

@ V_DDEXT= Max, V_IN= V_DDEXTMax

@ V_DDEXT= Max, V_IN= 0 V

7, 9

I_OZL

10

8

I_OZLPU

@ V_DDEXT= Max, V_IN= 0 V

200

10

I_DD

t_CCLK= 3.75 ns, V_DDINT= 1.2 V, 25°C

700

900

1050

1080

1100

mA

-

INTYP

t

_CCLK= 3.00 ns, V_DDINT= 1.2 V, 25°C

_CCLK= 2.85 ns, V_DDINT= 1.3 V, 25°C

_CCLK= 2.73 ns, V_DDINT= 1.3 V, 25°C

_CCLK= 2.50 ns, V_DDINT= 1.3 V, 25°C

11

AI_DD

Supply Current (Analog)

Input Capacitance

A_VDD= Max

11

mA

pF

12, 13

C_IN

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.3 V

4.7

¹Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO.

²See Output Drive Currents for typical drive current capabilities.

³Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.

⁴Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.

⁵Applies to input pins with internal pull-downs: IDx.

⁶Applies to input pins with internal pull-ups disabled: ACK, RPBA.

⁷Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.

⁸Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.

⁹Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10

¹⁰See the Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21368 SHARC Processors” (EE-299) for further information.

¹¹Characterized, but not tested.

¹²Applies to all signal pins.

¹³Guaranteed, but not tested.

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Table 10. Absolute Maximum Ratings

PACKAGE INFORMATION

The information presented in Figure 4 provides details about

the package branding for the ADSP-21367/ADSP-21368/

ADSP-21369 processors. For a complete listing of product avail-

ability, see Ordering Guide.

Parameter

Internal (Core) Supply Voltage (V_DDINT

Rating

)

–0.3 V to +1.5 V

–0.3 V to +4.6 V

–0.5 V to +3.8 V

–0.5 V to V_DDEXT+ 0.5 V

200 pF

Analog (PLL) Supply Voltage (A_VDD

)

External (I/O) Supply Voltage (V_DDEXT

Input Voltage

)

Output Voltage Swing

a

Load Capacitance

ADSP-2136x

Storage Temperature Range

Junction Temperature Under Bias

–65C to +150C

125C

tppZ-cc

vvvvvv.x n.n

#yyww country_of_origin

TIMING SPECIFICATIONS

S

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 41 under Test Conditions for voltage reference levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Figure 4. Typical Package Brand

Table 9. Package Brand Information

Brand Key

t

Field Description

Temperature Range

Package Type

pp

Z

RoHS Compliant Option

See Ordering Guide

Assembly Lot Code

Silicon Revision

cc

vvvvvv.x

n.n

#

RoHS Compliant Designation

Date Code

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

yyww

ESD CAUTION

Core Clock Requirements

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

MAXIMUM POWER DISSIPATION

See the Engineer-to-Engineer Note “Estimating Power Dissipa-

tion for ADSP-21368 SHARC Processors” (EE-299) for detailed

thermal and power information regarding maximum power dis-

sipation. For information on package thermal specifications, see

Thermal Characteristics.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

ABSOLUTE MAXIMUM RATINGS

f

_VCOspecified in Table 13.

Stresses at or above those listed in Table 10 may cause perma-

nent damage to the product. This is a stress rating only;

functional operation of the product at these or any other condi-

tions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum

operating conditions for extended periods may affect product

reliability.

• The product of CLKIN and PLLM must never exceed 1/2 of

f_VCO(max) in Table 13 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f_VCO

(max) in Table 13 if the input divider is enabled

(INDIV = 1).

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

The VCO frequency is calculated as follows:

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in and

Table 11. All of the timing specifications for the ADSP-2136x

peripherals are defined in relation to t_PCLK. See the peripheral spe-

cific timing section for each peripheral’s timing information.

f

_VCO= 2  PLLM  f_INPUT

_CCLK= (2  PLLM  f_INPUT)  (2  PLLD)

where:

_VCO= VCO output

f

Table 11. Clock Periods

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

Timing

Requirements

Description

PLLD = Divider value 1, 2, 4, or 8 based on the PLLD value pro-

t_CK

CLKIN Clock Period

grammed on the PMCTL register. During reset this value is 1.

t_CCLK

t_PCLK

Processor Core Clock Period

Peripheral Clock Period = 2 × t_CCLK

f

_INPUT= Input frequency to the PLL.

_INPUT= CLKIN when the input divider is disabled or

_INPUT= CLKIN  2 when the input divider is enabled

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the processor hardware reference.

PMCTL

(SDCKR)

PMCTL

(PLLBP)

PLL

f_VCO

f_INPUT

CCLK

SDRAM

DIVIDER

CLKIN

BUF

CLKIN

DIVIDER

LOOP

FILTER

PLL

DIVIDER

VCO

SDCLK

f_CCLK

XTAL

PMCTL

(2xPLLD)

PMCTL

(INDIV)

PCLK

DIVIDE

BY 2

PLL

MULTIPLIER

PMCTL

(PLLBP)

PCLK

CCLK

CLK_CFGx/PMCTL (2xPLLM)

CLKOUT (TEST ONLY)

DELAY OF

4096 CLKIN

BUF

CYCLES

Figure 5. Core Clock and System Clock Relationship to CLKIN

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Power-Up Sequencing

The timing requirements for processor start-up are given in

Table 12. Note that during power-up, a leakage current of

approximately 200μA may be observed on the RESET pin if it is

driven low before power up is complete. This leakage current

results from the weak internal pull-up resistor on this pin being

enabled during power-up.

Table 12. Power-Up Sequencing Timing Requirements (Processor Start-up)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_DDINT/V_DDEXTOn

V_DDINTOn Before V_DDEXT

0

ns

t_IVDDEVDD

–50

+200

200

ms

μs

1

t_CLKVDD

CLKIN Valid After V_DDINT/V_DDEXTValid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

0

t_CLKRST

10²

20

t_PLLRST

μs

Switching Characteristic

3, 4

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096t_CK+ 2 t_CCLK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate

default states at all I/O pins.

⁴The 4096 cycle count depends on t_srstspecification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles

maximum.

t_RSTVDD

RESET

V

DDINT

t_IVDDEVDD

V

DDEXT

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG1–0

RESETOUT

t_PLLRST

t_CORERST

Figure 6. Power-Up Sequencing

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Clock Input

Table 13. Clock Input

400 MHz¹

366 MHz²

350 MHz³

333 MHz⁴

266 MHz⁵

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_CK

CLKIN Period

15⁶

7.5¹

100

45

16.39⁶100

17.14⁶100

18⁶

9¹

100

45

22.5⁶

100

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

8.1¹

45

8.5¹

45

11.25¹45

3

ns

45

9¹

45

ns

3

ns

7

2.5⁶

10

2.73⁶

100

10

2.85⁶

100

10

3.0⁶

100

10

3.75⁶

10

ns

8

f_VCO

VCO Frequency

100

800

+250

800

+250

800

+250

800

+250

100

600

+250

MHz

ps

9, 10

t_CKJ

CLKIN Jitter Tolerance

–250

¹Applies to all 400 MHz models. See Ordering Guide.

²Applies to all 366 MHz models. See Ordering Guide.

³Applies to all 350 MHz models. See Ordering Guide.

⁴Applies to all 333 MHz models. See Ordering Guide.

⁵Applies to all 266 MHz models. See Ordering Guide.

⁶Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

⁷Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

⁸See Figure 5 for VCO diagram.

.

⁹Actual input jitter should be combined with ac specifications for accurate timing analysis.

¹⁰Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

t_CKJ

t_CK

CLKIN

t_CKH

t_CKL

Figure 7. Clock Input

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ADSP-21367/ADSP-21368/ADSP-21369

Clock Signals

The processors can use an external clock or a crystal. See the

CLKIN pin description in Table 8. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 8 shows the

component connections used for a crystal operating in funda-

mental mode.

Note that the clock rate is achieved using a 25 MHz crystal and a

PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed

of 400 MHz). To achieve the full core clock rate, programs need

to configure the multiplier bits in the PMCTL register.

ADSP-2136x

R1

1M⍀*

XTAL

CLKIN

R2

47⍀*

C1

22pF

C2

22pF

Y1

25.00 MHz

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

Figure 8. 400 MHz Operation (Fundamental Mode Crystal)

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ADSP-21367/ADSP-21368/ADSP-21369

Reset

Table 14. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

RESET Pulse Width Low

4t_CK

8

ns

t_SRST

RESET Setup Before CLKIN Low

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable

V_DDand CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 9. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 15. Interrupts

Parameter

Timing Requirement

Min

2 × t_PCLK+2

Max

Unit

t_IPW

IRQx Pulse Width

ns

INTERRUPT

INPUTS

t_IPW

Figure 10. Interrupts

Rev. G

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Table 16. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

TMREXP Pulse Width

4 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(TMREXP)

Figure 11. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DPI_P14–1 pins through the

DPI SRU. Therefore, the timing specifications provided below

are valid at the DPI_P14–1 pins.

Table 17. Timer PWM_OUT Timing

Parameter

Switching Characteristic

Min

Max

2 × (2³¹– 1) × t_PCLK

Unit

t_PWMO

Timer Pulse Width Output

2 × t_PCLK– 1.2

ns

t_PWMO

PWM

OUTPUTS

Figure 12. Timer PWM_OUT Timing

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Timer WDTH_CAP Timing

The following specification applies to Timer0, Timer1, and

Timer2 in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

DPI SRU. Therefore, the specification provided in Table 18 is

valid at the DPI_P14–1 pins.

Table 18. Timer Width Capture Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PWI

Timer Pulse Width

2 × t_PCLK

2 × (2³¹– 1) × t_PCLK

ns

t_PWI

TIMER

CAPTURE

INPUTS

Figure 13. Timer Width Capture Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 19. DAI/DPI Pin to Pin Routing

Parameter

Timing Requirement

Min

Max

12

Unit

t_DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid

1.5

ns

DAI_Pn

DPI_Pn

t_DPIO

DAI_Pm

DPI_Pm

Figure 14. DAI/DPI Pin to Pin Direct Routing

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ADSP-21367/ADSP-21368/ADSP-21369

inputs and outputs are not directly routed to/from DAI pins (via

Precision Clock Generator (Direct Pin Routing)

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01–20).

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 20. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIP

t_STRIG

Input Clock Period

t_PCLK× 4

4.5

ns

PCG Trigger Setup Before Falling

Edge of PCG Input Clock

t_HTRIG

PCG Trigger Hold After Falling

Edge of PCG Input Clock

3

ns

Switching Characteristics

t_DPCGIO

PCG Output Clock and Frame Sync Active Edge

2.5

10

Delay After PCG Input Clock

t_DTRIGCLK

PCG Output Clock Delay After PCG Trigger

PCG Frame Sync Delay After PCG Trigger

Output Clock Period

2.5 + (2.5 × t_PCGIP

)

10 + (2.5 × t_PCGIP

)

ns

t_DTRIGFS

2.5 + ((2.5 + D – PH) × t_PCGIP

2 × t_PCGIP– 1

)

10 + ((2.5 + D – PH) × t_PCGIP)

1

t_PCGOW

D = FSxDIV, and PH = FSxPHASE. For more information, see the processor hardware reference, “Precision Clock Generators” chapter.

¹In normal mode.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

t_PCGIP

DAI_Py

DPI_Py

PCG_CLKx_O

t_DTRIGCLK

t_PCGOW

t_DPCGIO

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 15. Precision Clock Generator (Direct Pin Routing)

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Flags

The timing specifications provided below apply to the FLAG3–0

and DPI_P14–1 pins, and the serial peripheral interface (SPI).

See Table 8 for more information on flag use.

Table 21. Flags

Parameter

Timing Requirement

Min

Max

Unit

ns

t_FIPW

Switching Characteristic

t_FOPWFLAG3–0 OUT Pulse Width

FLAG3–0 IN Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 1.5

ns

FLAG

INPUTS

t_FIPW

FLAG

OUTPUTS

t_FOPW

Figure 16. Flags

Rev. G

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

SDRAM Interface Timing (166 MHz SDCLK)

The 166 MHz access speed is for a single processor. When mul-

tiple ADSP-21368 processors are connected in a shared memory

system, the access speed is 100 MHz.

Table 22. SDRAM Interface Timing¹

All Other Speed

Grades

366 MHz

350 MHz

Max

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SSDAT

t_HSDAT

Switching Characteristics

DATA Setup Before SDCLK

500

ps

ns

DATA Hold After SDCLK

1.23

t_SDCLK

t_SDCLKH

t_SDCLKL

t_DCAD

SDCLK Period

6.83

3

7.14

3

6.0

2.6

ns

SDCLK Width High

SDCLK Width Low

3

Command, ADDR, Data Delay After SDCLK²

Command, ADDR, Data Hold After SDCLK²

Data Disable After SDCLK

Data Enable After SDCLK

4.8

5.3

4.8

5.3

4.8

5.3

t_HCAD

1.2

1.3

t_DSDAT

t_ENSDAT

1.3

¹The processor needs to be programmed in t_SDCLK= 2.5  t_CCLKmode when operated at 350 MHz, 366 MHz, and 400 MHz.

²Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

t_SDCLKH

t_SDCLK

SDCLK

t_SSDAT

t_HSDAT

t_SDCLKL

DATA (IN)

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

DATA (OUT)

t_DCAD

t_HCAD

COMMAND/ADDR

(OUT)

Figure 17. SDRAM Interface Timing

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ADSP-21367/ADSP-21368/ADSP-21369

SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)

Table 23. SDRAM Interface Enable/Disable Timing¹

Parameter

Min

Max

Unit

Switching Characteristics

t_DSDC

Command Disable After CLKIN Rise

Command Enable After CLKIN Rise

SDCLK Disable After CLKIN Rise

SDCLK Enable After CLKIN Rise

Address Disable After CLKIN Rise

Address Enable After CLKIN Rise

2 × t_PCLK+ 3

8.5

ns

t_ENSDC

t_DSDCC

t_ENSDCC

t_DSDCA

t_ENSDCA

4.0

3.8

9.2

2 × t_PCLK– 4

4 × t_PCLK

¹For f_CCLK= 400 MHz (SDCLK ratio = 1:2.5).

CLKIN

t_DSDC

t_DSDCC

t_DSDCA

COMMAND

SDCLK

ADDR

t_ENSDC

t_ENSDCA

t_ENSDCC

COMMAND

SDCLK

ADDR

Figure 18. SDRAM Interface Enable/Disable Timing

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ADSP-21367/ADSP-21368/ADSP-21369

Memory Read

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the processors are the bus

master accessing external memory space in asynchronous access

mode. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 24. Memory Read

Parameter

Min

Max

Unit

Timing Requirements

t_DAD

t_DRLD

t_SDS

Address, Selects Delay to Data Valid^{1, 2}

W + t_SDCLK–5.12

W – 3.2

ns

RD Low to Data Valid²

Data Setup to RD High

2.5

0

t_HDRH

t_DAAK

t_DSAK

Data Hold from RD High^{3, 4}

ACK Delay from Address, Selects^{1, 5}

ACK Delay from RD Low⁵

t_SDCLK–9.5 + W

W – 7.0

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address Selects Hold After RD High

RH + 0.20

t_SDCLK– 3.3

W – 1.4

ns

Address Selects to RD Low¹

RD Pulse Width

t_RWR

RD High to WR, RD Low

HI + t_SDCLK– 0.8

W = (number of wait states specified in AMICTLx register) × t_SDCLK

RHC = (number of Read Hold Cycles specified in AMICTLx register) × t_SDCLK

Where PREDIS = 0

HI = RHC (if IC = 0): Read to Read from same bank

HI = RHC+ t_SDCLK(if IC > 0): Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × t_SDCLK)): Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max (IC, (4 × t_SDCLK)): Read to Write from same or different bank

HI = RHC + (3 × t_SDCLK): Read to Read from same bank

HI = RHC + Max (IC, (3 × t_SDCLK)): Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

¹The falling edge of MSx is referenced.

²Themaximum limit of timing requirement values for t_DADand t_DRLDparametersareapplicable forthecase whereAMI_ACK isalways high and whenthe ACKfeature is not used.

³Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

⁴Data hold: User must meet t_HDAor t_HDRHin asynchronous access mode. See Test Conditions for the calculation of hold times given capacitive and dc loads.

⁵ACK delay/setup: User must meet t_DAAK, or t_DSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t_DAAKor t_DSAK

.

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ADSP-21367/ADSP-21368/ADSP-21369

ADDR

MSx

t_DARL

t_RW

t_DRHA

RD

t_DRLD

t_SDS

t_DAD

t_HDRH

DATA

t_DSAK

t_RWR

t_DAAK

ACK

WR

Figure 19. Memory Read

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

access mode. Note that timing for ACK, DATA, RD, WR, and

strobe timing parameters only applies to asynchronous access

mode.

Memory Write

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the processors are the bus

masters, accessing external memory space in asynchronous

Table 25. Memory Write

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

ACK Delay from Address, Selects^{1, 2}

ACK Delay from WR Low ^{1, 3}

t_SDCLK– 9.7 + W

W – 4.9

ns

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address, Selects to WR Deasserted²

t_SDCLK– 3.1+ W

t_SDCLK– 2.7

ns

Address, Selects to WR Low²

WR Pulse Width

W – 1.3

t_DDWH

t_DWHA

t_DWHD

t_WWR

t_DDWR

t_WDE

Data Setup Before WR High

Address Hold After WR Deasserted

Data Hold After WR Deasserted

WR High to WR, RD Low

t_SDCLK– 3.0+ W

H + 0.15

H + 0.02

t_SDCLK– 1.5+ H

2t_SDCLK– 4.11

t_SDCLK– 3.5

Data Disable Before RD Low

Data Enabled to WR Low

W = (number of wait states specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

.

¹ACK delay/setup: System must meet t_DAAK, or t_DSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t_DAAKor t_DSAK

.

²The falling edge of MSx is referenced.

³Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

ADDR

MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

WR

t_WWR

t_WDE

t_DATRWH

t_DDWH

t_DDWR

DATA

t_DSAK

t_DWHD

t_DAAK

ACK

RD

Figure 20. Memory Write

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ADSP-21367/ADSP-21368/ADSP-21369

Asynchronous Memory Interface (AMI) Enable/Disable

Use these specifications for passing bus mastership between

ADSP-21368 processors (BRx).

Table 26. AMI Enable/Disable

Parameter

Min

Max

Unit

Switching Characteristics

t_ENAMIAC

t_ENAMID

t_DISAMIAC

t_DISAMID

Address/Control Enable After Clock Rise

Data Enable After Clock Rise

4

ns

t_SDCLK+ 4

Address/Control Disable After Clock Rise

Data Disable After Clock Rise

8.7

0

CLKIN

t_DISAMIAC

t_DISAMID

ADDR, WR , RD,

MS1–0, DATA

t_ENAMIAC

t_ENAMID

ADDR , WR , RD,

MS1–0, DATA

Figure 21. AMI Enable/Disable

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ADSP-21367/ADSP-21368/ADSP-21369

Shared Memory Bus Request

Use these specifications for passing bus mastership between

ADSP-21368 processors (BRx).

Table 27. Multiprocessor Bus Request

Parameter

Min

Max

Unit

Timing Requirements

t_SBRI

t_HBRI

BRx, Setup Before CLKIN High

BRx, Hold After CLKIN High

9

ns

0.5

Switching Characteristics

t_DBRO

t_HBRO

BRx Delay After CLKIN High

BRx Hold After CLKIN High

9

ns

1.0

CLKIN

t_DBRO

t_HBRO

BR (OUT)

X

t_SBRI

t_HBRI

BR (IN)

X

Figure 22. Shared Memory Bus Request

Rev. G

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ADSP-21367/ADSP-21368/ADSP-21369

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals SCLK, frame sync (FS), data channel A, data

channel B are routed to the DAI_P20–1 pins using the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P20–1 pins.

Table 28. Serial Ports—External Clock

400 MHz

366 MHz

350 MHz

333 MHz

266 MHz

Parameter

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

1

t_SFSE

FS Setup Before SCLK

2.5

ns

(Externally Generated FS in Either

Transmit or Receive Mode)

1

t_HFSE

FS Hold After SCLK

2.5

ns

(Externally Generated FS in Either

Transmit or Receive Mode)

1

t_SDRE

Receive Data Setup Before Receive 1.9

SCLK

2.0

2.5

1

t_HDRE

t_SCLKW

t_SCLK

Receive Data Hold After SCLK

SCLK Width

2.5

ns

(t_PCLK× 4) ÷ 2 – 0.5

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 0.5

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 0.5

t_PCLK× 4

SCLK Period

Switching Characteristics

2

t_DFSE

FS Delay After SCLK

(Internally Generated FS in Either

Transmit or Receive Mode)

10.25

7.8

10.25

9.6

10.25

9.8

ns

2

t_HOFSE

FS Hold After SCLK

(Internally Generated FS in Either

Transmit or Receive Mode)

2

t_DDTE

Transmit Data Delay After Transmit

SCLK

ns

2

t_HDTE

Transmit Data Hold After Transmit

SCLK

¹Referenced to sample edge.

²Referenced to drive edge.

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ADSP-21367/ADSP-21368/ADSP-21369

Table 29. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSI

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

7

ns

1

t_HFSI

FS Hold After SCLK

2.5

(Externally Generated FS in Either Transmit or Receive Mode)

1

t_SDRI

t_HDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

7

ns

1

2.5

Switching Characteristics

2

t_DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

4

ns

2

t_HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

FS Delay After SCLK (Internally Generated FS in Receive Mode)

FS Hold After SCLK (Internally Generated FS in Receive Mode)

Transmit Data Delay After SCLK

–1.0

2

t_DFSIR

9.75

3.25

2

t_HOFSIR

2

t_DDTI

2

t_HDTI

Transmit Data Hold After SCLK

–1.0

3

t_SCLKIW

Transmit or Receive SCLK Width

2 × t_PCLK– 1.5

2 × t_PCLK+ 1.5 ns

¹Referenced to the sample edge.

²Referenced to drive edge.

³Minimum SPORT divisor register value.

Table 30. Serial Ports—Enable and Three-State

Parameter

Switching Characteristics

Min

2

Max

Unit

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

10

1

t_DDTIN

–1

¹Referenced to drive edge.

Table 31. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit FS or External Receive

FS with MCE = 1, MFD = 0

7.75

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

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ADSP-21367/ADSP-21368/ADSP-21369

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 23. Serial Ports

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

t_DDTEN

t_DDTTE

DAI_P20–1

(DATA

CHANNEL A/B)

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

t_DDTIN

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 24. Enable and Three-State

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ADSP-21367/ADSP-21368/ADSP-21369

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

SAMPLE DRIVE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE DRIVE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

Figure 25. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

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ADSP-21367/ADSP-21368/ADSP-21369

Input Data Port

The timing requirements for the IDP are given in Table 32. IDP

signals SCLK, frame sync (FS), and SDATA are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Table 32. IDP

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

t_SIHFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SDATA Setup Before SCLK Rising Edge

SDATA Hold After SCLK Rising Edge

Clock Width

4

ns

1

2.5

1

t_SISD

t_SIHD

2.5

1

2.5

t_IDPCLKW

t_IDPCLK

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IDPCLK

t_IDPCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 26. IDP Master Timing

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

chapter of the ADSP-21368 SHARC Processor Hardware

Parallel Data Acquisition Port (PDAP)

Reference. Note that the 20 bits of external PDAP data can be

provided through the external port DATA31–12 pins or the

DAI pins.

The timing requirements for the PDAP are provided in

Table 33. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

Table 33. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge

PDAP_HOLD Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

Clock Width

2.5

ns

1

t_HPHOLD

2.5

1

t_PDSD

3.85

1

t_PDHD

2.5

t_PDCLKW

t_PDCLK

(t_PCLK× 4) ÷ 2 – 3

t_PCLK× 4

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 1

ns

¹Data Source pins are DATA31–12, or DAI pins. Source pins for SCLK and FS are: 1) DATA11–10 pins, 2) DAI pins.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20–1

(PDAP_CLK)

t_HPHOLD

t_SPHOLD

DAI_P20–1

(PDAP_HOLD)

t_PDHD

t_PDSD

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

t_PDHLDD

t_PDSTRB

DAI_P20–1

(PDAP_STROBE)

Figure 27. PDAP Timing

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ADSP-21367/ADSP-21368/ADSP-21369

Pulse-Width Modulation Generators

Table 34. PWM Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

t_PCLK– 2

(2¹⁶– 2) × t_PCLK

(2¹⁶– 1) × t_PCLK

ns

2 × t_PCLK– 1.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 28. PWM Timing

Sample Rate Converter—Serial Input Port

The SRC input signals SCLK, frame sync (FS), and SDATA are

routed from the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided in Table 35 are valid at the

DAI_P20–1 pins.

Table 35. SRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SDATA Setup Before SCLK Rising Edge

SDATA Hold After SCLK Rising Edge

Clock Width

4

ns

1

t_SRCHFS

5.5

4

1

t_SRCSD

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Rev. G

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ADSP-21367/ADSP-21368/ADSP-21369

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCSD

t_SRCHD

DAI_P20–1

(SDATA)

Figure 29. SRC Serial Input Port Timing

Rev. G

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September 2017

ADSP-21367/ADSP-21368/ADSP-21369

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the

drive edge.

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

Table 36. SRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

Clock Width

4

ns

1

t_SRCHFS

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After SCLK Falling Edge

Transmit Data Hold After SCLK Falling Edge

9.9

ns

1

t_SRCTDH

1

DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCTDD

t_SRCTDH

DAI_P20–1

(SDATA)

Figure 30. SRC Serial Output Port Timing

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ADSP-21367/ADSP-21368/ADSP-21369

S/PDIF Transmitter—Serial Input Waveforms

S/PDIF Transmitter

Figure 31 shows the right-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

Serial data input to the S/PDIF transmitter can be formatted as

left justified, I²S, or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the

transmitter.

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data is right-

justified to the next LRCLK transition.

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_RJD

DAI_P20–1

LSB

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

SDATA

Figure 31. Right-Justified Mode

Figure 32 shows the default I²S-justified mode. LRCLK is low

for the left channel and high for the right channel. Data is valid

on the rising edge of SCLK. The MSB is left-justified to an

LRCLK transition but with a single SCLK period delay.

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_I2SD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 32. I²S-Justified Mode

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ADSP-21367/ADSP-21368/ADSP-21369

Figure 33 shows the left-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition with no MSB delay.

DAI_P20–1

FS

LEFT/RIGHT CHANNEL

DAI_P20–1

SCLK

t_LJD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 33. Left-Justified Mode

S/PDIF Transmitter Input Data Timing

The timing requirements for the input port are given in

Table 37. Input signals SCLK, frame sync (FS), and SDATA are

routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 37. S/PDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

t_SIHFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SDATA Setup Before SCLK Rising Edge

SDATA Hold After SCLK Rising Edge

Clock Width

3

ns

1

3

1

t_SISD

t_SIHD

3

1

3

t_SISCLKW

t_SISCLK

t_SITXCLKW

t_SITXCLK

36

80

9

Clock Period

Transmit Clock Width

Transmit Clock Period

20

1

DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Rev. G

|

Page 45 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

SAMPLE EDGE

t_SITXCLKW

t_SITXCLK

DAI_P20–1

(TxCLK)

t_SISCLK

t_SISCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 34. S/PDIF Transmitter Input Timing

Rev. G

|

Page 46 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter has an oversampling clock. This TxCLK

input is divided down to generate the biphase clock.

Table 38. Oversampling Clock (TxCLK) Switching Characteristics

Parameter

Min

Max

Unit

MHz

kHz

TxCLK Frequency for TxCLK = 384 × FS

TxCLK Frequency for TxCLK = 256 × FS

Frame Rate (FS)

Oversampling Ratio × FS <= 1/t_SITXCLK

49.2

192.0

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 39. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

LRCLK Delay After SCLK

LRCLK Hold After SCLK

5

ns

t_HOFSI

t_DDTI

t_HDTI

–2

Transmit Data Delay After SCLK

Transmit Data Hold After SCLK

Transmit SCLK Width

–2

40

1

t_SCLKIW

¹SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20–1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20–1

(FS)

t_DDTI

t_HDTI

DAI_P20–1

(DATA CHANNEL

A/B)

Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. G

|

Page 47 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

SPI Interface—Master

The processors contain two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DPI. The

timing provided in Table 40 and Table 41 applies

to both.

Table 40. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SPICLK Edge (Data Input Setup Time)

8.2

2

ns

SPICLK Last Sampling Edge to Data Input Not Valid

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_PCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

DPI Pin (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to DPI Pin (SPI Device Select) High

Sequential Transfer Delay

2.5

4 × t_PCLK– 2

4 × t_PCLK– 1

t_SPITDM

DPI

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

(INPUT)

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHASE = 0

MISO

(INPUT)

Figure 36. SPI Master Timing

Rev. G

|

Page 48 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

SPI Interface—Slave

Table 41. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

t_HDS

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

2 × t_PCLK

2

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

0

6.8

8

ns

1

SPIDS Assertion to Data Out Active (SPI2)

t_DSDHI

SPIDS Deassertion to Data High Impedance

6.8

8.6

9.5

1

t_DSDHI

SPIDS Deassertion to Data High Impedance (SPI2)

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

t_DDSPIDS

t_HDSPIDS

t_DSOV

2 × t_PCLK

5 × t_PCLK

¹The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral

Interface Port” chapter.

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0,

CP = 1)

(INPUT)

t_SDSCO

t_DSOE

t_DSDHI

t_HDSPIDS

t_DDSPIDS

MISO

(OUTPUT)

t_SSPIDSt_HSPIDS

CPHASE = 1

MOSI

(INPUT)

t_HDSPIDS

t_DSDHI

MISO

(OUTPUT)

t_DSOV

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

Figure 37. SPI Slave Timing

Rev. G

|

Page 49 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

JTAG Test Access Port and Emulation

Table 42. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_CK

5

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

6

1

t_SSYS

t_HSYS

7

1

18

4t_CK

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

7

ns

2

t_DSYS

t_CK÷ 2 + 7

¹System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

²System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 38. IEEE 1149.1 JTAG Test Access Port

Rev. G

|

Page 50 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

OUTPUT DRIVE CURRENTS

TEST CONDITIONS

Figure 39 shows typical I-V characteristics for the output driv-

ers and Figure 40 shows typical I-V characteristics for the

SDCLK output drivers. The curves represent the current drive

capability of the output drivers as a function of output voltage.

The ac signal specifications (timing parameters) appear in

Table 14 through Table 42. These include output disable time,

output enable time, and capacitive loading. The timing specifi-

cations for the SHARC apply for the voltage reference levels in

Figure 41.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 41. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

40

V_OH

30

3.3V, 25°C

20

3.47V, -45°C

10

0

3.11V, 125°C

INPUT

OR

3.11V, 105°C

1.5V

OUTPUT

-

10

20

30

40

3.11V, 125°C

3.11V, 105°C

-

3.3V, 25°C

Figure 41. Voltage Reference Levels for AC Measurements

V_OL

-

3.47V,

-

45°C

CAPACITIVE LOADING

-

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all pins (see Figure 42). Figure 47 and

Figure 48 show graphically how output delays and holds vary

with load capacitance. The graphs of Figure 43 through

Figure 48 may not be linear outside the ranges shown for Typi-

cal Output Delay vs. Load Capacitance and Typical Output Rise

Time (20% to 80%, V = Min) vs. Load Capacitance.

SWEEP (V_DDEXT) VOLTAGE (V)

Figure 39. Typical Drive at Junction Temperature

75

60

V

OH

3.47V,

-

45°C

45

30

15

3.3V, 25°C

TESTER PIN ELECTRONICS

3.13V, 125°C

3.13V, 105°C

1.5V

0

15

30

45

60

T1

DUT

-

OUTPUT

45Ω

3.13V, 125°C

3.13V, 105°C

70Ω

ZO = 50Ω (impedance)

TD = 4.04 1.18 ns

50Ω

3.3V, 2 5°C

3.47V, 45°C

0.5pF

75

90

4pF

2pF

-

V

OL

400Ω

-105

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SWEEP (V

) VOLTAGE (V)

D DEXT

NOTES:

Figure 40. SDCLK1–0 Drive at Junction Temperature

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 42. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Rev. G

|

Page 51 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

12

10

8

RISE

10

FALL

y = 0.049x + 1.5105

y = 0.0372x + 0.228

8

6

4

2

6

FALL

y = 0.0482x + 1.4604

4

y = 0.0277x + 0.369

2

0

50

100

150

200

250

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 43. Typical Output Rise/Fall Time

(20% to 80%, V_DDEXT= Min)

Figure 45. SDCLK Typical Output Rise/Fall Time

(20% to 80%, V_DDEXT= Min)

12

10

8

RISE

y = 0.0467x + 1.6323

y = 0.0364x + 0.197

FALL

8

6

FALL

6

4

y = 0.045x + 1.524

4

y = 0.0259x + 0.311

2

0

50

100

150

200

250

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 44. Typical Output Rise/Fall Time

(20% to 80%, V_DDEXT= Max)

Figure 46. SDCLK Typical Output Rise/Fall Time

(20% to 80%, V_DDEXT= Max)

Rev. G

|

Page 52 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

To determine the junction temperature of the device while on

the application PCB, use:

10

8

T_J= T_TOP+ _JT P_D

6

where:

y = 0.0488x

-

1.5923

T_J= junction temperature (C)

4

T

_TOP= case temperature (C) measured at the top center of the

2

0

package

_JT= junction-to-top (of package) characterization parameter is

the typical value from Table 43 and Table 44.

-

2

4

P_D= power dissipation (see Engineer-to-Engineer Note EE-299)

Values of _JAare provided for package comparison and PCB

design considerations. _JAcan be used for a first-order approxi-

mation of T_Jby the equation:

-

0

50

100

150

200

LOAD CAPACITANCE (pF)

T_J= T_A+ _JA P_D

Figure 47. Typical Output Delay or Hold vs. Load Capacitance

(at Junction Temperature)

where:

T_A= ambient temperature (C)

8

Values of _JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

This is only applicable when a heat sink is used.

6

y = 0.0256x

-0.021

Values of _JBare provided for package comparison and PCB

design considerations. The thermal characteristics values pro-

vided in Table 43 and Table 44 are modeled values @ 2 W.

4

2

0

2

Table 43. Thermal Characteristics for 256-Ball BGA_ED

Parameter

_JA

_JMA

_JC

_JB

_JT

_JMT

Condition

Typical

12.5

10.6

9.9

Unit

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

C/W

-

0

50

100

LOAD CAPACITANCE (pF)

150

200

0.7

5.3

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.3

Figure 48. SDCLK Typical Output Delay or Hold vs. Load Capacitance

(at Junction Temperature)

0.3

THERMAL CHARACTERISTICS

Table 44. Thermal Characteristics for 208-Lead LQFP EPAD

(With Exposed Pad Soldered to PCB)

The ADSP-21367/ADSP-21368/ADSP-21369 processors are

rated for performance over the temperature range specified in

Operating Conditions.

Table 43 and Table 44 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board design

complies with JEDEC standards JESD51-9 (BGA_ED) and

JESD51-8 (LQFP_EP). The junction-to-case measurement com-

plies with MIL-STD-883. All measurements use a 2S2P JEDEC

test board.

Parameter

_JA

Condition

Typical

17.1

14.7

14.0

9.6

Unit

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

C/W

_JMA

_JC

_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.23

0.39

0.45

11.5

11.2

11.0

_JMT

_JB

_JMB

The LQFP-EP package requires thermal trace squares and ther-

mal vias, to an embedded ground plane, in the PCB. Refer to

JEDEC standard JESD51-5 for more information.

Rev. G

|

Page 53 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

256-BALL BGA_ED PINOUT

The following table shows the ADSP-2136x’s pin names and

their default function after reset (in parentheses).

Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number)

Ball No. Signal

Ball No.

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

F01

F02

F03

F04

F17

F18

F19

F20

K01

K02

K03

K04

K17

K18

K19

K20

Signal

DAI_P05 (SD1A)

SDCLK1¹

Ball No.

C01

Signal

DAI_P09 (SD2A)

DAI_P07 (SCLK1)

GND

Ball No.

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

H01

H02

H03

H04

H17

H18

H19

H20

M01

M02

M03

M04

M17

M18

M19

M20

Signal

DAI_P10 (SD2B)

DAI_P06 (SD1B)

GND

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

E01

E02

E03

E04

E17

E18

E19

E20

J01

NC

TDI

C02

TMS

TRST

C03

CLK_CFG0

CLK_CFG1

EMU

TCK

C04

V_DDEXT

BOOT_CFG0

BOOT_CFG1

TDO

C05

GND

C06

GND

V_DDEXT

DAI_P04 (SFS0)

DAI_P01 (SD0A)

DPI_P14 (TIMER1)

DPI_P12 (TWI_CLK)

DPI_P10 (UART0RX)

DPI_P09 (UART0TX)

DPI_P07 (SPIFLG2)

DPI_P06 (SPIFLG1)

DPI_P03 (SPICLK)

DPI_P02 (SPIMISO)

RESETOUT

DATA31

C07

V_DDINT

DAI_P03 (SCLK0)

DAI_P02 (SD0B)

DPI_P13 (TIMER0)

C08

GND

C09

GND

V_DDEXT

C10

V_DDINT

DPI_P11 (TWI_DATA) C11

GND

DPI_P08 (SPIFLG3)

DPI_P05 (SPIFLG0)

DPI_P04 (SPIDS)

DPI_P01 (SPIMOSI)

RESET

C12

C13

C14

C15

C16

C17

C18

C19

C20

G01

G02

G03

G04

G17

G18

G19

G20

L01

L02

L03

L04

L17

L18

L19

L20

GND

V_DDEXT

V_DDINT

GND

V_DDEXT

V_DDINT

GND

DATA30

V_DDINT

V_DDEXT

DATA29

V_DDINT

GND

NC

DATA28

DATA27

NC/RPBA²

DAI_P15 (SD4A)

DAI_P13 (SCLK3)

GND

DATA26

DATA24

DAI_P17 (SD5A)

DAI_P16 (SD4B)

V_DDINT

NC

DAI_P11 (SD3A)

DAI_P08 (SFS1)

V_DDINT

DAI_P14 (SFS3)

DAI_P12 (SD3B)

GND

V_DDINT

GND

V_DDEXT

V_DDINT

GND

V_DDEXT

V_DDINT

V_DDEXT

GND

GND/ID2²

V_DDINT

GND

DATA25

DATA22

DATA20

FLAG2

FLAG1

V_DDINT

DATA19

DATA18

ACK

DATA23

DATA21

DAI_P19 (SCLK5)

DAI_P18 (SD5B)

GND

FLAG0

J02

DAI_P20 (SFS5)

GND

FLAG3

GND

J03

J04

GND

V_DDEXT

V_DDINT

GND

J17

GND

V_DDINT

V_DDEXT

J18

GND

GND/ID1²

V_DDINT

GND/ID0²

V_DDINT

GND

J19

DATA15

DATA14

DATA12

DATA13

J20

DATA17

DATA16

Rev. G

|

Page 54 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal

Ball No.

P01

P02

P03

P04

P17

P18

P19

P20

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

Signal

SDA10

WR

Ball No.

R01

Signal

SDWE

Ball No.

T01

T02

T03

T04

T17

T18

T19

T20

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Signal

SDCKE

SDCAS

GND

N01

N02

N03

N04

N17

N18

N19

N20

U01

U02

U03

U04

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

RD

SDCLK0

GND

V_DDEXT

GND

DATA11

DATA10

MS0

R02

SDRAS

GND

V_DDINT

R03

V_DDINT

R04

GND

V_DDEXT

V_DDINT

R17

V_DDEXT

GND

V_DDINT

R18

GND

DATA8

DATA9

ADDR22

ADDR23

V_DDINT

R19

DATA6

DATA7

GND

DATA5

DATA4

GND

R20

W01

W02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

MS1

ADDR21

ADDR19

ADDR20

ADDR17

ADDR16

ADDR15

ADDR14

A_VDD

NC

V_DDINT

NC

GND

V_DDEXT

GND

V_DDEXT

V_DDINT

GND

ADDR18

NC/BR1²

NC/BR2²

XTAL

GND

V_DDINT

CLKIN

NC

V_DDEXT

GND

V_DDEXT

V_DDINT

GND

A_VSS

NC

GND

ADDR13

ADDR12

ADDR10

ADDR8

ADDR5

ADDR4

ADDR1

ADDR2

ADDR0

NC

NC/BR3²

NC/BR4²

ADDR11

ADDR9

ADDR7

ADDR6

ADDR3

GND

V_DDINT

V_DDEXT

V_DDINT

V_DDEXT

GND

V_DDINT

V_DDEXT

V_DDINT

GND

V_DDINT

GND

DATA0

DATA2

DATA1

GND

DATA3

NC

¹The SDCLK1 signal is only available on the FCBGA package. SDCLK1 is not available on the LQFP_EP package.

²Applies to ADSP-21368 models only.

Rev. G

|

Page 55 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Figure 49 shows the bottom view of the BGA_ED ball configu-

ration. Figure 50 shows the top view of the BGA_ED ball

configuration.

2

4

6

8

10

12

14

16

18

20

18

16

14

12

10

8

6

4

2

1

3

5

7

9

11

13

15

17

19

5

3

1

19

17

15

13

11

9

7

A

B

A

B

C

D

E

F

G

H

J

C

D

E

F

G

H

J

TOP

VIEW

K

L

BOTTOM

VIEW

K

L

M

N

P

R

T

U

V

W

Y

M

N

P

R

T

U

V

W

Y

KEY

A_VDD

A_VSS

V_DDINT

I/O SIGNALS

V_DDEXT

GND

A

VSS

V

VDD

DDINT

DDEXT

GND

NO CONNECT

I/O SIGNALS

NO CONNECT

Figure 49. 256-Ball BGA_ED Ball Configuration (Bottom View)

Figure 50. 256-Ball BGA_ED Ball Configuration (Top View)

Rev. G

|

Page 56 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

208-LEAD LQFP_EP PINOUT

The following table shows the ADSP-2136x’s pin names and

their default function after reset (in parentheses).

Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number)

Lead

No.

1

Lead

No.

Lead

No.

85

Lead

No.

Lead

No.

Signal

V_DDINT

Signal

V_DDINT

Signal

V_DDEXT

Signal

V_DDINT

Signal

CLK_CFG0

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

2

DATA28

DATA27

GND

DATA4

DATA5

DATA2

DATA3

DATA0

DATA1

V_DDEXT

86

GND

BOOT_CFG0

CLK_CFG1

3

87

V_DDINT

V_DDEXT

4

88

ADDR14

GND

DAI_P19 (SCLK5)

DAI_P18 (SD5B)

DAI_P17 (SD5A)

DAI_P16 (SD4B)

DAI_P15 (SD4A)

DAI_P14 (SFS3)

DAI_P13 (SCLK3)

DAI_P12 (SD3B)

V_DDINT

EMU

5

V_DDEXT

89

BOOT_CFG1

TDO

6

DATA26

DATA25

DATA24

DATA23

GND

90

V_DDEXT

7

91

ADDR15

ADDR16

ADDR17

ADDR18

GND

DAI_P04 (SFS0)

DAI_P02 (SD0B)

DAI_P03 (SCLK0)

DAI_P01 (SD0A)

V_DDEXT

8

92

9

GND

93

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

V_DDINT

94

V_DDINT

95

DATA22

DATA21

DATA20

V_DDEXT

GND

96

V_DDEXT

GND

V_DDEXT

97

ADDR19

ADDR20

ADDR21

ADDR23

ADDR22

MS1

V_DDEXT

V_DDINT

ADDR0

ADDR2

ADDR1

ADDR4

ADDR3

ADDR5

GND

98

GND

99

V_DDINT

DPI_P14 (TIMER1)

DPI_P13 (TIMER0)

DPI_P12 (TWI_CLK)

DPI_P11 (TWI_DATA)

DPI_P10 (UART0RX)

DPI_P09 (UART0TX)

DPI_P08 (SPIFLG3)

DPI_P07 (SPIFLG2)

V_DDEXT

GND

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

GND

DATA19

DATA18

V_DDINT

DAI_P11 (SD3A)

DAI_P10 (SD2B)

DAI_P08 (SFS1)

DAI_P09 (SD2A)

DAI_P06 (SD1B)

DAI_P07 (SCLK1)

DAI_P05 (SD1A)

V_DDEXT

MS0

GND

V_DDINT

DATA17

V_DDINT

GND

V_DDEXT

V_DDINT

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

GND

SDCAS

SDRAS

SDCKE

SDWE

WR

GND

V_DDINT

DATA16

DATA15

DATA14

DATA13

DATA12

V_DDEXT

V_DDINT

GND

DPI_P06 (SPIFLG1)

DPI_P05 (SPIFLG0)

DPI_P04 (SPIDS)

DPI_P03 (SPICLK)

DPI_P01 (SPIMOSI)

DPI_P02 (SPIMISO)

RESETOUT

V_DDINT

SDA10

GND

V_DDINT

GND

V_DDEXT

V_DDINT

GND

V_DDEXT

SDCLK0

GND

V_DDINT

ADDR11

ADDR12

ADDR13

GND

V_DDINT

RESET

DATA11

DATA10

DATA9

DATA8

DATA7

RD

V_DDINT

V_DDEXT

ACK

V_DDINT

GND

V_DDINT

FLAG3

FLAG2

FLAG1

TDI

DATA30

A_VSS

TRST

DATA31

A_VDD

TCK

DATA29

Rev. G

|

Page 57 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued)

Lead

No.

40

41

42

Lead

No.

82

83

84

Lead

No.

124

125

126

Lead

No.

166

Lead

No.

208

Signal

DATA6

V_DDEXT

Signal

GND

Signal

FLAG0

Signal

GND

V_DDINT

Signal

V_DDINT

CLKIN

XTAL

DAI_P20 (SFS5) 167

GND 168

GND

TMS

Rev. G

|

Page 58 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

PACKAGE DIMENSIONS

The ADSP-21367/ADSP-21368/ADSP-21369 processors are

available in 256-ball RoHS compliant and leaded BGA_ED, and

208-lead RoHS compliant LQFP_EP packages.

30.20

30.00 SQ

29.80

25.50

REF

28.10

28.00 SQ

27.90

1.60 MAX

0.75

0.60

8.712

REF

0.45

208

157

156

157

156

208

1

1.00 REF

PIN 1

SEATING

PLANE

8.890

REF

TOP VIEW

(PINS DOWN)

EXPOSED

PAD

1.45

1.40

1.35

0.20

0.15

0.09

0.15

0.10

0.05

7°

3.5°

0°

BOTTOM VIEW

(PINS UP)

0.08

COPLANARITY

105

104

105

104

52

53

VIEW A

0.27

0.22

0.17

VIEW A

ROTATED 90° CCW

0.50

BSC

LEAD PITCH

COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD

NOTE:

THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS.

THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZE

AS THE EXPOSED PAD.THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB

WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.

Figure 51. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-208-1)

Dimensions shown in millimeters

Rev. G

|

Page 59 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

27.10

27.00 SQ

26.90

A1 BALL

PAD CORNER

20

18

16

14

12

10

8

6

4

2

3 1

19

17

15

13

11

9

7

5

A

C

E

G

J

B

D

F

H

K

M

P

T

21.00 REF

SQ

24.13 REF

SQ

L

N

R

U

1.27

BSC

V

W

Y

TOP VIEW

BOTTOM VIEW

1.30 REF

1.44 REF

19.00

DETAIL A

2.84

2.65

2.46

0.75

0.65

0.55

SIDE VIEW

0.59 REF

DETAIL A

0.91

0.76

0.61

SEATING

PLANE

COPLANARITY

0.20

BALL DIAMETER

Figure 52. 256-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

(BP-256-2)

Dimension shown in millimeters

SURFACE-MOUNT DESIGN

Table 47 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Table 47. BGA_ED Data for Use with Surface-Mount Design

Package

Ball Attach Type

Solder Mask Opening

Ball Pad Size

256-Lead Ball Grid Array BGA_ED

(BP-256-2)

Solder Mask Defined (SMD)

0.63 mm

0.73 mm

Rev. G

|

Page 60 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

AUTOMOTIVE PRODUCTS

An ADSP-21369 model is available for automotive applications

with controlled manufacturing. Note that this special model

may have specifications that differ from the general release

models.

The automotive grade product shown in Table 48 is available for

use in automotive applications. Contact your local ADI account

representative or authorized ADI product distributor for spe-

cific product ordering information. Note that all automotive

products are RoHS compliant.

Table 48. Automotive Products

Temperature

Range¹

Instruction

Rate

On-Chip

SRAM

Package

Option

Model

ROM

Package Description

AD21369WBSWZ1xx

–40°C to +85°C

266 MHz

2M bit

6M bit

208-Lead LQFP_EP

SW-208-1

¹Referenced temperature is ambient temperature.

ORDERING GUIDE

Temperature

Instruction On-Chip

Package

Option

Model

Notes

Range¹

Rate

SRAM

2M bit

ROM

Package Description

256-Ball BGA_ED

208-Lead LQFP_EP

256-Ball BGA_ED

208-Lead LQFP_EP

2, 3

ADSP-21367KBPZ-2A

ADSP-21367KBPZ-3A

ADSP-21367KSWZ-1A

ADSP-21367KSWZ-2A

ADSP-21368KBPZ-2A

ADSP-21368KBPZ-3A

ADSP-21369KBPZ-2A

ADSP-21369BBP-2A

ADSP-21369BBPZ-2A

ADSP-21369KBPZ-3A

ADSP-21369KSWZ-1A

ADSP-21369KSWZ-2A

ADSP-21369KSWZ-4A

ADSP-21369KSWZ-5A

ADSP-21369KSWZ-6A

ADSP-21369BSWZ-1A

ADSP-21369BSWZ-2A

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

333 MHz

400 MHz

266 MHz

333 MHz

400 MHz

333 MHz

400 MHz

266 MHz

333 MHz

350 MHz

366 MHz

400 MHz

266 MHz

333 MHz

6M bit

BP-256-2

SW-208-1

BP-256-2

SW-208-1

2, 3

3

2

3

¹Referenced temperature is ambient temperature.

²Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC.

³Z = RoHS Compliant Part.

Rev. G

|

Page 61 of 62

|

September 2017

ADSP-21367/ADSP-21368/ADSP-21369

registered trademarks are the property of their respective owners.

D05267-0-9/17(G)

Rev. G

|

Page 62 of 62

|

September 2017


型号：	ADSP-21369KSWZ-6A
厂家：	ADI
描述：	High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications 时钟外围集成电路
文件：	总62页 (文件大小：1222K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21369KSWZ-6A [ADI]

相关型号：

ADSP-21369KSZ-1A

ADSP-21369KSZ-ENG

ADSP-21371

ADSP-21371BSWZ-2B

ADSP-21371BSWZ-2B2

ADSP-21371KSWZ-2A

ADSP-21371KSWZ-2A2

ADSP-21371KSWZ-2B

ADSP-21371KSWZ-2B2

ADSP-21371KSZ-ENG

ADSP-21371_07

ADSP-21371_09