ADSP-21371KSWZ-2A_技术文档

SHARC Processor

ADSP-21371/ADSP-21375

SUMMARY

DEDICATED AUDIO COMPONENTS

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory, ADSP-21371—1M bits of on-chip SRAM

and 4M bits of on-chip mask-programmable ROM

On-chip memory, ADSP-21375—0.5M bits of on-chip

SRAM and 2M bits of on-chip mask-programmable ROM

ADSP-21371—S/PDIF-compatible digital audio

receiver/transmitter

ADSP-21371—8 dual data line serial ports that operate at up

to 33 Mbps on each data line — each has a clock, frame

sync, and two data lines that can be configured as either a

receiver or transmitter pair

16 PWM outputs configured as four groups of four outputs

ROM-based security features include

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Code compatible with all other members of the SHARC family

The ADSP-21371/ADSP-21375 processors are available with a

200/266 MHz core instruction rate with unique audiocen-

tric peripherals such as the digital applications interface,

S/PDIF transceiver, serial ports, precision clock generators,

and more. For complete ordering information, see Order-

ing Guide on Page 56.

Available in a 208-lead LQFP_EP package

Internal Memory

SIMD Core

Block 0

RAM/ROM

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

Instruction

Cache

5 stage

Sequencer

B2D

64-BIT

B0D

64-BIT

B3D

64-BIT

B1D

64-BIT

S

DAG1/2

PEx

Timer

PEy

DMD 64-BIT

PMD 64-BIT

DMD 64-BIT

Core Bus

Cross Bar

Internal Memory I/F

PMD 64-BIT

IODO 32-BIT

FLAGx/IRQx/

TMREXP

EPD BUS 48-BIT

JTAG

PERIPHERAL BUS

32-BIT

IOD1

32-BIT

IOD0 BUS

MTM/

DTCP

PERIPHERAL BUS

EP

IDP/

PDAP

7-0

S/PDIF

Tx/Rx

CORE PCG

FLAGS

TIMER

PCG

SPORT

CORE PWM

AMI

TWI

SPI/B

UART

SDRAM

C

-

D

1-0

A

-

D

7-0

FLAGS

3-0

DPI Routing/Pins

External Port Pin MUX

DAI Routing/Pins

External

Port

DPI Peripherals

DAI Peripherals

Peripherals

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. D Document Feedback

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-21371/ADSP-21375

TABLE OF CONTENTS

Summary ............................................................... 1

Dedicated Audio Components ................................. 1

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 6

I/O Processor Features ......................................... 10

System Design .................................................... 10

Development Tools ............................................. 11

Additional Information ........................................ 12

Related Signal Chains .......................................... 12

Pin Function Descriptions ....................................... 13

ADSP-21371/ADSP-21375 Specifications .................... 16

Operating Conditions .......................................... 16

Electrical Characteristics ....................................... 17

Package Information ............................................ 18

Maximum Power Dissipation ................................. 18

Absolute Maximum Ratings ................................... 18

ESD Sensitivity ................................................... 18

Timing Specifications ........................................... 18

Output Drive Currents ......................................... 49

Test Conditions .................................................. 49

Capacitive Loading .............................................. 49

Thermal Characteristics ........................................ 50

208-Lead LQFP_EP Pinout ....................................... 51

Package Dimensions ............................................... 55

Automotive Products .............................................. 56

Ordering Guide ..................................................... 56

REVISION HISTORY

4/13—Rev. C to Rev. D

Added 1.0 V, 200 MHz specifications to the following timing

specifications.

Corrected Extended Precision Normal or Instruction Word

(48 bits) ADSP-21375 Internal Memory Space .................7

Clock Input ............................................................21

Precision Clock Generator (Direct Pin Routing) .............26

SDRAM Interface Timing ..........................................28

Memory Read—Bus Master .......................................29

Memory Write—Bus Master ......................................31

Serial Ports ............................................................33

Input Data Port (IDP) ..............................................38

S/PDIF Transmitter Input Data Timing ........................42

S/PDIF Receiver ......................................................43

SPI Interface—Slave .................................................45

Updated Development Tools ..................................... 11

Added section Related Signal Chains ...........................12

Revised MS_1-0pin description in

Pin Function Descriptions ........................................ 13

Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in

Pin Function Descriptions ........................................ 13

Corrected T_JUNCTIONspecifications in

Operating Conditions .............................................. 16

Added footnote 3 to Table 25 in

Memory Read—Bus Master ....................................... 29

Updated Serial Ports timing parameter data in Serial Ports—

External Clock ....................................................... 33

Updated Serial Ports timing parameter data in Serial Ports—

Internal Clock ........................................................ 34

Changed Max values in Table 33 in Pulse-Width Modulation

Generators (PWM) ................................................. 40

Updated timing parameters in Table 37 and in Figure 31 in

SPI Interface—Master .............................................. 44

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ADSP-21371/ADSP-21375

GENERAL DESCRIPTION

The ADSP-21371/ADSP-21375 SHARC^®processors are mem-

bers of the SIMD SHARC family of DSPs that feature Analog

Devices’ Super Harvard Architecture. The processors are source

code compatible with the ADSP-2126x, ADSP-2136x, and

ADSP-2116x DSPs, as well as with first generation ADSP-2106x

SHARC processors in SISD (single-instruction, single-data)

mode. The processors are 32-bit/40-bit floating-point proces-

sors optimized for high performance automotive audio

applications with their large on-chip SRAM and mask-pro-

grammable ROM, multiple internal buses to eliminate I/O

bottlenecks, and an innovative digital applications interface

(DAI).

Table 2. ADSP-21371/ADSP-21375 Features (Continued)

Feature

ADSP-21371

ADSP-21375

Yes

Digital Peripheral Interface

(DPI)

S/PDIF Transceiver

Yes

No

SPI

2

TWI

Yes

208-Lead LQFP_EP

Package

As shown in the functional block diagram on Page 1, the pro-

cessors use two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. Fabricated in a state-of-the-art, high

speed, CMOS process, the processors achieve an instruction

cycle time of 3.75 ns at 266 MHz. With its SIMD computational

hardware, the processors can perform 1.596 GFLOPS running

at 266 MHz.

The diagram on Page 1 shows the two clock domains that make

up the ADSP-2137x processors. The core clock domain contains

the following features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

Table 1 shows performance benchmarks for these devices.

Table 2 shows the features of the individual product offerings.

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

Table 1. Processor Benchmarks (at 266 MHz)

• One periodic interval timer with pinout

Speed

• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,

ADSP-21375)

Benchmark Algorithm

(at 266 MHz)

1024 Point Complex FFT (Radix 4, With Reversal) 34.5 s

• On-chip mask-programmable ROM (4M bit, ADSP-21371;

2M bit, ADSP-21375)

FIR Filter (per Tap)¹

IIR Filter (per Biquad)¹

1.88 ns

7.5 ns

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allow flexible exception handling.

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

16.91 ns

30.07 ns

The diagram on Page 1 also shows the peripheral clock domains

(also known as the I/O processor) and contains the following

features:

Divide (y/x)

13.1 ns

20.4 ns

Inverse Square Root

¹Assumes two files in multichannel SIMD mode

• IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

Table 2. ADSP-21371/ADSP-21375 Features

• Peripheral and external port bus for core connection

• Digital applications interface that includes four precision

clock generators (PCG), an S/PDIF-compatible digital

audio receiver/transmitter, an input data port (IDP), eight

serial ports, eight serial interfaces, a 20-bit parallel input

port (PDAP), and a flexible signal routing unit (DAI SRU).

Feature

ADSP-21371

ADSP-21375

Frequency

266 MHz

(3.75 ns)

266 MHz

(3.75 ns)

RAM

1M bit

4M bits

Yes

0.5M bit

2M bits

No

• Digital peripheral interface that includes two timers, one

UART, two serial peripheral interfaces (SPI), a 2-wire

interface (TWI), and a flexible signal routing unit

(DPI SRU).

ROM

Pulse-Width Modulation

Serial Ports

8

4

• External port with AMI and SDRAM controller

• Four units for PWM control

UART

1

Digital Application

Interface (DAI)

Yes

• One MTM for internal to internal memory transfers

Rev. D

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ADSP-21371/ADSP-21375

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21371/ADSP-21375 processors are code compatible

at the assembly level with the ADSP-2136x, ADSP-2126x,

ADSP-21160x, and ADSP-21161N, and with the first generation

ADSP-2106x SHARC processors. The ADSP-21371/

ADSP-21375 processors share architectural features with the

ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC

processors, as shown in Figure 2 and detailed in the following

sections.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

SIMD Computational Engine

The processors contain two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and

PEY, and each contains an ALU, multiplier, shifter, and register

file. PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

S

JTAG

FLAG TIMER INTERRUPT CACHE

SIMD Core

PM ADDRESS 24

DMD/PMD 64

5 STAGE

PROGRAM SEQUENCER

PM DATA 48

DAG2

16x32

DAG1

16x32

PM ADDRESS 32

SYSTEM

I/F

DM ADDRESS 32

PM DATA 64

USTAT

4x32-BIT

PX

64-BIT

DM DATA 64

DATA

SWAP

RF

Rx/Fx

PEx

RF

Sx/SFx

PEy

ALU

SHIFTER

MULTIPLIER

ALU

SHIFTER

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MRF

80-BIT

MSF

80-BIT

ASTATy

STYKy

ASTATx

STYKx

Figure 2. SHARC Core Block Diagram

Rev. D

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ADSP-21371/ADSP-21375

processing, and are commonly used in digital filters and Fourier

transforms. The two DAGs contain sufficient registers to allow

the creation of up to 32 circular buffers (16 primary register sets,

16 secondary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) register files,

combined with the SHARC’s enhanced Harvard architecture,

allow unconstrained data flow between computation units and

internal memory. The registers in PEX are referred to as

R0–R15 and in PEY as S0–S15.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the proces-

sors can conditionally execute a multiply, an add, and a subtract

in both processing elements while branching and fetching up to

four 32-bit values from memory—all in a single instruction.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result register all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

On-Chip Memory

The ADSP-21371 processor contains 1 megabit of internal RAM

and four megabits of internal mask-programmable ROM (see

Table 3 on Page 6) and the ADSP-21375 processor contains 0.5

megabits of internal RAM and two megabits of internal mask-

programmable ROM (see Table 4 on Page 7). Each block can be

configured for different combinations of code and data storage.

Each memory block supports single-cycle, independent accesses

by the core processor and I/O processor. The processor’s mem-

ory architecture, in combination with its separate on-chip buses,

allow two data transfers from the core and one from the I/O

processor, in a single cycle.

Universal Registers

Universal registers can be used for general purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all system registers (control/status) of

the core.

The data bus exchange register PX permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM data bus. These reg-

isters contain hardware to handle the data width difference.

The ADSP-21371 processor’s SRAM can be configured as a

maximum of 32k words of 32-bit data, 64k words of 16-bit data,

21.3k words of 48-bit instructions (or 40-bit data), or combina-

tions of different word sizes up to 1 megabit. All of the memory

can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-

bit floating-point storage format is supported that effectively

doubles the amount of data that may be stored on-chip. Conver-

sion between the 32-bit floating-point and 16-bit floating-point

formats is performed in a single instruction. While each mem-

ory block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Timer

The processors contain a core timer that can generate periodic

software interrupts. The core timer can be configured to use

FLAG3 as a timer expired signal.

Single-Cycle Fetch of an Instruction and Four Operands

The processors feature an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With the processor’s separate program and data

memory buses and on-chip instruction cache, the processor can

simultaneously fetch four operands (two over each data bus)

and one instruction (from the cache), all in a single cycle.

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in

the cache.

Instruction Cache

The processors include an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

On-Chip Memory Bandwidth

The internal memory architecture allows four accesses at the

same time to any of the four blocks, assuming no block con-

flicts. The total bandwidth is gained with DMD and PMD buses

(2  64-bits, core CLK) and the IOD0/1 buses (2  32-bit,

PCLK).

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

ROM-Based Security

The processors have a ROM security feature that provides hard-

ware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

The processors’s two data address generators (DAGs) are used

for indirect addressing and implementing circular data buffers

in hardware. Circular buffers allow efficient programming of

delay lines and other data structures required in digital signal

Rev. D

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ADSP-21371/ADSP-21375

Table 3. ADSP-21371 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

Instruction Word (48 bits)

Normal Word (32 bits)

Short Word (16 bits)

BLOCK 0 ROM

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 BFFF

0x0008 AAAA–0x0008 FFFF

0x0009 0000–0x0009 7FFF

0x0012 0000–0x0012 FFFF

BLOCK 0 RAM

0x0004 C000–0x0004 CFFF

0x0009 0000–0x0009 1554

0x0009 8000–0x0009 9FFF

0x0013 0000–0x0013 3FFF

Reserved

0x0004 D000–0x0004 FFFF

0x0009 1555–0x0009 FFFF

0x0009 A000–0x0009 FFFF

0x0013 4000–0x0013 FFFF

BLOCK 1 ROM

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000A FFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 BFFF

0x000A AAAA–0x000A FFFF

0x000B 0000–0x000B 7FFF

0x0016 0000–0x0016 FFFF

BLOCK 1 RAM

0x0005 C000–0x0005 CFFF

0x000B 0000–0x000B 1554

0x000B 8000–0x000B 9FFF

0x0017 0000–0x0017 3FFF

Reserved

0x0005 D000–0x0005 FFFF

0x000B 1555–0x000B FFFF

0x000B A000–0x000B FFFF

0x0017 4000–0x0017 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 0FFF

0x000C 0000–0x000C 1554

0x000C 0000–0x000C 1FFF

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000–0x0006 FFFF

0x000C 1555–0x000D FFFF

0x000C 2000–0x000D FFFF

0x0018 4000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 0FFF

0x000E 0000–0x000E 1554

0x000E 0000–0x000E 1FFF

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

0x000E 1555–0x000F FFFF

0x000E 2000–0x000F FFFF

0x001C 4000–0x001F FFFF

external code, executing exclusively from internal ROM. Addi-

tionally, the processor is not freely accessible via the JTAG port.

Instead, a unique 64-bit key, which must be scanned in through

the JTAG or Test Access Port will be assigned to each customer.

The device will ignore a wrong key. Emulation features and

external boot modes are only available after the correct key is

scanned.

External Port

The external port on the ADSP-21371/ADSP-21375 SHARC

processors provide a high performance, glueless interface to a

wide variety of industry-standard memory devices. The 32-bit

wide bus (ADSP-21371) may be used to interface to synchro-

nous and/or asynchronous memory devices through the use of

its separate internal memory controllers: the first is an SDRAM

controller for connection of industry-standard synchronous

DRAM devices and DIMMs (dual inline memory module),

while the second is an asynchronous memory controller

intended to interface to a variety of memory devices. Four

memory select pins enable up to four separate devices to coexist,

supporting any desired combination of synchronous and asyn-

chronous device types.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-21371/ADSP-21375 family contains a rich set of

peripherals that support a wide variety of applications, includ-

ing high quality audio, medical imaging, communications,

military, test equipment, 3D graphics, speech recognition, mon-

itor control, imaging, and other applications.

Rev. D

| Page 6 of 56 | April 2013

ADSP-21371/ADSP-21375

Table 4. ADSP-21375 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

Instruction Word (48 bits)

Normal Word (32 bits)

Short Word (16 bits)

BLOCK 0 ROM

0x0004 0000–0x0004 3FFF

0x0008 0000–0x0008 5554

0x0008 0000–0x0008 7FFF

0x0010 0000–0x0010 FFFF

Reserved

0x0004 4000–0x0004 BFFF

0x0008 5555–0x0008 FFFF

0x0008 8000–0x0009 7FFF

0x0011 0000–0x0012 FFFF

BLOCK 0 RAM

0x0004 C000–0x0004 C7FF

0x0009 0000–0x0009 0AA9

0x0009 8000–0x0009 8FFF

0x0013 0000–0x0013 1FFF

Reserved

0x0004 C800–0x0004 FFFF

0x0009 0AAA–0x0009 FFFF

0x0009 9000–0x0009 FFFF

0x0013 2000–0x0013 FFFF

BLOCK 1 ROM

0x0005 0000–0x0005 3FFF

0x000A 0000–0x000A 5554

0x000A 0000–0x000A 7FFF

0x0014 0000–0x0014 FFFF

Reserved

0x0005 4000–0x0005 BFFF

0x000A 5555–0x000A FFFF

0x000A 8000–0x000B 7FFF

0x0015 0000–0x0016 FFFF

BLOCK 1 RAM

0x0005 C000–0x0005 C7FF

0x000B 0000–0x000B 0AA9

0x000B 8000–0x000B 8FFF

0x0017 0000–0x0017 1FFF

Reserved

0x0005 C800–0x0005 FFFF

0x000B 0AAA–0x000B FFFF

0x000B 9000–0x000B FFFF

0x0017 2000–0x0017 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 07FF

0x000C 0000–0x000C 0AA9

0x000C 0000–0x000C 0FFF

0x0018 0000–0x0018 1FFF

Reserved

0x0006 0800–0x0006 FFFF

0x000C 0AAA–0x000D FFFF

0x000C 1000–0x000D FFFF

0x0018 2000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 07FF

0x000E 0000–0x000E 0AA9

0x000E 0000–0x000E 0FFF

0x001C 0000–0x001C 1FFF

Reserved

0x0007 0800–0x0007 FFFF

0x000E 0AAA–0x000F FFFF

0x000E 1000–0x000F FFFF

0x001C 2000–0x001F FFFF

Table 5. External Memory for SDRAM Addresses

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs.

Fully compliant with the SDRAM standard, each bank has its

own memory select line (MS0–MS3), and can be configured to

contain between 16M bytes and 256M bytes of memory.

SDRAM external memory address space is shown in Table 5.

Bank

Size in Words Address Range

Bank 0

Bank 1

Bank 2

Bank 3

62M

64M

0x0020 0000–0x03FF FFFF

0x0400 0000–0x07FF FFFF

0x0800 0000–0x0BFF FFFF

0x0C00 0000–0x0FFF FFFF

The controller maintains all of the banks as a contiguous

address space so that the processor sees this as a single address

space, even if different size devices are used in the

different banks.

Note that the external memory bank addresses shown in Table 5

are for normal word accesses. If 48-bit instructions are placed in

any such bank (with two instructions packed into three 32-bit

locations), then care must be taken to map data buffers in the

same bank. For example, if 2k instructions are placed starting at

the bank 0 base address (0x0020 0000), then the data buffers can

be placed starting at an address that is offset by 3k words

(0x0020 0C00).

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as 16 bits wide or as

32 bits wide. The SDRAM controller address, data, clock, and

command pins can drive loads up to 30 pF. For larger memory

systems, the SDRAM controller external buffer timing should

be selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

External Memory Code Execution

The program sequencer can execute code directly from external

memory bank 0 (SRAM, SDRAM) over the 48-bit external port

data bus (EPD). This allows a reduction in internal memory

size, thereby reducing the die area. Because instructions on the

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ADSP-21371/ADSP-21375

SHARC processor are 48 bits wide, instruction throughput

when executing code from external SDRAM memory is 2

instructions every 3 SDCLK (peripheral) clock cycles over a 32-

bit wide external port, and 2 instructions every 6 SDCLK clock

cycles over a 16-bit external port. Non SDRAM external mem-

ory address space is shown in Table 6.

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the processor’s DAI pins

(DAI_P1 to DAI_P20).

Table 6. External Memory for Non SDRAM Addresses

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

Bank

Size in Words Address Range

Bank 0

Bank 1

Bank 2

Bank 3

14M

16M

0x0020 0000–0x00FF FFFF

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

0x0400 0000–0x04FF FFFF

0x0800 0000–0x08FF FFFF

0x0C00 0000–0x0CFF FFFF

External Port Throughput

The throughput for the external port, based on 133 MHz clock

and 32-bit data bus, is 177M bytes/s for the AMI and 532M

bytes/s for SDRAM.

In the ADSP-21371, the DAI includes eight serial ports, four

precision clock generators (PCG), and an input data port (IDP).

For the ADSP-21375, the DAI includes four serial ports, four

precision clock generators (PCG) and an input data port (IDP).

Asynchronous Memory Controller

The IDP provides an additional input path to the core of the

processor, configurable as either eight channels of I²S serial

data, or a single 20-bit wide synchronous parallel data acquisi-

tion port. Each data channel has its own DMA channel that is

independent from the processor’s serial ports.

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit or 16-bit wide buses for ease of interfac-

ing to a range of memories and I/O devices tailored either to

high performance or to low cost and power.

Serial Ports

The processors feature eight synchronous serial ports on the

ADSP-21371 and four on the ADSP-21375. The SPORTs pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Pulse-Width Modulation

For the ADSP-21371, serial ports are enabled via 16 program-

mable pins and simultaneous receive or transmit pins that

support up to 32 transmit or 32 receive channels of audio data

when all eight SPORTs are enabled, or eight duplex TDM

streams of 128 channels per frame.

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

For the ADSP-21375, serial ports are enabled via eight program-

mable pins and simultaneous receive or transmit pins that

support up to 16 transmit or 16 receive channels of audio data

when all four SPORTs are enabled, or four duplex TDM streams

of 128 channels per frame.

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The serial ports operate at a maximum data rate of f_PCLK/4.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec-

ond updating of the PWM registers is implemented at the mid-

Rev. D

| Page 8 of 56 | April 2013

ADSP-21371/ADSP-21375

but data is sent to the FIFO as 32-bit words (that is, one-half of a

frame at a time). The processor supports 24- and 32-bit I²S, 24-

and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi-

fied formats.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for packed I²S

mode

• I²S mode

• Packed I²S mode

Precision Clock Generator (PCG)

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface (SPI) ports, one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a 2-wire interface

(TWI), and two general-purpose timers.

Each of the serial ports supports the left-justified sample pair

and I²S protocols (I²S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I²S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I²S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I²S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional -law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

Serial Peripheral (Compatible) Interface

The ADSP-21371/ADSP-21375 SHARC processors contain two

serial peripheral interface ports (SPIs). The SPI is an industry-

standard synchronous serial link, enabling the SPI-compatible

ports of the processors to communicate with other SPI compati-

ble devices. The SPI consists of two data pins, one device select

pin, and one clock pin. It is a full-duplex synchronous serial

interface, supporting both master and slave modes. The SPI port

can operate in a multimaster environment by interfacing with

up to four other SPI-compatible devices, either acting as a mas-

ter or slave device.

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

The SPI-compatible peripheral implementation also features

programmable baud rates and clock phases and polarities. The

SPI-compatible port uses open drain drivers to support a multi-

master configuration and to avoid data contention.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

UART Port

The ADSP-21371 S/PDIF receiver/transmitter has no separate

DMA channels. It receives audio data in serial format and con-

verts it into a biphase encoded signal. The serial data input to

the receiver/transmitter can be formatted as left justified, I²S or

right justified with word widths of 16, 18, 20, or

24 bits.

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface stan-

dard. The UART port also includes support for 5 to 8 data bits, 1

or 2 stop bits, and none, even, or odd parity. The UART port

supports two modes of operation:

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources such as the

SPORTs, external pins, the precision clock generators (PCGs),

and are controlled by the SRU control registers.

The ADSP-21375 does not have an S/PDIF-compatible digital

receiver/transmitter.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

Input Data Port (IDP)

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I²S, left-justified sample pair, or right-justified

mode. One frame sync cycle indicates one 64-bit left/right pair,

Rev. D

| Page 9 of 56 | April 2013

ADSP-21371/ADSP-21375

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

port (PDAP), or the UART (see Table 7).

Table 7. DMA Channels

The UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable. The port:

Peripheral

ADSP-21371

ADSP-21375

SPORT

16

8

• Supports bit rates ranging from (f_PCLK/1,048,576) to

(f_PCLK/16) bits per second.

PDAP

8

SPI

2

• Supports data formats from 7 to 12 bits per frame.

UART

2

• Can be configured to generate maskable interrupts for both

transmit and receive operations.

EP

2

MTM/DTCP

Total DMA Channels

2

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

32

24

Delay Line DMA

Peripheral Timers

The processors provide delay line DMA functionality. This

allows processor reads and writes to external delay line buffers

(and hence to external memory) with limited core interaction.

Two general-purpose timers can generate periodic interrupts

and be independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

Scatter/Gather DMA

The ADSP-2137x processor provides scatter/gather DMA func-

tionality. This allows processor DMA reads/writes to/from non-

contiguous memory blocks.

Each general-purpose timer has one bidirectional pin and four

registers that implement its mode of operation: a 6-bit configu-

ration register, a 32-bit count register, a 32-bit period register,

and a 32-bit pulse width register. A single control and status

register enables or disables the general-purpose timers

independently.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues. For complete system design

information, see the ADSP-2137x SHARC Processor Hardware

Reference.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

Program Booting

The internal memory of the processor boots at system power-up

from an 8-bit EPROM via the external port, an SPI master, or an

SPI slave. Booting is determined by the boot configuration

(BOOT_CFG1–0) pins in Table 8. Selection of the boot source

is controlled via the SPI as either a master or slave device, or it

can immediately begin executing from ROM.

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 7-bit addressing

Table 8. Boot Mode Selection

• 100 kbps and 400 kbps data rates

• Low interrupt rate

BOOT_CFG1–0

Booting Mode

SPI Slave Boot

00

01

10

11

I/O PROCESSOR FEATURES

SPI Master Boot

EPROM/FLASH Boot

The I/O processor provides many channels of DMA and con-

trols the extensive set of peripherals described in the previous

sections.

No boot (processor executes from

internal ROM after reset)

DMA Controller

The “Running Reset” feature allows programs to perform a reset

of the processor core and peripherals, but without resetting the

PLL and SDRAM controller, or performing a boot. The RESET-

OUT pin acts as the input for initiating a running reset.

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the ADSP-2137x processor’s internal memory and its

serial ports, the SPI-compatible (serial peripheral interface)

ports, the IDP (input data port), the parallel data acquisition

Rev. D

| Page 10 of 56 | April 2013

ADSP-21371/ADSP-21375

EZ-KIT Lite Evaluation Kits

Power Supplies

The processors have separate power supply connections for the

internal (V_DDINT), and external (V_DDEXT) power supplies. The

internal supplies must meet the 1.2 V requirement. The external

supply must meet the 3.3 V requirement. All external supply

pins must be connected to the same power supply.

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the processor to moni-

tor and control the target board processor during emulation.

Analog Devices DSP Tools product line of JTAG emulators pro-

vides emulation at full processor speed, allowing inspection and

modification of memory, registers, and processor stacks. The

processor’s JTAG interface ensures that the emulator will not

affect target system loading

or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User’s Guide”.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore^®Embed-

ded Studio and/or VisualDSP++^®), evaluation products,

emulators, and a wide variety of software add-ins.

Board Support Packages for Evaluation Hardware

Integrated Development Environments (IDEs)

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

The newest IDE, CrossCore Embedded Studio, is based on the

Eclipse^TMframework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

www.analog.com/cces.

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/lwip

EZ-KIT Lite Evaluation Board

Algorithmic Modules

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com

and search on “Blackfin software modules” or “SHARC software

modules”.

Rev. D

| Page 11 of 56 | April 2013

ADSP-21371/ADSP-21375

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the Engineer-to-Engineer

Note “Analog Devices JTAG Emulation Technical Reference”

(EE-68) on the Analog Devices website (www.analog.com)—use

site search on “EE-68.” This document is updated regularly to

keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the processor’s

architecture and functionality. For detailed information on the

core architecture and instruction set, refer to the ADSP-2137x

SHARC Processor Hardware Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

TM

The Circuits from the Lab site (www.analog.com/signal

chains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Rev. D

| Page 12 of 56 | April 2013

ADSP-21371/ADSP-21375

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 9:

A = asynchronous, I = input, O = output, S = synchronous,

(A/D) = active drive, (O/D) = open drain, and T = three-state,

(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 9. Pin Descriptions

State During

and After

Name

Type

Reset

Description

ADDR_23–0

O/T (pu)

Pulled high/

driven low

External Address. The processor outputs addresses for external memory and periph-

erals on these pins.

DATA_31–0

I/O (pu)

Pulled high/

pulled high

External Data. The data pins can be multiplexed to support the external memory

interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After

reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).

When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port

data pins for parallel input data. PDAP over 16-bit external port DATA is not supported

on the ADSP-21375 processor.

DAI _P_20–1

I/O with

Pulled high/

pulled high

Digital Applications Interface Pins. These pins provide the physical interface to the

DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio-

centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.

The configuration registers of these peripherals then determine the exact behavior of

the pin. Any input or output signal present in the DAI SRU may be routed to any of these

pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module

(ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled

via the DAI_PIN_PULLUP register.

programmable

(pu)¹

DPI _P_14–1

I/O with

Pulled high/

pulled high

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

TheDPISRUconfigurationregistersdefinethecombinationofon-chipperipheralinputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU

provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and general-

purpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP

register.

programmable

(pu)¹

ACK

I (pu)

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to

an external memory access. ACK is used by I/O devices, memory controllers, or other

peripherals to hold off completion of an external memory access.

RD

O/T (pu)

Pulled high/

driven high

External Port Read Enable. RD is asserted whenever the processor reads a word from

external memory. RD has a 22.5 k internal pull-up resistor.

WR

Pulled high/

driven high

External Port Write Enable. WR is asserted when the processor writes a word to

external memory. WR has a 22.5 k internal pull-up resistor.



SDRAS

SDCAS

SDWE

Pulled high/

driven high

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

Pulled high/

driven high

SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

Pulled high/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

Rev. D

| Page 13 of 56 | April 2013

ADSP-21371/ADSP-21375

Table 9. Pin Descriptions (Continued)

State During

and After

Name

Type

Reset

Description

SDCKE

O/T (pu)

Pulled high/

driven high

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDA10

O/T (pu)

Pulled high/

driven low

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDCLK

MS_0–1

O/T

High-Z/driving

SDRAM Clock.

O/T (pu)

Pulled high/

driven high

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

sponding banks of external memory. The MS_1-0lines are decoded memory address lines

that change at the same time as the other address lines. The MS1 pin can be used in

EPORT/FLASH boot mode. For more information, see the ADSP-2137x SHARC Processor

Hardware Reference.

FLAG[0]/IRQ0

FLAG[1]/IRQ1

I/O

FLAG[0] INPUT

FLAG[1] INPUT

FLAG[2] INPUT

FLAG0/Interrupt Request0.

FLAG1/Interrupt Request1.

FLAG[2]/IRQ2/

MS2

I/O with

programmable pu

(for MS mode)

FLAG2/Interrupt Request/Memory Select2.

FLAG[3]/

I/O with

FLAG[3] INPUT

FLAG3/Timer Expired/Memory Select3.

TMREXP/ MS3

programmable pu

(for MS mode)

TDI

I (pu)

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 k internal pull-up resistor.

TDO

TMS

O/T

Test Data Output (JTAG). Serial scan output of the boundary scan path.

I (pu)

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k

internal pull-up resistor.

TCK

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the processor.

TRST

I (pu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the processor. TRST has a 22.5 k



internal pull-up resistor.

EMU

O (O/D) (pu)

Emulation Status. Must be connected to the processor. Analog Devices DSP Tools

product line of JTAG emulators target board connector only. EMU has a 22.5 k

pull-up resistor.

internal

CLK_CFG_1–0

I

Core to CLKIN Ratio Control. These pins set the start up clock frequency. See the

ADSP-2137x SHARC Processor Hardware Reference for a description of the clock configu-

ration modes.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

BOOT_CFG_1–0

I

Boot Configuration Select. These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before reset is asserted. See the ADSP-2137x SHARC

Processor Hardware Reference for information about boot modes.

Rev. D

| Page 14 of 56 | April 2013

ADSP-21371/ADSP-21375

Table 9. Pin Descriptions (Continued)

State During

and After

Reset

Name

Type

Description

RESET

I

Processor Reset. Resets the processor to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

XTAL

O

I

CrystalOscillatorTerminal. Usedinconjunctionwith CLKINtodrivean externalcrystal.

CLKIN

Local Clock In. Used in conjunction with XTAL. CLKIN is the processor clock input. It

configures the processor to use either its internal clock generator or an external clock

source. Connecting the necessary components to CLKIN and XTAL enables the internal

clock generator. Connecting the external clock to CLKIN while leaving XTAL uncon-

nected configures the processor to use the external clock source such as an external

clock oscillator. CLKIN may not be halted, changed, or operated below the specified

frequency.

RESETOUT/

RUNRSTIN

I/O (pu)

Reset Out/Running Reset In. The default setting is reset out. This pin also has a second

function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For

more information, see the ADSP-2137x SHARC Processor Hardware Reference

.

¹Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

Rev. D

| Page 15 of 56 | April 2013

ADSP-21371/ADSP-21375

ADSP-21371/ADSP-21375 SPECIFICATIONS

OPERATING CONDITIONS

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter¹Description

Min

Unit

V_DDINT

V_DDEXT

Internal (Core) Supply Voltage

0.95

3.13

2.0

1.05

1.14

3.13

2.0

1.26

V

ºC

External (I/O) Supply Voltage

3.47

2

V_IH

High Level Input Voltage @ V_DDEXT= Max

Low Level Input Voltage @ V_DDEXT= Min

High Level Input Voltage @ V_DDEXT= Max

Low Level Input Voltage @ V_DDEXT= Min

V_DDEXT+ 0.5

+0.8

V_DDEXT+ 0.5

+0.8

2

V_IL

–0.5

1.74

–0.5

N/A

–0.5

1.74

–0.5

0

3

V_IH

_

V_DDEXT+ 0.5

+1.10

V_DDEXT+ 0.5

+1.10

95

CLKIN

3

V_IL

_

CLKIN

T_JUNCTION

Junction Temperature 208-Lead LQFP_EP @ T_AMBIENT

0°C to +70°C

N/A

Junction Temperature 208-Lead LQFP_EP @ T_AMBIENT

–40°C to +85°C

N/A

–40

N/A

–40

N/A

+110

N/A

ºC

Junction Temperature 208-Lead LQFP_EP @ T_AMBIENT

–40°C to +105°C

+120

¹Specifications subject to change without notice.

²Applies to inputandbidirectionalpins:ADDR23–0, DATA31–0 (DATA15–0 onADSP-21375), FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOT_CFGx, CLK_CFGx, RUNRSTIN,

RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

Rev. D

| Page 16 of 56 | April 2013

ADSP-21371/ADSP-21375

ELECTRICAL CHARACTERISTICS

1.0 V, 200 MHz

1.2 V, 266 MHz

Parameter¹Description

Test Conditions

Min Typ

2.4

Max

Min Typ

2.4

Max

Unit

2

V_OH

High Level Output Voltage @ V_DDEXT= Min, I_OH= –1.0 mA³

V

2

V_OL

Low Level Output Voltage

High Level Input Current

Low Level Input Current

@ V_DDEXT= Min, I_OL= 1.0 mA³

@ V_DDEXT= Max, V_IN= V_DDEXTmax

@ V_DDEXT= Max, V_IN= 0 V

0.4

10

0.4

10

V

4, 5

I_IH

μA

4

I_IL

10

5

I_ILPU

Low Level Input Current

Pull-up

@ V_DDEXT= Max, V_IN= 0 V

200

6, 7

I_OZH

Three-State Leakage Current @ V_DDEXT= Max, V_IN= V_DDEXTMax

Three-State Leakage Current @ V_DDEXT= Max, V_IN= 0 V

10

μA

6

I_OZL

10

7

I_OZLPU

Three-State Leakage Current @ V_DDEXT= Max, V_IN= 0 V

Pull-up

200

8, 9

I_DD

-

Supply Current (Internal)

1.0V, 200 MHz: t_CCLK= 5.00 ns,

V_DDINT= 1.0 V, 25ºC

INTYP

400

mA

1.2V, 266 MHz: t_CCLK= 3.75 ns,

V_DDINT= 1.2 V, 25ºC

600

mA

pF

10, 11

C_IN

Input Capacitance

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.2 V

4.7

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, SDRAS, SDCAS, SDWE,

SDCKE, SDA10, and SDCLK.

³See Output Drive Currents on Page 49 for typical drive current capabilities.

⁴Applies to input pins: BOOT_CFGx, CLKCFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with 22.5 k internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pins: FLAG3–0.

⁷Applies to three-statable pins with 22.5 k pull-ups: DAI_Px, DPI_Px, EMU.

⁸Typical internal current data reflects nominal operating conditions.

⁹See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for further information.

¹⁰Applies to all signal pins.

¹¹Guaranteed, but not tested.

Rev. D

| Page 17 of 56 | April 2013

ADSP-21371/ADSP-21375

PACKAGE INFORMATION

Table 11. Absolute Maximum Ratings (Continued)

The information presented in Figure 3 provides details about

the package branding for the ADSP-21371/ADSP-21375 proces-

sor. For a complete listing of product availability, see Ordering

Guide on Page 56.

Parameter

Rating

Load Capacitance

200 pF

Storage Temperature Range

Junction Temperature under Bias

–65C to +150C

125C

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

a

ADSP-2137x

tppZ-cc

vvvvvv.x n.n

yyww country_of_origin

S

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 38 on Page 49 under Test Conditions for voltage refer-

ence levels.

Figure 3. Typical Package Brand

Table 10. Package Brand Information

Brand Key

Field Description

Temperature Range

Package Type

t

pp

Z

RoHS Compliant Part

See Ordering Guide

Assembly Lot Code

Silicon Revision

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

cc

vvvvvv.x

n.n

yyww

Date Code

MAXIMUM POWER DISSIPATION

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

See Engineer-to-Engineer Note “Estimating Power Dissipation

for ADSP-2137x SHARC Processors” (EE-318) for detailed ther-

mal and power information regarding maximum power

dissipation. For information on package thermal specifications,

see Thermal Characteristics on Page 50.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 11 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 4). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Table 11. Absolute Maximum Ratings

Parameter

Rating

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +1.5 V

–0.3 V to +4.6 V

+0.5 V

External (I/O) Supply Voltage (V_DDEXT

Input Voltage –0.5 V to V_DDEXT

)

Output Voltage Swing –0.5 V to V_DDEXT

+0.5 V

Rev. D

| Page 18 of 56 | April 2013

ADSP-21371/ADSP-21375

Voltage Controlled Oscillator

f

_INPUT= CLKIN when the input divider is disabled or

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

f_VCOspecified in Table 14.

_INPUT= CLKIN  2 when the input divider is enabled

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 12. All

of the timing specifications for the ADSP-2137x peripherals are

defined in relation to t_PCLK. See the peripheral specific section

for each peripheral’s timing information.

• The product of CLKIN and PLLM must never exceed 1/2

f

_VCO(max) in Table 14 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f_VCO

(max) in Table 14 if the input divider is enabled

(INDIV = 1).

Table 12. Clock Periods

Timing

The VCO frequency is calculated as follows:

Requirements

Description

t_CK

CLKIN Clock Period

f

_VCO= 2 × PLLM × f_INPUT

_CCLK= (2 × PLLM × f_INPUT)  (2 × PLLD)

t_CCLK

t_PCLK

Processor Core Clock Period

Peripheral Clock Period = 2 × t_CCLK

where:

_VCO= VCO output

f

Figure 4 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the ADSP-2137x SHARC Processor Hard-

ware Reference.

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the

PMCTL register. During reset this value is 1.

f

_INPUT= Input frequency to the PLL.

PMCTL

(SDCKR)

PMCTL

(PLLBP)

PLL

f

VCO

f

CCLK

CLKIN

BUF

INPUT

SDRAM

DIVIDER

CLKIN

DIVIDER

LOOP

FILTER

PLL

DIVIDER

VCO

SDCLK

f

CCLK

XTAL

PMCTL

(2xPLLD)

PMCTL

(INDIV)

PCLK

DIVIDE

BY 2

PLL

MULTIPLIER

PMCTL

(PLLBP)

PCLK

CLK_CFGx/PMCTL (2xPLLM)

CCLK

CLKOUT (TEST ONLY)

DELAY OF

4096 CLKIN

CYCLES

RESETOUT

CORERST

RESETOUT

BUF

RESET

Figure 4. Core Clock and System Clock Relationship to CLKIN

Rev. D

| Page 19 of 56 | April 2013

ADSP-21371/ADSP-21375

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 13.

Note that during power-up, a leakage current of approximately

200 μA may be observed on the RESET pin. This leakage current

results from the weak internal pull-up resistor on this pin being

enabled during power-up.

Table 13. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_DDINT/V_DDEXTOn

V_DDINTon Before V_DDEXT

0

ns

t_IVDDEVDD

–50

0

10²

20³

+200

200

ms

μs

1

t_CLKVDD

CLKIN Valid After V_DDINT/V_DDEXTValid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_CLKRST

t_PLLRST

μs

Switching Characteristic

4, 5

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096 × t_CK+ 2 × t_CCLK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

t_RSTVDD

RESET

V

DDINT

t_IVDDEVDD

V

DDEXT

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG1–0

RESETOUT

t_PLLRST

t_CORERST

Figure 5. Power-Up Sequencing

Rev. D

| Page 20 of 56 | April 2013

ADSP-21371/ADSP-21375

Clock Input

Table 14. Clock Input

200 MHz

Max

266 MHz

Unit

Parameter

Min

Max

Timing Requirements

t_CK

CLKIN Period

30¹

15¹

100

45

6

22.5¹

11.25¹

100

45

6

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

ns

2

t_CCLK

f_VCO

5

10

800

3.75

200

10

800

ns

VCO Frequency

200

MHz

¹Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.

²Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

.

t_CK

CLKIN

t_CKH

t_CKL

Figure 6. Clock Input

Clock Signals

The processor can use an external clock or a crystal. See the

CLKIN pin description in Table 9. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 7 shows the

component connections used for a crystal operating in funda-

mental mode. Note that the clock rate is achieved using a

16.67 MHz crystal and a PLL multiplier ratio 16:1

ADSP-2137x

R1

XTAL

CLKIN

1M⍀*

R2

47⍀*

C1

C2

22pF

(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

Y1

16.67 MHz

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

*TYPICAL VALUES

Figure 7. 266 MHz Operation (Fundamental Mode Crystal)

Rev. D

| Page 21 of 56 | April 2013

ADSP-21371/ADSP-21375

Reset

Table 15. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

t_SRST

RESET Pulse Width Low

4 × t_CK

8

ns

RESET Setup Before CLKIN Low

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable

V_DDand CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 8. Reset

Running Reset

The following timing specification applies to the RESETOUT/

RUNRSTIN pin when it is configured as RUNRSTIN.

Table 16. Running Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRUNRST

t_SRUNRST

Running RESET Pulse Width Low

4 × t_CK

8

ns

Running RESET Setup Before CLKIN High

CLKIN

t_WRUNRST

t_SRUNRST

RUNRSTIN

Figure 9. Running Reset

Rev. D

| Page 22 of 56 | April 2013

ADSP-21371/ADSP-21375

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP pin).

Table 17. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

TMREXP Pulse Width

4 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(TMREXP)

Figure 10. Core Timer

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts as well as the DAI_P20–1 and

DPI_P14–1 pins when they are configured as interrupts.

Table 18. Interrupts

Parameter

Min

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

2 × t_PCLK+2

ns

INTERRUPT

INPUTS

t_IPW

Figure 11. Interrupts

Rev. D

| Page 23 of 56 | April 2013

ADSP-21371/ADSP-21375

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0 and

Timer1 in PWM_OUT (pulse-width modulation) mode. Timer

signals are routed to the DPI_P14–1 pins through the DPI SRU.

Therefore, the specifications provided below are valid at the

DPI_P14–1 pins.

Table 19. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

2 × t_PCLK– 2

2 × (2³¹– 1) × t_PCLK

ns

t_PWMO

PWM

OUTPUTS

Figure 12. Timer PWM_OUT Timing

Timer WDTH_CAP Timing

The following timing specification applies to Timer0 and

Timer1 in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the specifications provided below are valid at

the DPI_P14–1 pins.

Table 20. Timer Width Capture Timing

Parameter

Min

Max

Unit

ns

Timing Requirement

t_PWI

Timer Pulse Width

2 × t_PCLK

2 × (2³¹– 1) × t_PCLK

t_PWI

TIMER

CAPTURE

INPUTS

Figure 13. Timer Width Capture Timing

Rev. D

| Page 24 of 56 | April 2013

ADSP-21371/ADSP-21375

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 21. DAI/DPI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid

1.5

10

ns

DAI_Pn

DPI_Pn

t_DPIO

DAI_Pm

DPI_Pm

Figure 14. DAI/DPI Pin to Pin Direct Routing

Rev. D

| Page 25 of 56 | April 2013

ADSP-21371/ADSP-21375

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 through DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 22. Precision Clock Generator (Direct Pin Routing)

1.0 V, 200 MHz

1.2 V, 266 MHz

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_PCGIP

t_STRIG

Input Clock Period

t_PCLK× 4

4.5

t_PCLK× 4

4.5

ns

PCG Trigger Setup Before

Falling Edge of PCG Input Clock

t_HTRIG

PCG Trigger Hold After Falling 3

Edge of PCG Input Clock

3

ns

Switching Characteristics

t_DPCGIO

PCG Output Clock and Frame

Sync Active Edge Delay After 2.5

PCG Input Clock

12.8

2.5

10

ns

t_DTRIGCLK

t_DTRIGFS

PCG Output Clock Delay After 2.5 + ((2.5) × t_PCGIW

PCG Trigger

)

12.8 + ((2.5) × t_PCGIW

)

2.5 + ((2.5) × t_PCGIW

)

10 + ((2.5) × t_PCGIW)

PCG Frame Sync Delay After

PCG Trigger

2.5 + ((2.5 + D – PH) 12.8 + ((2.5 + D – PH) 2.5 + ((2.5 + D – PH) 10 + ((2.5 + D – PH)

× t_PCGIW× t_PCGIW× t_PCGIW× t_PCGIW

2 × t_PCGIW– 1 2 × t_PCGIW– 1

)

1

t_PCGOW

Output Clock Period

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.

¹Normal mode of operation.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

t_PCGIP

DAI_Py

DPI_Py

PCG_CLKx_O

t_DTRIGCLK

t_PCGOW

t_DPCGIO

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 15. Precision Clock Generator (Direct Pin Routing)

Rev. D

| Page 26 of 56 | April 2013

ADSP-21371/ADSP-21375

Flags

The timing specifications provided below apply to the FLAG3–0

and DPI_P14–1 pins, and the DATA31–0 pins. See Table 9 on

Page 13 for more information on flag use.

Table 23. Flags

Parameter

Min

Max

Unit

ns

Timing Requirement

t_FIPW

Switching Characteristic

t_FOPWDPI_P14–1, DATA31–0, FLAG3–0 _OUTPulse Width

DPI_P14–1, DATA31–0, FLAG3–0 _INPulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 2

ns

FLAG

INPUTS

t_FIPW

FLAG

OUTPUTS

t_FOPW

Figure 16. Flags

Rev. D

| Page 27 of 56 | April 2013

ADSP-21371/ADSP-21375

SDRAM Interface Timing

Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.

Table 24. SDRAM Interface Timing¹

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter

Min

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before SDCLK

DATA Hold After SDCLK

0.58

2.2

0.58

2.2

ns

Switching Characteristics

t_SDCLK

t_SDCLKH

t_SDCLKL

t_DCAD

SDCLK Period

10

4

7.5

3

ns

SDCLK Width High

SDCLK Width Low

4

3

Command, ADDR, Data Delay After SDCLK²

Command, ADDR, Data Hold After SDCLK²

Data Disable After SDCLK

6.4

5.3

t_HCAD

1.3

1.6

1.3

1.6

t_DSDAT

t_ENSDAT

Data Enable After SDCLK

¹For F_CCLK= 133 MHz (SDCLK ratio = 1:2).

²Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.

t_SDCLKH

t_SDCLK

SDCLK

t_SSDAT

t_HSDAT

t_SDCLKL

DATA (IN)

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

DATA (OUT)

t_DCAD

t_HCAD

COMMAND/ADDR

(OUT)

Figure 17. SDRAM Interface Timing for 133 MHz SDCLK

Rev. D

| Page 28 of 56 | April 2013

ADSP-21371/ADSP-21375

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 25. Memory Read—Bus Master

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Parameter

Min

Max

Unit

Timing Requirements

t_DAD

Address, Selects Delay to Data Valid^{1, 2, 3}

RD Low to Data Valid^{1, 3}

W + t_SDCLK– 5.12

W + t_SDCLK– 5.12 ns

t_DRLD

t_SDS

W – 3

ns

Data Setup to RD High

2.2

0

2.2

0

t_HDRH

t_DAAK

t_DSAK

Data Hold from RD High^{4, 5}

ACK Delay from Address, Selects^{2, 6}

ACK Delay from RD Low⁵

t_SCDCLK– 11.4 + W

W – 7.25

t_SCDCLK– 10.1 + W ns

W – 7.0

ns

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address Selects Hold After RD High

Address Selects to RD Low²

RHC + 0.38

t_SDCLK– 3.8

RHC + 0.38

t_SDCLK– 3.3

ns

RD Pulse Width

W – 1.4

t_RWR

RD High to WR, RD, Low

HI + t_SDCLK– 0.8

W = (number of wait states specified in AMICTLx register) × t_SDCLK

HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × t_SDCLK

IC = (number of idle cycles specified in AMICTLx register) × t_SDCLK

)

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

¹Data delay/setup: System must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx, is referenced.

³The maximum limit of timing requirement values for t_DADand t_DRLDparameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not

used.

⁴Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

⁵Data hold: User must meet t_HDRHin asynchronous access mode. See Test Conditions on Page 49 for the calculation of hold times given capacitive and dc loads.

⁶ACK delay/setup: User must meet t_DAAK, or t_DSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t_DAAKor t_DSAK

.

Rev. D

| Page 29 of 56 | April 2013

ADSP-21371/ADSP-21375

ADDR

MSx

t_DARL

t_RW

t_DRHA

RD

t_DRLD

t_SDS

t_DAD

t_HDRH

DATA

t_DSAK

t_RWR

t_DAAK

ACK

WR

Figure 18. Memory Read—Bus Master

Rev. D

| Page 30 of 56 | April 2013

ADSP-21371/ADSP-21375

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 26. Memory Write—Bus Master

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

Switching Characteristics

ACK Delay from Address, Selects^{1, 2}

ACK Delay from WR Low ^{1, 3}

t_SDCLK– 11 + W

t_SDCLK– 10.1 + W

W – 7.1

ns

W – 7.35

t_DAWH

t_DAWL

t_WW

Address, Selects to WR Deasserted²

Address, Selects to WR Low²

t_SDCLK– 4.3 + W

t_SDCLK– 2.7

t_SDCLK– 3.6 + W

t_SDCLK– 2.7

ns

WR Pulse Width

W – 1.3

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup Before WR High

Address Hold After WR Deasserted

Data Hold After WR Deasserted

Data Disable After WR Deasserted⁴

WR High to WR, RD Low

t_SDCLK– 3.0 + W

H + 0.15

t_SDCLK– 3.0 + W

H + 0.15

H + 0.02

t_SDCLK– 1.37 + H

t_SDCLK– 1.5+ H

2t_SDCLK– 12

t_SDCLK– 4.1

t_SDCLK+ 10.7+ H

t_SDCLK– 1.37 + H

t_SDCLK– 1.5+ H

2t_SDCLK– 5.1

t_SDCLK– 4.1

t_SDCLK+ 4.9+ H

t_DDWR

t_WDE

Data Disable Before RD Low

WR Low to Data Enabled

W = (number of wait states specified in AMICTLx register) × t_SDCLK, H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

¹ACK delay/setup: System must meet t_DAAK, or t_DSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t_DAAKor t_DSAK

²The falling edge of MSx is referenced.

.

³Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

⁴See Test Conditions on Page 49 for calculation of hold times given capacitive and dc loads.

Rev. D

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ADSP-21371/ADSP-21375

ADDR

MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

WR

t_WWR

t_WDE

t_DATRWH

t_DDWH

t_DDWR

DATA

t_DSAK

t_DWHD

t_DAAK

ACK

RD

Figure 19. Memory Write—Bus Master

Rev. D

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ADSP-21371/ADSP-21375

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) serial clock

(SCLK) width.

Serial port signals are routed to the DAI_P20–1 pins using the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 27. Serial Ports—External Clock

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter

Min

Unit

Timing Requirements

1

t_SFSE

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in either Transmit 2.8

or Receive Mode)

2.5

ns

1

t_HFSE

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit 2.5

or Receive Mode)

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

3.1

2.5

ns

1

t_HDRE

t_SCLKW

t_SCLK

(t_PCLK× 4) ÷ 2 – 1.5

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 1.5

t_PCLK× 4

SCLK Period

Switching Characteristics

2

t_DFSE

Frame Sync Delay After SCLK (Internally Generated

Frame Sync in either Transmit or Receive Mode)

13.5

13.9

10.5

11

ns

2

t_HOFSE

Frame Sync Hold After SCLK (Internally Generated

Frame Sync in either Transmit or Receive Mode)

2

ns

2

t_DDTE

t_HDTE

Transmit Data Delay After Transmit SCLK

Transmit Data Hold After Transmit SCLK

¹Referenced to sample edge.

²Referenced to drive edge.

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ADSP-21371/ADSP-21375

Table 28. Serial Ports—Internal Clock

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter

Min

Unit

Timing Requirements

1

t_SFSI

Frame Sync Setup Before SCLK (Externally Generated Frame

Sync in either Transmit or Receive Mode)

7

ns

1

t_HFSI

Frame Sync Hold After SCLK (Externally Generated Frame Sync

in either Transmit or Receive Mode)

2.5

7

2.5

7

ns

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

FrameSyncDelayAfterSCLK(InternallyGeneratedFrameSync

in Transmit Mode)

4

ns

2

t_HOFSI

Frame Sync Hold After SCLK (Internally Generated Frame Sync –1.0

in Transmit Mode)

–1.0

2

t_DFSIR

FrameSyncDelayAfterSCLK(InternallyGeneratedFrameSync

in Receive Mode)

13.5

4.6

10.7

3.6

2

t_HOFSIR

Frame Sync Hold After SCLK (Internally Generated Frame Sync –1.0

in Receive Mode)

–1.0

2

t_DDTI

Transmit Data Delay After SCLK

ns

2

t_HDTI

Transmit Data Hold After SCLK

Transmit or Receive SCLK Width

–1.0

3

t_SCKLIW

2 × t_PCLK– 1.5

2 × t_PCLK+ 1.5 2 × t_PCLK– 1.5 2 × t_PCLK+ 1.5 ns

¹Referenced to the sample edge.

²Referenced to drive edge.

³Minimum SPORT divisor register value.

Rev. D

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ADSP-21371/ADSP-21375

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 20. Serial Ports

Rev. D

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ADSP-21371/ADSP-21375

Table 29. Serial Ports—Enable and Three-State

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter

Min

2

Min

2

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

11.3

10

1

t_DDTIN

–1

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

t_DDTEN

t_DDTTE

DAI_P20–1

(DATA

CHANNEL A/B)

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

t_DDTIN

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 21. Enable and Three-State

Rev. D

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ADSP-21371/ADSP-21375

Table 30. Serial Ports—External Late Frame Sync

1.0 V, 200 MHz

1.2 V, 266 MHz

Max

Parameter

Min

Max

Min

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit Frame Sync

12.7

10

ns

or External Receive Frame Sync with

MCE = 1, MFD = 0

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

ns

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE DRIVE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

Figure 22. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

Rev. D

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ADSP-21371/ADSP-21375

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 31. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 31. Input Data Port (IDP)

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter

Min

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

4.95

2.5

3.8

2.5

ns

1

t_SIHFS

1

t_SISD

3.35

2.5

1

t_SIHD

t_IDPCLKW

t_IDPCLK

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The data, serial clock, and frame sync signals can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either

CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IDPCLK

t_IDPCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 23. IDP Master Timing

Rev. D

| Page 38 of 56 | April 2013

ADSP-21371/ADSP-21375

Note that the 20-bits of external PDAP data can be provided

through the external port DATA31–12 pins. On the

ADSP-21375 processors, PDAP can not be multiplexed on the

external port (since only DATA15–0). Use the SRU DAI

instead.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 32. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

PDAP chapter of the ADSP-2137x SHARC Processor Hardware

Reference.

Table 32. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge

PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge

Clock Width

2.5

ns

1

t_HPCLKEN

2.5

1

t_PDSD

3.85

1

t_PDHD

2.5

t_PDCLKW

t_PDCLK

(t_PCLK× 4) ÷ 2 – 3

t_PCLK× 4

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRIBPDAP Strobe Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 1

ns

¹Data source pins are DATA31–12 or DAI pins. Source pins for serial clock and frame sync are: 1) DATA11–10 pins, 2) DAI pins.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20–1

(PDAP_CLK)

t_HPHOLD

t_SPHOLD

DAI_P20–1

(PDAP_HOLD)

t_PDHD

t_PDSD

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

t_PDHLDD

t_PDSTRB

DAI_P20–1

(PDAP_STROBE)

Figure 24. PDAP Timing

Rev. D

| Page 39 of 56 | April 2013

ADSP-21371/ADSP-21375

Pulse-width modulation generator information does not apply

to the ADSP-21375.

Pulse-Width Modulation Generators (PWM)

For the ADSP-21371, the following timing specifications apply

when the DATA31–16 pins are configured as PWM.

Table 33. Pulse-Width Modulation (PWM) Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

t_PCLK– 2.5

(2¹⁶– 2) × t_PCLK

(2¹⁶– 1) × t_PCLK

ns

2 × t_PCLK– 2.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 25. PWM Timing

Rev. D

| Page 40 of 56 | April 2013

ADSP-21371/ADSP-21375

output mode) from an LRCLK transition, so that when there are

64 serial clock periods per LRCLK period, the LSB of the data

will be right-justified to the next LRCLK transition.

S/PDIF Transmitter

For the ADSP-21371, serial data input to the S/PDIF transmitter

can be formatted as left-justified, I²S, or right-justified with

word widths of 16-, 18-, 20-, or 24-bits. The following sections

provide timing for the transmitter.

S/PDIF transmitter information does not apply to the

ADSP-21375.

Figure 27 shows the default I²S-justified mode. LRCLK is low

for the left channel and high for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to an

LRCLK transition but with a single serial clock period delay.

S/PDIF Transmitter-Serial Input Waveforms

Figure 26 shows the right-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of serial clock. The MSB is delayed 12-bit clock peri-

ods (in 20-bit output mode) or 16-bit clock periods (in 16-bit

Figure 28 shows the left-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of serial clock. The MSB is left-justified to an LRCLK

transition with no MSB delay.

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_RJD

DAI_P20–1

LSB

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

SDATA

Figure 26. Right-Justified Mode

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_I2SD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 27. I²S-Justified Mode

DAI_P20–1

FS

LEFT/RIGHT CHANNEL

DAI_P20–1

SCLK

t_LJD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 28. Left-Justified Mode

Rev. D

| Page 41 of 56 | April 2013

ADSP-21371/ADSP-21375

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 34. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 34. S/PDIF Transmitter Input Data Timing

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter

Min

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Transmit Clock Width

3

ns

1

t_SIHRS

3

1

t_SISD

3.2

3

t_SIHD

3

t_SITXCLKW

t_SITXCLK

t_SISCLKW

t_SISCLK

9

Transmit Clock Period

20

36

80

20

36

80

Clock Width

Clock Period

1

The data, serial clock, and frame sync can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN

or any of the DAI pins.

SAMPLE EDGE

t_SITXCLKW

t_SITXCLK

DAI_P20–1

(TxCLK)

t_SISCLK

t_SISCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 29. S/PDIF Transmitter Input Timing

Oversampling Clock (HFCLK) Switching Characteristics

The S/PDIF transmitter has an oversampling clock. This

HFCLK input is divided down to generate the biphase clock.

Table 35. Oversampling Clock HFxCLK) Switching Characteristics

Parameter

Max

Unit

MHz

kHz

HFCLK Frequency for HFCLK = 384 × Frame Sync

HFCLK Frequency for HFCLK = 256 × Frame Sync

Frame Rate (FS)

Oversampling Ratio × Frame Sync <= 1/t_SITXCLK

49.2

192.0

Rev. D

| Page 42 of 56 | April 2013

ADSP-21371/ADSP-21375

Internal Digital PLL Mode

S/PDIF Receiver

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × Frame Sync clock. The S/PDIF

receiver information does not apply to the ADSP-21375.

For the ADSP-21371, the following section describes timing as it

relates to the S/PDIF receiver.

Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing

1.0 V, 200 MHz

Max

1.2 V, 266 MHz

Max

Parameter

Min

Unit

Switching Characteristics

t_DFSI

LRCLK Delay After Serial Clock

LRCLK Hold After Serial Clock

5

ns

t_HOFSI

t_DDTI

–2

Transmit Data Delay After Serial Clock

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

t_HDTI

–2

52

–2

1

t_SCLKIW

38.5

¹Serial lock frequency is 64 × Frame Sync where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20–1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20–1

(FS)

t_DDTI

t_HDTI

DAI_P20–1

(DATA CHANNEL

A/B)

Figure 30. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. D

| Page 43 of 56 | April 2013

ADSP-21371/ADSP-21375

SPI Interface—Master

The processor contains two SPI ports. Both primary and sec-

ondary are available through DPI only. The timing provided in

Table 37 and Table 38 applies to both.

Table 37. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid To SPICLK Edge (Data Input Setup Time)

8.2

2

ns

SPICLK Last Sampling Edge To Data Input Not Valid

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_PCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

DPI Pin (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to DPI Pin (SPI Device Select) High

Sequential Transfer Delay

2.5

4 × t_PCLK– 2

4 × t_PCLK– 1

t_SPITDM

DPI

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

(INPUT)

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHASE = 0

MISO

(INPUT)

Figure 31. SPI Master Timing

Rev. D

| Page 44 of 56 | April 2013

ADSP-21371/ADSP-21375

SPI Interface—Slave

Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications

1.0 V, 200 MHz

1.2 V, 266 MHz

Max

Parameter

Min

Max

Min

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

4 × t_PCLK– 2

2 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t_PCLK

t_HDS

Last SPICLK Edge to SPIDS Not Asserted (CPHASE=0)

Data Input Valid to SPICLK edge (Data Input Set-up Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE=0)

2 × t_PCLK

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

0

6.8

9.9

9.5

0

6.8

9.5

ns

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPIDS Deassertion to Data High Impedance

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

2 × t_PCLK

5 × t_PCLK

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0,

CP = 1)

(INPUT)

t_SDSCO

t_DSOE

t_DSDHI

t_DDSPIDS

t_HDSPIDS

MISO

(OUTPUT)

t_SSPIDSt_HSPIDS

CPHASE = 1

MOSI

(INPUT)

t_HDSPIDS

t_DSDHI

MISO

(OUTPUT)

t_DSOV

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

Figure 32. SPI Slave Timing

Rev. D

| Page 45 of 56 | April 2013

ADSP-21371/ADSP-21375

generation of internal UART interrupts and the external data

operations. These latencies are negligible at the data transmis-

sion rates for the UART.

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing

Figure 33 describes UART port receive and transmit operations.

The maximum baud rate is PCLK/16 where PCLK = 1/t_PCLK. As

shown in Figure 33 there is some latency between the

Table 39. UART Port

Parameter

Min

Max

Unit

ns

Timing Requirement

1

t_TXD

Incoming Data Pulse Width

16t_PCLK–1

Switching Characteristic

1

t_RXD

Incoming Data Pulse Width

ns

¹UART signals TXD and RXD are routed through DPI P14-1 pins using the SRU.

DPI_P14–1

[RxD]

DATA (5–8)

STOP

RECEIVE

t_RXD

INTERNAL

UART RECEIVE

INTERRUPT

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

START

DPI_P14–1

[TxD]

DATA (5–8)

STOP (1–2)

TRANSMIT

t_TXD

INTERNAL

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

UART TRANSMIT

INTERRUPT

Figure 33. UART Port—Receive and Transmit Timing

Rev. D

| Page 46 of 56 | April 2013

ADSP-21371/ADSP-21375

TWI Controller Timing

Table 40 and Figure 34 provide timing information for the TWI

interface. Input signals (SCL, SDA) are routed to the

DPI_P14–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DPI_P14–1 pins.

Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices¹

Standard Mode

Fast Mode

Max

400

Parameter

f_SCL

Min

Max

Min

Unit

SCL Clock Frequency

0

100

0

kHz

t_HDSTA

Hold Time (repeated) Start Condition. After This

Period, the First Clock Pulse is Generated.

4.0

4.7

4.0

4.7

0

0.6

1.3

0.6

0

μs

ns

μs

ns

t_LOW

Low Period of the SCL Clock

t_HIGH

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTO

t_BUF

High Period of the SCL Clock

Setup Time for a Repeated Start Condition

Data Hold Time for TWI-Bus Devices

Data Setup Time

250

4.0

4.7

100

0.6

1.3

0

Setup Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

t_SP

Pulse Width of Spikes Suppressed By the Input Filter N/A

N/A

50

¹All values referred to V_IHminand V_ILmaxlevels. For more information, see Electrical Characteristics on page 17.

DPI_P14–1

SDA

t_BUF

t_SUDAT

t_HDSTA

t_SP

t_LOW

DPI_P14–1

SCL

t_SUSTA

t_SUSTO

t_HDSTA

t_HIGH

S

Sr

P

S

t_HDDAT

Figure 34. Fast and Standard Mode Timing on the TWI Bus

Rev. D

| Page 47 of 56 | April 2013

ADSP-21371/ADSP-21375

JTAG Test Access Port and Emulation

Table 41. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_CK

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

5

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

18

4 × t_CK

7

ns

2

t_DSYS

t_CK2 + 7

¹System Inputs = ADDR15–0, CLKCFG1–0, RESET, BOOT_CFG1–0, DAI_Px, and FLAG3–0.

²System Outputs = DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 35. IEEE 1149.1 JTAG Test Access Port

Rev. D

| Page 48 of 56 | April 2013

ADSP-21371/ADSP-21375

CAPACITIVE LOADING

OUTPUT DRIVE CURRENTS

Figure 36 shows typical I-V characteristics for the output driv-

ers of the processors. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 37). Figure 41 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 39, Figure 40, and Figure 41 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

40

V

OH

30

3.3V, 25°C

20

3.47V, -45°C

12

10

0

3.11V, 125°C

RISE

y = 0.0467x + 1.6323

FALL

-

10

8

3.11V, 125°C

20

6

3.3V, 25°C

3.5

V

-

30

OL

3.47V,

-

45°C

4

40

y = 0.045x + 1.524

0

0.5

1.0

1.5

2.0

2.5

3.0

SWEEP (V

) VOLTAGE (V)

DDEXT

2

0

Figure 36. Typical Drive at Junction Temperature

50

100

150

200

250

0

LOAD CAPACITANCE (pF)

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 15 on Page 22 through Table 41 on Page 48. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 37.

Figure 39. Typical Output Rise/Fall Time (20% to 80%,

V_DDEXT= Max)

12

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 38. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

RISE

10

y = 0.049x + 1.5105

FALL

8

6

y = 0.0482x + 1.4604

TO

OUTPUT

4

ꢀꢁȍ

V

LOAD

30pF

2

0

50

100

150

200

250

Figure 37. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

LOAD CAPACITANCE (pF)

Figure 40. Typical Output Rise/Fall Time (20% to 80%,

V_DDEXT= Min)

INPUT

OR

1.5V

OUTPUT

Figure 38. Voltage Reference Levels for AC Measurements

Rev. D

| Page 49 of 56 | April 2013

ADSP-21371/ADSP-21375

Values of _JBare provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 42 are modeled values.

10

8

Table 42. Thermal Characteristics for 208-Lead LQFP

E_PAD (With Exposed Pad Soldered to PCB)

Y = 0.0488X - 1.5923

6

4

Parameter

_JA

Condition

Typical

17.1

14.7

14.0

9.6

Unit

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

C/W

2

0

_JMA

_JC

-2

-4

_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.23

0.39

0.45

11.5

11.2

11.0

_JMT

_JB

_JMB

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 41. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

THERMAL CHARACTERISTICS

The processor is rated for performance over the temperature

range specified in Operating Conditions on Page 16.

Table 42 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6 and the junction-to-board measure-

ment complies with JESD51-8. Test board design complies with

JEDEC standard JESD51-7 (LQFP_EP). The junction-to-case

measurement complies with MIL- STD-883. All measurements

use a 2S2P JEDEC test board.

To determine the junction temperature of the device while on

the application PCB, use

T

= T

+   P 

CASE JT

D

J

where:

T_J= junction temperature C

T

_CASE= case temperature (C) measured at the top center of the

package

_JT= junction-to-top (of package) characterization parameter

is the Typical value from Table 42.

P_D= power dissipation

Values of _JAare provided for package comparison and PCB

design considerations. _JAcan be used for a first order approxi-

mation of T_Jby the equation

T

= T +   P 

A JA D

J

where:

T_A= ambient temperature C

Values of _JCare provided for package comparison and PCB

design considerations when an external heatsink is required.

Rev. D

| Page 50 of 56 | April 2013

ADSP-21371/ADSP-21375

208-LEAD LQFP_EP PINOUT

Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)

Pin No.

1

Signal

V_DDINT

Pin No.

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

Signal

V_DDINT

Pin No.

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

Signal

Pin No.

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Signal

V_DDINT

2

DATA28

DATA27

GND

V_DDINT

3

V_DDEXT

GND

4

ADDR0

ADDR2

ADDR1

ADDR4

ADDR3

ADDR5

GND

SDCAS

V_DDINT

5

V_DDEXT

SDRAS

V_DDINT

6

DATA26

DATA25

DATA24

DATA23

GND

SDCKE

V_DDINT

7

SDWE

TDI

8

WR

TRST

9

SDA10

TCK

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

GND

V_DDINT

V_DDEXT

V_DDINT

DATA22

DATA21

DATA20

V_DDEXT

GND

SDCLK

TMS

V_DDEXT

GND

CLK_CFG0

BOOT_CFG0

CLK_CFG1

EMU

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

GND

V_DDINT

RD

GND

ACK

DATA19

DATA18

V_DDINT

FLAG3

BOOT_CFG1

TDO

FLAG2

FLAG1

DAI_P4 (SFS0)

DAI_P2 (SD0B)

DAI_P3 (SCLK0)

DAI_P1 (SD0A)

V_DDEXT

GND

V_DDINT

FLAG0

DATA17

V_DDINT

GND

DAI_P20 (SFS5)

GND

V_DDEXT

GND

ADDR11

ADDR12

ADDR13

GND

V_DDINT

GND

V_DDEXT

V_DDINT

DATA16

DATA15

DATA14

DATA13

DATA12

V_DDEXT

DAI_P19 (SCLK5)

DAI_P18 (SD5B)

DAI_P17 (SD5A)

DAI_P16 (SD4B)

DAI_P15 (SD4A)

DAI_P14 (SFS3)

DAI_P13 (SCLK3)

DAI_P12 (SD3B)

V_DDINT

GND

V_DDINT

DPI_P14 (TIMER1)

DPI_P13 (TIMER0)

DPI_P12 (TWI_CLK)

DPI_P11 (TWI_DATA)

DPI_P10 (UART0RX)

DPI_P09 (UART0TX)

DPI_P08 (SPIFLG3)

DPI_P07 (SPIFLG2)

V_DDEXT

NC

GND

CLKIN

XTAL

GND

V_DDINT

V_DDEXT

GND

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

V_DDEXT

V_DDINT

V_DDEXT

ADDR14

GND

V_DDINT

V_DDEXT

GND

ADDR15

ADDR16

ADDR17

ADDR18

GND

DAI_P11 (SD3A)

DAI_P10 (SD2B)

DAI_P8 (SFS1)

DAI_P9 (SD2A)

DAI_P6 (SD1B)

DAI_P7 (SCLK1)

DPI_P06 (SPIFLG1)

DPI_P05 (SPIFLG0)

DPI_P04 (SPIDS)

DPI_P03 (SPICLK)

DPI_P01 (SPIMOSI)

DPI_P02 (SPIMISO)

GND

V_DDINT

DATA4

V_DDEXT

Rev. D

| Page 51 of 56 | April 2013

ADSP-21371/ADSP-21375

Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

45

DATA5

97

ADDR19

149

DAI_P5 (SD1A)

201

RESETOUT/

RUNRSTIN

46

47

48

49

50

51

52

DATA2

DATA3

DATA0

DATA1

V_DDEXT

98

ADDR20

ADDR21

ADDR23

ADDR22

MS1

150

151

152

153

154

155

156

V_DDEXT

GND

V_DDINT

GND

V_DDINT

GND

V_DDINT

202

203

204

205

206

207

208

RESET

V_DDEXT

99

100

101

102

103

104

GND

DATA30

DATA31

DATA29

V_DDINT

GND

MS0

V_DDINT

Rev. D

| Page 52 of 56 | April 2013

ADSP-21371/ADSP-21375

Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)

Pin No.

1

Signal

V_DDINT

NC

Pin No.

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

Signal

V_DDINT

Pin No.

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

Signal

Pin No.

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Signal

V_DDINT

2

GND

V_DDINT

3

NC

V_DDEXT

GND

4

GND

V_DDEXT

NC

ADDR0

ADDR2

ADDR1

ADDR4

ADDR3

ADDR5

GND

SDCAS

V_DDINT

5

SDRAS

V_DDINT

6

SDCKE

V_DDINT

7

NC

SDWE

TDI

8

NC

WR

TRST

9

NC

SDA10

TCK

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

GND

V_DDINT

NC

GND

V_DDINT

V_DDEXT

V_DDINT

GND

SDCLK

TMS

NC

V_DDEXT

GND

CLK_CFG0

BOOT_CFG0

CLK_CFG1

EMU

NC

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

GND

V_DDINT

NC

RD

NC

ACK

NC

FLAG3

BOOT_CFG1

TDO

NC

FLAG2

NC

FLAG1

DAI_P4 (SFS0)

DAI_P2 (SD0B)

DAI_P3 (SCLK0)

DAI_P1 (SD0A)

V_DDEXT

NC

V_DDINT

FLAG0

NC

GND

DAI_P20 (SFS5)

GND

V_DDINT

GND

V_DDINT

GND

NC

V_DDEXT

ADDR11

ADDR12

ADDR13

GND

V_DDINT

GND

V_DDEXT

V_DDINT

DAI_P19 (SCLK5)

DAI_P18 (SD5B)

DAI_P17 (SD5A)

DAI_P16 (SD4B)

DAI_P15 (SD4A)

DAI_P14 (SFS3)

DAI_P13 (SCLK3)

DAI_P12 (SD3B)

V_DDINT

GND

DATA15

DATA14

DATA13

DATA12

V_DDEXT

GND

V_DDINT

GND

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

V_DDEXT

GND

V_DDINT

DATA4

V_DDINT

DPI_P14 (TIMER1)

DPI_P13 (TIMER0)

DPI_P12 (TWI_CLK)

DPI_P11 (TWI_DATA)

DPI_P10 (UART0RX)

DPI_P09 (UART0TX)

DPI_P08 (SPIFLG3)

DPI_P07 (SPIFLG2)

V_DDEXT

NC

GND

CLKIN

XTAL

V_DDEXT

GND

V_DDINT

V_DDEXT

ADDR14

GND

V_DDINT

V_DDEXT

GND

ADDR15

ADDR16

ADDR17

ADDR18

GND

DAI_P11 (SD3A)

DAI_P10 (SD2B)

DAI_P8 (SFS1)

DAI_P9 (SD2A)

DAI_P6 (SD1B)

DAI_P7 (SCLK1)

DPI_P06 (SPIFLG1)

DPI_P05 (SPIFLG0)

DPI_P04 (SPIDS)

DPI_P03 (SPICLK)

DPI_P01 (SPIMOSI)

DPI_P02 (SPIMISO)

V_DDEXT

Rev. D

| Page 53 of 56 | April 2013

ADSP-21371/ADSP-21375

Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

Pin No.

Signal

45

DATA5

97

ADDR19

149

DAI_P5 (SD1A)

201

RESETOUT/

RUNRSTIN

46

47

48

49

50

51

52

DATA2

DATA3

DATA0

DATA1

V_DDEXT

98

ADDR20

ADDR21

ADDR23

ADDR22

MS1

150

151

152

153

154

155

156

V_DDEXT

GND

V_DDINT

GND

V_DDINT

GND

V_DDINT

202

203

204

205

206

207

208

RESET

V_DDEXT

99

100

101

102

103

104

GND

DATA30

DATA31

DATA29

V_DDINT

GND

MS0

V_DDINT

Rev. D

| Page 54 of 56 | April 2013

ADSP-21371/ADSP-21375

PACKAGE DIMENSIONS

The processors are available in a 208-lead RoHS compliant

LQFP_EP package.

30.20

30.00 SQ

29.80

25.50

REF

28.10

28.00 SQ

27.90

1.60 MAX

0.75

0.60

8.712

REF

0.45

208

157

156

157

156

208

1

1.00 REF

PIN 1

SEATING

PLANE

8.890

REF

TOP VIEW

(PINS DOWN)

*

EXPOSED

PAD

1.45

1.40

1.35

0.20

0.15

0.09

0.15

0.10

0.05

7°

3.5°

0°

BOTTOM VIEW

(PINS UP)

0.08

COPLANARITY

105

104

105

104

52

53

VIEW A

0.27

0.22

0.17

VIEW A

ROTATED 90° CCW

0.50

BSC

LEAD PITCH

COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD

*

NOTE:

THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO GND.

THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS THE SAME SIZE

AS THE EXPOSED PAD. THE GND PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN THE PCB

WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.

Figure 42. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-208-1)

Dimensions shown in millimeters

Rev. D

| Page 55 of 56 | April 2013

ADSP-21371/ADSP-21375

AUTOMOTIVE PRODUCTS

Some ADSP-21371/ADSP-21375 models are available for automotive applications with controlled manufacturing. Note that this special

model may have specifications that differ from the general release models.

The automotive grade products shown in Table 45 are available for use in automotive applications. Contact your local ADI account repre-

sentative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS

compliant.

Table 45. Automotive Products

Temperature

Range¹

Instruction

Rate

On-Chip

SRAM

Model

ROM

Package Description

208-Lead LQFP_EP

Package Option

SW-208-1

AD21371WBSWZ2xx

AD21371WYSWZ1xx

AD21375WBSWZ2xx

AD21375WYSWZ1xx

–40ºC to 85ºC

–40ºC to 105ºC

–40ºC to 85ºC

–40ºC to 105ºC

266 MHz

200 MHz

266 MHz

200 MHz

1M bit

4M bit

2M bit

1M bit

SW-208-1

0.5M bit

SW-208-1

¹Referenced temperature is ambient temperature.

ORDERING GUIDE

Temperature

Instruction

Rate

On-Chip

Model

Notes Range¹

SRAM

1M bit

0.5M bit

ROM

Package Description

208-Lead LQFP_EP

Package Option

SW-208-1

2

ADSP-21371KSWZ-2A

ADSP-21371KSWZ-2B

ADSP-21371BSWZ-2B

ADSP-21375KSWZ-2B

ADSP-21375BSWZ-2B

0ºC to +70ºC

–40ºC to +85ºC

0ºC to +70ºC

–40ºC to +85ºC

266 MHz

4M bit

2M bit

2

SW-208-1

2, 3

2

SW-208-1

2, 3

SW-208-1

¹Referenced temperature is ambient temperature.

²Z = RoHS Compliant Part.

³Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software.

For a complete list, visit our website at www.analog.com/SHARC.

registered trademarks are the property of their respective owners.

D07170-0-4/13(D)

Rev. D

| Page 56 of 56 | April 2013


型号：	ADSP-21371KSWZ-2A
厂家：	ADI
描述：	32-BIT, 16.67MHz, OTHER DSP, PQFP208, ROHS COMPLIANT, MS-026BJB-HD, LQFP-208 时钟外围集成电路
文件：	总56页 (文件大小：1121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21371KSWZ-2A [ADI]

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