ADM8830ACP-REEL [ADI]
IC SWITCHED CAPACITOR REGULATOR, 140 kHz SWITCHING FREQ-MAX, QCC20, 4 X 4 MM, MO-220VGGD-1, LFCSP-20, Switching Regulator or Controller;
| 型号： | ADM8830ACP-REEL |
| 厂家： | 
ADI |
| 描述： | IC SWITCHED CAPACITOR REGULATOR, 140 kHz SWITCHING FREQ-MAX, QCC20, 4 X 4 MM, MO-220VGGD-1, LFCSP-20, Switching Regulator or Controller 开关 |
| 文件： | 总8页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Charge Pump Regulator
for Color TFT Panel
a
ADM8830
FEATURES
FUNCTIONAL BLOCK DIAGRAM
3 Output Voltages (+5.1 V, +15.3 V, –10.2 V) from
One 3 V Input Supply
Power Efficiency Optimized for Use with TFT in
Mobile Phones
C5
2.2ꢀF
V
CC
C1+
Low Quiescent Current
Low Shutdown Current (<1 ꢀA)
Fast Transient Response
Shutdown Function
Power Saving during Blanking Period
Option to Use External LDO
VOLTAGE
C1
C1–
ADM8830
DOUBLER
2.2ꢀF
VOUT
LDO IN
OSCILLATOR
CLKIN
C6
2.2ꢀF
LDO
VOLTAGE
REGULATOR
SCAN/BLANK
LDO_ON/OFF
+5VOUT
+5VIN
CONTROL
LOGIC
+5.1V
C7
2.2ꢀF
APPLICATIONS
Handheld Instruments
TFT LCD Panels
C2+
DOUBLE
TRIPLE
C2
1ꢀF
C2–
C3+
C3–
Cellular Phones
TIMING
GENERATOR
C3
1ꢀF
+15VOUT
+15.3V
C8
1ꢀF
VOLTAGE
TRIPLER
C4+
C4
VOLTAGE
INVERTER
C4–
1ꢀF
SHUTDOWN
CONTROL
DISCHARGE
SHDN
–10VOUT
–10.2V
C9
GND
1ꢀF
GENERAL DESCRIPTION
the charge pumps during scanning mode where the current is highest.
During blanking periods, the ADM8830 switches to use an external,
lower frequency clock. This allows the user to vary the frequency and
maximize power efficiency during blanking periods. The tolerances
on the output voltages are seamlessly maintained when switching
from scanning mode to blanking mode or vice versa.
The ADM8830 is a charge pump regulator used for color thin film
transistor (TFT) liquid crystal displays (LCD). Using charge
pump technology, the device can be used to generate three output
voltages (+5.1 V 2%, +15.3 V 4%, –10.2 V 4%) from a
single 3 V input supply. These outputs are then used to provide
supplies for the LCD controller (5.1 V) and the gate drives for
the transistors in the panel (+15.3 V and –10.2 V). Only a few
external capacitors are needed for the charge pumps. An efficient
low dropout voltage regulator also ensures that the power efficiency
is high and provides a low ripple 5.1 V output. This LDO can be
shut down and an external LDO used to regulate the 5 V dou-
bler output and drive the input to the charge pump section, which
generates the +15.3 V and –10.2 V outputs if so required by the user.
The ADM8830 has a number of power saving features, including
low power shutdown and reduced quiescent current consumption
during the blanking periods mentioned above. The 5.1 V output
consumes the most power, so power efficiency is also maximized
on this output with an oscillator enabling scheme (Green Idle™).
This effectively senses the load current that is flowing and turns
on the charge pump only when charge needs to be delivered to
the 5 V pump doubler output.
The ADM8830 has an internal 100 kHz oscillator for use in scanning
mode, but the part must be clocked by an external clock source in
blanking (low current) mode. The internal oscillator is used to clock
The ADM8830 is fabricated using CMOS technology for minimal
power consumption. The part is packaged in 20-lead LFCSP
(lead frame chip scale package) and TSSOP packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADM8830–SPECIFICATIONS (CV7 ==2.22.6ꢀVFt,oC32.,6CV3,, TC4=, C–84,0Cꢁ9C=to1+ꢀ85Fꢁ,CC,LuKnINles=s1otkhHezrwinisBelannokteindg, CM1o,dCe5.), C6,
CC
A
Parameter
Min
Typ
Max
Unit
Test Conditions
INPUT VOLTAGE, VCC
SUPPLY CURRENT, ICC
2.6
3.6
V
150
70
400
140
1
µA
µA
µA
Unloaded, Scanning Period
Unloaded, Blanking Period
Shutdown Mode, TA = 25°C
+5.1 V OUTPUT
Output Voltage
Output Current
5.0
5.1
4
5
50
80
70
10
5
5.2
5
8
V
IL = 10 µA to 8 mA
Scanning Period
Scanning Period, VCC > 2.7 V
Blanking Period
VCC = 3 V, IL = 5 mA (Scanning)
VCC = 3 V, IL = 200 µA (Blanking)
8 mA Load
mA
mA
µA
%
%
mV p-p
µs
200
Power Efficiency
Output Ripple
Transient Response
IL Stepped from 10 µA to 8 mA
+15.3 V OUTPUT
Output Voltage
Output Current
14.4
15.3
50
1
15.6
100
10
V
µA
µA
IL = 1 µA to 100 µA
Scanning Period
Blanking Period
IL = 100 µA
Output Ripple
50
mV p-p
–10.2 V OUTPUT
Output Voltage
Output Current
–10.4
–100
–10
–10.2
–50
–1
–9.6
V
µA
µA
IL = –1 µA to –100 µA
Scanning Period
Blanking Period
IL = –100 µA
Output Ripple
50
mV p-p
POWER EFFICIENCY
(+15.3 V and –10.2 V Outputs)
90
80
%
%
Relative to 5.1 V Output, IL = 100 µA (Scanning)
Relative to 5.1 V Output, IL =10 µA (Blanking)
CHARGE PUMP FREQUENCY 60
100
140
kHz
Scanning Period
CONTROL PINS
SHDN
Input Voltage, VSHDN
0.3 VCC
V
V
SHDN Low = Shutdown Mode
SHDN High = Normal Mode
0.7 VCC
Digital Input Current
Digital Input Capacitance*
SCAN/BLANK
1
10
µA
pF
Input Voltage
0.3 VCC
V
Low = BLANK Period
0.7 VCC
0.7 VCC
V
µA
pF
High = SCAN Period
Digital Input Current
Digital Input Capacitance*
LDO_ON/OFF
1
10
Input Voltage
0.3 VCC
V
V
Low = External LDO
High = Internal LDO
Digital Input Current
Digital Input Capacitance*
CLKIN
1
10
µA
pF
Minimum Frequency
Input Voltage
VIL
0.9
1
kHz
Duty Cycle = 50%, Rise/Fall Times = 20 ns
0.3 VCC
V
VIH
0.7 VCC
V
µA
pF
Digital Input Current
Digital Input Capacitance*
1
10
*Guaranteed by design. Not 100% production tested.
Specifications are subject to change without notice.
–2–
REV. A
ADM8830
(VCC = 2.6 V to 3.6 V, TA = –40؇C to +85؇C, unless otherwise noted, C1, C5, C6,
C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in Blanking Mode.)
TIMING SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER-UP SEQUENCE
+5 V Rise Time, tR5V
+15 V Rise Time, tR15V
–10 V Fall Time, tF10V
Delay between –10 V Fall
and +15 V, tDELAY
300
8
12
µs
10% to 90%, Figure 2
10% to 90%, Figure 2
90% to 10%, Figure 2
ms
ms
3
ms
Figure 2
POWER-DOWN SEQUENCE
+5 V Fall Time, tF5V
+15 V Fall Time, tF15V
–10 V Rise Time, tR10V
75
40
40
ms
ms
ms
90% to 10%, Figure 2
90% to 10%, Figure 2
10% to 90%, Figure 2
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
THERMAL CHARACTERISTICS
20-Lead TSSOP Package:
θ
JA = 72°C/W
20-Lead LFCSP Package:
JA = 31°C/W
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.0 V
Input Voltage to Digital Inputs . . . . . . . . . . –0.3 V to +4.0 V
Output Short Circuit Duration to GND . . . . . . . . . . . 10 sec
Output Voltage
θ
+5.1 V Output . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
–10.2 V Output . . . . . . . . . . . . . . . . . . . . . –12 V to +0.3 V
+15.3 V Output . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.55 W
(Derate 33 mW/°C above 25°C)
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I
*This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for
extended periods of time may affect reliability.
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
ADM8830ACP
ADM8830ARU
–40°C to +85°C
–40°C to +85°C
Lead Frame Chip Scale Package
Thin Shrink Small Outline Package
CP-20
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADM8830 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–3–
REV. A
ADM8830
PIN CONFIGURATIONS
TSSOP
LFCSP
1
2
20
19
18
17
16
15
14
13
12
11
C1–
C1+
GND
–10VOUT
C4+
3
V
CC
VOUT
LDO_IN
+5VOUT
+5VIN
4
C4–
PIN 1
15 C4–
14 C2+
13 C2–
12 C3+
11 C3–
V
1
CC
INDICATOR
5
C2+
ADM8830
TOP VIEW
(Not to Scale)
VOUT 2
LDO_IN 3
+5VOUT 4
+5VIN 5
ADM8830
TOP VIEW
6
C2–
7
C3+
8
C3–
LDO_ON/OFF
SHDN
9
+15VOUT
CLKIN
10
SCAN/BLANK
PIN FUNCTION DESCRIPTIONS
Function
Pin No.
TSSOP
LFCSP
Mnemonic
1, 2
19, 20
C1–, C1+
External capacitor C1 is connected between these pins. A 2.2 µF capacitor is
recommended.
3
4
5
6
7
8
1
2
3
4
5
6
VCC
Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 µF
decoupling capacitor.
VOUT
Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 µF
capacitor to ground is required on this pin.
Voltage Regulator Input. The user has the option to bypass this circuit using the
LDO_ON/OFF pin.
+5.1 V Output Pin. This is derived by doubling and regulating the +3 V supply.
A 2.2 µF capacitor to ground is required on this pin to stabilize the regulator.
+5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter
charge pump circuits.
Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for
regulation of the 5 V voltage doubler output. A logic low isolates the internal
LDO from the rest of the charge pump circuits. This allows the use of an exter-
nal LDO to regulate the 5 V voltage doubler output. The output of this LDO is
then fed back into the voltage tripler and doubler/inverter circuits of the ADM8830.
LDO_IN
+5VOUT
+5VIN
LDO_ON/OFF
9
7
8
SHDN
Digital Input. 3 V CMOS logic. Active low shutdown control. This shuts down
the timing generator and enables the discharge circuit to dissipate the charge on
the voltage outputs, thus driving them to 0 V.
Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high
current) mode and the charge pump is driven by the internal oscillator. A logic
low places the part in blanking (low current) mode and the charge pump is driven by
the (slower) external oscillator. This is a power saving feature on the ADM8830.
10
SCAN/BLANK
11
9
CLKIN
External CLOCK Input. During a blanking period, the oscillator circuit selects
this pin to drive the charge pump circuit. This is at a lower frequency than the
internal oscillator, resulting in lower quiescent current consumption, thus
saving power.
12
10
+15VOUT
C3–, C3+
C2–, C2+
C4–, C4+
–10VOUT
GND
+15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output.
A 1 µF capacitor is required on this pin.
13, 14
15, 16
17, 18
19
11, 12
13, 14
15, 16
17
External capacitor C3 is connected between these pins. A 1 µF capacitor is
recommended.
External capacitor C2 is connected between these pins. A 1 µF capacitor is
recommended.
External capacitor C4 is connected between these pins. A 1 µF capacitor is
recommended.
–10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V
regulated output. A 1 µF capacitor is required on this pin.
20
18
Device Ground Pin.
–4–
REV. A
Typical Performance Characteristics–ADM8830
80
70
60
50
40
30
20
10
5.0752
5.104
5.102
5.100
5.098
5.0750
5.0748
5.0746
5.0744
5.0742
5.0740
5.0738
5.0736
5.0734
5.096
5.094
5.092
5.090
100
1000
10000
0
1
2
3
I
4
5
6
7
8
10 30 50 70 90 110 130 150 170 190
BLANKING FREQUENCY – Hz
– mA
OUTPUT CURRENT – ꢀA
LOAD
TPC 1. LDO Efficiency in Blanking
Mode with VCC = 3 V
TPC 2. LDO Output Voltage (Unloaded)
vs. Blanking Mode Frequency
TPC 3. LDO O/P Voltage vs. Load Current
in Scanning Mode, VCC = 3.3 V
100
90
100
90
80
70
60
50
40
85
84
83
82
80
81
80
79
78
70
60
2
4
6
8
10
0
20
40
60
80
100
0
1
2
3
4
5
6
7
8
OUTPUT CURRENT – ꢀA
OUTPUT CURRENT – ꢀA
OUTPUT CURRENT – mA
TPC 5. +15 V/–10 V Efficiency vs.
Output Current in Blanking Mode,
VCC = 3 V
TPC 6. +15 V/–10 V Efficiency vs.
Output Current in Scanning
Mode, VCC = 3 V
TPC 4. LDO Efficiency in Scanning
Mode with VCC = 3 V
300
250
200
5.30
5.25
V
OUT
5.20
DEVICE 1 @ +85ꢁC
5.15
I
(SCAN)
CC
DEVICE 1 @ +25ꢁC
5V OUPUT RIPPLE
5.10
150
100
50
5.05
V
RIPPLE
CC
DEVICE 1 @ –40ꢁC
I
(BLANK)
CC
5.00
4.95
4.90
0
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
V
–V
V
–V
CC
CC
TPC 7. LDO Variation over Supply
and Temperature
TPC 8. Supply Current vs. Voltage
TPC 9. Output Ripple on LDO
(5 V Output)
–5–
REV. A
ADM8830
+15V OUTPUT
LOAD DISABLE
5V OUTPUT
LOAD ENABLE
5V OUTPUT
–10V OUTPUT
5VOUT
TPC 10. 5 V Output Transient
Response for Max Load Current
TPC 11. 5 V Output Transient
Response, Load Disconnected
TPC 12. +15 V and –10 V Outputs at
Power-Up
20.1
+15V OUTPUT
20.0
19.9
19.8
19.7
19.6
–10V OUTPUT
5VOUT
19.5
19.4
60
40
TEMPERATURE – ꢁC
80
–40
–20
0
20
TPC 13. +15 V and –10 V Outputs at
Power-Down (Unloaded)
TPC 14. Power Dissipation over
Temperature, VCC = 3.6 V, Scanning
Mode with All O/Ps at Maximum Load
–6–
REV. A
ADM8830
SCANNING AND BLANKING
V
A TFT LCD panel is essentially made up of a bank of capaci-
tors, each representing a pixel in the display. These capacitors
store different levels of charge, depending on the amount of
luminescence required for a given pixel. When a picture is being
displayed on the panel, a scan of all the pixel capacitors is
performed, placing different levels of charge on each in order to
create the image. The process of updating the display like this is
called “scanning.” Once scanned, an image will be held by pixel
capacitance and the controller and source line drivers can be put
into a low power mode. This low power mode is referred to as the
blanking mode on the ADM8830. Over a finite period of time, this
pixel charge will leak and the capacitors will have to be refreshed
in order to maintain the image.
CC
SHDN
tR5V
90%
10%
tF5V
+5V
tR15V
tF15V
+15V
–10V
tDELAY
–3V
90%
10%
tR10V
tF10V
LOAD
The ADM8830 caters to the two modes of operation described
above as follows. When the TFT LCD panel is in scanning
mode, a logic high on the SCAN/BLANK input places the
device in high current power mode, providing extra power
(extra current) to the LCD controller and the source line drivers.
If the panel continues to be updated (as when a moving picture is
being displayed), then the ADM8830 can be continually operated
in scanning mode. If the same image is kept on the panel, a logic
low is applied to the SCAN/BLANK input and the ADM8830
enters blanking (low current) mode. Depending on how often the
image is being updated, the ADM8830 can be operated with a
variable SCAN/BLANK duty cycle. This helps to maximize
power efficiency and therefore extends the battery life.
SCAN/BLANK
EXTERNAL CLOCK
Figure 2. Power Sequence
TRANSIENT RESPONSE
The ADM8830 features extremely fast transient response, making
it very suitable for fast image updates on TFT LCD panels. This
means that even under changing load conditions there is still very
effective regulation of the 5 V output. TPCs 10 and 11 show how
the 5.1 V output responds when a maximum load is dynamically
connected and disconnected. Note that the output settles within
5 µs to less than 1% of the output level.
POWER SEQUENCING
EXTERNAL CLOCK
The gate drive supplies must be sequenced such that the –10 V
supply is up before the +15 V supply for the TFT panel to
power up correctly. The ADM8830 controls this sequence. When
the device is turned on (a logic high on SHDN), the ADM8830
allows the –10 V output to ramp immediately but holds off
the +15 V output. It continues to do this until the negative
output has reached –3 V. At this point, the positive output is
enabled and allowed to ramp up to +15 V. This sequence is
highlighted in Figure 2.
The ADM8830 has an internal 100 kHz oscillator, but an external
clock source can also be used to clock the part. This clock
source must be applied to the CLKIN pin. Power is saved
during blanking periods by disabling the internal oscillator and
switching to the lower frequency external clock source. To
achieve optimum performance of the charge pump circuitry, it is
important that the duty cycle of the external clock source be
50% and that the rise and fall times be less than 20 ns.
90%
10%
tR
tF
tR: RISETIME
tF: FALLTIME
tH
tH
tT
@ 100% = DUTY CYCLE
tT
Figure 1. Duty Cycle of External Clock
SOLDER MASK
BOARD METALLIZATION
Figure 3. Suggested LFCSP 4 ϫ 4 20-Lead Land Pattern
REV. A
–7–
ADM8830
OUTLINE DIMENSIONS
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8ꢀ
0ꢀ
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-153AC
20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm ꢁ 4 mm Body
(CP-20)
Dimensions shown in millimeters
0.60
MAX
4.0
BSC SQ
0.25 MIN
0.60
MAX
16
15
20
1
5
PIN 1
2.25
2.10 SQ
1.95
INDICATOR
3.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
11
10
0.75
0.60
0.50
6
0.80 MAX
0.65 NOM
0.30
0.23
0.18
12ꢀ MAX
0.90 MAX
0.85 NOM
0.05
0.01
0.00
SEATING
PLANE
COPLANARITY
0.08
0.50
BSC
0.20
REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Revision History
Location
Page
3/03—Data Sheet changed from REV. SpA to REV. A.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to TPC 12 and TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
11/02—Data Sheet changed from REV. 0 to REV. SpA.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to captions of TPCs 2, 3, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to caption of TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Added TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–8–
REV. A
相关型号：
ADM8832ACP
SWITCHED CAPACITOR REGULATOR, 140 kHz SWITCHING FREQ-MAX, QCC20, 4 X 4 MM, MO-220VGGD-1, LFCSP-20
ROCHESTER
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