ADL5812-EVALZ [ADI]
Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier; 双高IP3 , 700 MHz至2800 MHz的双平衡无源混频器, IF放大器和宽带LO放大器![ADL5812-EVALZ](http://pdffile.icpdf.com/pdf1/p00189/img/icpdf/ADL581_1071336_icpdf.jpg)
型号: | ADL5812-EVALZ |
厂家: | ![]() |
描述: | Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier |
文件: | 总28页 (文件大小:693K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Dual High IP3, 700 MHz to 2800 MHz, Double Balanced,
Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADL5812
FUNCTIONAL BLOCK DIAGRAM
FEATURES
RF frequency: 700 MHz to 2800 MHz continuous
LO frequency: 250 MHz to 2800 MHz, high-side or
low-side inject
40
39
38
37
36
35
34
33
32
31
RF1
RFCT1
NC
1
2
30
29
28
27
26
V1LO1
NC
IF range: 30 MHz to 450 MHz
Power conversion gain of 6.7 dB at 1900 MHz
SSB noise figure of 11.6 dB at 1900 MHz
Input IP3 of 27.2 dBm at 1900 MHz
Input P1dB of 12.5 dBm at 1900 MHz
Typical LO drive of 0 dBm
ADL5812
3
NC
NC
4
NC
NC
5
LOIP
BIAS
GEN
NC
6
25 LOIN
24 LE
Single-ended, 50 Ω RF port
NC
7
Single-ended or balanced LO input port
Single-supply operation: 3.6 V to 5.0 V
Serial port interface control on all functions
Exposed paddle 6 mm × 6 mm, 40-lead LFCSP package
NC
8
23 DATA
SERIAL
PORT
INTERFACE
RFCT2
RF2
CLK
9
22
21
V2LO1
10
11
12
13
14
15
16
17
18
19
20
APPLICATIONS
Figure 1.
Multiband/multistandard cellular base station diversity
receivers
Wideband radio link diversity downconverters
Multimode cellular extenders and broadband receivers
GENERAL DESCRIPTION
The ADL5812 uses revolutionary new broadband, square wave
limiting, local oscillator (LO) amplifiers to achieve an
wideband applications where in-band blocking signals may
otherwise result in the degradation of dynamic range. Blocker
noise figure performance is comparable to narrow-band passive
mixer designs. High linearity IF buffer amplifiers follow the
passive mixer cores, yielding typical power conversion gains of
6.7 dB, and can be used with a wide range of output
impedances. For low voltage applications, the ADL5812 is
capable of operation at voltages down to 3.6 V with
substantially reduced current. Two logic bits are provided to
individually power down (1.5 mA for both channels) the two
channels as desired.
unprecedented radio frequency (RF) bandwidth of 700 MHz
to 2800 MHz. Unlike conventional narrow-band sine wave LO
amplifier solutions, this permits the LO to be applied either
above or below the RF input over an extremely wide bandwidth.
Because energy storage elements are not used, the dc current
consumption also decreases with decreasing LO frequency.
The ADL5812 uses highly linear, doubly balanced, passive mixer
cores along with integrated RF and LO balancing circuits to
allow single-ended operation. The ADL5812 incorporates
programmable RF baluns, allowing optimal performance over
a 700 MHz to 2800 MHz RF input frequency. The balanced
passive mixer arrangement provides outstanding LO-to-RF and
LO-to-IF leakages, excellent RF-to-IF isolation, and excellent
intermodulation performance over the full RF bandwidth.
All features of the ADL5812 are controlled via a 3-wire serial
port interface, resulting in optimum performance and
minimum external components.
The ADL5812 is fabricated using a BiCMOS high performance
IC process. The device is available in a 40-lead, 6mm × 6mm,
LFCSP package and operates over a −40°C to +85°C
The balanced mixer cores also provide extremely high input
linearity, allowing the device to be used in demanding
temperature range. An evaluation board is also available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADL5812
TABLE OF CONTENTS
Features .............................................................................................. 1
RF Subsystem.............................................................................. 20
LO Subsystem ............................................................................. 21
Applications Information.............................................................. 22
Basic Connections...................................................................... 22
IF Port .......................................................................................... 22
Bias Resistor Selection ............................................................... 22
VGS Programming..................................................................... 23
Low-Pass Filter Programming.................................................. 23
RF Balun Programming ............................................................ 23
Register Structure........................................................................... 24
Evaluation Board ............................................................................ 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
3.6 V Performance...................................................................... 16
Spurious Performance................................................................ 17
Circuit Description......................................................................... 20
REVISION HISTORY
7/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADL5812
SPECIFICATIONS
VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 1200 Ω, ZO = 50 Ω, optimum
SPI settings, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB broadband via serial port
10
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
700
30
2800
450
Differential impedance, f = 200 MHz
Externally generated
260||1.2
VS
Ω||pF
MHz
V
LO INTERFACE
LO Power
Return Loss
−6
0
13.3
50
+10
dBm
dB
Ω
Input Impedance
LO Frequency Range
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Low-side or high-side LO
250
2800
MHz
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
6.7
dB
dB
dB
dB
13.1
11.6
21
SSB Noise Figure Under Blocking
5 dBm blocker present 10 MHz from wanted RF input,
LO source filtered
Input Third-Order Intercept
Input Second-Order Intercept
fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each RF tone
at −10 dBm
fRF1 = 1900 MHz, fRF2 = 2000 MHz, fLO = 1697 MHz, each RF tone
at −10 dBm
27.2
55
dBm
dBm
Input 1 dB Compression Point
LO-to-IF Output Leakage
LO-to-RF Input Leakage
RF-to-IF Output Isolation
IF/2 Spurious
12.5
−37
−46
26
−70
−78
dBm
dBm
dBm
dB
dBc
dBc
Unfiltered IF output
−10 dBm input power
−10 dBm input power
IF/3 Spurious
POWER INTERFACE
Supply Voltage, VS
3.6
5
5.5
V
Quiescent Current
Power-Down Current
Resistor programmable IF current
412
1.5
mA
mA
1 Supply voltage must be applied from external circuit through choke inductors.
Rev. 0 | Page 3 of 28
ADL5812
TIMING CHARACTERISTICS
Low logic level ≤ 0.4 V, and high logic level ≥ 1.4 V.
Table 2. Serial Interface Timing
Parameter
Limit
Unit
Test Conditions/Comments
LE setup time
DATA-to-CLK setup time
DATA-to-CLK hold time
CLK high duration
CLK low duration
CLK-to-LE setup time
LE pulse width
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DATA
LE
(CONTROL BIT C2)
t6
t7
t1
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 28
ADL5812
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
Supply Voltage, VPOS
5.5 V
CLK, DATA, LE
5.5 V
IF Output Bias
6.0 V
RF Input Power
LO Input Power
20 dBm
13 dBm
2.5 W
30°C
150°C
ESD CAUTION
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−40°C to +85°C
−65°C to +150°C
Rev. 0 | Page 5 of 28
ADL5812
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RF1
RFCT1
NC
1
2
3
4
5
6
7
8
9
30 V1LO1
29 NC
28 NC
NC
NC
27
ADL5812
NC
26 LOIP
25 LOIN
24 LE
TOP VIEW
NC
(Not to Scale)
NC
NC
23 DATA
RFCT2
22
CLK
RF2 10
21 V2LO1
NOTES
1. NC = NO CONNECT. CAN BE GROUNDED.
2. EXPOSED PAD MUST BE CONNECTED
TO GROUND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 10
RF1, RF2
RF Input. Should be ac-coupled.
2, 9
RFCT1, RFCT2
NC
VPIF1, VPIF2
IFGM1, IFGM2
IFOP1, IFOP2, IFON1, IFON2
RF Balun Center Tap (AC Ground).
No Connect. Can be grounded.
Supply Voltage for IF Amplifier.
IF Amplifier Bias Control.
Differential Open-Collector IF Outputs. Should be pulled up to VCC via
external inductors.
3 to 8, 13, 16, 27 to 29, 35, 38
11, 40
12, 39
14, 15, 36, 37
17, 34
18 to 21, 30 to 33
IFGD1, IFGD2
V1LO1, V1LO2, V1LO3, V1LO4,
V2LO1, V2LO2, V2LO3, V2LO4
Supply Return for IF Amplifier. Must be grounded.
Positive Supply Voltages for LO Amplifiers.
22, 23, 24
25
26
CLK, DATA, LE
LOIN
LOIP
Serial Port Interface Control.
Ground Return for LO Input. Must be ac coupled.
LO Input. Should be ac-coupled.
EPAD
Exposed pad must be connected to ground.
Rev. 0 | Page 6 of 28
ADL5812
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 1200 Ω, ZO = 50 Ω, optimum
SPI settings, unless otherwise noted.
70
65
60
55
50
45
40
35
30
450
400
350
300
250
200
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 4. Supply Current vs. RF Frequency
Figure 7. Input IP2 vs. RF Frequency
12
11
10
9
20
19
18
17
16
15
14
13
12
11
10
9
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
8
7
6
5
4
3
8
2
7
1
6
0
5
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 5. Power Conversion Gain vs. RF Frequency
Figure 8. Input P1dB vs. RF Frequency
16
15
14
13
12
11
10
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
8
7
6
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 6. Input IP3 vs. RF Frequency
Figure 9. SSB Noise Figure vs. RF Frequency
Rev. 0 | Page 7 of 28
ADL5812
65
63
61
59
57
55
53
51
49
47
45
450
400
350
300
250
V
V
V
= 4.75V
= 5.00V
= 5.25V
V
V
V
= 4.75V
= 5.00V
= 5.25V
POS
POS
POS
POS
POS
POS
200
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
80
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Supply Current vs. Temperature
Figure 13. Input IP2 vs. Temperature
8.0
V
16
15
14
13
12
11
10
9
= 4.75V
POS
V
V
V
= 4.75V
= 5.00V
= 5.25V
POS
POS
POS
V
V
= 5.00V
= 5.25V
POS
POS
7.5
7.0
6.5
6.0
5.5
5.0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Power Conversion Gain vs. Temperature
Figure 14. Input P1dB vs. Temperature
14
13
12
11
10
9
30
29
28
27
26
25
24
23
22
21
20
V
POS
POS
= 4.75V
= 5.00V
= 5.25V
V
V
V
= 4.75V
= 5.00V
= 5.25V
POS
POS
POS
POS
V
V
8
–40
–20
0
20
40
60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. SSB Noise Figure vs. Temperature
Figure 12. Input IP3 vs. Temperature
Rev. 0 | Page 8 of 28
ADL5812
70
65
60
55
50
45
40
35
30
450
400
350
300
250
200
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
30
80
130
180
230
280
330
380
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 19. Input IP2 vs. IF Frequency
Figure 16. Supply Current vs. IF Frequency
16
14
12
10
8
10
9
8
7
6
5
4
3
2
1
0
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
6
4
2
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
0
30
80
130
180
230
280
330
380
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 20. Input P1dB vs. IF Frequency
Figure 17. Power Conversion Gain vs. IF Frequency
35
33
31
29
27
25
23
21
19
17
15
16
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
14
12
10
8
6
4
2
0
30
30
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 18. Input IP3 vs. IF Frequency
Figure 21. SSB Noise Figure vs. IF Frequency
Rev. 0 | Page 9 of 28
ADL5812
9
16
15
14
13
12
11
10
RF = 900MHz
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
RF = 1900MHz
RF = 2500MHz
8
7
6
5
4
3
–6
–4
–2
0
2
4
6
8
10
10
10
–6
–4
–2
0
2
4
6
8
10
LO POWER (dBm)
LO POWER (dBm)
Figure 22. Power Conversion Gain vs. LO Power
Figure 25. Input P1dB vs. LO Power
30
29
28
27
26
25
24
23
22
–40
–45
–50
–55
–60
–65
–70
–75
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–6
–4
–2
0
2
4
6
8
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 26. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm
Figure 23. Input IP3 vs. LO Power
75
70
65
60
55
50
45
40
35
–50
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–55
–60
–65
–70
–75
–80
–85
–90
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
–6
–4
–2
0
2
4
6
8
RF FREQUENCY(MHz)
LO POWER (dBm)
Figure 27. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm
Figure 24. Input IP2 vs. LO Power
Rev. 0 | Page 10 of 28
ADL5812
100
500
400
300
200
100
0
10
MEAN: 7.37
SD: 0.12%
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
8
6
4
2
0
80
60
40
20
0
30
80
130
180
230
280
330
380
430
480
7.0
7.2
7.4
7.6
7.8
IF FREQUENCY (MHz)
CONVERSION GAIN (dBm)
Figure 31. IF Output Impedance (R Parallel C Equivalent)
Figure 28. Conversion Gain Distribution
–5
100
MEAN: 26.43
SD: 0.55%
–6
–7
–8
80
60
40
20
0
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
22
24
26
28
30
RF FREQUENCY (MHz)
INPUT IP3 (dBm)
Figure 32. RF Port Return Loss, Fixed IF
Figure 29. Input IP3 Distribution
–5
–6
–7
–8
–9
100
MEAN: 11.82
SD: 0.30%
80
60
40
20
0
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
10.8
11.3
11.8
12.3
12.8
LO FREQUENCY (MHz)
INPUT P1dB (dBm)
Figure 33. LO Return Loss
Figure 30. Input P1dB Distribution
Rev. 0 | Page 11 of 28
ADL5812
–10
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
2 × LO TO RF
2 × LO TO IF
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–15
–20
–25
–30
–35
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 37. 2XLO Leakage vs. LO Frequency
Figure 34. RF-to-IF Isolation vs. RF Frequency
–10
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
3 × LO TO RF
3 × LO TO IF
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 38. 3XLO Leakage vs. LO Frequency
Figure 35. LO-to-IF Leakage vs. LO Frequency
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
500 700 900 1100 1300 1500 1700 1900 2100 2300 2500
LO FREQUENCY (MHz)
Figure 36. LO-to-RF Leakage vs. LO Frequency
Rev. 0 | Page 12 of 28
ADL5812
550
500
450
400
350
300
250
16
14
12
10
8
VGS = 0
VGS = 1
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
RF = 900MHz
RF = 1900MHz
RF = 2500MHz
NOISE FIGURE
6
GAIN
4
500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
IF BIAS RESISTOR VALUE (Ω)
RF FREQUENCY (MHz)
Figure 42. Supply Current vs. IF Bias Resistor Value
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency
for All VGS Settings, RFB and LPF Use Optimum Settings
22
20
18
16
14
12
10
8
30
30
RF = 900MHz
RF = 1900MHz
INPUT IP3
27
24
RF = 2500MHz
INPUT IP3
25
20
15
10
21
18
NOISE FIGURE
15
12
GAIN
9
6
3
0
6
5
4
INPUT P1dB
VGS = 0
VGS = 1
VGS = 2
VGS = 3
VGS = 4
VGS = 5
VGS = 6
VGS = 7
2
0
500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
IF BIAS RESISTOR VALUE (Ω)
RF FREQUENCY (MHz)
Figure 43. Power Conversion Gain, Noise Figure, and Input IP3 vs.
IF Bias Resistor Value
Figure 40. Input IP3 and Input P1dB vs. RF Frequency for All VGS Settings,
RFB and LPF Use Optimum Settings
70
30
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
RF = 956MHz
RF = 1950MHz
RF = 2583MHz
60
50
40
30
20
10
0
25
20
15
10
5
0
–30
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
–25
–20
–15
–10
–5
0
5
10
RF FREQUENCY (MHz)
RF BLOCKER LEVEL (dBm)
Figure 44. IF Channel-to-Channel Isolation vs. RF Frequency
Figure 41. SSB Noise Figure vs. 10 MHz Offset Blocker Level
Rev. 0 | Page 13 of 28
ADL5812
17
16
15
14
13
12
11
10
9
12
RFB = 0
11
10
9
RFB = 1
RFB = 2
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
8
7
6
5
4
RFB = 0
RFB = 1
RFB = 2
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
3
8
7
2
1
6
5
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 45. Conversion Gain vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
Figure 47. Input P1dB vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
30
29
28
27
26
25
18
16
14
12
10
24
RFB = 0
23
RFB = 1
8
6
4
RFB = 0
RFB = 1
RFB = 2
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
RFB = 2
22
21
20
RFB = 3
RFB = 4
RFB = 5
RFB = 6
RFB = 7
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 48. Noise Figure vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
Figure 46. Input IP3 vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
Rev. 0 | Page 14 of 28
ADL5812
16
14
12
10
8
10
9
8
7
6
5
4
3
2
1
0
6
4
LPF = 0
LPF = 1
LPF = 2
LPF = 3
LPF = 0
LPF = 1
LPF = 2
LPF = 3
2
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 49. Conversion Gain vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings
Figure 51. Input P1dB vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings
16
30
28
26
24
22
20
18
16
LPF = 0
LPF = 1
LPF = 2
LPF = 3
15
14
13
12
11
10
9
8
14
LPF = 0
LPF = 1
7
12
LPF = 2
LPF = 3
6
10
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 52. Noise Figure vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings.
Figure 50. Input IP3 vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings
Rev. 0 | Page 15 of 28
ADL5812
3.6 V PERFORMANCE
VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 800 Ω, ZO = 50 Ω, optimum
SPI settings, unless otherwise noted.
70
60
50
40
30
20
10
0
290
285
280
275
270
265
260
255
250
245
240
235
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 56. Input IP2 vs. RF Frequency at 3.6 V
Figure 53. Supply Current vs. RF Frequency at 3.6 V
9
12
8
7
6
5
4
3
2
1
0
10
8
6
4
2
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
-
A
A
A
A
A
A
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 54. Power Conversion Gain vs. RF Frequency at 3.6 V
Figure 57. Input P1dB vs. RF Frequency at 3.6 V
30
25
20
15
10
5
24
22
20
18
16
14
12
10
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
8
6
4
2
0
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 58. SSB Noise Figure vs. RF Frequency at 3.6 V
Figure 55. Input IP3 vs. RF Frequency at 3.6 V
Rev. 0 | Page 16 of 28
ADL5812
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was only measured for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 1200 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.
Table 5. RF = 900 MHz, LO = 697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−38.6
0.0
−19.2
−36.3
−78.0
−97.8
−37.5
−19.2
−54.1
−90.8
−22.2
−52.5
−67.2
−48.1
−41.5
−77.8
−42.0
−60.6
−76.1
−98.0
−63.0
−53.8
−97.7
−99.3
−59.2
−78.7
−91.5
1
−30.4
−60.9
−86.0
−64.8
2
−54.1
−81.3
<−100 <−100 <−100
3
<−100 −90.2
<−100 <−100 <−100 <−100 <−100
4
−100.0 <−100 −94.9
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5
<−100
<−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
Table 6. RF = 1900 MHz, LO = 1697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−26.1
0.0
−25.2
−46.0
−71.9
−88.9
−55.4
−54.5
−66.0
−76.3
1
−26.1
−70.8
−78.8
−80.4
−97.8
2
−68.3
−97.7
3
<−100 −91.4
<−100 <−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
<−100
Rev. 0 | Page 17 of 28
ADL5812
Table 7. RF = 2500 MHz, LO = 2297 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
0
−29.3
0.0
−41.2
−45.0
−57.9
1
−26.2
−84.5
−46.1
−67.1
−83.4
2
−72.0
−96.5
3
<−100 −87.7
<−100 <−100
4
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
<−100
3.6 V Performance
VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = R2 = 800 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.
Table 8. RF = 900 MHz, LO = 697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−44.7
0.0
−24.2
−34.6
−79.4
−95.9
−35.2
−19.9
−57.4
−82.8
−25.5
−57.5
−65.0
−96.0
−46.6
−39.2
−76.9
−80.8
−45.9
−59.8
−77.5
−64.1
−50.8
−92.8
−65.9
−76.1
−85.8
1
−30.9
−69.9
−84.9
−60.0
2
−56.7
−78.6
<−100 <−100 <−100
3
<−100 −96.7
<−100 <−100 <−100 <−100 <−100
4
<−100 <−100 −94.6
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100
<−100
Rev. 0 | Page 18 of 28
ADL5812
Table 9. RF = 1900 MHz, LO = 1697 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−32.6
0.0
−29.0
−53.6
−82.0
−60.9
−56.6
−73.1
1
−34.0
−72.9
−86.3
−76.8
−95.9
2
−72.4
<−100
3
<−100 <−100 <−100 −73.5
<−100 <−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
5
6
7
N
8
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
<−100
Table 10. RF = 2500 MHz, LO = 2297 MHz
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−24.9
−49.5
−46.6
−60.1
1
−30.5 0.0
−52.0
−68.5
−71.2
2
−92.7 −78.3
−95.6
3
<−100 −96.3
<−100 <−100
4
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
<−100
Rev. 0 | Page 19 of 28
ADL5812
CIRCUIT DESCRIPTION
The ADL5812 consists of two primary components: the RF
subsystem and the LO subsystem. The combination of design,
process, and packaging technology allows the functions of these
subsystems to be integrated into a single die, using mature
packaging and interconnection technologies to provide a high
performance device with excellent electrical, mechanical, and
thermal properties. The wideband frequency response and
flexible frequency programming simplifies the receiver design,
saves on-board space, and minimizes the need for external
components.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input in accordance with the output of the
LO subsystem. The passive mixer is essentially a balanced, low
loss switch that adds minimum noise to the frequency translation.
The only noise contribution from the mixer is due to the resistive
loss of the switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input of
the IF amplifier, where high peak signal levels can compromise the
compression and intermodulation performance of the system. This
termination is accomplished by the addition of a programmable
low-pass filter network between the IF amplifier and the mixer
and in the feedback elements in the IF amplifier.
The RF subsystem consists of an integrated, tunable, low loss RF
balun; a double balanced, passive MOSFET mixer; a tunable sum
termination network; and an IF amplifier.
The LO subsystem consists of a multistage limiting LO amplifier.
The purpose of the LO subsystem is to provide a large, fixed
amplitude, balanced signal to drive the mixer independent of
the level of the LO input. A block diagram of the device is shown
in Figure 59.
The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance
that is required to achieve the overall performance. The balanced
open-collector output of the IF amplifier, with an impedance
modified by the feedback within the amplifier, permits the
output to be connected directly to a high impedance filter, a
differential amplifier, or an analog-to-digital converter (ADC)
input while providing optimum second-order intermodulation
suppression. The differential output impedance of the IF amplifier
is approximately 200 Ω. If operation in a 50 Ω system is desired,
the output can be transformed to 50 Ω by using a 4:1 transformer
or an LC impedance matching network.
40
39
38
37
36
35
34
33
32
31
RF1
RFCT1
NC
1
2
30
29
28
27
26
25
V1LO1
NC
ADL5812
3
NC
NC
4
NC
NC
5
LOIP
LOIN
BIAS
GEN
NC
6
NC
7
24 LE
The intermodulation performance of the design is generally limited
by the IF amplifier. The IP3 performance can be optimized by
adjusting the low-pass filter between the mixer and the IF amplifier.
Further optimization can be made by adjusting the IF current
with an external resistor. Figure 42 and Figure 43 illustrate how
various IF resistors affect the performance with a 5 V supply.
Additionally, dc current can be saved by increasing the IF resistor.
It is permissible to reduce the IF amplifier’s dc supply voltage
to as low as 3.3 V, further reducing the dissipated power of the
part. (Note that no performance enhancement is obtained by
reducing the value of these resistors, and excessive dc power
dissipation may result.)
NC
8
23 DATA
SERIAL
PORT
RFCT2
RF2
CLK
9
22
21
INTERFACE
V2LO1
10
11
12
13
14
15
16
17
18
19
20
Figure 59. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a tunable, low loss, unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range of
700 MHz to 2800 MHz. This balun is tuned over the frequency
range by SPI controlled switched capacitor networks at the
input and output of the RF balun.
Because the mixer is bidirectional, the tuning of the RF and IF
ports is linked, and it is possible for the user to optimize gain,
noise figure, IP3, and impedance match via the SPI. This feature
permits high performance operation and is achieved entirely
using SPI control. Additionally, the performance of the mixer
can be improved by setting the optimum gate voltage on the
passive mixer, which is also controlled by the SPI to enable
optimum performance of the part. See the Applications
Information section for examples of this tuning.
Rev. 0 | Page 20 of 28
ADL5812
The performance of this amplifier is critical in achieving a high
intercept passive mixer without degrading the noise floor of the
system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. Blocking dynamic
range can benefit from a higher level of LO drive, which pushes
the LO amplifier stages harder into compression and causes them
to switch harder and to limit the small signal gain of the chain.
Both of these conditions are beneficial to low noise figure under
blocking. NF under blocking can be improved several decibels
for LO input power levels above 0 dBm.
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation and compression
performance. The resulting LO amplifier provides very high
performance over a wide range of LO input frequencies.
The ideal waveshape for switching the passive mixer is a square
wave at the LO frequency to cause the mixer to switch through
its resistive region (from on to off and off to on) as rapidly as
possible. While it has always been possible to generate such a
square wave, the amount of dc current required to generate a
large amplitude square wave at high frequencies has made it
impractical to create such a mixer. Novel circuitry within the
ADL5812 permits the generation of a near-square wave output
at frequencies up to 2800 MHz with dc current that compares
favorably with that employed by narrow-band passive mixers.
The LO amplifier topology inherently minimizes the dc current
based on the LO operating voltage and the LO operating frequency.
It is permissible to reduce the LO supply voltage down as low as
3.6 V, which drops the dc current rapidly. The mixer dynamic
range varies accordingly with the LO supply voltage. No external
biasing resistor is required for optimizing the LO amplifier.
The input stages of the LO amplifier provide common-mode
rejection, permitting the LO input to be driven either single ended
or balanced. For a single-ended input, either LOIP or LOIN can
be grounded. It is desirable to dc block the LO inputs to avoid
damaging the part by the accidental application of a large dc
voltage to the part. In addition, the LO inputs are internally dc
blocked.
In addition, the ADL5812 has a power-down mode. This power-
down mode can be used with any supply voltage applied to the part.
All of the SPI inputs are designed to work with any logic family that
provides a Logic 0 input level of less than 0.4 V and a Logic 1 input
level that exceeds 1.4 V.
All pins, including the RF pins, are ESD protected and have been
tested up to a level of 2000 V HBM and 1250 V CDM.
Because the LO amplifier is inherently wideband, the ADL5812
can be driven with either high-side or low-side LO by simply
setting the optimum RF balun and LPF inputs to the SPI.
The LO amplifier converts a variable level, single or balanced input
signal (−6 dBm to +10 dBm) to a hard voltage limited, balanced
signal internally to drive the mixer. Excellent performance can be
obtained with a 0 dBm input level; however, the circuit continues to
function at considerably lower levels of LO input power.
Rev. 0 | Page 21 of 28
ADL5812
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The real part of the output impedance is approximately 200 Ω,
as seen in Figure 31, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion gain that is approximately 6 dB higher than the power
conversion gain. When a 50 Ω output impedance is needed, use a
4:1 impedance transformer, as shown in Figure 60.
The ADL5812 mixer is designed to downconvert radio
frequencies (RF) primarily between 700 MHz and 2800 MHz
to lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 60 depicts the basic connections of the mixer.
It is recommended to ac couple RF and LO input ports to
prevent nonzero dc voltages from damaging the RF balun or LO
input circuit. A RFIN capacitor value of 22 pF is recommended.
BIAS RESISTOR SELECTION
External resistors, R1 and R2, are used to adjust the bias current
of the integrated amplifier at the IF terminal. It is necessary to have
a sufficient amount of current to bias both the internal IF amplifier
to optimize dc current vs. optimum input IP3 performance.
Figure 42 and Figure 43 provide the reference for the bias
resistor selection when lower power consumption is considered at
the expense of conversion gain and input IP3 performance.
IF PORT
The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.
C3
120pF
L1
470nH
T1
TC4-1W+
IFOP
VCC
VCC
3
4
L2
R20
C1
0.1µF
2
1
470nH
OPEN
C11
10pF
6
IFON
C5
120pF
C4
120pF
C2
0.1µF
R21
0ꢀ
VCC
R1
910ꢀ
C12
10pF
AGND
VPOS
C8
0.1µF
VCC
BLK
RED
VCC
C13
10pF
PAD
RFIN1
VCC
C14
C6
10pF
22pF
1
2
30
RF1
V1LO1
29
28
27
26
25
24
23
22
21
RFCT1
NC
NC
NC
RFIN2
3
C7
22pF
4
NC
NC
5
NC
LOIP
LOIN
LE
ADL5812
6
NC
C17
22pF
LE
7
NC
C25
8
DATA
CLK
VCC
NC
DATA
CLK
22pF
9
RFCT2
RF2
10
V2LO1
RFIN2
C15
10pF
C16
22pF
C24
22pF
VCC
C2.3
10pF
C18
10pF
R2
910ꢀ
VCC
C19
10pF
VCC
C3
120pF
C20
10pF
L3
470nH
T1
TC4-1W+
IFOP
VCC
3
4
L4
470nH
R23
C26
0.1µF
2
1
OPEN
6
IFON
C30
120pF
C4
120pF
C27
0.1µF
R22
0ꢀ
Figure 60. Evaluation Board Schematic
Rev. 0 | Page 22 of 28
ADL5812
VGS PROGRAMMING
RF BALUN PROGRAMMING
The ADL5812 allows programmability for internal gate-to-source
voltages for optimizing mixer performance over the desired
frequency bands. The ADL5812 defaults the VGS setting to 0. Both
channels of the ADL5812 are programmed together using the
same VGS setting. Power conversion gain, input IP3, NF, and input
P1dB can be optimized, as shown in Figure 39 and Figure 40.
The ADL5812 allows programmability for the RF balun by
allowing capacitance to be switched into both the input and the
output, which allows the balun to be tuned to cover the entire
frequency band (700 MHz to 2800 MHz). Under most circum-
stances, the input and output can be tuned together though
sometimes it may be advantageous for matching reasons to tune
them separately. The ADL5812 defaults the RFB setting to 0. Both
channels of the ADL5812 are programmed together using the same
RFB settings. Power conversion gain, input IP3, NF, and input
P1dB can be optimized, as shown in Figure 45 and Figure 48.
LOW-PASS FILTER PROGRAMMING
The ADL5812 allows programmability for the low-pass filter
terminating the mixer output. This filter helps to block sum term
mixing products at the expense of some noise figure and gain
and can significantly increase input IP3. The ADL5812 defaults the
LPF setting to 0. Both channels of the ADL5812 are programmed
together using the same LPF settings. Power conversion gain,
input IP3, NF, and input P1dB can be optimized, as shown in
Figure 49 to Figure 52.
Rev. 0 | Page 23 of 28
ADL5812
REGISTER STRUCTURE
Figure 61 illustrates the register map of the ADL5812. The
ADL5812 uses only Register 5. Because of this, set all of the
control bits to five. When set to 0, the MAIN ENB and DIV
ENB bits, DB7 and DB6, respectively, enable the part. By setting
one of these bits to 1, its channel is powered down. Either
channel can be powered down independently of the other. The
RFB IN CAP DAC and RFB OUT CAP DAC bits are used to
tune the RF balun. In most cases, they are tuned together with
the higher settings, 7, tuning for the low frequencies, and with
the lower settings, 0, tuning for the high frequencies. There are
times where it becomes advantageous to tune the input and
output of the RF balun separately and that ability is provided.
The LPF bits control the low-pass filter settings at the IF output.
The ability to tune the low-pass filter allows some trade-off
between gain, noise figure, and input IP3 with higher settings,
3, providing higher input IP3 at the cost of some gain and noise
figure and lower settings, 0, providing higher gain and lower NF
at the cost of lower input IP3. The VGS bits control the VGS
settings of the mixer core and allow further tuning of the device.
Table 11 lists the optimum settings characterized for each
frequency band. All register bits default to 0.
MAIN DIV
RESERVED
VGS
LPF
RFB OUT CAP DAC
RFB IN CAP DAC
RESERVED
CONTROL BITS
ENB ENB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6
VGS2 VGS1 VGS0 LPF1 LPF0 CDO2 DCDO1 CDO0 CDI2 CDI1 CDI0 MEN DEN
DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
C3(1) C2(0) C1(1)
DEN DIVERSITY ENABLE
VGS2 VGS1 VGS0
VGS SETTING
0
1
DEVICE ENABLED
DEVICE DISABLED
0
'
0
'
0
'
0
'
1
1
1
7
MEN
0
1
MAIN ENABLE
DEVICE ENABLED
DEVICE DISABLED
LPF1 LPF0 LOW PASS FILTER SETTING
0
'
0
'
0
'
CDI2 CDI1 CDI0 RF BALUN INTPUT TUNING
1
1
3
0
'
0
'
0
'
0
'
1
1
1
7
CDO2 CDO1 CDO0 RF BALUN OUTPUT TUNING
0
'
0
'
0
'
0
'
1
1
1
7
Figure 61. ADL5812 Register Maps
Table 11. Optimum Settings
RF Frequency (MHz) LO Frequency (MHz) VGS
LPF
3
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
1
1
3
1
1
2
RFB OUT CAP DAC
RFB IN CAP DAC
700
497
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
7
7
4
3
7
7
7
7
5
6
5
5
5
4
4
3
3
3
2
2
2
1
7
7
4
3
7
7
7
7
5
6
5
5
5
4
4
3
3
3
2
2
2
1
800
597
900
697
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
797
897
997
1097
1197
1297
1397
1497
1597
1697
1797
1897
1997
2097
2197
2297
2397
2497
2597
Rev. 0 | Page 24 of 28
ADL5812
EVALUATION BOARD
An evaluation board is available for the ADL5812. The standard
evaluation board schematic is presented in Figure 62. The USB
interface circuitry schematic is presented in Figure 65. The
evaluation board layout is shown in Figure 63 and Figure 64.
The evaluation board is fabricated using Rogers® 3003 material.
Table 12 details the configuration for the mixer characterization.
The evaluation board software is available on www.analog.com.
C3
120pF
L1
470nH
T1
TC4-1W+
IFOP
VCC
VCC
3
4
L2
R20
C1
0.1µF
2
1
470nH
OPEN
C11
10pF
6
IFON
C5
120pF
C4
120pF
C2
0.1µF
R21
0ꢀ
VCC
R1
910ꢀ
C12
10pF
AGND
VPOS
C8
0.1µF
VCC
BLK
RED
VCC
C13
10pF
PAD
RFIN1
VCC
C14
C6
10pF
22pF
1
2
30
RF1
V1LO1
29
28
27
26
25
24
23
22
21
RFCT1
NC
NC
NC
RFIN2
3
C7
22pF
4
NC
NC
5
NC
LOIP
LOIN
LE
ADL5812
6
NC
C17
22pF
7
LE
NC
C25
8
DATA
CLK
VCC
NC
DATA
CLK
22pF
9
RFCT2
RF2
10
V2LO1
RFIN2
C15
10pF
C16
22pF
C24
22pF
VCC
C2.3
10pF
C18
10pF
R2
910ꢀ
VCC
C19
10pF
VCC
C3
120pF
C20
10pF
L3
470nH
T1
TC4-1W+
IFOP
VCC
3
4
L4
470nH
R23
C26
0.1µF
2
1
OPEN
6
IFON
C30
120pF
C4
120pF
C27
0.1µF
R22
0ꢀ
Figure 62. Evaluation Board Schematic
Table 12. Evaluation Board Configuration
Components
Description
Default Conditions
C1, C2, C8, C11, C12,
C13, C14, C15, C18,
C19, C20, C23, C26,
C27
Power supply decoupling. Nominal supply decoupling consists of a
0.1 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
C1, C2, C26, C27 = 0.1 μF (size 0402),
C8, C11, C12, C13, C14, C15, C18, C19,
C20, C23 = 10 pF (size 0402)
C6, C7, C24, C25
RF input interface. The input channels are ac-coupled through C6 and
C24. C7 and C25 provide bypassing for the center tap of the RF input
baluns.
C6, C24 = 22 pF (size 0402),
C7, C25 = 22 pF (size 0402)
C3, C4, C5, C28, C29, IF output interface. The open-collector IF output interfaces are biased
C3, C4, C5, C28, C29, C30 = 120 pF (size 0402),
L1, L2, L3, L4 = 470 nH (size 0603),
R20, R23 = open,
R21, R22 = 0 Ω (size 0402),
T1, T2 = TC4-1W+ (Mini-Circuits®)
C30, L1, L2, L3, L4,
R20, R21, R22, R23,
T1, T2
through pull-up choke inductors L1, L2, L3, and L4. T1 and T2 are 4:1
impedance transformers used to provide single-ended IF output
interfaces, with C5 and C30 providing center-tap bypassing. Remove
R21 and R22 for balanced output operation.
C17
LO interface. C17 provides ac coupling for the LOIP local oscillator input.
Bias control. R1and R2 set the bias point for the internal IF amplifier.
C17 = 22 pF (size 0402)
R1, R2 = 910 Ω (size 0402)
R1, R2
Rev. 0 | Page 25 of 28
ADL5812
Figure 63. Evaluation Board Top Layer
Figure 64. Evaluation Board Bottom Layer
Y2
24.000000MHZ
1
3
5V_USB
C41
CASE
22PF
2
4
C40
22PF
DGND
DGND
DGND
J6
C34
1
2
3
4
5
3V3_USB
10PF
3V3_USB
C35
C36
U7
8
DGND
0.1UF
5
G1
10PF
C37
VCC
1
R7
2K
R8
2K
A0
A1
G2
G3
G4
GND
PINS
2
3
6
7
3V3_USB
VCC
A2
SCL
DGND
0.1UF
SDA
897-43-005-00-100001
DGND
WC_N
GND
U6
P1
4
AVCC
24LC64-I-SN
4
8
9
13
54
29
30
31
1
2
3
XTALOUT
DPLUS
DMINUS
IFCLK
SAMTECTSW10608GS3PIN
LE
DGND
CLKOUT
CTL0_FLAGA
CTL1_FLAGB
CTL2_FLAGC
R11
0
R17
0
15
16
SCL
33
34
35
36
37
38
39
40
PA0_INT0_N
PA1_INT1_N
R12
0
R18
0
SDA
DATA
CLK
R9
3V3_USB
R10
PA2_SLOE
100K
PA3_WU2
100K
PA4_FIFOADR0
PA5_FIFOADR1
PA6_PKTEND
5
R13
R19
0
XTALIN
42
C38
0.1UF
C39
0.1UF
RESET_N
0
PA7_FLAGD_SLCS_N
C49
TBD0402
330PF
C50
R15
1K
18
19
20
21
22
23
24
25
45
46
47
48
49
50
51
52
R14
1K
R16
1K
C51
TBD0402
PB0_FD0
PB1_FD1
PB2_FD2
PB3_FD3
PB4_FD4
PB5_FD5
PB6_FD6
PB7_FD7
PD0_FD8
PD1_FD9
PD2_FD10
PD3_FD11
PD4_FD12
PD5_FD13
PD6_FD14
PD7_FD15
TBD0402
330PF
44
14
WAKEUP
DGND
DNI
DNI
DNI
330PF
DNI
DNI
RESERVED
DNI
DGND
DGND
DGND
DGND
DGND
DGND
1
2
RDY0_SLRD
RDY1_SLWR
DGND
DGND
AGND
GND
PAD
CY7C68013A-56LTXC
DGND
3V3_USB
5V_USB
3P3V
ORG
3V3_USB
1
DNI
U5
DECOUPLING FOR U6
C31
1.0UF
C33
1.0UF
R4
2K
C32
1000PF
R6
140K
R3
0
7
8
6
1
2
3
IN1
OUT1
DGND
IN2 OUT2
DGND
A
SD_N
PAD
FB
GND
DGND
AGND
C42
0.1UF
C43
0.1UF
C44
0.1UF
C45
0.1UF
C46
0.1UF
C47
0.1UF
C48
0.1UF
PAD
5
D1
C
R5
78.7K
DGND
DGND
1
BLK
DGND
DNI
DGND
DGND
DGND
ADP3334ACPZ
Figure 65. USB Interface Circuitry on the Evaluation Board
Rev. 0 | Page 26 of 28
ADL5812
OUTLINE DIMENSIONS
0.30
0.25
0.20
6.00
BSC SQ
PIN 1
INDICATOR
40
1
31
30
0.50
BSC
PIN 1 INDEX
AREA
*
4.19
4.14 SQ
4.09
EXPOSED
PAD
21
20
10
11
0.45
0.40
0.35
0.58
0.53
0.48
BOTTOM VIEW
TOP VIEW
0.90
0.85
0.80
0.21 MAX
0.19 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.02 REF
*
COMPLIANT TO JEDEC STANDARDS MO-208
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 66. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad (CP-40-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Quantity
ADL5812ACPZ-R7
ADL5812-EVALZ
−40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-40-6
750
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
ADL5812
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09913-0-7/11(0)
Rev. 0 | Page 28 of 28
相关型号:
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ADL5812ACPZ-R7
Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
ADI
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