ADL5902 [ADI]
50 MHz to 9 GHz 65 dB TruPwr Detector; 50 MHz至9 GHz的65分贝TruPwr检测器
| 型号： | ADL5902 |
| 厂家： | 
ADI |
| 描述： | 50 MHz to 9 GHz 65 dB TruPwr Detector |
| 文件： | 总28页 (文件大小：2359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 MHz to 9 GHz
65 dB TruPwr Detector
ADL5902
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VPOS
3
POS
10
Accurate rms-to-dc conversion from 50 MHz to 9 GHz
Single-ended input dynamic range of 65 dB
No balun or external input matching required
Waveform and modulation independent, such as
GSM/CDMA/W-CDMA/TD-SCDMA/WiMAX/LTE
Linear-in-decibels output, scaled 53 mV/dB
Transfer function ripple: < 0.1 dB
TEMPERATURE
SENSOR
8
7
TEMP
VSET
ADL5902
14
15
INHI
I
DET
2
X
INLO
LINEAR-IN-dB VGA
(NEGATIVE SLOPE)
2
X
Temperature stability: < 0.3 dB
I
TGT
All functions temperature and supply stable
Operates from 4.5 V to 5.5 V from −40°C to +125°C
Power-down capability to 1.5 mW
2
NC
6
5
G = 5
VOUT
CLPF
16
13
NC
NC
VREF
2.3V
BIAS AND POWER-
DOWN CONTROL
Pin-compatible with the 50 dB dynamic range AD8363
APPLICATIONS
26pF
11
12
VTGT
1
9
4
Power amplifier linearization/control loops
Transmitter power controls
Transmitter signal strength indication (TSSI)
RF instrumentation
TADJ/PWDN
VREF
COMM COMM
Figure 1.
GENERAL DESCRIPTION
The ADL5902 is a true rms responding power detector that has
a 65 dB measurement range when driven with a single-ended
50 Ω source. This feature makes the ADL5902 frequency
versatile by eliminating the need for a balun or any other form
of external input tuning for operation up to 9 GHz.
logarithm of the rms value of the input. In other words, the
reading is presented directly in decibels and is scaled 1.06 V per
decade, or 53 mV/dB; other slopes are easily arranged. In
controller mode, the voltage applied to VSET determines the
power level required at the input to null the deviation from the
set point. The output buffer can provide high load currents.
The ADL5902 provides a solution in a variety of high frequency
systems requiring an accurate measurement of signal power.
Requiring only a single supply of 5 V and a few capacitors, it is
easy to use and capable of being driven single-ended or with a
balun for differential input drive. The ADL5902 can operate
from 50 MHz to 9 GHz and can accept inputs from −62 dBm to
at least +3 dBm with large crest factors, such as GSM, CDMA,
W-CDMA, TD-SCDMA, WiMAX, and LTE modulated signals.
The ADL5902 has 1.5 mW power consumption when powered
down by a logic high applied to the PWDN pin. It powers up
within approximately 5 μs to its nominal operating current of
73 mA at 25°C. The ADL5902 is supplied in a 4 mm × 4 mm,
16-lead LFCSP for operation over the wide temperature range
of −40°C to +125°C.
The ADL5902 is also pin-compatible with the AD8363, 50 dB
dynamic range TruPwr™ detector. This feature allows the
designer to create one circuit layout for projects requiring
different dynamic ranges. A fully populated RoHS-compliant
evaluation board is available.
The ADL5902 can determine the true power of a high
frequency signal having a complex low frequency modulation
envelope or can be used as a simple low frequency rms
voltmeter. Used as a power measurement device, VOUT is
connected to VSET. The output is then proportional to the
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADL5902
TABLE OF CONTENTS
Features .............................................................................................. 1
VSET Interface............................................................................ 18
Output Interface ......................................................................... 18
VTGT Interface .......................................................................... 18
Basis for Error Calculations...................................................... 18
Measurement Mode Basic Connections.................................. 19
Setting VTADJ.................................................................................. 20
Setting VTGT .................................................................................. 20
Choosing a Value for CLPF ............................................................ 20
Output Voltage Scaling.............................................................. 22
System Calibration and Error Calculation.............................. 23
High Frequency Performance................................................... 23
Low Frequency Performance.................................................... 24
Description of Characterization............................................... 24
Evaluation Board Schematics and Artwork................................ 25
Assembly Drawings.................................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 15
Square Law Detector and Amplitude Target.............................. 15
RF Input Interface ...................................................................... 16
Small Signal Loop Response ..................................................... 16
Temperature Sensor Interface................................................... 17
VREF Interface ........................................................................... 17
Temperature Compensation Interface..................................... 17
Power-Down Interface............................................................... 18
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADL5902
SPECIFICATIONS
VS = 5 V, T A = 25°C, ZO = 50 Ω, single-ended input drive, RT = 60.4 Ω, VOUT connected to VSET, VTGT = 0.8 V, CLPF = 0.1 µF. Negative
current values imply that the ADL5902 is sourcing current out of the indicated pin.
Table 1.
Parameter
Test Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
50 to 9000
MHz
RF INPUT INTERFACE
Input Impedance
Common Mode Voltage
100 MHz
Pins INHI, INLO, ac-coupled
Single-ended drive, 50 MHz
2000
2.5
Ω
V
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
Deviation vs. Temperature
CW input, TA = +25°C, VTADJ = 0.5 V
63
3
−60
dB
dBm
dBm
Calibration at −60 dBm, −45 dBm, and 0 dBm
Calibration at −60 dBm, −45 dBm, and 0 dBm
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm
dB
−0.11/+0.25
−0.22/+0.15
−0.35/+0.25
−0.22/+0.15
53.8
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −45 dBm
dB
dB
dB
Logarithmic Slope
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
mV/dB
Logarithmic Intercept
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
dBm
−62.1
700 MHz
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
Deviation vs. Temperature
CW input, TA = +25°C,VTADJ = 0.4 V
Calibration at −60 dBm, −45 dBm, and 0 dBm
Calibration at −60 dBm, −45 dBm, and 0 dBm
Deviation from output at 25°C
61
1
−60
dB
dBm
dBm
−40°C < TA < +85°C; PIN = 0 dBm
+0.3/−0.2
−0.1/0
+0.3/−0.4
−0.1/0
dB
dB
dB
dB
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −45 dBm
Logarithmic Slope
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
53.7
mV/dB
Logarithmic Intercept
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
−62.8
dBm
900 MHz
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
Deviation vs. Temperature
CW input, TA = +25°C, VTADJ = 0.4 V
Calibration at −60 dBm, −45 dBm, and 0 dBm
Calibration at −60 dBm, −45 dBm, and 0 dBm
Deviation from output at 25°C
61
1
−60
dB
dBm
dBm
−40°C < TA < +85°C; PIN = 0 dBm
+0.3/−0.2
0/−0.1
+0.3/−0.4
0/−0.1
dB
dB
dB
dB
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −45 dBm
Logarithmic Slope
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
53.7
mV/dB
Logarithmic Intercept
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
−62.7
dBm
Rev. 0 | Page 3 of 28
ADL5902
Parameter
Test Conditions
Min
Typ
Max
Unit
dB
dB
Deviation from CW Response
11.02 dB peak-to-rms ratio (CDMA2000)
5.13 dB peak-to-rms ratio (16 QAM)
2.76 dB peak-to-rms ratio (QPSK)
−0.1
−0.05
−0.05
dB
1.9 GHz
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
Deviation vs. Temperature
CW input, TA = +25°C, VTADJ = 0.4 V
Calibration at −60 dBm, −45 dBm, and 0 dBm
Calibration at −60 dBm, −45 dBm, and 0 dBm
Deviation from output at 25°C
64
3
−61
dB
dBm
dBm
−40°C < TA < +85°C; PIN = 0 dBm
−0.1/0
dB
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −45 dBm
−45 dBm < PIN < 0 dBm; calibration at −45 dBm,
and 0 dBm
−0.3/+0.3
−0.1/0
−0.3/+0.4
52.6
dB
dB
dB
mV/dB
Logarithmic Slope
Logarithmic Intercept
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
−62.6
dBm
2.14 GHz
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
Deviation vs. Temperature
CW input, TA = +25°C, VTADJ = 0.4 V
Calibration at −60 dBm, −45 dBm, and 0 dBm
Calibration at −60 dBm, −45 dBm, and 0 dBm
Deviation from output at 25°C
65
3
−62
dB
dBm
dBm
−40°C < TA < +85°C; PIN = 0 dBm
−0.1/0
dB
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −45 dBm
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
−0.3/+0.3
−0.1/0
−0.3/+0.4
52.4
dB
dB
dB
mV/dB
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
12.16 dB peak-to-rms ratio (four-carrier W-CDMA)
11.58 dB peak-to-rms ratio (LTE TM1 1CR 20 MHz
BW)
−62.9
dBm
−0.1
−0.1
dB
dB
10.56 dB peak-to-rms ratio (one-carrier W-CDMA)
6.2 dB peak-to-rms ratio (64 QAM)
−0.1
−0.07
dB
dB
2.6 GHz
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
Deviation vs. Temperature
CW input, TA = +25°C, VTADJ = 0.45 V
Calibration at −60, −45 and 0 dBm
Calibration at −60, −45 and 0 dBm
Deviation from output at 25°C
65
5
−60
dB
dBm
dBm
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −45 dBm
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
0.4/0
+0.5/−0.6
0.6/0
+0.7/−0.6
51.0
dB
dB
dB
dB
Logarithmic Slope
mV/dB
Logarithmic Intercept
−45 dBm < PIN < 0 dBm; calibration at −45 dBm
and 0 dBm
−62.1
dBm
3.5 GHz
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
CW input, TA = +25°C, VTADJ = 0.5 V
Calibration at −60 dBm, −40 dBm, and 0 dBm
Calibration at −60 dBm, −40 dBm, and 0 dBm
57
8
−49
dB
dBm
dBm
Rev. 0 | Page 4 of 28
ADL5902
Parameter
Test Conditions
Min
Typ
Max
Unit
Deviation vs. Temperature
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −40 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −40 dBm
0.2/0
dB
−0.2/+0.4
+0.2/−0.3
−0.2/+0.4
49.6
dB
dB
dB
mV/dB
Logarithmic Slope
−40 dBm < PIN < 0 dBm; calibration at −30 dBm
and 0 dBm
Logarithmic Intercept
−40 dBm < PIN < 0 dBm; calibration at −30 dBm
and 0 dBm
−63.1
dBm
5.8 GHz
1.0 dB Dynamic Range
Maximum Input Level, 1.0 dB
Minimum Input Level, 1.0 dB
Deviation vs. Temperature
CW input, TA = +25°C, VTADJ = 0.95 V
Calibration at −50 dBm, −30 dBm, and 0 dBm
Calibration at −50 dBm, −30 dBm, and 0 dBm
Deviation from output at 25°C
61
9
−52
dB
dBm
dBm
−40°C < TA < +85°C; PIN = 0 dBm
−0.8/0
dB
−40°C < TA < +85°C; PIN = −30 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−1.3/+0.1
−1.6/0
dB
dB
−40°C < TA < +125°C; PIN = −30 dBm
−30 dBm < PIN < 0 dBm; calibration at −30 dBm
and 0 dBm
−1.3/+0.1
42.7
dB
mV/dB
Logarithmic Slope
Logarithmic Intercept
−30 dBm < PIN < 0 dBm; calibration at −30 dBm
and 0 dBm
−54.1
dBm
OUTPUT INTERFACE
VOUT (Pin 6)
Output Swing, Controller Mode
Swing range minimum, RL ≥ 500 Ω to ground
Swing range maximum, RL ≥ 500 Ω to ground
0.03
4.8
V
V
Current Source/Sink Capability
Voltage Regulation
Output Noise
10/10 mA
ILOAD = 8 mA, source/sink
RFIN = 2.14 GHz, −20 dBm, fNOISE = 100 kHz,
CLPF = 220 pF
+0.2/−0.2
25
%
nV/√Hz
Rise Time
Fall Time
Transition from no input to 1 dB settling at
PIN = −10 dBm, CLPF = 220 pF
Transition from −10 dBm to off (1 dB of final value),
3
µs
µs
25
C
LPF = 220 pF
SETPOINT INPUT
Voltage Range
VSET (Pin 7)
Log conformance error ≤ 1 dB, minimum 2.14 GHz
Log conformance error ≤ 1 dB, maximum 2.14 GHz
3.5
0.23
72
V
V
kΩ
Input Resistance
Logarithmic Scale Factor
Logarithmic Intercept
TEMPERATURE COMPENSATION
Input Voltage Range
Input Bias Current
f = 2.14 GHz
f = 2.14 GHz
52.4
−62.9
mV/dB
dBm
Pin TADJ/PWDN (Pin 1)
0
VS
V
µA
kΩ
VTADJ = 0.4 V
VTADJ = 0.4 V
2
200
Input Resistance
VOLTAGE REFERENCE
Output Voltage
Temperature Sensitivity
VREF (Pin 11)
PIN = −55 dBm
25°C ≤ TA ≤ 125°C
−15°C ≤ TA ≤ +25°C
−40°C ≤ TA ≤ −15°C
25°C ≤ TA ≤ 125°C
2.3
V
−0.16
0.045
−0.04
4/0.05
mV/°C
mV/°C
mV/°C
mA
Short-Circuit Current Source/
Sink Capability
−40°C ≤ TA < +25°C
TA = 25°C, ILOAD = 2 mA
3/0.05
−0.4
mA
%
Voltage Regulation
Rev. 0 | Page 5 of 28
ADL5902
Parameter
Test Conditions
Min
Typ
Max
Unit
TEMPERATURE REFERENCE
Output Voltage
Temperature Coefficient
Short-Circuit Current Source/
Sink Capability
TEMP (Pin 8)
TA = 25°C, RL ≥ 10 kΩ
−40°C ≤ TA ≤ +125°C, RL ≥ 10 kΩ
25°C ≤ TA ≤ 125°C
1.4
4.9
4/0.05
V
mV/°C
mA
−40°C ≤ TA < +25°C
TA = 25°C, ILOAD = 1 mA
VTGT (Pin 12)
3/0.05
−2.8
mA
%
Voltage Regulation
RMS TARGET INTERFACE
Input Voltage Range
Input Bias Current
0.2
4.9
2.5
4
V
µA
kΩ
VTGT = 0.8 V
8
100
Input Resistance
POWER-DOWN INTERFACE
Voltage Level to Enable
Voltage Level to Disable
Input Current
Pin TADJ/PWDN (Pin 1)
VPWDN decreasing
VPWDN increasing
VPWDN = 5 V
V
V
µA
µA
1
500
VPWDN = 4.5 V
VPWDN = 0 V
VTADJ low to VOUT at 1 dB of final value,
3
5
µA
µs
Enable Time
Disable Time
C
LPA/B = 220 pF, PIN = 0 dBm
VTADJ high to VOUT at 1 dB of final value,
CLPA/B = 220 pF, PIN = 0 dBm
3
µs
POWER SUPPLY INTERFACE
Supply Voltage
VPOS (Pin 3, Pin 10)
4.5
5
5.5
V
Quiescent Current
TA = 25°C, PIN < −60 dBm
TA = 125°C, PIN < −60 dBm
VTADJ > VS − 0.1 V
73
90
300
mA
mA
µA
Power-Down Current
Rev. 0 | Page 6 of 28
ADL5902
ABSOLUTE MAXIMUM RATINGS
Table 2.
ESD CAUTION
Parameter
Rating
Supply Voltage, VPOS
Input Average RF Power1
Equivalent Voltage, Sine Wave Input
Internal Power Dissipation
5.5 V
21 dBm
2.51 V p-p
550 mW
10.6°C/W
35.3°C/W
57.2°C/W
1.0°C/W
2
θJC
2
θJB
2
θJA
2
ΨJT
2
ΨJB
34°C/W
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
150°C
−40°C to +125°C
−65°C to +150°C
300°C
Lead Temperature (Soldering, 60 sec)
1 This is for long durations. Excursions above this level, with durations much
less than 1 second, are possible without damage.
2 No airflow with the exposed pad soldered to a 4-layer JEDEC board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 28
ADL5902
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 VTGT
11 VREF
10 VPOS
TADJ/PWDN
NC
1
2
3
4
ADL5902
VPOS
TOP VIEW
(Not to Scale)
COMM
9 COMM
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE IS COMM AND SHOULD
HAVE BOTH A GOOD THERMAL AND GOOD
ELECTRICAL CONNECTION TO GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
TADJ/PWDN
This is a dual function pin used for controlling the amount of nonlinear intercept temperature compensation at
voltages <2.5 V and/or for shutting down the device at voltages >4 V. If the shutdown function is not used, this pin
can be connected to the VREF pin through a voltage divider. See Figure 41 for an equivalent circuit.
2
NC
No Connect.
3, 10
VPOS
Supply for the Device. Connect this pin to a 5 V power supply. Pin 3 and Pin 10 are not internally connected;
therefore, both must connect to the source.
4, 9, EPAD
5
COMM
CLPF
System Common Connection. Connect these pins via low impedance to system common. The exposed paddle
is also COMM and should have both a good thermal and good electrical connection to ground.
Connection for RMS Averaging Capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be
connected in series with this capacitor to modify loop stability and response time. See Figure 43 for an
equivalent circuit.
6
7
VOUT
VSET
Output. In measurement mode, this pin is connected to VSET. In controller mode, this pin can be used to drive
a gain control element. See Figure 43 for an equivalent circuit.
The voltage applied to this pin sets the decibel value of the required RF input voltage that results in zero
current flow in the loop integrating capacitor pin, CLPF. This pin controls the variable gain amplifier (VGA) gain
such that a 50 mV change in VSET changes the gain by approximately 1 dB. See Figure 42 for an equivalent
circuit.
8
11
12
TEMP
VREF
VTGT
Temperature Sensor Output of 1.4 V at 25°C with a Coefficient of 5 mV/°C. See Figure 38 for an equivalent circuit.
General-Purpose Reference Voltage Output of 2.3 V at 25°C. See Figure 39 for an equivalent circuit.
The voltage applied to this pin determines the target power at the input of the RF squaring circuit. The intercept
voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest
factor capacity; however, this may affect the system loop response. See Figure 44 for an equivalent circuit.
13
14
NC
INHI
No Connect.
RF Input. The RF input signal is normally ac-coupled to this pin through a coupling capacitor. See Figure 37 for
an equivalent circuit.
15
16
INLO
NC
RF Input Common. This pin is normally ac-coupled to ground through a coupling capacitor. See Figure 37 for
an equivalent circuit.
No Connect.
Rev. 0 | Page 8 of 28
ADL5902
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, Z O = 50 Ω, single-ended input drive, VOUT connected to VSET, VTGT = 0.8 V, CLPF = 0.1 µF, TA = +25°C (black), −40°C (blue),
+85°C (red), +125°C (orange) where appropriate. Error referred to the best fit line (linear regression) from − 10 dBm to − 40 dBm, unless
otherwise indicated. Input RF signal is a sine wave (CW), unless otherwise indicated.
6.0
6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
V = 0.5V
TADJ
T
= 0.5V
ADJ
CALIBRATION AT 0dBm, –45dBm, AND –60dBm
5.5 REPRESENTS 55 DEVICES FROM 2 LOTS
5
5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
IN
IN
Figure 6. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 100 MHz
Figure 3. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 100 MHz, CW
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
6
V
= 0.4V
T
= 0.4V
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
ADJ
CALIBRATION AT 0dBm, –45dBm, AND –60dBm
5
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
IN
IN
Figure 4. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 700 MHz, CW
Figure 7. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 700 MHz
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
6
V
= 0.4V
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
T
= 0.4V
ADJ
CALIBRATION AT 0dBm, –45dBm, AND –60dBm
5
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
–20
(dBm)
IN
–10
0
10
–60
–50
–40
–30
–20
(dBm)
–10
0
10
P
P
IN
Figure 5. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 900 MHz, CW
Figure 8. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 900 MHz
Rev. 0 | Page 9 of 28
ADL5902
6.0
6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
V
= 0.4V
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
T
= 0.4V
ADJ
CALIBRATION AT 0dBm, –45dBm, AND –60dBm
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
IN
IN
Figure 9. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 1.9 GHz, CW
Figure 12. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 1.9 GHz
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
V
= 0.4V
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
T
= 0.4V
ADJ
CALIBRATION AT 0dBm, –45dBm, AND –60dBm
5
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
IN
IN
Figure 10. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 2.14 GHz, CW
Figure 13. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 2.14 GHz
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
V
= 0.45V
T
= 0.45V
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
ADJ
CALIBRATION AT 0dBm, –45dBm, AND –60dBm
5
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
–20
(dBm)
–10
0
10
–60
–50
–40
–30
–20
(dBm)
–10
0
10
P
P
IN
IN
Figure 11. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 2.6 GHz, CW
Figure 14. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 2.6 GHz
Rev. 0 | Page 10 of 28
ADL5902
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
T
= 0.5V
V
= 0.5V
ADJ
CALIBRATION AT 0dBm, –40dBm, AND –60dBm
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
5
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
10
–60
–50
–40
–30
–20
(dBm)
–10
0
10
–60
–50
–40
–30
–20
(dBm)
–10
0
P
P
IN
IN
Figure 15. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 3.5 GHz, CW
Figure 18. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 3.5 GHz
3.0
2.5
2.0
1.5
1.0
0.5
0
6
3.0
2.5
2.0
1.5
1.0
0.5
0
6
V
= 0.95V
T
= 0.95V
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
ADJ
CALIBRATION AT 0dBm, –30dBm, AND –50dBm
5
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
–60
–50
–40
–30
P
–20
(dBm)
–10
0
10
IN
IN
Figure 16. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal
Line over Temperature vs. Input Amplitude at 5.8 GHz, CW
Figure 19. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 5.8 GHz
350
REPRESENTS 1900
PARTS FROM 3 LOTS
REPRESENTS 1900
PARTS FROM 3 LOTS
350
300
300
250
200
150
100
50
250
200
150
100
50
0
2.65
0
0.20
2.70
2.75
2.80
2.85
(V)
2.90
2.95
3.00
3.05
0.25
0.30
0.35
(V)
0.40
0.45
0.50
V
OUT
V
OUT
Figure 17. Distribution of VOUT, PIN = −10 dBm, 900 MHz
Figure 20. Distribution of VOUT, PIN = −60 dBm, 900 MHz
Rev. 0 | Page 11 of 28
ADL5902
6.0
6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
V
CW PEP = 0dB
V
V
V
V
V
CW PEP = 0dB
OUT
OUT
OUT
OUT
OUT
OUT
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
V
QPSK PEP = 2.76
16 QAM PEP = 5.13
CDMA2000 PEP = 11.02
64 QAM PEP = 6.2dB
1CR W-CDMA PEP = 10.56dB
4CR W-CDMA
5
5
OUT
OUT
OUT
4
4
LTE TM1 1CR 20MHz PEP = 11.58dB
ERROR CW
3
3
ERROR QPSK
ERROR 16 QAM
ERROR CDMA2000
ERROR CW
ERROR 64 QAM
ERROR 1CR W-CDMA
ERROR 4CR W-CDMA
ERROR LTE TM1 1CR 20MHz
2
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–60
–50
–40
–30
–20
(dBm)
–10
0
10
–60
–50
–40
–30
–20
(dBm)
–10
0
10
P
P
IN
IN
Figure 21. Error from CW Linear Reference vs. Signal Modulation,
Frequency = 900 MHz, CLPF = 0.1µF, Three-Point Calibration at 0 dBm,
−45 dBm, and −60 dBm
Figure 24. Error from CW Linear Reference vs. Signal Modulation,
Frequency = 2.14 GHz, CLPF = 0.1 µF, Three-Point Calibration at −10 dBm,
−45 dBm, and −60 dBm
6
6
RF ENVELOPE
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
RF ENVELOPE
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
5
4
3
2
1
0
5
4
3
2
1
0
–1
0
1
2
3
4
5
6
7
8
9
–4
0
4
8
12
16
20
24
28
32
36
TIME (µs)
TIME (µs)
Figure 22. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
CLPF = 220 pF, Rising Edge
Figure 25. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
CLPF = 220 pF, Falling Edge
6
6
RF ENVELOPE
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
RF ENVELOPE
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
5
4
3
2
1
5
4
3
2
1
0
–200
0
0
200 400 600 800 1000 1200 1400 1600 1800
TIME (µs)
–2000
0
2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000
TIME (µs)
Figure 23. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
LPF = 0.1 μF, Rising Edge
Figure 26. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
CLPF = 0.1 µF, Falling Edge
C
Rev. 0 | Page 12 of 28
ADL5902
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
2.5
2.0
1.5
1.0
0.5
0
REPRESENTS 1900
PARTS FROM 3 LOTS
400
300
200
100
0
–0.5
–1.0
–1.5
–2.0
–2.5
125
1.29
1.32
1.35
1.38
1.41
1.44
1.47
1.50
–55
–35
–15
5
25
45
65
85
105
VTEMP VOLTAGE (V)
TEMPERATURE (°C)
Figure 27. Distribution of VTEMP Voltage at 25°C, No RF Input
Figure 30. VTEMP and Linearity Error with Respect to Straight Line vs.
Temperature for Typical Device
0.2
REPRESENTS 1900
PARTS FROM 3 LOTS
400
0
–0.2
–0.4
–0.6
–0.8
–1.0
300
200
100
0
2.19
2.22
2.25
2.28
2.31
2.34
2.37
2.40
2.43
–50
–40
–30
–20
–10
(dBm)
0
10
20
V
BIAS VOLTAGE (V)
REF
P
IN
Figure 31. Change in VREF vs. Input Amplitude with Respect to −40 dBm,
25°C, Typical Device
Figure 28. Distribution of VREF Voltage at 25°C, No RF Input
40
100
30
20
10
0
10
–10
V
PWDN
DECREASING
1
–20
–30
–40
V
PWDN
INCREASING
–55
–35
–15
5
25
45
65
85
105
125
0.1
4.0
4.1
4.2
4.3
4.4
4.5
4.6
(V)
4.7
4.8
4.9
5.0
TEMPERATURE (°C)
V
PWDN
Figure 32. Supply Current vs. VPWDN
Figure 29. Change in VREF vs. Temperature with Respect to 25°C,
RF Input = −40 dBm, Typical Device
Rev. 0 | Page 13 of 28
ADL5902
7
6
5
4
3
2
1
200
180
160
140
120
100
80
TADJ/PWDN PULSE
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
60
40
20
0
–4
0
100
0
4
8
12
16
20
24
28
32
1k
10k
100k
1M
10M
TIME (µs)
FREQUENCY (Hz)
Figure 33. Output Response Using Power-Down Mode for Various RF Input
Levels Carrier Frequency 2.14 GHz, CLPF = 220 pF
Figure 35. Noise Spectral Density of VOUT, RF Input = −20 dBm, All CLPF Values
3.5
3.0
2.5
–10dBm
2.0
–30dBm
1.5
1.0
0.5
0
0
1
2
3
4
5
6
7
8
9
FREQUENCY (GHz)
Figure 34. Typical VOUT vs. Frequency for Two RF Input Amplitudes,
50 MHz to 9 GHz
Rev. 0 | Page 14 of 28
ADL5902
THEORY OF OPERATION
The ADL5902 is a 50 MHz to 9 GHz true rms responding
detector with a 65 dB measurement range at 2.14 GHz and a
greater than 56 dB measurement range at frequencies up to
6 GHz. It incorporates a modified AD8362 architecture that
increases the frequency range and improves measurement
accuracy at high frequencies. Transfer function peak-to-peak
ripple has been reduced to < 0.1 dB over the entire dynamic
range. Temperature stability of the rms output measurements
provides < 0.3 dB error, typically, over the specified temperature
range of −40°C to 125°C through proprietary techniques. The
device accurately measures waveforms that have a high peak-to-
rms ratio (crest factor).
V
GNS is a scaling voltage that defines the gain slope (the decibel
change per voltage). The gain decreases with increasing VSET
The VGA output is
SIG = GSET × RFIN = GO × RFIN e
.
− (VSET / VGNS
)
V
(2)
where RFIN is the ac voltage applied to the input terminals of the
ADL5902.
The output of the VGA, VSIG, is applied to a wideband square
law detector. The detector provides the true rms response of the
RF input signal, independent of waveform. The detector output,
I
SQR, is a fluctuating current with positive mean value. The
difference between ISQR and an internally generated current,
TGT, is integrated by the parallel combination of CF and the
I
The ADL5902 consists of a high performance AGC loop. As
shown in Figure 36, the AGC loop comprises a wide bandwidth
variable gain amplifier (VGA), square law detectors, an amplitude
target circuit, and an output driver. For a more detailed description
of the functional blocks, see the AD8362 data sheet.
external capacitor attached to the CLPF pin at the summing
node. CF is an on-chip 26 pF filter capacitor, and CLPF, the
external capacitance connected to the CLPF pin, can be used to
arbitrarily increase the averaging time while trading off with the
response time. When the AGC loop is at equilibrium
The nomenclature used in this data sheet to distinguish
between a pin name and the signal on that pin is as follows:
Mean(ISQR) = ITGT
(3)
This equilibrium occurs only when
•
The pin name is all uppercase, for example, VPOS,
COMM, and VOUT.
The signal name or a value associated with that pin is the
pin mnemonic with a partial subscript, for example, CLPF
2
Mean(VSIG2) = VTGT
(4)
•
where VTGT is the voltage presented at the VTGT pin. This pin
can conveniently be connected to the VREF pin through a voltage
divider to establish a target rms voltage, VATG, of ~40 mV rms when
and VOUT
.
VTGT = 0.8 V.
SQUARE LAW DETECTOR AND AMPLITUDE TARGET
The VGA gain has the form
Because the square law detectors are electrically identical and
well matched, process and temperature dependent variations
are effectively cancelled.
− (VSET / VGNS
)
G
SET = GO e
(1)
where:
GO is the basic fixed gain.
VPOS
C
H
(INTERNAL)
V
TGT
20
SUMMING
NODE
V
=
ATG
INHI
V
I
I
TGT
SIG
SQR
2
2
VGA
VTGT
X
X
INLO
G
SET
CLPF
VOUT
VSET
C
C
F
LPF
(EXTERNAL)
(INTERNAL)
COMM
TEMPERATURE COMPENSATION
AND BIAS
TADJ/PWDN
TEMPERATURE
SENSOR
TEMP (1.4V)
VREF (2.3V)
BAND GAP
REFERENCE
Figure 36. Simplified Architecture Details
Rev. 0 | Page 15 of 28
ADL5902
When forcing the previous identity by varying the VGA setpoint, it
is apparent that
half the supply voltage on each pin is established internally.
Either the INHI or INLO pin can be used as the single-ended
RF input pin. Signal coupling capacitors must be connected
from the input signal to the INHI and INLO pins. A single
external 60.4 Ω resistor to ground from the desired input
creates an equivalent 50 Ω impedance over a broad section of
the operating frequency range. The other input pin should be
RF ac-coupled to common (ground). The input signal high-pass
corner formed by the input coupling capacitor’s internal and
external resistances is
RMS(VSIG) = √(Mean(VSIG2)) = √(VATG2) = VATG
(5)
Substituting the value of VSIG from Equation 2 results in
(VSET / VGNS
RMS(G0 × RFIN e
) ) = VATG
(6)
When connected as a measurement device, VSET = VOUT. Solving
for VOUT as a function of RFIN,
V
OUT = VSLOPE × log10(RMS(RFIN)/VZ)
(7)
where:
f
HIGHPASS = 1/(2 × π × 50 × C)
(11)
V
SLOPE is 1.06 V/decade (or 53 mV/dB) at 2.14 GHz.
where C is the capacitance in farads and fHIGHPASS is in hertz. The
input coupling capacitors must be large enough in value to pass
the input signal frequency of interest and determine the low end
of the frequency response. INHI and INLO can also be driven
differentially using a balun.
VZ is the intercept voltage.
When RMS(RFIN) = VZ, this implies that VOUT = 0 V because
log10(1) = 0. This makes the intercept the input that forces VOUT
0 V if the ADL5902 had no sensitivity limit. The PINTERCEPT (in
=
decibels relative to 1 milliwatt, that is, dBm) corresponding to
VBIAS
Vz (in volts) in ADL5902 is given by the following equation:
VPOS
P
INTERCEPT = −(VPEDISTAL/VSLOPE) + PMINDET
where VPEDISTAL is the VSET interface’s pedestal voltage, and
MINDET is the minimum detectable signal in decibels relative to 1
(8)
ESD
ESD
2kΩ
2kΩ
P
INHI
INLO
milliwatt, given by the following expression:
LOAD
PMINDET = dBm (VATG) – GO
(9)
where dBm(VATG) is the equivalent power in decibels relative to
1 milliwatt corresponding to a given VTGT
Combining Equation 8 and Equation 9 results in
INTERCEPT = −(VPEDISTAL/VSLOPE) + dBm (VATG) – GO
.
ESD
ESD
ESD
ESD
ESD
ESD
ESD
ESD
P
(10)
ESD
ESD
ESD
COMM
For the ADL5902, VPEDISTAL is approximately 0.275 V and VATG is
given by VTGT/20. GO is 45 dB below approximately 4 GHz and
then decreases at higher frequencies. VTGT = 0.8 V; therefore,
Figure 37. RF Inputs
Extensive ESD protection is employed on the RF inputs, and
this protection limits the maximum possible input to the
ADL5902.
V
ATG = 40 mV
and
SMALL SIGNAL LOOP RESPONSE
dBm (VATG) = 10 log10((40 mV)2/50 Ω)/1 mW) ≈ −14.9 dBm
The ADL5902 uses a VGA in a loop to force a squared RF signal
to be equal to a squared dc voltage. This nonlinear loop can be
simplified and solved for a small signal loop response. The low-
pass corner pole is given by
At 2.14 GHz, VSLOPE ≈ 53 mV/dB and GO at 2.14 GHz = 45 dB.
This results in a PINTERCEPT ≈ −65 dBm. This differs slightly from
the value in Table 1 due to the choice of calibration points and
the slight nonideality of the response.
FreqLP ≈ 1.83 × ITGT/(CLPF
where:
TGT is in amperes.
LPF is in farads.
FreqLP is in hertz.
TGT is derived from VTGT; however, ITGT is a squared value of
)
(12)
In most applications, the AGC loop is closed through the
setpoint interface and the VSET pin. In measurement mode,
VOUT is directly connected to VSET (see the Measurement
Mode Basic Connections section for more information). In
controller mode, a control voltage is applied to VSET, and the
VOUT pin typically drives the control input of an amplification
or attenuation system. In this case, the voltage at the VSET pin
forces a signal amplitude at the RF inputs of the ADL5902 that
balances the system through feedback.
I
C
I
V
TGT multiplied by a transresistance, namely
2
I
TGT = gm × VTGT
(13)
gm is approximately 18.9 μs; therefore, with VTGT equal to the
RF INPUT INTERFACE
typically recommended 0.8 V, ITGT is approximately 12 μA. The
value of this current varies with temperature; therefore, the
small signal pole varies with temperature. However, because the
RF squaring circuit and dc squaring circuit track with temperature,
Figure 37 shows the RF input connections within the ADL5902.
The input impedance is set primarily by an internal 2 kΩ resistor
connected between INHI and INLO. A dc level of approximately
Rev. 0 | Page 16 of 28
ADL5902
there is no temperature variation contribution to the absolute value
of VOUT
For CW signals,
Table 4. Recommended VTADJ for Selected Frequencies
.
R9 in Figure 54
Frequency VTADJ (V) (Ω)
R12 in Figure 54
(Ω)
100 MHz
700 MHz
900 MHz
1.9 GHz
2.14 GHz
2.6 GHz
3.5 GHz
5.8 GHz
0.5
0.4
0.4
0.4
0.4
0.45
0.5
1430
1430
1430
1430
1430
1430
1430
1430
402
301
301
301
301
348
402
1007
FreqLP ≈ 67.7 × 10−6/(CLPF
)
(14)
However, signals with large crest factors include low pseudo-
random frequency content that must be either filtered out or
sampled and averaged out (see the Choosing a Value for CLPF
section for more information).
TEMPERATURE SENSOR INTERFACE
0.95
The ADL5902 provides a temperature sensor output with a
scaling factor of the output voltage of approximately 4.9 mV/°C.
The output is capable of sourcing 4 mA and sinking 50 μA
maximum at 25°C. An external resistor can be connected from
TEMP to COMM to provide additional current sink capability.
The typical output voltage at 25°C is approximately 1.4 V.
VPOS
The values in Table 4 were chosen to give the best drift
performance at the high end of the usable dynamic range
over the −40°C to +85°C temperature range. There is often a
trade off in setting values, and optimizing for one area of the
dynamic range may mean less than optimal drift performance
at other input amplitudes.
Compensating the device for temperature drift using TADJ
allows for great flexibility. If the user requires minimum
temperature drift at a given input power, a subset of the
dynamic range, or even over a different temperature range than
shown in this data sheet, the VTADJ can be swept while
monitoring VOUT over the temperature at the frequency and
amplitude of interest. The optimal VTADJ to achieve minimum
temperature drift at a given power and frequency is the value of
INTERNAL
VPAT
TEMP
12kΩ
4kΩ
COMM
Figure 38. TEMP Interface Simplified Schematic
V
TADJ where the output has minimum movement.
VREF INTERFACE
2.83
The VREF pin provides an internally generated voltage reference
for the user. The VREF voltage is a temperature stable 2.3 V
reference that is capable of sourcing 4 mA and sinking 50 μA
maximum. An external resistor can be connected from VREF to
COMM to provide additional current sink capability. The
voltage on this pin can be used to drive the TADJ/PWDN and
VTGT pins.
+125°C
2.81
2.79
2.77
2.75
2.73
+105°C
+85°C
+55°C
+25°C
0°C
–20°C
VPOS
–40°C
INTERNAL
VOLTAGE
VREF
0.1
0.2
0.3
0.4
0.5
(V)
0.6
0.7
0.8
16kΩ
V
TADJ
Figure 40. Effect of VTADJ at Various Temperatures, 2.14 GHz, −10 dBm
COMM
Figure 39. VREF Interface Simplified Schematic
Varying VTADJ has only a very slight effect on VOUT at device
temperatures near 25°C; however, the compensation circuit
has more and more effect as the temperature departs farther
from 25°C.
TEMPERATURE COMPENSATION INTERFACE
While the ADL5902 has a highly stable measurement output
with respect to temperature using proprietary techniques, for
optimal performance, the output temperature drift must be
compensated for using the TADJ pin. The absolute value of
compensation varies with frequency and VTGT. Table 4 shows the
recommended voltages for VTADJ to maintain a temperature drift
error of typically 0.5 dB or better over the intended temperature
range (−40°C < TA < +85°C) when driven single-ended and
The TADJ pin has a high input impedance and can be conven-
iently driven from an external source or from an attenuated
value of VREF using a resistor divider. Table 4 gives suggested
voltage divider values to generate the required voltage from
VREF. The resistors are shown in the evaluation board schematic
(see Figure 54). VREF does change slightly with temperature and
also input RF amplitude; however, the amount of change is
unlikely to result in a significant effect on the final temperature
VTGT = 0.8 V.
Rev. 0 | Page 17 of 28
ADL5902
stability of the RF measurement system. Typically, the
temperature compensation circuit responds only to voltages
between 0 and VS/2, or about 2.5 V when VS = 5 V.
no load is approximately 58 MHz with a single-pole roll off of
approximately −20 dB/decade. The output noise is approxi-
mately 25 nV/√Hz at 100 kHz. The VOUT pin can source and
sink up to 10 mA. There is also an internal load from VOUT
to COMM of 2500 Ω.
Figure 41 in the Power-Down Interface section shows a simpli-
fied schematic representation of the TADJ/PWDN interface.
VPOS
POWER-DOWN INTERFACE
ESD
The quiescent and disabled currents for the ADL5902 at 25°C
are approximately 73 mA and 300 µA, respectively. The dual
function TADJ/PWDN pin is connected to the temperature
compensation circuit as well as the power-down circuit.
Typically, the temperature compensation circuit responds only
to voltages between 0 and VS/2, or about 2.5 V when VS = 5 V.
2pF
CLPF
VOUT
ESD
2kΩ
ESD
500Ω
When the voltage on this pin is greater than VS − 0.1 V, t h e
device is fully powered down. Figure 32 shows this charac-
teristic as a function of VPWDN. Note that, because of the design
of this section of the ADL5902, as VPWDN passes through a
narrow range at ~4.5 V (or ~VS − 0.5 V), the TADJ/PWDN pin
sinks approximately 500 µA. The source used to disable the
ADL5902 must have a sufficiently high current capability for this
reason. Figure 33 shows the typical response times for various
RF input levels. The output reaches within 0.1 dB of its steady-
state value in approximately 5 µs; however, the reference voltage is
available to full accuracy in a much shorter time. This wake-up
COMM
Figure 43. VOUT Interface Simplified Schematic
VTGT INTERFACE
The target voltage can be set with an external source or by
connecting the VREF pin (nominally 2.3 V) to the VTGT pin
through a resistive voltage divider. With 0.8 V on the VTGT pin,
the rms voltage that must be provided by the VGA to balance the
AGC feedback loop is 0.8 V × 0.05 = 40 mV rms. Most of the
characterization information in this data sheet was collected at
response varies depending on the input coupling and CLPF
.
V
TGT = 0.8 V. Voltages higher and lower than this can be used;
VPOS
however, doing so increases or decreases the gain at the internal
squaring cell, which results in a corresponding increase or
decrease in intercept. This, in turn, affects the sensitivity and the
usable measurement range, in addition to the sensitivity to
different carrier modulation schemes. As VTGT decreases, the
squaring circuits produce more noise; this becomes noticeable
in the output response at low input signal amplitudes. As VTGT
increases, measurement error due to modulation increases and
temperature drift tends to decrease. The chosen VTGT value of
0.8 V represents a compromise between these characteristics.
VPOS
ESD
ESD
SHUTDOWN POWER-UP
7kΩ
200Ω
7kΩ
CIRCUIT CIRCUIT
VREF
200Ω
TADJ/
PWDN
200Ω
INTERCEPT
ESD
TEMPERATURE
COMPENSATION
COMM
Figure 41. TADJ/PWDN Interface Simplified Schematic
VSET INTERFACE
The VSET interface has a high input impedance of 72 kΩ. The
voltage at VSET is converted to an internal current used to set
the internal VGA gain. The VGA attenuation control is approx-
imately 19 d B / V.
ESD
2
g × X
ITGT
VTGT
50kΩ
50kΩ
ESD
GAIN ADJUST
54kΩ
VSET
ESD
10kΩ
COMM
18kΩ
Figure 44. VTGT Interface
2.5kΩ
BASIS FOR ERROR CALCULATIONS
The slope and intercept used in the error plots are calculated using
the coefficients of a linear regression performed on data collected
in its central operating range. The error plots in the Typical
Performance Characteristics section are shown in two formats:
error from the ideal line and error with respect to the 25°C
output voltage. The error from the ideal line is the decibel
difference in VOUT from the ideal straight-line fit of VOUT
ACOM
Figure 42. VSET Interface Simplified Schematic
OUTPUT INTERFACE
The ADL5902 incorporates rail-to-rail output drivers with pull-
up and pull-down capabilities. The closed-loop, − 3dB band-
width from the input of the output amplifier to the output with
Rev. 0 | Page 18 of 28
ADL5902
calculated by the linear-regression fit over the linear range of
the detector, typically at 25°C. The error in decibels is calculated
The error calculations for Figure 30 are similar to those for the
VOUT plots. The slope and intercept of the VTEMP function vs.
by
temperature are determined and applied as follows:
Error (°C) = (VTEMP − Slope × (Temp − TZ))/Slope
(16)
Error (dB) = (VOUT − Slope × (PIN − PZ))/Slope
(15)
where:
where PZ is the x-axis intercept expressed in decibels relative to
1 milliwatt (the input amplitude that would produce a 0 V output
if such an output were possible).
TZ is the x-axis intercept expressed in degrees Celsius (the
temperature that would result in a VTEMP of 0 V if this were
possible).
Temp is the ambient temperature of the ADL5902 in degrees
Celsius.
The error from the ideal line is not a measure of absolute accuracy
because it is calculated using the slope and intercept of each
device. However, it verifies the linearity and the effect of
temperature and modulation on the response of the device. An
example of this type of plot is Figure 3. The slope and intercept
that form the ideal line are those at 25°C with CW modulation.
Figure 21 and Figure 24 show the error with various popular
forms of modulation with respect to the ideal CW line. This
method for calculating error is accurate, assuming that each
device is calibrated at room temperature.
Slope is, typically, 4.9 mV/°C.
V
TEMP is the voltage at the TEMP pin at that temperature.
MEASUREMENT MODE BASIC CONNECTIONS
The ADL5902 requires a single supply of nominally 5 V. The
supply is connected to the two VPOS supply pins. These pins
should each be decoupled using the two capacitors with values
equal or similar to those shown in Figure 45. These capacitors
should be placed as close as possible to the VPOS pins.
In the second plot format, the VOUT voltage at a given input
amplitude and temperature is subtracted from the corresponding
An external 60.4 Ω resistor combines with the relatively high RF
input impedance of the ADL5902 to provide a broadband 50 Ω
match. An ac coupling capacitor should be placed between this
resistor and INHI. The INLO input should be ac-coupled to
ground using the same value capacitor. Because the ADL5902
has a minimum input operating frequency of 50 MHz, 100 pF
ac coupling capacitors can be used.
VOUT at 25°C and then divided by the 25°C slope to obtain an
error in decibels. This type of plot does not provide any
information on the linear-in-dB performance of the device; it
merely shows the decibel equivalent of the deviation of VOUT
over temperature, given a calibration at 25°C. When calculating
error from any one particular calibration point, this error
format is accurate. It is accurate over the full range shown on
the plot assuming that enough calibration points are used.
Figure 6 shows this plot type.
The ADL5902 is placed in measurement mode by connecting
VOUT to VSET. In measurement mode, the output voltage is
proportional to the log of the rms input signal level.
5V
5V
C3
0.1µF
C7
0.1µF
C4
100pF
C5
100pF
VPOS
3
POS
10
TEMPERATURE
SENSOR
TEMP
VSET
8
7
ADL5902
C10
100pF
VOUT
INHI
14
15
RFIN
I
DET
2
R3
60.4Ω
X
INLO
C12
100pF
LINEAR-IN-dB VGA
(NEGATIVE SLOPE)
2
X
I
TGT
VOUT
CLPF
2
NC
6
5
G = 5
16
13
NC
NC
BIAS AND POWER-
DOWN CONTROL
VREF
2.3V
C9
10µF
26pF
9
(SEE THE
CHOOSING A
VALUE FOR
11
12
VTGT
1
4
TADJ/PWDN
VREF
COMM COMM
C
SECTION.)
LPF
R9
R10
3.74kΩ
R12
(SEE TABLE 4)
R11
2kΩ
(SEE
TABLE 4)
Figure 45. Basic Connections for Operation in Measurement Mode
Rev. 0 | Page 19 of 28
ADL5902
Figure 46 shows how output noise varies with CLPF when the
ADL5902 is driven by a single-carrier W-CDMA signal (Test
Model TM1-64, peak envelope power = 10.56 dB, bandwidth =
3.84 MHz). With a 10 µF capacitor on CLPF, there is residual
noise on VOUT of 4.4 mV p-p, which is less than 0.1 dB error
(assuming a slope of approximately 53 mV/dB).
SETTING VTADJ
As discussed in the Theory of Operation section, the output
temperature drift must be compensated by applying a voltage to
the TADJ pin. The compensating voltage varies with frequency.
The voltage for the TADJ pin can be easily derived from a resistor
divider connected to the VREF pin. Table 5 shows the recom-
mended VTADJ for operation from −40°C to +85°C, along with
resistor divider values. Resistor values are chosen so that they
neither pull too much current from VREF (VREF short-circuit
current is 4 mA) nor are so large that the TADJ pin’s bias current of
3 µA affects the resulting voltage at the TADJ pin.
300
250
200
150
100
50
1M
100k
10k
1k
OUTPUT NOISE (mV p-p)
10% TO 90% RISE TIME (µs)
90% TO 10% FALL TIME (µs)
Table 5. Recommended VTADJ for Selected Frequencies
Frequency
VTADJ (V) R9 (Ω)
R12 (Ω)
100
10
100 MHz
700 MHz to 2.14 GHz
2.6 GHz
3.5 GHz
5.8 GHz
0.5
1430
1430
1430
1430
1430
402
301
348
402
0.4
0.45
0.5
1
1000
0
0.95
1007
1
10
100
C
(nF)
LPF
SETTING VTGT
Figure 46. Output Noise, Rise and Fall Times vs. CLPF Capacitance, Single-
Carrier W-CDMA (TM1-64) at 2.14 GHz with PIN = 0 dBm
As discussed in the Theory of Operation section, setting the
voltage on VTGT to 0.8 V represents a compromise between
achieving excellent rms compliance and maximizing dynamic
range. The voltage on VTGT can be derived from the VREF pin
using a resistor divider as shown Figure 45. Like the resistors
chosen to set the VTADJ voltage, the resistors setting VTGT should
have reasonable values that do not pull too much current from
VREF or cause bias current errors. Also, attention should be
paid to the combined current that VREF must deliver to
generate the VTADJ and VTGT voltages. This current should be
kept well below the VREF short-circuit current of 4 mA.
Figure 46 also shows how the response time is affected by the
value of CLPF. To measure this, a RF burst at 2.14 GHz at
−10 dBm was applied to the ADL5902. The 10% to 90% rise
time and 90% to 10% fall time were then measured. It is notable
that the fall time is much longer than the rise time. This can
also be seen in the response time plots, Figure 22, Figure 23,
Figure 25, and Figure 26.
In applications where the response time is critical, a different
approach to signal filtering can be taken. This is shown in
Figure 47. The capacitor on the CLPF pin is set to the minimum
value that ensures that a valid rms computation has been
performed. The job of noise removal is then handed off to an
RC filter on the VOUT pin. This approach ensures that there is
enough averaging to ensure good rms compliance and does not
burden the rms computation loop with extra filtering that will
significantly slow down the response time. By finishing the
filtering process using an RC filter after VOUT, faster fall times
can be achieved with an equivalent amount of output noise. It
should be noted that the RC filter can also be implemented in
the digital domain after the analog-to-digital converter.
CHOOSING A VALUE FOR CLPF
CLPF provides the averaging function for the internal rms
computation. Using the minimum value for CLPF allows the
quickest response time to a pulsed waveform but leaves
significant output noise on the output voltage signal. By the
same token, a large filter cap reduces output noise but at the
expense of response time.
For non response-time critical applications, a relatively large
capacitor can be placed on the CLPF pin. In Figure 45, a value
of 10 µF is used. For most signal modulation schemes, this value
ensures excellent rms measurement compliance and low
residual output noise. There is no maximum capacitance limit
for CLPF
.
Rev. 0 | Page 20 of 28
ADL5902
VPOS
3
POS
10
TEMPERATURE
SENSOR
ADL5902
8
7
TEMP
VSET
14
15
INHI
I
DET
2
X
INLO
LINEAR-IN-dB VGA
(NEGATIVE SLOPE)
2
X
I
R
TGT
FILTER
2kΩ
2
NC
6
5
VOUT
FILTER
(SEE FIGURE 48.)
G = 5
26pF
VOUT
C
16
13
NC
NC
BIAS AND POWER-
DOWN CONTROL
VREF
2.3V
CLPF
C9
10nF
(SEE TABLE 6 AND
FIGURE 46.)
11
12
1
9
4
TADJ/PWDN
VREF
VTGT
COMM
COMM
Figure 47. Optimizing Setting Time and Residual Ripple
In Figure 47, CLPF is equal to 10 nF. This value was experiment-
ally determined to be the minimum capacitance that ensures
good rms compliance when the ADL5902 is driven by a 1 C
W-CDMA signal (TM1-64). This test was carried out by
starting out with a large capacitance value on the CLPF pin (for
example, 10 µF). The value of VOUT was noted for a fixed input
power level (for example, −10 dBm). The value of CLPF was then
progressively reduced (this can be done with press-down
capacitors) until the value of VOUT started to deviate from its
original value (this indicates that the accuracy of the rms
computation is degrading and that CLPF is getting too small).
For large values of CFILTER, the fall time is dramatically reduced
compared to Figure 46. This comes at the expense of a moderate
increase in rise time.
As CFILTER is reduced, the fall time flattens out. This is because
the fall time is now dominated by the 10 nF CLPF which is
present throughout the measurement.
Table 6 shows recommended minimum values of CLPF for
popular modulation schemes, using just a single filter capacitor
at the CLPF pin. Using lower capacitor values results in rms
measurement errors. Output response time (10% to 90%) is also
shown. If the output noise shown in Table 6 is unacceptably
high, it can be reduced by
Figure 48 shows the resulting rise and fall times (signal is pulsed
between off and −10 dBm) with CLPF equal to 10 nF. A 2 kΩ
resistor is placed in series with the VOUT pin, and the
capacitance from this resistor to ground (CFILTER in Figure 47) is
varied up to 1 µF.
•
•
•
Increasing CLPF
Adding an RC filter at VOUT, as shown in Figure 47
Implementing an averaging algorithm after the ADL5902’s
output voltage has been digitized by an ADC
300
250
200
150
100
50
1M
100k
10k
1k
RESIDUAL RIPPLE (V p-p)
10% TO 90% RISE TIME (µs)
90% TO 10% FALL TIME (µs)
100
10
0
1
1k
1
10
100
C
(nF)
FILTER
Figure 48. Residual Ripple, Rise and Fall Times Using an RC Low-Pass Filter
at VOUT, PIN = 0 dBm at 2.14 GHz
Rev. 0 | Page 21 of 28
ADL5902
Table 6. Recommended Minimum CLPF Values for Various Modulation Schemes
Peak-Envelope Signal
Modulation/Standard
Power
Bandwidth CLPF (min) Output Noise
Rise/Fall Time (10% to 90%)
12/330 µs
W-CDMA, One-Carrier, TM1-64
10.56 dB
12.08 dB
3.84 MHz
10 nF
5.6 nF
95 mV p-p
W-CDMA Four-Carrier, TM1-64, TM1-32,
TM1-16, TM1-8
18.84 MHz
164 mV p-p
7/200 µs
LTE, TM1 1CR 20 MHz (2048 Subcarriers,
QPSK Subcarrier Modulation)
11.58 dB
20 MHz
1000 pF
452 mV p-p
1.3/38 µs
Table 7. Output Voltage Range Scaling
OUTPUT VOLTAGE SCALING
Desired
Input Range
(dBm)
New
Slope
The output voltage range of the ADL5902 (nominally 0.3 V to
R1
(Ω)
665
R2
(Ω)
Nominal Output
3.5 V) can be easily increased or decreased. There are a number
of situations where adjustment of the output scaling makes
sense. For example, if the ADL5902 is driving an analog-to-
digital converter (ADC) with a 0 V to 5 V input range, it makes
sense to increase the detector’s nominal maximum output
voltage of 3.5 V so that it is closer to 5 V. This makes better use
of the input range of the ADC and maximizes the resolution of
the system in terms of bits/dB.
(mV/dB) Voltage Range (V)
0 to −60
−10 to −50
0 to −60
2000 72.1
1180 2000 86.3
0.195 to 4.52
1.096 to 4.55
0.103 to 2.49
0.587 to 2.43
806
324
2000 38.3
2000 46.2
−10 to −50
Equation 17 is the general function that governs this.
'
VO
VO
(17)
R1 = (R2 || RIN )
−1
If only a part of the ADL5902’s RF input power range is being
used (for example, −10 dBm to −60 dBm), it may make sense to
increase the scaling so that this reduced input range fits into the
ADL5902’s available output swing of 0 V to 4.8 V.
where:
VO is the nominal maximum output voltage (see Figure 6
through Figure 18).
V'O is the new maximum output voltage (for example, up
to 4.8 V).
The output swing can also be reduced by simply adding a
voltage divider on the output pin, as shown in Figure 49.
Reducing the output scaling may be used when interfacing the
ADL5902 to an ADC with a 0 V to 2.5 V input range.
RIN is the VSET input resistance (72 kΩ).
When choosing R1 and R2, attention must be paid to the
current drive capability of the VOUT pin and the input
The output voltage swing can be increased using a technique
that is analogous to setting the gain of an op amp in non-
inverting mode with the VSET pin being the equivalent of the
inverting input of the op amp.
resistance of the VSET pin. The choice of resistors should not
result in excessive current draw out of VOUT. However, making
R1 and R2 too large is also problematic. If the value of R2 is
compatible with the input resistance of the VSET input (72 kΩ),
this input resistance, which will vary slightly from part to part,
contributes to the resulting slope and output voltage. In general,
the value of R2 should be at least ten times smaller than the
input resistance of VSET. Values for R1 and R2 should, therefore,
be in the 1 kΩ to 5 kΩ range.
Connecting VOUT to VSET results in the nominal 0 V to 3.5 V
swing and a slope of approximately 53 mV/dB (this varies
slightly with frequency). Figure 49 and Table 7 show the con-
figurations for increasing the slope, along with recommended
standard resistor values for particular input ranges and output
swings.
It is also important to take into account part-to-part and
frequency variation in output swing along with the ADL5902
output stage’s maximum output voltage of 4.8 V. The VOUT
distribution is well characterized at major frequencies’ bands in
the Typical Performance Characteristics section (see Figure 6
through Figure 8, Figure 12 through Figure 14, Figure 18, and
Figure 19). The resistor values in Table 7, which were calculated
based on 900 MHz performance, are conservatively chosen so
that there is no chance that the output voltages exceed the
ADL5902 output swing or the input range of a 0 V to 2.5 V and
0 V to 5 V ADC. Because the output swing does not vary much
with frequency (it does start to drop off above 3 GHz), these
values work for multiple frequencies.
VSET
VOUT
VSET
VOUT
7
6
7
6
R1
R2
R1
R2
Figure 49. Decreasing and Increasing Slope
Rev. 0 | Page 22 of 28
ADL5902
error at the calibration points (in this case, −40 dBm and 0dBm)
is equal to 0 by definition.
SYSTEM CALIBRATION AND ERROR CALCULATION
The measured transfer function of the ADL5902 at 2.14 GHz is
shown in Figure 50, which contains plots of both output voltage
vs. input amplitude (power) and calculated error vs. input level. As
the input level varies from −62 dBm to +3 dBm, the output
voltage varies from ~0.25 V to ~3.5 V.
The residual nonlinearity of the transfer function that is
apparent in the two-point calibration error plot can be reduced
by increasing the number of calibration points. Figure 50 shows
the postcalibration error plots for three-point and four-point
calibrations. With a multipoint calibration, the transfer function
is segmented, with each segment having its own slope and
intercept. Multiple known power levels are applied, and
multiple voltages are measured. When the equipment is in
operation, the measured voltage from the detector is first used
to determine which of the stored slope and intercept calibration
coefficients are to be used. Then the unknown power level is
calculated by inserting the appropriate slope and intercept into
Equation 21.
6
5
4
3
2
1
0
6
V
OUT
5
ERROR 2-POINT CAL AT 0dBm, AND 40dBm
ERROR 3-POINT CAL AT 0 dBm,
–45dBm, AND 60dBm
ERROR 4-POINT CAL AT 0dBm, –20dBm,
–45dBm, AND –60dBm
4
3
2
1
0
–1
–2
–3
–4
–5
–6
Figure 51 shows the output voltage and error at 25°C and over
temperature when a four-point calibration is used (calibration
points are 0 dBm, −20 dBm, −45 dBm, and −60 dBm). When
choosing calibration points, there is no requirement for, or
value, in equal spacing between the points. There is also no
limit to the number of calibration points used. However, using
more calibration points increases calibration time.
–70
–60
–50
–40
–30
–20
–10
0
10
P
(dBm)
IN
Figure 50. 2.14 GHz Transfer Function, Using Various Calibration Techniques
Because slope and intercept vary from device to device, board-
level calibration must be performed to achieve high accuracy.
The equation for the idealized output voltage can be written as
6
5
4
3
2
1
0
6
+85°C VOUT
+25°C VOUT
–40°C VOUT
+85°C ERROR 4-POINT CAL
+25°C ERROR 4-POINT CAL AT 0dBm,
–20dBm, –45dBm, AND –60dBm
5
4
V
OUT(IDEAL) = Slope × (PIN − Intercept)
(18)
3
–40°C ERROR 4-POINT CAL
2
where:
1
Slope is the change in output voltage divided by the change in
input power (dB).
Intercept is the calculated input power level at which the output
voltage is 0 V (note that Intercept is an extrapolated theoretical
value not a measured value).
0
–1
–2
–3
–4
–5
–6
In general, calibration is performed during equipment manu-
facture by applying two or more known signal levels to the
input of the ADL5902 and measuring the corresponding output
voltages. The calibration points are generally within the linear-
in-dB operating range of the device.
–70
–60
–50
–40
–30
–20
–10
0
10
P
(dBm)
IN
Figure 51. 2.14 GHz Transfer Function and Error at +25°C, −40°C, and +85°C
Using a Four-Point Calibration (0 dBm, −20 dBm, −45 dBm, −60 dBm)
With a two-point calibration, the slope and intercept are
calculated as follows:
The −40°C and +85°C error plots in Figure 51 are generated
using the 25°C calibration coefficients. This is consistent with
equipment calibration in a mass production environment where
calibration at just a single temperature is practical.
Slope = (VOUT1 − VOUT2)/(PIN1 − PIN2
Intercept = PIN1 − (VOUT1/Slope)
)
(19)
(20)
After the slope and intercept are calculated and stored in non-
volatile memory during equipment calibration, an equation can
be used to calculate an unknown input power based on the
output voltage of the detector.
HIGH FREQUENCY PERFORMANCE
The ADL5902 is specified to 6 GHz; however, operation is
possible to as high as 9 GHz with sufficient dynamic range for
many purposes. Figure 52 shows the typical VOUT response and
conformance error at 7 GHz, 8 GHz, and 9 GHz.
PIN (Unknown) = (VOUT1(MEASURED)/Slope) + Intercept
(21)
The log conformance error is the difference between this
straight line and the actual performance of the detector.
Error (dB) = (VOUT(MEASURED) − VOUT(IDEAL))/Slope
(22)
Figure 50 includes a plot of this error when using a two-point
calibration (calibration points are 0 dBm and −40 dBm). The
Rev. 0 | Page 23 of 28
ADL5902
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
6
was driven in a single-ended configuration for most character-
ization, except where noted.
7GHz
8GHz
9GHz
5
4
Much of the data was taken using an Agilent E4438C signal
source as a RF input stimulus. Several ADL5902 devices
mounted on circuit boards constructed of Rodgers 3006
material were put into a test chamber simultaneously, and a
Keithley S46 RF switching network connected the signal source
to the appropriate device under test. The test chamber
temperature was set to cycle over the appropriate temperature
range. The signal source, switching, and chamber temperature
were all controlled by a PC running Agilent VEE Pro.
3
2
1
0
–1
–2
–3
–4
–5
–6
0
–50
The subsequent response to stimulus was measured with a
voltmeter and the results stored in a database for analysis later.
In this way, multiple ADL5902 devices were characterized over
amplitude, frequency, and temperature in a minimum amount
of time. The RF stimulus amplitude was calibrated up to the
circuit board that carries the ADL5902, and, thus, it does not
account for the slight losses due to the connector on the circuit
board that carries the ADL5902 nor for the loss of traces on the
circuit board. For this reason, there is a small absolute amplitude
error (generally <0.5 dB) not accounted for in the characteriza-
tion data, but this is generally not important because the
ADL5902’s relative accuracy is unaffected.
–40
–30
–20
–10
0
10
P
(dBm)
IN
Figure 52. Typical VOUT and Log Conformance Error at 7 GHz, 8 GHz,
and 9 GHz, 25°C Only
LOW FREQUENCY PERFORMANCE
The lowest frequency of operation of the ADL5902 is approxi-
mately 50 MHz. This is the result of the circuit design and
architecture of the ADL5902.
DESCRIPTION OF CHARACTERIZATION
The general hardware configuration used for most of the
ADL5902 characterization is shown in Figure 53. The ADL5902
AGILENT E3631A
DC POWER
SUPPLIES
AGILENT 34980A
SWITCH MATRIX/
DC METER
ADL5902
CHARACTERIZ ATION
BOARD – TEST SITE 1
AGILENT E8251A
MICROWAVE
SIGNAL
KEITHLEY S46
MICROWAVE
SWITCH
ADL5902
CHARACTERIZ ATION
BOARD – TEST SITE 2
GENERATOR
ADL5902
CHARACTERIZ ATION
BOARD – TEST SITE 3
PERSONAL
COMPUTER
RF
DC
DATA AND CONTROL
Figure 53. General Characterization Configuration
Rev. 0 | Page 24 of 28
ADL5902
EVALUATION BOARD SCHEMATICS AND ARTWORK
VTGT
VREF
VPOS2
C7
0.1µF
VPOS
R7
0Ω
R8
0Ω
R14
0Ω
C5
100pF
R11
1kΩ
R10
1.87kΩ
12 11 10
9
VSET
TEMP
R2
OPEN
R13
OPEN
VOUT
13
8
7
6
C10
C11
NC
TEMP
0.1µF OPEN
14
15
16
R6
0Ω
R15
0Ω
IN
INHI
INLO
NC
VSET
VOUT
CLPF
R1
0Ω
ADL5902
DUT1
VOUTP
R3
60.4Ω
C6
OPEN
C12
0.1µF
5
C9
0.1µF
C8
OPEN
R5
0Ω
1
2
3
4
PADDLE
AGND
TC2_PWDN
R12
C4
100pF
GND
GND
R9
R16
0Ω
C13
0.1µF
301Ω
1430Ω
VPOSC
VREF
VPOS1
Figure 54. Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options
Component
Function/Notes
Default Value
C6, C10, C11,
C12, R3
RF input. The ADL5902 is generally driven single-ended. When driving INHI, populate C10 and C12 C6 = open,
with an appropriate capacitor value for the frequency of operation and leave C6 and C11 open.
When driving INLO, populate C6 and C11 with an appropriate capacitor value for the frequency of
operation and leave C10 and C12 open. R3 is the input termination resistor and is chosen to give a
50 Ω input impedance over a broad frequency range.
C10 = C12 = 0.1 µF,
C11 = open,
R3 = 60.4 Ω
R7, R8, R10,
R11
VTGT interface. R10 and R11 are set up to provide 0.8 V to VTGT derived from VREF. If R10 and R11
are removed, an external voltage can be applied. Alternatively, R7 and R11 can be used to form a
voltage divider for an external reference.
R7 = R8 = 0 Ω,
R10 = 1.87 kΩ,
R11 = 1k Ω
C4, C5, C7,
Power supply decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor
C4 = C5 = 100 pF,
C13, R14, R16
placed close to the ADL5902, a 0 Ω series resistor, and a 0.1 μF capacitor placed close to the power C7 = C13 = 0.1 µF,
supply input pin.
R14 = R16 = 0 Ω
R1, R2, R6,
R13, R15
Output interface. In measurement mode, a portion of the voltage at the VOUT pin is fed back to
the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude of the slope of
VOUT is increased by reducing the portion of VOUT that is fed back to VSET. In controller mode, R6
must be open and R13 must have a 0 Ω resistor. In this mode, the ADL5902 can control the gain of
an external component. A setpoint voltage is applied to the VSET pin, the value of which
corresponds to the desired RF input signal level applied to the ADL5902.
R1 = R6 = R15 = 0 Ω,
R2 = R13 = open
C8, C9, R5
R9, R12
Paddle
Low-pass filter capacitors, CLPF. The low-pass filter capacitors reduce the noise on the output and
affect the response time of the ADL5902.
C8 = open,
C9 = 0.1 µF,
R5 = 0 Ω,
R9 = 1430 Ω
R12 = 301 Ω
TADJ/PWDN. The TADJ/PWDN pin controls the amount of nonlinear intercept temperature
compensation and/or shuts down the device. The evaluation board is configured with TADJ
connected to VREF through a resistor divider (R9, R12).
The paddle should be tied to both a thermal ground and an electrical ground.
Rev. 0 | Page 25 of 28
ADL5902
ASSEMBLY DRAWINGS
Figure 56. Evaluation Board Layout, Bottom Side
Figure 55. Evaluation Board Layout, Top Side
Rev. 0 | Page 26 of 28
ADL5902
OUTLINE DIMENSIONS
4.00
BSC SQ
0.60 MAX
0.60 MAX
0.65 BSC
PIN 1
INDICATOR
13
16
1
12
9
PIN 1
INDICATOR
2.50
2.35 SQ
2.20
TOP
VIEW
EXPOSED
3.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
4
8
5
0.25 MIN
0.80 MAX
0.65 TYP
12° MAX
1.95 BSC
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.35
0.30
0.25
0.20 REF
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-10)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Ordering
Package Option Quantity
Model1
Package Description
ADL5902ACPZ-R7
ADL5902ACPZ-R2
ADL5902ACPZ-WP
ADL5902-EVALZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-10
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-10
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-10
Evaluation Board
1,500
250
64
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
ADL5902
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08218-0-4/10(0)
Rev. 0 | Page 28 of 28
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