ADL5330_05 [ADI]
10 MHz to 3 GHz VGA with 60 dB Gain Control Range; 10MHz到3GHz的VGA，具有60分贝增益控制范围
| 型号： | ADL5330_05 |
| 厂家： | 
ADI |
| 描述： | 10 MHz to 3 GHz VGA with 60 dB Gain Control Range |
| 文件： | 总24页 (文件大小：865K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10 MHz to 3 GHz VGA with
60 dB Gain Control Range
ADL5330
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Voltage-controlled amplifier/attenuator
Operating frequency 10 MHz to 3 GHz
Optimized for controlling output power
High linearity: OIP3 31 dBm @ 900 MHz
Output noise floor: −150 dBm/Hz @ 900 MHz
50 Ω input and output impedances
Single-ended or differential operation
Wide gain-control range: −34 dB to +22 dB @ 900 MHz
Linear-in-dB gain control function, 20 mV/dB
Single-supply 4.75 V to 5.25 V
GAIN
VPS1
ENBL VPS2 VPS2 VPS2 VPS2
VPS2
GAIN
CONTROL
COM1
INHI
COM2
OPHI
INPUT
GM
O/P
(TZ)
RFOUT
RFIN
STAGE
STAGE
INLO
OPLO
COM2
BALUN
COM1
BIAS
AND
VREF
VPS1
VREF
VPS2
APPLICATIONS
Transmit and receive power control at RF and IF
IPBS OPBS COM1 COM2 COM2
Figure 1.
GENERAL DESCRIPTION
The ADL5330 is a high performance, voltage-controlled
variable gain amplifier/attenuator for use in applications with
frequencies up to 3 GHz. The balanced structure of the signal
path minimizes distortion while it also reduces the risk of
spurious feed-forward at low gains and high frequencies caused
by parasitic coupling. While operation between a balanced
source and load is recommended, a single-sided input is
internally converted to differential form.
The output of the high accuracy wideband attenuator is applied
to a differential transimpedance output stage. The output stage
sets the 50 Ω differential output impedances and drives
Pin OPHI and Pin OPLO. The ADL5330 has a power-down
function. It can be powered down by a Logic LO input on the
ENBL pin. The current consumption in power-down mode is
250 μA.
The ADL5330 is fabricated on an ADI proprietary high
performance, complementary bipolar IC process. The ADL5330
is available in a 24-lead (4 mm × 4 mm), Pb-free LFCSP_VQ
package and is specified for operation from ambient
temperatures of −40°C to +85°C. An evaluation board is also
available.
The input impedance is 50 Ω from INHI to INLO. The outputs
are usually coupled into a 50 Ω grounded load via a 1:1 balun. A
single supply of 4.75 V to 5.25 V is required.
The 50 Ω input system converts the applied voltage to a pair of
differential currents with high linearity and good common
rejection even when driven by a single-sided source. The signal
currents are then applied to a proprietary voltage-controlled
attenuator providing precise definition of the overall gain under
the control of the linear-in-dB interface. The GAIN pin accepts
a voltage from 0 V at minimum gain to 1.4 V at full gain with a
20 mV/dB scaling factor.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADL5330
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 12
Applications..................................................................................... 13
Basic Connections...................................................................... 13
RF Input/Output Interface ........................................................ 14
Gain Control Input .................................................................... 15
Automatic Gain Control............................................................ 15
Interfacing to an IQ Modulator................................................ 17
WCDMA Transmit Application ............................................... 18
CDMA2000 Transmit Application........................................... 19
Soldering Information ............................................................... 19
Evaluation Board........................................................................ 20
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 6
Changes to Figure 27...................................................................... 11
Changes to Figure 35...................................................................... 14
Changes to the Gain Control Input Section................................ 15
Changes to Figure 42...................................................................... 17
4/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADL5330
SPECIFICATIONS
VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
GENERAL
Usable Frequency Range
Nominal Input Impedance
Nominal Output Impedance
100 MHz
0.01
3
GHz
Ω
Ω
Via 1:1 single-sided-to-differential balun
Via 1:1 differential-to-single-sided balun
50
50
Gain Control Span
Maximum Gain
Minimum Gain
3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.1 V
30 MHz around center frequencyꢀ
VGAIN = 1.0 V (differential output)
58
23
−35
0.09
dB
dB
dB
dB
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Noise Figure
20.7
0.88
1.8
−0.3
38
−140
7.8
−12.8
−15.5
mV/dB
V
Gain = 0 dBꢀ gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offsetꢀ VGAIN = 1.4 V
VGAIN = 1.4 V
dBm
dBm
dBm
dBm/Hz
dB
Input Return Loss2
1 V < VGAIN < 1.4 V
dB
dB
Output Return Loss2
450 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.1 V
57
22
−35
0.08
dB
dB
dB
dB
30 MHz around center frequencyꢀ
V
GAIN = 1.0 Vꢀ (differential output)
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Noise Figure
20.4
0.89
3.3
1.2
36
−146
8.0
−19
−13.4
mV/dB
V
Gain = 0 dBꢀ gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offsetꢀ VGAIN = 1.4 V
VGAIN = 1.4 V
dBm
dBm
dBm
dBm/Hz
dB
Input Return Loss2
1 V < VGAIN < 1.4 V
dB
dB
Output Return Loss2
900 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.2 V
53
21
−32
0.14
dB
dB
dB
dB
30 MHz around center frequencyꢀ
V
GAIN = 1.0 V (differential output)
Gain Control Slope
19.7
0.92
2.7
mV/dB
V
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Gain = 0 dBꢀ gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offsetꢀ VGAIN = 1.4 V
VGAIN = 1.4 V
dBm
dBm
dBm
dBm/Hz
dB
1.3
31.5
−144
9.0
−18
−18
Noise Figure
Input Return Loss2
1 V < VGAIN < 1.4 V
dB
dB
Output Return Loss2
Rev. A | Page 3 of 24
ADL5330
Parameter
Conditions
Min
Typ
Max
Unit
2200 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.6 V
30 MHz around center frequencyꢀ
VGAIN = 1.0 V (differential output)
46
16
−30
0.23
dB
dB
dB
dB
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Noise Figure
16.7
1.06
0.9
−2.0
21.2
−147
12.5
−11.7
−9.5
mV/dB
V
Gain = 0 dBꢀ gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offsetꢀ VGAIN = 1.4 V
VGAIN = 1.4 V
dBm
dBm
dBm
dBm/Hz
dB
Input Return Loss2
1 V < VGAIN < 1.4 V
dB
dB
Output Return Loss2
2700 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.7 V
30 MHz around center frequencyꢀ
VGAIN = 1.0 V (differential output)
42
10
−32
0.3
dB
dB
dB
dB
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
16
1.15
1.2
−0.9
17
−152
14.7
−9.7
−5
mV/dB
V
Gain = 0 dBꢀ gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offsetꢀ VGAIN = 1.4 V
VGAIN = 1.4 V
dBm
dBm
dBm
dBm/Hz
dB
Noise Figure
Input Return Loss2
1 V < VGAIN < 1.4 V
dB
dB
Output Return Loss2
GAIN CONTROL INPUT
Gain Control Voltage Range3
Incremental Input Resistance
Response Time
GAIN pin
0
1.4
V
GAIN pin to COM1 pin
1
380
20
MΩ
ns
ns
Full scale: to within 1 dB of final gain
3 dB gain stepꢀ POUT to within 1 dB of final gain
Pin VPS1ꢀ Pin VPS2ꢀ Pin COM1ꢀ Pin COM2ꢀ Pin ENBL
POWER SUPPLIES
Voltage
4.75
5
5.25
V
Currentꢀ Nominal Active
VGN = 0 V
VGN = 1.4 V
ENBL = LO
100
215
250
mA
mA
μA
Currentꢀ Disabled
1 Noise floor varies slightly with output power level. See Figure 9 through Figure 13.
2 See Figure 27 and Figure 29 for differential input and output impedances.
3 Minimum gain voltage varies with frequency. See Figure 3 through Figure 7.
Rev. A | Page 4 of 24
ADL5330
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPS1ꢀ VPS2
RF Input Power at Maximum Gain
OPHIꢀ OPLO
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
5 dBm at 50 Ω
5.5 V
VPS1ꢀ VPS2
2.5 V
1.1 W
60°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
ENBL
GAIN
Internal Power Dissipation
θJA (with Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitryꢀ permanent damage may occur on devices subjected to high energy
electrostatic discharges. Thereforeꢀ proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 24
ADL5330
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPS1
COM1
INHI
INLO
COM1
VPS1
1
2
3
4
5
6
18 VPS2
17 COM2
16 OPHI
15 OPLO
14 COM2
13 VPS2
PIN 1
INDICATOR
ADL5330
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
VPS1ꢀ VPS2
COM1
INHIꢀ INLO
VREF
Descriptions
1ꢀ 6ꢀ 13ꢀ 18 to 22
2ꢀ 5ꢀ 10
3ꢀ 4
7
8
9
Positive Supply. Nominally equal to 5 V.
Common for Input Stage.
Differential Inputsꢀ AC-Coupled.
Voltage Reference. Output at 1.5 V; normally ac-coupled to ground.
Input Bias. Normally ac-coupled to ground.
Output Bias. AC-Coupled to ground.
IPBS
OPBS
11
12ꢀ 14ꢀ 17
15
16
23
24
GNLO
COM2
OPLO
OPHI
ENBL
Gain Control Common. Connect to ground.
Common for Output Stage.
Low Side of Differential Output. Bias to VP with RF chokes.
High Side of Differential Output. Bias to VP with RF chokes.
Device Enable. Apply logic high for normal operation.
Gain Control Voltage Input. Nominal range 0 V to 1.4 V.
GAIN
Rev. A | Page 6 of 24
ADL5330
TYPICAL PERFORMANCE CHARACTERISTICS
30
4
30
20
12
9
–40°C ERROR
+25°C ERROR
–40°C GAIN
20
3
10
2
10
6
+85°C ERROR
–40°C ERROR
0
1
0
3
–10
–20
–30
–40
–50
0
–10
–20
–30
–40
–50
0
+25°C ERROR
–1
–2
–3
–4
–3
–6
–9
+85°C GAIN
+85°C ERROR
+25°C GAIN
–40°C GAIN
+85°C GAIN
+25°C GAIN
0.2 0.4
–12
1.4
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
0
0.6
V
0.8
(V)
1.0
1.2
GAIN
GAIN
Figure 3. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 100 MHz
Figure 6. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 2200 MHz
30
20
4
20
10
12
9
–40°C GAIN
–40°C GAIN
3
–40°C ERROR
+25°C GAIN
10
2
0
6
0
1
–10
–20
–30
–40
–50
–60
3
–40°C ERROR
–10
–20
–30
–40
–50
0
0
+85°C GAIN
+25°C ERROR
–1
–2
–3
–4
–3
–6
–9
–12
+25°C ERROR
+85°C ERROR
+85°C ERROR
+25°C GAIN
0.2 0.4
+85°C GAIN
0
0.6
V
0.8
(V)
1.0
1.2
1.4
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
GAIN
GAIN
Figure 4. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 450 MHz
Figure 7. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 2700 MHz
30
20
180
160
140
120
100
80
4
–40°C GAIN
+25°C GAIN
3
10
2
–40°C ERROR
0
1
V
= 1.0V
–10
–20
–30
–40
–50
0
GAIN
–1
–2
–3
–4
+25°C ERROR
60
40
+85°C ERROR
+85°C GAIN
20
0
10
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
100
1,000
10,000
FREQUENCY (kHz)
GAIN
Figure 5. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 900 MHz
Figure 8. Frequency Response of Gain Control Input,
Carrier Frequency = 900 MHz
Rev. A | Page 7 of 24
ADL5330
40
30
20
–115
–120
–125
–130
–135
–140
–145
–150
–155
–115
–120
–125
–130
–135
–140
–145
–150
–155
OIP3
OIP3
30
20
10
INPUT P1dB
INPUT P1dB
10
0
0
–10
–20
–30
–40
–50
–10
–20
–30
–40
OUTPUT P1dB
OUTPUT P1dB
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
GAIN
GAIN
Figure 9. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 100 MHz
Figure 12. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 2200 MHz
40
30
–120
–125
–130
–135
–140
–145
–150
–155
–160
–115
OIP3
OIP3
30
20
–120
–125
–130
–135
–140
–145
–150
–155
20
10
INPUT P1dB
INPUT P1dB
10
0
0
–10
–20
–30
–40
–50
OUTPUT P1dB
–10
–20
–30
–40
OUTPUT P1dB
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
GAIN
GAIN
Figure 10. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 450 MHz
Figure 13. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 2700 MHz
T
40
–115
–120
–125
–130
–135
–140
–145
–150
–155
T
30
20
OIP3
INPUT P1dB
10
0
2
–10
–20
–30
–40
OUTPUT P1dB
1
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
CH1 200mV CH2 100mV Ω M100ns
382.000ns
A CH4
2.70V
GAIN
T
Figure 11. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 900 MHz
Figure 14. Step Response of Gain Control Input
Rev. A | Page 8 of 24
ADL5330
30
20
40
30
OIP3 (–40°C)
20
10
10
OIP3 (–40°C)
OIP3 (+85°C)
0
OIP3 (+85°C)
OP1dB (–40°C)
OIP3 (+25°C)
0
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
OP1dB (+85°C)
OIP3 (+25°C)
OP1dB (+85°C)
OP1dB (–40°C)
0.2 0.4
OP1dB (+25°C)
OP1dB (+25°C)
0
0.6
V
0.8
(V)
1.0
1.2
1.4
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
GAIN
GAIN
Figure 18. OP1dB and OIP3 vs. Gain over Temperature at 2200 MHz
Figure 15. OP1dB and OIP3 vs. Gain over Temperature at 100 MHz
20
10
40
OIP3 (+85°C)
30
20
0
OIP3 (+85°C)
10
0
OIP3 (–40°C)
OIP3 (+25°C)
–10
OIP3 (+25°C)
OP1dB (+25°C)
–20
–10
–20
–30
–40
OP1dB (–40°C)
OIP3 (–40°C)
OP1dB (+25°C)
OP1dB (+85°C)
–30
–40
–50
OP1dB (+85°C)
OP1dB (–40°C)
0.2 0.4
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
0
0.6
V
0.8
(V)
1.0
1.2
1.4
GAIN
GAIN
Figure 16. OP1dB and OIP3 vs. Gain over Temperature at 450 MHz
Figure 19. OP1dB and OIP3 vs. Gain over Temperature at 2700 MHz
40
250
OIP3 (–40°C)
OP1dB (+25°C)
30
OIP3 (+85°C)
200
20
TEMP = +85°C
10
150
OIP3 (+25°C)
TEMP = +25°C
0
TEMP = –40°C
100
–10
OP1dB (+85°C)
–20
50
0
–30
OP1dB (–40°C)
–40
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
GAIN
GAIN
Figure 20. Supply Current vs. VGAIN and Temperature
Figure 17. OP1dB and OIP3 vs. Gain over Temperature at 900 MHz
Rev. A | Page 9 of 24
ADL5330
70
60
50
40
30
20
10
0
30
25
20
15
10
5
0
18.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5
18 18.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24
OP1dB (dBm)
OIP3 (dBm)
Figure 21. OP1dB Distribution at 900 MHz at Maximum Gain, VGAIN = 1.4 V
Figure 24. OIP3 Distribution at 2200 MHz at Maximum Gain; VGAIN = 1.4 V
30
25
20
15
10
5
30
V
V
= 1.4V
= 1.2V
GAIN
GAIN
20
10
V
V
V
= 1.0V
= 0.8V
= 0.6V
GAIN
GAIN
GAIN
0
–10
–20
–30
–40
–50
V
V
= 0.4V
= 0.2V
GAIN
GAIN
0
9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16
10
100
1,000
10,000
OP1dB (dBm)
FREQUENCY (MHz)
Figure 22. OP1dB Distribution at 2200 MHz at Maximum Gain, VGAIN = 1.4 V
Figure 25. Gain vs. Frequency (Differential)
30
20
30
25
20
15
10
5
V
= 1.4V
= 1.2V
GAIN
V
V
GAIN
10
= 1.0V
= 0.8V
= 0.6V
GAIN
0
V
V
V
GAIN
GAIN
GAIN
–10
–20
–30
–40
–50
= 0.4V
= 0.2V
V
GAIN
0
28
10
100
1,000
10,000
29
30
31
32
33
34
35
28.5
29.5
30.5
31.5
32.5
33.5
34.5
33.5
FREQUENCY (MHz)
OIP3 (dBm)
Figure 26. Gain vs. Frequency (Using ETC1-1-13 Baluns)
Figure 23. OIP3 Distribution at 900 MHz at Maximum Gain, VGAIN = 1.4 V
Rev. A | Page 10 of 24
ADL5330
90
90
60
60
120
120
150
30
150
30
450MHz
V
= 0.2V
GAIN
450MHz
V
= 0.2V
GAIN
V
= 1.2V
GAIN
3GHz
180
0
180
0
3GHz
1.9GHz
V
= 1.2V
GAIN
1.9GHz
210
330
210
330
240
300
240
300
270
270
Figure 27. Input Impedance (Differential)
Figure 29. Output Impedance (Differential)
0
–5
0
–5
–10
–15
–20
–25
–30
–35
–10
–15
–20
–25
–30
–35
100
600
1100
1600
2100
2600
100
600
1100
1600
2100
2600
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 28. Input Return Loss with ETC1-1-13 Baluns
Figure 30. Output Return Loss with ETC1-1-13 Baluns
Rev. A | Page 11 of 24
ADL5330
THEORY OF OPERATION
The ADL5330 is a high performance, voltage-controlled
variable gain amplifier/attenuator for use in applications with
frequencies up to 3 GHz. This device is intended to serve as an
output variable gain amplifier (OVGA) for applications where a
reasonably constant input level is available and the output level
adjusts over a wide range. One aspect of an OVGA is the output
metrics, IP3 and P1dB, decrease with decreasing gain.
Linear-in-dB gain control is accomplished by the application of
a voltage in the range of 0 Vdc to 1.4 Vdc to the gain control pin,
with maximum gain occurring at the highest voltage.
The output of the ladder attenuator is passed into a fixed-gain
transimpedance amplifier (TZA) to provide gain and buffer the
ladder terminating impedance from load variations. The TZA
uses feedback to improve linearity and to provide controlled
50 Ω differential output impedance. The quiescent current of
the output amplifier is adaptive; it is slaved to the gain control
voltage to conserve power at times when the gain (and hence,
output power) are low.
The signal path is fully differential throughout the device in
order to provide the usual benefits of differential signaling,
including reduced radiation, reduced parasitic feedthrough, and
reduced susceptibility to common-mode interference with other
circuits. Figure 31 provides a simplified schematic of the
ADL5330.
The outputs of the ADL5330 require external dc bias to the
positive supply voltage. This bias is typically supplied through
external inductors. The outputs are best taken differentially to
avoid any common-mode noise that is present, but, if necessary,
can be taken single-ended from either output.
TRANSIMPEDANCE
AMPLIFIER
INHI
OPHI
INLO
OPLO
If only a single output is used, it is still necessary to provide
bias to the unused output pin, and it is advisable to arrange a
reasonably equivalent ac load on the unused output. Differential
output can be taken via a 1:1 balun into a 50 Ω environment. In
virtually all cases, it is necessary to use dc blocking in the
output signal path.
Gm STAGE
GAIN
CONTROL
Figure 31. Simplified Schematic
At high gain settings, the noise floor is set by the input stage, in
which case the noise figure (NF) of the device is essentially
independent of the gain setting. Below a certain gain setting,
however, the input stage noise that reaches the output of the
attenuator falls below the input-equivalent noise of the output
stage. In such a case, the output noise is dominated by the
output stage itself; therefore, the overall NF of the device gets
worse on a dB-per-dB basis, because the gain is reduced below
the critical value. Figure 9 through Figure 13 provide details of
this behavior.
A controlled input impedance of 50 Ω is achieved through a
combination of passive and active (feedback-derived)
termination techniques in an input Gm stage. The input
compression point of the Gm stage is 1 dBm to 3 dBm,
depending on the input frequency.
Note that the inputs of the Gm stage are internally biased to a
dc level, and dc blocking capacitors are generally needed on the
inputs to avoid upsetting operation of the device.
The currents from the Gm stage are then injected into a
balanced ladder attenuator at a deliberately diffused location
along the ladder, wherein the location of the centroid of the
injection region is dependent on the applied gain control
voltage. The steering of the current injection into the ladder is
accomplished by proprietary means to achieve linear-in-dB gain
control and low distortion.
Rev. A | Page 12 of 24
ADL5330
APPLICATIONS
Since the differential outputs are biased to the positive supply,
ac-coupling capacitors, preferably 100 pF, are needed between
the ADL5330 outputs and the next stage in the system.
Similarly, the INHI and INLO input pins are at bias voltages of
about 3.3 V above ground.
BASIC CONNECTIONS
Figure 32 shows the basic connections for operating the
ADL5330. There are two positive supplies, VPS1 and VPS2,
which must be connected to the same potential. Both COM1
and COM2 (common pins) should be connected to a low
impedance ground plane.
The nominal input and output impedance looking into each
individual RF input/output pin is 25 Ω. Consequently, the
differential impedance is 50 Ω.
A power supply voltage between 4.75 V and 5.25 V should be
applied to VPS1 and VPS2. Decoupling capacitors with 100 pF
and 0.1 μF power supplies should be connected close to each
power supply pin. The VPS2 pins (Pin 18 through Pin 22) can
share a pair of decoupling capacitors because of their proximity
to each other.
To enable the ADL5330, the ENBL pin must be pulled high.
Taking ENBL low puts the ADL5330 in sleep mode, reducing
current consumption to 250 μA at ambient. The voltage on
ENBL must be greater than 1.7 V to enable the device. When
enabled, the device draws 100 mA at low gain to 215 mA at
maximum gain.
The outputs of the ADL5330, OPHI and OPLO, are open
collectors that need to be pulled up to the positive supply with
120 nH RF chokes. The ac-coupling capacitors and the RF
chokes are the principle limitations for operation at low
frequencies. For example, to operate down to 1 MHz, 0.1 μF ac-
coupling capacitors and 1.5 μH RF chokes should be used. Note
that in some circumstances, the use of substantially larger
inductor values results in oscillations.
VPOS
VPOS
C1
C3
0.1μF
0.1μF
C2
C4
100pF
100pF
GAIN
L1
120nH
VPOS
C12
C16
L2
120nH
0.1μF
100pF
VPS1
COM1
INHI
VPS2
COM2
OPHI
C13
100pF
C5
100pF
RF INPUT
VPOS
RF OUTPUT
ADL5330
INLO
COM1
VPS1
OPLO
COM2
VPS2
C14
100pF
C6
100pF
C12
0.1μF
C11
100pF
C7
100pF
C8
0.1μF
C9
1nF
C10
1nF
VPOS
Figure 32. Basic Connections
Rev. A | Page 13 of 24
ADL5330
band baluns can be used for applications requiring lower
insertion loss over smaller bandwidths.
RF INPUT/OUTPUT INTERFACE
The ADL5330 is primarily designed for differential signals;
however, there are several configurations that can be
implemented to interface the ADL5330 to single-ended
applications. Figure 33 to Figure 35 show three options for
differential-to-single-ended interfaces. All three configurations
use ac-coupling capacitors at the input/output and RF chokes at
the output.
The device can be driven single-ended with similar
performance, as shown in Figure 34. The single-ended input
interface can be implemented by driving one of the input
terminals and terminating the unused input to ground. To
achieve the optimal performance, the output must remain
balanced. In the case of Figure 34, a transformer balun is used at
the output.
+5V
As an alternative to transformer baluns, lumped-element baluns
comprised of passive L and C components can be designed at
specific frequencies. Figure 35 illustrates differential balance at
the input and output of the ADL5330 using discrete lumped-
element baluns. The lumped-element baluns present 180° of
phase difference while also providing impedance
transformation from source to load, and vice versa. Table 4 lists
recommended passive values for various center frequencies
with single-ended impedances of 50 Ω. Agilent’s free
AppCADTM program allows for simple calculation of passive
components for lumped-element baluns.
120nH
120nH
ADL5330
RF VGA
100pF
100pF
100pF
100pF
RFIN
INHI
OPHI
RFOUT
INLO
OPLO
ETC1-1-13
ETC1-1-13
Figure 33. Differential Operation with Balun Transformers
+5V
The lumped-element baluns offer 0.5 dB flatness across
50 MHz for 900 MHz and 2200 MHz. At 2.7 GHz, the
frequency band is limited by stray capacitances that dominate
the passive components in the lumped-element balun at these
high frequencies. Thus, PCB parasitics must be considered
during lumped-element balun design and board layout.
120nH
120nH
ADL5330
100pF
100pF
100pF
100pF
RF VGA
RFIN
INHI
OPHI
RFOUT
INLO
OPLO
Table 4. Recommended Passive Values for Lumped-Element
Balun, 50 Ω Impedance Match
ETC1-1-13
Input
Output
Center
Frequency
Figure 34. Single-Ended Drive with Balanced Output
Ci
Li
Cip
Co
Lo Cop
Figure 33 illustrates differential balance at the input and output
using a transformer balun. Input and output baluns are recom-
mended for optimal performance. Much of the characterization
for the ADL5330 was completed using 1:1 baluns at the input
and output for single-ended 50 Ω match. Operation using
M/A-COM ETC1-1-13 transmission line transformer baluns
is recommended for a broadband interface; however, narrow-
100 MHz
900 MHz
2.2 GHz
2.7 GHz
27 pF 82 nH 1 pF
3.3 pF 9 nH
1.5 pF 3.3 nH 16 nH 1.5 pF 3.6 nH 27 nH
33 pF 72 nH 3.3 pF
3.9 pF 8.7 nH 0.5 pF
1.5 pF 2.4 nH
1.3 pF 2.7 nH 33 nH
+5V
120nH
120nH
L
L
o
100pF
100pF
i
INHI
OPHI
C
C
C
C
o
i
i
o
ADL5330
RF VGA
RFIN
RFOUT
C
C
op
ip
INLO
OPLO
C
C
100pF
100pF
C
C
o
i
i
o
L
L
o
i
Figure 35. Differential Operation with Discrete LC Baluns
Rev. A | Page 14 of 24
ADL5330
GAIN CONTROL INPUT
The detector’s error amplifier uses CFLT, a ground-referenced
capacitor pin, to integrate the error signal (in the form of a
current). A capacitor must be connected to CFLT to set the loop
bandwidth and to ensure loop stability.
When the VGA is enabled, the voltage applied to the GAIN pin
sets the gain. The input impedance of the GAIN pin is 1 MΩ.
The gain control voltage range is between 0 V and +1.4 V, which
corresponds to a typical gain range between −38 dB and
+22 dB. The useful lower limit of the gain control voltage
increases at high frequencies to about 0.5 V and 0.6 V for
2.2 GHz and 2.7 GHz, respectively. The supply current to the
ADL5330 can vary from approximately 100 mA at low gain
control voltages to 215 mA at 1.4 V.
+5V
+5V
VPOS
COMM
OPHI
RFIN
INHI
ADL5330
DIRECTIONAL
COUPLER
INLO
OPLO
GAIN
The 1 dB input compression point remains constant at 3 dBm
through the majority of the gain control range, as shown in
Figure 9 through Figure 13. The output compression point
increases dB for dB with increasing gain setting. The noise floor
is constant up to 1 V where it begins to rise.
ATTENUATOR
VOUT
LOG AMP OR
TRUPWR
DETECTOR
VSET
RFIN
DAC
The bandwidth on the gain control pin is approximately 3 MHz.
Figure 14 shows the response time of a pulse on the GAIN pin.
CLPF
AUTOMATIC GAIN CONTROL
Figure 36. ADL5330 in AGC Loop
Although the ADL5330 provides accurate gain control, precise
regulation of output power can be achieved with an automatic
gain control (AGC) loop. Figure 36 shows the ADL5330 in an
AGC loop. The addition of the log amp (AD8318/AD8315) or a
TruPwr™ detector (AD8362) allows the AGC to have improved
temperature stability over a wide output power control range.
The basic connections for operating the ADL5330 in an AGC
loop with the AD8318 are shown in Figure 37. The AD8318 is a
1 MHz to 8 GHz precision demodulating logarithmic amplifier.
It offers a large detection range of 60 dB with 0.5 dB tempera-
ture stability. This configuration is similar to Figure 36.
To operate the ADL5330 in an AGC loop, a sample of the
output RF must be fed back to the detector (typically using a
directional coupler and additional attenuation). A setpoint
voltage is applied to the VSET input of the detector while
VOUT is connected to the GAIN pin of the ADL5330. Based on
the detector’s defined linear-in-dB relationship between VOUT
and the RF input signal, the detector adjusts the voltage on the
GAIN pin (the detector’s VOUT pin is an error amplifier
output) until the level at the RF input corresponds to the
applied setpoint voltage. The GAIN setting settles to a value
that results in the correct balance between the input signal level
at the detector and the setpoint voltage.
The gain of the ADL5330 is controlled by the output pin of the
AD8318. This voltage, VOUT, has a range of 0 V to near VPOS.
To avoid overdrive recovery issues, the AD8318 output voltage
can be scaled down using a resistive divider to interface with the
0 V to 1.4 V gain control range of ADL5330.
A coupler/attenuation of 23 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8318 (at approximately −5 dBm
at 900 MHz).
Rev. A | Page 15 of 24
ADL5330
+5V
+5V
RF INPUT
SIGNAL
RF OUTPUT
SIGNAL
120nH
100pF
120nH
VPOS
COMM
OPHI
100pF
100pF
INHI
ADL5330
100pF
DIRECTIONAL
INLO
OPLO
COUPLER
GAIN
412Ω
+5V
ATTENUATOR
1kΩ
VOUT
SETPOINT
VOLTAGE
VPOS
1nF
VSET
INHI
DAC
AD8318
LOG AMP
1nF
CLPF
INLO
220pF
COMM
Figure 37. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318
Figure 38 shows the transfer function of the output power vs.
the VSET voltage over temperature for a 900 MHz sine wave
with an input power of −1.5 dBm. Note that the power control
of the AD8318 has a negative sense. Decreasing VSET, which
corresponds to demanding a higher signal from the ADL5330,
tends to increase GAIN.
In order for the AGC loop to remain in equilibrium, the
AD8318 must track the envelope of the ADL5330 output signal
and provide the necessary voltage levels to the ADL5330’s gain
control input. Figure 39 shows an oscilloscope screenshot of the
AGC loop depicted in Figure 37. A 100 MHz sine wave with
50% AM modulation is applied to the ADL5330. The output
signal from the ADL5330 is a constant envelope sine wave with
amplitude corresponding to a setpoint voltage at the AD8318 of
1.5 V. Also shown is the gain control response of the AD8318 to
the changing input envelope.
The AGC loop is capable of controlling signals just under the
full 60 dB gain control range of the ADL5330. The performance
over temperature is most accurate over the highest power range,
where it is generally most critical. Across the top 40 dB range of
output power, the linear conformance error is well within
0.5 dB over temperature.
T
AM MODULATED INPUT
T
1
30
4
20
3
AD8318 OUTPUT
10
2
0
1
–10
–20
–30
–40
–50
0
–1
–2
–3
–4
3
ADL5330 OUTPUT
CH1 250mV Ω
CH3 250mV Ω
M2.00ms
0.00000s
A CH4
1.80V
T
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
Figure 39. Oscilloscope Screenshot Showing an AM Modulated Input Signal
SETPOINT VOLTAGE (V)
Figure 38. ADL5330 Output Power vs. AD8318 Setpoint Voltage,
PIN = −1.5 dBm
The broadband noise added by the logarithmic amplifier is
negligible.
Rev. A | Page 16 of 24
ADL5330
Figure 40 shows the response of the AGC RF output to a pulse
on VSET. As VSET decreases to 1 V, the AGC loop responds
with an RF burst. Response time and the amount of signal
integration are controlled by the capacitance at the AD8318 CFLT
pin—a function analogous to the feedback capacitor around an
integrating amplifier. An increase in the capacitance results in
slower response time.
The output of the AD8349 is designed to drive 50 Ω loads and
easily interfaces with the ADL5330. The input to the ADL5330
can be driven single-ended, as shown in Figure 42. Similar con-
figurations are possible with the AD8345 (250 MHz to 1 GHz)
and AD8346 (800 MHz to 2.5 GHz) quadrature modulators.
Figure 41 shows how output power, EVM, ACPR, and noise
vary with the gain control voltage. VGAIN is varied from 0 V to
1.4 V. Figure 41 shows that the modulation generated by the
AD8349 is a 1 GHz 64 QAM waveform with a 1 MHz symbol
rate. The ACPR values are measured in 1 MHz bandwidths at
1.1 MHz and 2.2 MHz carrier offsets. Noise floor is measured at
a 20 MHz carrier offset.
T
T
AD8318 WITH PULSED V
SET
1
20
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
OUTPUT POWER
–20
ADL5330 OUTPUT
2
–40
ACPR 1.1MHz OFFSET
–60
–80
CH1 2.00V CH2 50.0mVΩ
M10.0μs
20.2000μs
A CH1
2.60V
ACPR 2.2MHz OFFSET
EVM
–100
–120
–140
–160
T
Figure 40. Oscilloscope Screenshot Showing the
Response Time of the AGC Loop
NOISE FLOOR
More information on the use of AD8318 in an AGC application
can be found in the AD8318 data sheet.
0
0.2
0.4
0.6
V
0.8
(V)
1.0
1.2
1.4
GAIN
INTERFACING TO AN IQ MODULATOR
Figure 41. AD8349 and ADL5330 Output Power, ACPR, EVM, and Noise vs.
VGAIN for a 1 GHz 64 QAM Waveform with 1 MHz Symbol Rate
The basic connections for interfacing the AD8349 with the
ADL5330 are shown in Figure 42. The AD8349 is an RF
quadrature modulator with an output frequency range of
700 MHz to 2.7 GHz. It offers excellent phase accuracy and
amplitude balance, enabling high performance direct RF
modulation for communication systems.
The output of the AD8349 driving the ADL5330 should be
limited to the range that provides the optimal EVM and ACPR
performance. The power range is found by sweeping the output
power of the AD8349 to find the best compromise between
EVM and ACPR of the system. In Figure 41, the AD8349 output
power is set to −15 dBm.
+5V
120nH
+5V
+5V
120nH
VPOS
IBBP
COMM
VPOS
COMM
100pF
100pF
100pF
100pF
AD8349
ADL5330
RF VGA
DAC
DAC
IBBN
V
INHI
OPHI
RF OUTPUT
OUT
DIFFERENTIAL I/Q
BASEBAND INPUTS
IQ MOD
INLO
OPLO
QBBP
QBBN
ETC1-1-13
100pF
100pF
200Ω
200Ω
LO
GAIN CONTROL
ETC1-1-13
Figure 42. AD8349 Quadrature Modulator and ADL5330 Interface
Rev. A | Page 17 of 24
ADL5330
–20
–30
–40
–50
–60
–70
–80
–90
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
WCDMA TRANSMIT APPLICATION
Figure 43 shows a plot of the output spectrum of the ADL5330
transmitting a single-carrier WCDMA signal (Test Model 1-64
at 2140 MHz). The carrier power output is approximately
−9.6 dBm. The gain control voltage is equal to 1.4 V giving a
gain of approximately 14.4 dB. At this power level, an adjacent
channel power ratio of −65.61 dBc is achieved. The alternate
channel power ratio of −71.37 dBc is dominated by the noise
floor of the ADL5330.
ACPR +5MHZ OFFSET
ACPR +10MHZ
OFFSET
NOISE –50MHz OFFSET
MARKER 1 [T1]
RBW 30kHz
RF ATT 0dB
REF LVL
–20dBm
–29.78dBm VBW 300kHz
2.13996994GHz SWT 100ms UNIT
dBm
–20
–30
1 [T1]
–29.78 dBm
2.13996994 GHz
0.4 dB OFFSET
–40 –35 –30 –25 –20 –15 –10
–5
0
5
10
A
OUTPUT POWER (dBm)
CH PWR
ACP Up
–9.56 dBm
–66.30 dB
–65.61 dB
–71.37 dB
–72.79 dB
ACP Low
ALT1 Up
ALT1 Low
–40
Figure 44. ACPR and Noise vs. Output Power; Single-Carrier
WCDMA Input (Test Model 1-64 at 2140 MHz), VGAIN = 1.4 V (Fixed)
–50
1 AVG
1RM
EXT
Figure 45 shows how output power, ACPR, and noise vary with
the gain control voltage. VGAIN is varied from 0 V to 1.4 V and
input power is held constant at −19 dBm.
–60
–70
–80
10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–90
C0
CL2
CL2
C0
CL1
0
–100
–110
–120
CU2
CU1
CU2
CL1
CU1
OUTPUT POWER
ACPR 5MHz
–10
–20
–30
–40
–50
–60
–70
CENTER 2.14GHz
2.46848MHz/
SPAN 24.6848MHz
Figure 43. Single-Carrier WCDMA Spectrum at 2140 MHz;
VGAIN = 1.4 V, PIN = −23 dBm
Figure 44 shows how ACPR and noise vary with different input
power levels (gain control voltage is held at 1.4 V). At high
power levels, both adjacent and alternate channel power ratios
sharply increase. As output power drops, adjacent and alternate
channel power ratios both reach minima before the measure-
ment becomes dominated by the noise floor of the ADL5330. At
this point, adjacent and alternate channel power ratios become
approximately equal.
ACPR 10MHz
NOISE –50MHz OFFSET
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
V
(V)
GAIN
Figure 45. Output Power, ACPR, and Noise vs. VGAIN
;
Single-Carrier WCDMA (Test Model 1-64 at 2140 MHz) Input at −19 dBm
As the output power drops, the noise floor, measured in dBm/
Hz at 50 MHz carrier offset, initially falls and then levels off.
Rev. A | Page 18 of 24
ADL5330
The results show that up to a total output power of +8 dBm,
CDMA2000 TRANSMIT APPLICATION
ACPR remains in compliance with the standard (<−45 dBc @
750 kHz and <−60 dBc @ 1.98 MHz). At low output power
levels, ACPR at 1.98 MHz carrier offset degrades as the noise
floor of the ADL5330 becomes the dominant contributor to
measured ACPR. Measured noise at 4 MHz carrier offset begins
to increase sharply above 0 dBm output power. This increase is
not due to noise but results from increased carrier-induced
distortion. As output power drops below 0 dBm total, the noise
floor drops towards −85 dBm.
To test the compliance to the CDMA2000 base station standard,
an 880 MHz, three-carrier CDMA2000 test model signal
(forward pilot, sync, paging, and six traffic, as per 3GPP2
C.S0010-B, Table 6.5.2.1) was applied to the ADL5330. A cavity-
tuned filter with a 4.6 MHz pass band was used to reduce noise
from the signal source being applied to the device.
Figure 46 shows the spectrum of the output signal under
nominal conditions. Total POUT of the three-carrier signal is
equal to 0.46 dBm and VGAIN = 1.4 V. Adjacent and alternate
channel power ratio is measured in a 30 kHz bandwidth at
750 kHz and 1.98 MHz carrier offset, respectively.
With a fixed input power of −23 dBm, the output power was
again swept by exercising the gain control input. VGAIN was
swept from 0 V to 1.4 V. The resulting total output power,
ACPR, and noise floor are shown in Figure 48.
MARKER 1 [T1]
RBW 30kHz
RF ATT 10dB
REF LVL
–10dBm
–18.55dBm VBW 300kHz MIXER –10dBm
UNIT dBm
10
–30
–40
–50
–60
–70
–80
–90
–100
880.00000000MHz SWT 200ms
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.4 dB OFFSET
1 [T1]
–18.55dBm
880MHz
1
A
0
CH PWR
ACP Up
0.46dBm
–65.13dB
–64.40dB
–89.05dB
–83.68dB
–80.72dB
–81.24dB
OUTPUT POWER
ACP Low
ALT1 Up
ALT1 Low
ALT2 Up
ALT2 Low
–10
–20
–30
–40
–50
–60
1 AVG
1RM
EXT
ACPR 750kHz OFFSET
ACPR 1.98MHz OFFSET
C0
C0
CL3
CL3
CL2
CL2
CL1
CL1
CU1
CU1
CU2
CU2
NOISE 4MHz OFFSET
0.8 1.0
(V)
CU3
CU3
0
0.2
0.4
0.6
V
1.2
1.4
GAIN
CENTER 880MHz
1.5MHz/
SPAN 15MHz
Figure 48. Total Output Power and ACPR vs. VGAIN, 880 MHz Three-Carrier
CDMA2000 Test Model at −23 dBm Total Input Power; ACPR Measured in
30 kHz Bandwidth at 750 kHz and 1.98 MHz Carrier Offset
Figure 46. 880 MHz Output Spectrum, Three-Carrier CDMA2000 Test Model
at −23 dBm Total Input Power, VGAIN = 1.4 V, ACPR Measured at 750 kHz and
1.98 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter
(Pass Band = 4.6 MHz)
Above VGAIN = 0.4 V, the ACPR is still in compliance with the
standard. As the gain control input drops below 1.0 V, the noise
floor drops below −90 dBm.
In testing, by holding the gain control voltage steady at 1.4 V,
input power was swept. Figure 47 shows ACPR and noise floor
vs. total output power. Noise floor is measured at 1 MHz
bandwidth at 4 MHz carrier offset.
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
chip’s ground. Solder the paddle to the low impedance ground
plane on the printed circuit board to ensure specified electrical
performance and to provide thermal relief. It is also
recommended that the ground planes on all layers under the
paddle be stitched together with vias to reduce thermal
impedance.
–30
–0
–40
–10
–20
–30
–40
–50
–60
–70
–80
–90
–50
–60
ACPR 750kHz OFFSET
–70
–80
–90
ACPR 1.98MHz OFFSET
NOISE 4MHz OFFSET
–100
–110
–120
–30
–25
–20
–15
–10
–5
0
5
10
15
TOTAL OUTPUT POWER (dBm)
Figure 47. ACPR vs. Total Output Power, 880 MHz Three-Carrier CDMA2000
Test Model; VGAIN = 1.4 V (Fixed), ACPR Measured in 30 kHz Bandwidth at
750 kHz and 1.98 MHz Carrier Offset
Rev. A | Page 19 of 24
ADL5330
available on the circuit side of the board. Components M1
through M9 are used for the input interface, and M10 through
M18 are used for the output interface. DC blocking capacitors
of 100 pF must be installed in C15 and C16 for the input and
C17 and C18 for the output. The C5, C6, C11, and C12
capacitors must be removed. An alternate set of SMA
connectors, INPUT2 and OUT2, are used for this
configuration.
EVALUATION BOARD
Figure 49 shows the schematic of the ADL5330 evaluation
board. The silkscreen and layout of the component and circuit
sides are shown in Figure 50 through Figure 53. The board is
powered by a single-supply in the 4.75 V to 5.25 V range. The
power supply is decoupled by 100 pF and 0.1 μF capacitors at
each power supply pin. Additional decoupling, in the form of a
series resistor or inductor at the supply pins, can also be added.
Table 5 details the various configuration options of the
evaluation board.
The ADL5330 can be driven single-ended; use the RF input
path on the circuit side of the board. A set of 100 pF dc blocking
capacitors must be installed in C15 and C16. C5 and C6 must
be removed. Use the INPUT2 SMA to drive one of the
differential input pins. The unused pin should be terminated to
ground, as shown in Figure 34.
The output pins of the ADL5330 require supply biasing with
120 nH RF chokes. Both the input and output pins have 50 Ω
differential impedances and must be ac-coupled. These pins are
converted to single-ended with a pair of baluns (M/A-COM
part number ETC1-1-13).
The ADL5330 is enabled by applying a logic high voltage to the
ENBL pin by placing a jumper across the SW1 header in the
O position. Remove the jumper for disable. This pulls the ENBL
pin to ground through the 10 kΩ resistor.
Instead of using balun transformers, lumped-element baluns
comprising passive L and C components can be designed.
Alternate input and output RF paths with component pads are
Rev. A | Page 20 of 24
ADL5330
V P S 2
V P S 2
V P S 2
V P S 2
N E B L
C O M 2
G N L O
C O M 1
O P B S
I P B S
G A I N
E F V R
Figure 49. Evaluation Board Schematic
Rev. A | Page 21 of 24
ADL5330
Table 5. Evaluation Board Configuration Options
Components
Function
Default Conditions
C1ꢀ C4ꢀ C7ꢀ C10ꢀ C13 = 100 pF
(size 0603)
C2ꢀ C3ꢀ C8ꢀ C9ꢀ C14 = 0.1 μF
(size 0603)
R2ꢀ R4ꢀ R5ꢀ R6ꢀ R12 = 0 Ω
(size 0402)
C1 to C4ꢀ C7 to C10ꢀ C13ꢀ
C14ꢀ R2ꢀ R4ꢀ R5ꢀ R6ꢀ R12
Power Supply Decoupling. The nominal supply decoupling consists of
100 pF and 0.1 μF capacitors at each power supply pin (the VPS2 pinsꢀ Pin 18
to Pin 22ꢀ share a pair of decoupling capacitors because of their proximity). A
series inductor or small resistor can be placed between the capacitors for
additional decoupling.
T1ꢀ C5ꢀ C6
Input Interface. The 1:1 balun transformer T1 converts a 50 Ω single-ended
input to the 50 Ω differential input. C5 and C6 are dc blocks.
T1 = ETC1-1-13 (M/A-COM)
C5ꢀ C6 = 100 pF (size 0603)
T2ꢀ C11ꢀ C12ꢀ L1ꢀ L2
Output Interface. The 1:1 balun transformer T2 converts the 50 Ω differential T2 = ETC1-1-13 (M/A-COM)
output to 50 Ω single-ended output. C11 and C2 are dc blocks. L3 and
L4 provide dc biases for the output.
C11ꢀ C12 = 100 pF (size 0603)
L1ꢀ L2 = 120 nH (size 0805)
SW1ꢀ R1ꢀ R13
Enable Interface. The ADL5330 is enabled by applying a logic high voltage
to the ENBL pin by placing a jumper across SW1 to the O position. Remove
the jumper for disable. To exercise the enable function by applying an
external high or low voltageꢀ use the pin labeled O on the SW1 header.
SW1 = installed
R1 = 0 Ω (size 0402)
R13 = 10 kΩ (size 0402)
M1 to M18 = not installed
(size 0603)
C15 to C18 = not installed
(size 0603)
C15 to C18ꢀ M1 to M18
Alternate Input/Output Interface. The circuit side of the evaluation board
offers an alternate RF input and output interface. A lumped-element balun
can be built using L and C components instead of using the balun
transformer (see the Applications section). The componentsꢀ M1 through
M9ꢀ are used for the inputꢀ and M10 through M18 are used for the output.
To use the alternate RF pathsꢀ disconnect the dc blocking capacitors
(Capacitor C5 and Capacitor C6 for the input and Capacitor C11 and
Capacitor C12 for the output). Place 100 pF dc blocking capacitors on
C15ꢀ C16ꢀ C17ꢀ and C18. Use the alternate set of SMA connectorsꢀ
INPUT2 and OUT2.
Rev. A | Page 22 of 24
ADL5330
Figure 50. Component Side Silkscreen
Figure 52. Component Side Layout
Figure 51. Circuit Side Silkscreen
Figure 53. Circuit Side Layout
Rev. A | Page 23 of 24
ADL5330
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
*
2.45
2.30 SQ
2.15
TOP
3.75
EXPOSED
VIEW
BSC SQ
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
12
7
0.23 MIN
2.50 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Package Ordering
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Option
CP-24-2
CP-24-2
CP-24-2
Quantity
ADL5330ACPZ-WP1ꢀ 2
ADL5330ACPZ-REEL71
ADL5330ACPZ-R21
ADL5330-EVAL
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
64
1ꢀ500
250
1
1 Z = Pb-free part.
2 WP = waffle pack.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05134–0–6/05(A)
Rev. A | Page 24 of 24
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