ADL5335ACPZN [ADI]
DGA;
| 型号： | ADL5335ACPZN |
| 厂家： | 
ADI |
| 描述： | DGA |
| 文件： | 总16页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
700 MHz to 4200 MHz,
Tx DGA
Data Sheet
ADL5335
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VPOS1 VPOS2 VPOS3
Differential input to single-ended output conversion
Broad input frequency range: 700 MHz to 4200 MHz
Maximum gain: 12.0 dB typical
Gain range of 20 dB typical
Gain step size: 0.5 dB typical
Glitch free, thermometer-based digital step attenuator
Fast attack, gain switching with programmable gain step
Matched 50 Ω inputs and output
1
4
13
ADL5335
11
10
ENBL
RFIN–
RFIN+
2
3
12dB
RFOUT
0dB TO –20dB
16
15
14
12
CS
SCLK
SDIO
FA
5
6
7
8
9
APPLICATIONS
GND1 GND2 GND3 GND4 GND5
RF power control and calibration in wireless transmitters
Figure 1.
GENERAL DESCRIPTION
The ADL5335 is a digital gain amplifier (DGA) optimized for
use in wireless transmitters. A differential input and single-
ended output facilitates a balun free connection between the
broadband integrated transceivers with differential outputs and
the RF gain blocks and drivers amplifiers with single-ended inputs.
size of 0.5 dB. The ADL5335 also features a fast attack function
where the gain can rapidly increase or decrease by the
application of a single pulse.
The use of a thermometer-based digital step attenuator (DSA)
ensures that gain changes are fundamentally glitch free. The
ADL5335 is packaged in a 4 mm × 4 mm, 16-lead LFCSP. A
fully populated evaluation board and system demonstration
platform (SDP)-based control software are available.
The gain is programmable via a standard Analog Devices, Inc.,
serial peripheral interface (SPI) port from a maximum gain of
12.0 dB down to a minimum gain of −8.0 dB with a gain step
Rev. 0
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
ADL5335
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................8
Typical Performance Characteristics ..............................................9
Theory of Operation ...................................................................... 13
Basic Structure............................................................................ 13
Digital Interface Overview........................................................ 13
Applications Information .............................................................. 15
Basic Connections...................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Logic Timing.................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thremal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
REVISION HISTORY
12/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
ADL5335
SPECIFICATIONS
VPOS1, VPOS2, VPOS3 = 5 V, TA = 25°C, impedance out (ZOUT) = 50 Ω, and a differential input drive, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max
Unit
OVERALL FUNCTION
Input Frequency Range
Impedance
700
4200 MHz
Input
Output
Differential input drive
Single-ended output
50
50
Ω
Ω
GAIN CONTROL
Gain Range
Maximum Gain
Minimum Gain
Gain Step Size
20
dB
dB
dB
dB
12.0
−8.0
0.5
BAND 8: 925 MHz TO 960 MHz
Gain Range
20
dB
Maximum Gain
Minimum Gain
Gain Flatness
Gain Step Error
Group Delay Variation
Output Third-Order Intercept (IP3)
13.0
−7.0
0.3
0.2
50
dB
dB
dB
dB
200 MHz, all gains
All gain states
Between any attenuation step
Maximum gain, 4 dBm per tone
Minimum gain, −18 dBm per tone
Maximum gain
ps
34
dBm
dBm
dBm
dBm
dB
13.6
18.0
−0.6
5.4
Output 1 dB Compression Point (P1dB)
Noise Figure
Minimum gain
Maximum gain
Minimum gain
8.3
dB
Return Loss
Input
Output
−18
−17
−30
20
dB
dB
dB
dB
Minimum gain
Maximum gain
vs. frequency ( 200 MHz)
Common-Mode Rejection Ratio (CMRR)
BAND 3: 1805 MHz TO 1880 MHz
Gain Range
20
dB
Maximum Gain
Minimum Gain
Gain Flatness
Gain Step Error
Group Delay Variation
Output IP3
12.8
−7.2
0.5
0.4
45
33
12
18.3
0
6.9
10.6
dB
dB
dB
dB
200 MHz, all gains
All gain states
Between any attenuation step
Maximum gain, 4 dBm per tone
Minimum gain, −18 dBm per tone
Maximum gain
Minimum gain
Maximum gain
Minimum gain
ps
dBm
dBm
dBm
dBm
dB
Output P1dB
Noise Figure
dB
Return Loss
Input
Output
−32
−23
−17
22
dB
dB
dB
dB
Minimum gain
Maximum gain
vs. frequency ( 200 MHz)
CMRR
Rev. 0 | Page 3 of 16
ADL5335
Data Sheet
Parameter
Test Conditions/Comments
Min Typ
Max
Unit
BAND 1: 2110 MHz TO 2170 MHz
Gain Range
20
dB
Maximum Gain
Minimum Gain
Gain Flatness
Gain Step Error
Group Delay Variation
Output IP3
12.5
−7.5
0.5
0.38
20
dB
dB
dB
dB
200 MHz, all gains
All gain states
Between any attenuation step
Maximum gain, 4 dBm per tone
Minimum gain, −18 dBm per tone
Maximum gain
ps
32
dBm
dBm
dBm
dBm
dB
11.6
18.1
−0.2
6.9
Output P1dB
Noise Figure
Minimum gain
Maximum gain
Minimum gain
10.4
dB
Return Loss
Input
Output
−32
−25
−19
25
dB
dB
dB
dB
Minimum gain
Maximum gain
vs. frequency ( 200 MHz)
CMRR
BAND 7: 2620 MHz TO 2690 MHz
Gain Range
20
dB
Maximum Gain
Minimum Gain
Gain Flatness
Gain Step Error
Group Delay Variation
Output IP3
12.0
−8.0
0.7
0.37
30
dB
dB
dB
dB
200 MHz, all gains
All gain states
Between any attenuation step
Maximum gain, 4 dBm per tone
Minimum gain, −18 dBm per tone
Maximum gain
ps
32
dBm
dBm
dBm
dBm
dB
13.1
17.8
−1.1
7.5
Output P1dB
Noise Figure
Minimum gain
Maximum gain
Minimum gain
10.5
dB
Return Loss
Input
Output
−19
−24
−17
26
dB
dB
dB
dB
Minimum gain
Maximum gain
vs. frequency ( 200 MHz)
CMRR
BAND 42: 3400 MHz TO 3600 MHz
Gain Range
20
dB
Maximum Gain
Minimum Gain
Gain Flatness
Gain Step Error
Group Delay Variation
Output IP3
10.2
−9.8
0.7
0.36
20
dB
dB
dB
dB
200 MHz, all gains
All gain states
Between any attenuation step
Maximum gain, 4 dBm per tone
Minimum gain, −18 dBm per tone
Maximum gain
ps
31
dBm
dBm
dBm
dBm
dB
10.9
16.8
2.3
Output P1dB
Noise Figure
Minimum gain
Maximum gain
7.5
Minimum gain
12.2
dB
Rev. 0 | Page 4 of 16
Data Sheet
ADL5335
Parameter
Return Loss
Input
Test Conditions/Comments
Min Typ
Max
Unit
−19
−17
−11
28
dB
dB
dB
dB
Output
Minimum gain
Maximum gain
vs. frequency ( 200 MHz)
CMRR
FREQUENCY = 4.2 GHz
Gain Range
20
dB
Maximum Gain
Minimum Gain
Gain Flatness
Gain Step Error
Group Delay Variation
Output IP3
9.3
−10.7
0.9
0.49
25
29
11
15.8
−3.7
8.7
dB
dB
dB
dB
200 MHz, all gains
All gain states
Between any attenuation step
Maximum gain, −4 dBm per tone
Minimum gain, −18 dBm per tone
Maximum gain
ps
dBm
dBm
dBm
dBm
dB
Output P1dB
Noise Figure
Minimum gain
Maximum gain
Minimum gain
13.5
dB
Return Loss
Input
Output
−24
−12
−11
29
dB
dB
dB
dB
Minimum gain
Maximum gain
CMRR
SPI PORT AND FAST ATTACK
Logic Low
Logic High
SDIO, SCLK, CS, FA pins
0.18
1.8
V
V
1.62
Fast Attack Response Time
ENABLE INTERFACE
Voltage Level
To Enable
20
ns
ENBL pin
ENBL voltage (VENBL) increasing
Enable/disable voltage (VENBLDN) increasing
1.62
0
1.8
0.18
V
V
To Disable
Time
Enable
Disable
30
30
ns
ns
POWER SUPPLY INTERFACE
Supply Voltage
Quiescent Current
Power Consumption
VPOSx pins
Main supply
Device enabled
Device enabled
Power-down mode
4.75
5
5.25
V
125
625
18.5
mA
mW
mW
Rev. 0 | Page 5 of 16
ADL5335
Data Sheet
DIGITAL LOGIC TIMING
Table 2.
Parameter
Description
Min Typ Max Unit
tCLK
tHI
tLO
tS
Maximum serial clock rate
25
10
10
15
MHz
ns
ns
Minimum period that SCLK is in a logic high state
Minimum period that SCLK is in a logic low state
Setup time between falling edge of CS and SCLK
ns
tH
tDS
tDH
tZ
Hold time between data and rising edge of SCLK
Setup time between data and rising edge of SCLK
SCLK to SDIO Hold Time
Maximum time delay between CS deactivation and SDIO bus to return to high impedance
Maximum time delay between falling edge of SCLK and out data valid for a read operation
5
ns
ns
ns
ns
ns
15
10
5
tACCESS
5
SPI Timing Diagram
tDS
tHI
tCLK
tH
tACCESS
tS
tDH
tLO
CS
SCLK DON’T CARE
DON’T CARE
tZ
SDIO
DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2. SPI Timing
Rev. 0 | Page 6 of 16
Data Sheet
ADL5335
ABSOLUTE MAXIMUM RATINGS
Table 3.
THREMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltage, VPOS
SCLK, SDIO, CS, FA
5.5 V
3.9 V
Table 4 shows the thermal resistance from the die to ambient
(θJA) and die to lead (θJC), respectively.
Enable Voltage, ENBL
2.2 V
Input Average RF Power
Equivalent Voltage, Sine Wave Input1
Internal Power Dissipation
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
12 dBm
2.5 V p-p
725 mW
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
CP-16-39
58.7
2.2
°C/W
ESD CAUTION
1 If the common-mode voltage at the inputs (VCOM) is closer than 0.625 V from
either rail voltage (VRAIL), the equivalent voltage reduces to (|VRAIL − VCOM|) × 4,
where VRAIL is the rail closest to VCOM
.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 7 of 16
ADL5335
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPOS1 1
RFIN– 2
RFIN+ 3
12 FA
ADL5335
11 ENBL
TOP VIEW
10
9
RFOUT
GND5
(Not to Scale)
4
VPOS2
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO
A GROUND PLANE WITH A LOW THERMAL AND
ELECTRICAL IMPEDANCE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4, 13
VPOS1, VPOS2,
VPOS3
Power Supplies. Separately decouple each power supply pin using 100 pF and 0.1μF capacitors.
2, 3
RFIN−, RFIN+
RF Negative and Positive Inputs. These pins have a 50 Ω differential input pair and are internally ac-
coupled.
5 to 9
GND1, GND2, GND3, Ground. Connect these ground pins to a low impedance ground plane.
GND4, GND5
10
11
RFOUT
ENBL
RF Output. This pin has a 50 Ω single-ended output and is internally ac-coupled.
Enable. A logic high on this pin (1.8 V logic) enables operation and a logic low on this pin puts the
device in a low power sleep mode.
12
FA
Fast Attack. A logic high on this pin (1.8 V logic) decreases the programmed gain by an additional 2 dB,
4 dB, 8 dB, or 16 dB. The fast attack attenuation step is defined by the last two bits of an 8-bit
programming byte that is written to the device via the SPI. When FA returns to a logic low, the gain
returns to its normal programmed level. When not using the fast attack function, tie the FA pin to
ground.
14
15
16
SDIO
SCLK
CS
Serial Data Input/Output (SDIO), 1.8 V Logic. The gain and fast attack attenuation levels are programmed
using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register
address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast
attack attenuation (−2 dB, −4 dB, −8 dB, or −16 dB).
Serial Clock (SCLK), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight
bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the
eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack
attenuation (−2 dB, −4 dB, −8 dB, or −16 dB).
Chip Select Bar (CS), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using
eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address,
and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack
attenuation (−2 dB, −4 dB, −8 dB, or −16 dB).
EP
Exposed Pad. Connect the exposed pad to a ground plane with a low thermal and electrical
impedance.
Rev. 0 | Page 8 of 16
Data Sheet
ADL5335
TYPICAL PERFORMANCE CHARACTERISTICS
129
25
20
15
10
5
127
125
123
121
119
GAIN = +12dB
GAIN = –8dB
0
5.25V
5V
4.75V
117
–5
–10
+85°C
+25°C
–40°C
115
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
FREQUENCY (GHz)
Figure 4. Supply Current vs. Temperature for Various Power Supplies (VPOS
)
Figure 7. Output 1dB Compression vs. Frequency for
Various Temperatures and Gains, VPOS = 5 V
36
34
32
30
28
26
24
15
14
13
12
11
10
9
8
7
+12dB GAIN
+10dB GAIN
+8dB GAIN
+6dB GAIN
+4dB GAIN
+2dB GAIN
0dB GAIN
6
5
4
3
–2dB GAIN
–4dB GAIN
–6dB GAIN
–8dB GAIN
+85°C
+25°C
–40°C
5V
4.75V
5.25V
2
22
20
1
0
0.5
5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 5. Output Third-Order Intercept (OIP3) vs. Frequency for
Various VPOS and Temperatures, Maximum Gain = 12 dB,
Output Tones = 4 dBm
Figure 8. Noise Figure vs. Frequency for Various Gain Steps at VPOS = 5 V
24
22
20
18
16
14
12
10
8
12
11
10
9
8
7
6
5
4
6
3
4
2
+85°C
+25°C
–40°C
5V
4.75V
5.25V
+85°C
+25°C
–40°C
5V
4.75V
5.25V
2
0
1
0
0.5
5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. OIP3 vs. Frequency for Various VPOS and Temperatures,
Minimum Gain = −8 dB, Output Tones = −18 dBm
Figure 9. Noise Figure vs. Frequency for Various Temperatures and VPOS at
Maximum Gain = 12 dB
Rev. 0 | Page 9 of 16
ADL5335
Data Sheet
0.5
0.4
16
15
14
13
12
11
10
9
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
8
7
6
+85°C
+25°C
–40°C
5V
4.75V
5.25V
+85°C
+25°C
–40°C
5
4
0.5
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
8
9
10 11 12
5
GAIN SETTING (dB)
FREQUENCY (GHz)
Figure 10. Gain Step Error vs. Gain Setting for Various Temperatures, VPOS = 5 V
Figure 13. Gain vs. Frequency for Various Temperatures and VPOS
20
15
14
12
10
8
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
6
4
2
0
0.5
5
0.5
1
1.5
2
2.5
3
3.5 4 4.5 5
FREQUENCY LOGARITHMIC RESPONSE (GHz)
FREQUENCY (GHz)
Figure 11. Gain vs. Frequency Logarithmic Response with a Maximum Gain =
+12 dB to a Minimum Gain = −8 dB in 1 dB Steps
Figure 14. Forward Transmission (SSD21) vs. Frequency, Gain = 12 dB
15
10
5
–24
–26
–28
–30
–32
–34
–36
–38
–40
0
–5
–10
–15
0.6
1.8
2.4
3.0
3.6 4.2
0.5
1
1.5
2
2.5
3
3.5 4 4.5 5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Gain vs. Frequency for All Gain Steps (+12 dB to −8 dB,
0.5 dB Step Size), VPOS = 5 V, Temperature = 25°C
Figure 15. Reverse Transmission (SDS12) vs. Frequency, Gain = 12 dB
Rev. 0 | Page 10 of 16
Data Sheet
ADL5335
0
40
35
30
25
20
15
10
–5
–10
–15
–20
–25
–30
–35
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
0.5
1
1.5
2
2.5
3
3.5 4 4.5 5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Output Reflection Coefficient (SSS22) vs. Frequency, Gain = 12 dB
Figure 19. Common-Mode Rejection Ratio (CMRR) vs. Frequency, Gain = 12 dB
0
–5
2.0
1.5
1.0
0.5
0
–10
–15
–20
–25
–30
–35
–40
–0.5
–1.0
–1.5
FA
RF
–2.0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
–40
–30
–20
–10
0
10
20
30
40
FREQUENCY (GHz)
TIME (ns)
Figure 17. Input Reflection Coefficient (SDD11) vs. Frequency, Gain = 12 dB
Figure 20. Fast Attack Response, On at 16 dB
1600
1400
1200
1000
800
600
400
200
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
FA
RF
0.5
5
–40
–30
–20
–10
0
10
20
30
40
FREQUENCY (GHz)
TIME (ns)
Figure 18. Group Delay vs. Frequency, Gain = 12 dB
Figure 21. Fast Attack Response, Off at 16 dB
Rev. 0 | Page 11 of 16
ADL5335
Data Sheet
–30
–40
–50
–60
–70
–80
–90
–100
ENBL
RF
HD2
HD3
0dBm = P
2dBm = P
4dBm = P
OUT
OUT
OUT
0
100
200
300
400
500
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
TIME (ns)
FREQUENCY (GHz)
Figure 22. Enable/Disable Time Domain Response
Figure 23. Distortion (HD2 and HD3) vs. Frequency for
Various Output Powers (POUT
)
Rev. 0 | Page 12 of 16
Data Sheet
ADL5335
THEORY OF OPERATION
6-Bit Binary Gain Code, Bits[D5:D0]
Gain (dB)
+4.0
+3.5
+3.0
+2.5
+2.0
+1.5
+1.0
+0.5
0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
−3.5
−4.0
−4.5
−5.0
−5.5
−6.0
−6.5
−7.0
−7.5
−8.0
−8.0
BASIC STRUCTURE
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
100011 to 111111
The ADL5335 is an SPI controlled DGA. An integrated, on-chip
balun converts a 50 Ω differential RF input into a 50 Ω single-
ended RF output. The RF inputs and the RF output utilize
internal ac coupling capacitors.
The DGA core consists of a fixed gain amplifier and digitally
controlled attenuator. The amplifier has a gain of 12.0 dB. The
attenuator has a range of 0 dB to −8.0 dB with +0.5 dB steps and
uses a thermometer coding technique to eliminate transient
glitches during gain changes.
DIGITAL INTERFACE OVERVIEW
The ADL5335 digital section includes an enable pin (ENBL),
a fast attack pin (FA), and a SPI.
Serial Peripheral Interface (SPI)
The SPI uses the three following pins: the serial data
input/output (SDIO), the serial clock (SCLK), and the chip
CS
select bar ( ).
The SPI data register consists of three bytes: one read/write bit
(R/W), 15 address bits (A14 to A0), two fast attack (FA)
attenuation step size bits (D7 and D6), and six gain control bits
(D5 to D0), as shown in Figure 24.
The gain code and fast attack attenuation step size bits are
controlled via Register Address 0x100. See Table 6 and Table 7,
respectively, for their truth tables.
Table 6. Gain Code Truth Table
6-Bit Binary Gain Code, Bits[D5:D0]
Fast Attack (FA)
Gain (dB)
+12.0
+11.5
+11.0
+10.5
+10.0
+9.5
+9.0
+8.5
+8.0
+7.5
+7.0
+6.5
+6.0
+5.5
+5.0
+4.5
The fast attack feature allows the gain to be reduced from its
present setting by a predetermined step size. Four different
attenuation step sizes are available (see Table 7).
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
The FA pin controls fast attack mode. A logic high on the FA
pin results in an attenuation that is selected by Bits[D7:D6] in
the SPI register (Register Address 0x100).
Table 7. Fast Attack Attenuation Step Size Truth Table
6-Bit Binary Gain Code, Bits[D7:D6]
00
01
10
11
Step Size (dB)
−2
−4
−8
−16
Rev. 0 | Page 13 of 16
ADL5335
Data Sheet
READ
WRITE
REGISTER ADDRESS
FAST ATTACK
D7 D6
GAIN
R/W
A14
0
A13
0
A12
0
A11
0
A10
0
A9
0
A8
1
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
D5
D4
D3
D2
D1
D0
DB1
0
READ/WRITE
WRITE
1
READ
D7
0
D6
0
ATTENUATION
–2dB
0
1
–4dB
1
0
–8dB
1
1
–16dB
GAIN
12.0dB
11.5dB
11.0dB
10.5dB
.
D5
0
0
0
0
.
D4
0
0
0
0
.
D3
0
0
0
0
.
D2
0
0
0
0
.
D1
0
0
1
1
.
D0
0
1
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
.
0
0
0
0
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
–7.0dB
–7.5dB
–8.0dB
–8.0dB
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
–8.0dB
Figure 24. Gain and Fast Attack Programming via Register Address 0x100
Rev. 0 | Page 14 of 16
Data Sheet
ADL5335
APPLICATIONS INFORMATION
CS
SDIO, and ), fast attack (FA), and enable (ENBL) pins
operate at an 1.8 V voltage. To enable the ADL5335, pull the
ENBL pin high (1.8 V). A low on the ENBL pin sets the device
to power-down mode, reducing the current to approximately
3.7 mA.
BASIC CONNECTIONS
Figure 25 shows the basic connections for operating the
ADL5335. Apply a 5 V voltage to the supply pins (VPOS1,
VPOS2, and VPOS3). Decouple each supply pin with at least
one low inductance, surface-mount ceramic, 0.1 μF capacitor
placed as close to the device as possible. The balanced differential
inputs are decoupled using 100 pF capacitors and so is the 50 Ω
load on the RF output. The serial peripheral interface pins (SCLK,
For additional information on device operation, see the
EV-ADL5335SD1Z User Guide.
0.1µF
SERIAL PERIPHERAL INTERFACE
100pF
0.1µF
100pF
1
12
FA
VPOS1
1.8V
100pF
2
11
RFIN–
ENBL
BALANCED SOURCE
3
ADL5335
100pF
10
9
1.8V
RFIN+
RFOUT
GND5
100pF
4
VPOS2
100pF
50Ω LOAD
0.1µF
NOTES
1. THE 100pF CAPACITORS ON THE RFIN– AND RFIN+ PINS ARE
OPTIONAL BECAUSE THE DEVICE IS INTERNALLY AC-COUPLED.
Figure 25. Basic Connections
Rev. 0 | Page 15 of 16
ADL5335
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.32
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
13
16
0.65
BSC
1
12
2.44
2.34 SQ
2.24
EXPOSED
PAD
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-4.
Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-39)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADL5335ACPZN
ADL5335ACPZN-R7
EV-ADL5335SD1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-16-39
CP-16-39
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16304-0-12/17(0)
Rev. 0 | Page 16 of 16
相关型号：
ADL5336
An IQ Demodulator-Based IF-to-Baseband Receiver with IF and Baseband Variable Gain and Programmable Baseband Filtering
ADI
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