ADL5331 [ADI]
1 MHz to 1.2 GHz VGA with 30 dB Gain Control Range; 1 MHz至1.2 GHz的VGA 30 dB增益控制范围
| 型号： | ADL5331 |
| 厂家： | 
ADI |
| 描述： | 1 MHz to 1.2 GHz VGA with 30 dB Gain Control Range |
| 文件： | 总16页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 MHz to 1.2 GHz VGA with
30 dB Gain Control Range
ADL5331
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Voltage-controlled amplifier/attenuator
Operating frequency: 1 MHz to 1.2 GHz
Optimized for controlling output power
High linearity: OIP3 47 dBm @ 100 MHz
Output noise floor: −149 dBm/Hz @ maximum gain
Input impedance: 50 Ω
Output impedance: 20 Ω
Wide gain-control range: 30 dB
Linear-in-dB gain control function: 40 mV/dB
Single-supply voltage: 4.75 V to 5.25 V
GAIN
ENBL VPS2 VPS2 VPS2 VPS2
VPS2
VPS1
ADL5331
GAIN
CONTROL
COM1
INHI
COM2
OPHI
INPUT
GM
OUTPUT
(TZ)
RFOUT
RFIN
STAGE
STAGE
INLO
OPLO
COM2
COM1
BIAS
AND
VREF
VPS1
VPS2
APPLICATIONS
NC
IPBS OPBS COM2 COM2 COM2
Transmit and receive power control at RF and IF
CATV distribution
Figure 1.
GENERAL DESCRIPTION
The ADL5331 is a high performance, voltage-controlled
variable gain amplifier/attenuator for use in applications with
frequencies up to 1.2 GHz. The balanced structure of the signal
path maximizes signal swing, eliminates common-mode noise
and minimizes distortion while it also reduces the risk of spu-
rious feed-forward at low gains and high frequencies caused by
parasitic coupling.
The output of the high accuracy wideband attenuator is applied
to a differential transimpedance output stage. The output stage
provides a differential output at OPHI and OPLO, which must be
pulled up to the supply with RF chokes or a center-tapped balun.
The ADL5331 consumes 240 mA of current including the out-
put pins and operates off a single supply ranging from 4.75 V
to 5.25 V. A power-down function is provided by applying a
logic low input on the ENBL pin. The current consumption in
power-down mode is 250 μA.
The 50 Ω differential input system converts the applied
differential voltage at INHI and INLO to a pair of differential
currents with high linearity and good common-mode rejection.
The signal currents are then applied to a proprietary voltage-
controlled attenuator providing precise definition of the overall
gain under the control of the linear-in-dB interface. The GAIN
pin accepts a voltage from 0 V at a minimum gain to 1.4 V at a
full gain with a 40 mV/dB scaling factor over most of the range.
The ADL5331 is fabricated on an Analog Devices, Inc., pro-
prietary high performance, complementary bipolar IC process.
The ADL5331 is available in a 24-lead (4 mm × 4 mm), Pb-free
LFCSP_VQ package and is specified for operation from ambient
temperatures of −40°C to +85°C. An evaluation board is also
available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADL5331
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation .........................................................................9
Applications Information.............................................................. 10
Basic Connections...................................................................... 10
Gain Control Input .................................................................... 11
CMTS Transmit Application .................................................... 13
Interfacing to an IQ Modulator................................................ 14
Soldering Information............................................................... 14
Evaluation Board Schematic ......................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
5/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADL5331
SPECIFICATIONS
VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match.
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
GENERAL
Usable Frequency Range
Nominal Input Impedance
Nominal Output Impedance
FREQUENCY INPUT = 100 MHz
Gain Control Span
Minimum Gain
0.001
1.2
GHz
Ω
Ω
50
20
3 dB gain law conformance
VGAIN = 0.1 V
VGAIN = 1.4 V
30
−14
17
dB
dB
dB
Maximum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Output IP3
Output Noise Floor
Noise Figure
30 MHz around center frequency, VGAIN = 1.0 V (differential output)
0.09
40
700
47
−149
9
dB
mV/dB
mV
dBm
dBm/Hz
dB
Gain = 0 dB, gain = slope (VGAIN − intercept)
VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement
VGAIN = 1.4 V
VGAIN = 1.4 V
FREQUENCY INPUT = 400 MHz
Gain Control Span
Minimum Gain
3 dB gain law conformance
VGAIN = 0.1 V
VGAIN = 1.4 V
30
−15
15
dB
dB
dB
Maximum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Output IP3
Output Noise Floor
Noise Figure
30 MHz around center frequency, VGAIN = 1.0 V (differential output)
0.09
39.5
730
39
−150
9
dB
mV/dB
mV
dBm
dBm/Hz
dB
Gain = 0 dB, gain = slope (VGAIN − intercept)
VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement
20 MHz carrier offset, VGAIN = 1.4 V
VGAIN = 1.4 V
FREQUENCY INPUT = 900 MHz
Gain Control Span
Minimum Gain
3 dB gain law conformance
VGAIN = 0.1 V
VGAIN = 1.4 V
35
−18
15
dB
dB
dB
Maximum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Third-Order Harmonic
Output IP3
30 MHz around center frequency, VGAIN = 1.0 V (differential output)
0.09
37
800
−75
32
dB
mV/dB
mV
dBc
dBm
dBm/Hz
dB
Gain = 0 dB, gain = slope (VGAIN − intercept)
−8 dBm output at 900 MHz fundamental
VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement
20 MHz carrier offset, VGAIN = 1.4 V
VGAIN = 1.4 V
Output Noise Floor
Noise Figure
−150
9
GAIN CONTROL INPUT
Gain Control Voltage Range1
Incremental Input Resistance
Response Time
Pin GAIN
0.1
1.4
V
Pin GAIN to Pin COM1
Full scale, to within 1 dB of final gain
3 dB gain step, POUT to within 1 dB of final gain
1
380
20
MΩ
ns
ns
Rev. 0 | Page 3 of 16
ADL5331
Parameter
Conditions
Min
4.75
2.3
Typ
Max Unit
POWER SUPPLIES
Voltage
Current, Nominal Active
ENBL, Logic 1, Device Enabled
ENBL, Logic 0, Device Disabled
Current, Disabled
Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL
5
240
5.25
0.8
V
mA
V
V
ENBL = Logic 0
250
μA
1 Minimum gain voltage varies with frequency (see Figure 3, Figure 4, and Figure 5).
Rev. 0 | Page 4 of 16
ADL5331
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage VPS1
Supply Voltage VPS2
VPS2 to VPS1
5.5 V
5.5 V
200 mV
RF Input Power
OPHI, OPLO
5 dBm at 50 Ω
5.5 V
ENBL
VPS1
ESD CAUTION
GAIN
VPS1
Internal Power Dissipation
θJA (with Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
1.2 W
56.1°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Rev. 0 | Page 5 of 16
ADL5331
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPS1
COM1
INHI
INLO
COM1
VPS1
1
2
3
4
5
6
18 VPS2
17 COM2
16 OPHI
15 OPLO
14 COM2
13 VPS2
PIN 1
INDICATOR
ADL5331
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. CONNECT THE EXPOSED PAD
TO COM1 AND COM2.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 6
2, 5
VPS1
COM1
Positive Supply. Nominally equal to 5 V.
Common for the Input Stage.
3, 4
7
INHI, INLO
NC
Differential Inputs, AC-Coupled.
No Connect.
8
9
IPBS
OPBS
COM2
VPS2
OPLO, OPHI
ENBL
GAIN
Input Bias. Normally ac-coupled to VPS1. A 10 nF capacitor is recommended.
Output Bias. Internally compensated, do not connect externally.
Common for the Output Stage.
Positive Supply. Nominally equal to 5 V.
Differential Outputs. Bias to VPOS with RF chokes.
Device Enable. Apply logic high for normal operation.
Gain Control Voltage Input. Nominal range is 0 V to 1.4 V.
Exposed Paddle.
10 to 12, 14, 17
13, 18 to 22
15, 16
23
24
25 (EPAD)
EP (EPAD)
Rev. 0 | Page 6 of 16
ADL5331
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match.
20
4
30
25
20
15
10
3
2
5
0
1
0
15
10
5
–5
–1
–2
–3
–4
–10
–15
–20
0
0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1
10
100
1k
V
(V)
FREQUENCY (MHz)
GAIN
Figure 6. Gain Slope vs. Frequency, RFIN = −20 dBm @ 500 MHz, VGAIN = 1 V
Figure 3. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 100 MHz
20
4
55
50
45
40
35
30
25
20
15
10
3
2
5
0
1
0
–5
–1
–2
–3
–4
–10
–15
–20
15
10
0.1
0.3
0.5
0.7
0.9
1.1
1.3
0.5
0.6
0.7
0.8
0.9
1.0
(V)
1.1
1.2
1.3
1.4
V
(V)
V
GAIN
GAIN
Figure 4. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 400 MHz
Figure 7. Output IP3 vs. VGAIN at 100 MHz
20
4
45
15
10
3
2
40
35
30
25
20
5
0
1
0
–5
–1
–2
–3
–4
–10
–15
–20
15
10
0.1
0.3
0.5
0.7
0.9
1.1
1.3
0.5
0.6
0.7
0.8
0.9
1.0
(V)
1.1
1.2
1.3
1.4
V
(V)
V
GAIN
GAIN
Figure 5. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 900 MHz
Figure 8. Output IP3 vs. VGAIN at 400 MHz
Rev. 0 | Page 7 of 16
ADL5331
40
35
30
25
20
V
V
= 1.4V
= 1.2V
GAIN
GAIN
15
10
5
V
V
= 1.0V
= 0.8V
GAIN
GAIN
25
20
15
10
0
–5
V
V
V
= 0.6V
= 0.4V
= 0.2V
GAIN
GAIN
GAIN
–10
–15
–20
–25
V
= 0V
GAIN
0.5
0.6
0.7
0.8
0.9
1.0
(V)
1.1
1.2
1.3
1.4
50
500
1000
V
GAIN
FREQUENCY (MHz)
Figure 9. Output IP3 vs. VGAIN at 900 MHz
Figure 12. Gain vs. Frequency (Differential 100 Ω Output Load)
–148
100MHz
400MHz
–150
900MHz
–152
t1: 2.24µs
t2: 1.2µs
Δt: –1.04µs
1/Δt: –961.5kHz
–154
–156
–158
–160
MEAN(C1) 1.358V
AMPL(C1) 3.36V
AMPL(C2) 900mV
2
0.1
0.3
0.5
0.7
0.9
1.1
1.3
CH2 500mV
M 2.0µs 25.0MS/s 40.0ns/pt
A CH1 150mV
V
(V)
GAIN
CH3 200mV
Ω
Figure 10. Step Response of Gain Control Input
Figure 13. Output Noise Spectral Density vs. VGAIN
30
25
20
15
V
V
= 1.4V
= 1.2V
GAIN
GAIN
10
5
V
V
= 1.0V
= 0.8V
GAIN
GAIN
0
–5
–10
V
V
V
= 0.6V
= 0.4V
= 0.2V
GAIN
GAIN
GAIN
–15
–20
–25
V
= 0V
GAIN
–30
50
500
1000
FREQUENCY (MHz)
Figure 11. Gain vs. Frequency (Differential 50 Ω Output Load)
Rev. 0 | Page 8 of 16
ADL5331
THEORY OF OPERATION
The ADL5331 is a high performance, voltage-controlled
variable gain amplifier/attenuator for use in applications
with frequencies up to 1.2 GHz. This device is intended to
serve as an output variable gain amplifier (OVGA) for applica-
tions where a reasonably constant input level is available and
the output level adjusts over a wide range. One aspect of an
OVGA is that the output metrics, OIP3 and OP1dB, decrease
with decreasing gain.
Linear-in-dB gain control is accomplished by the application of
a voltage in the range of 0 V dc to 1.4 V dc to the gain control
pin, with maximum gain occurring at the highest voltage.
The output of the ladder attenuator is passed into a fixed-gain
transimpedance amplifier (TZA) to provide gain and to buffer
the ladder terminating impedance from load variations. The
TZA uses feedback to improve linearity and to provide controlled
50 Ω differential output impedance. The quiescent current of
the output amplifier is adaptive; it is controlled by an output
level detector, which biases the output stage for signal levels
above a threshold.
The signal path is fully differential throughout the device to
provide the usual benefits of differential signaling, including
reduced radiation, reduced parasitic feedthrough, and reduced
susceptibility to common-mode interference with other circuits.
Figure 14 provides a simplified schematic of the ADL5331.
The outputs of the ADL5331 require external dc bias to the
positive supply voltage. This bias is typically supplied through
external inductors. The outputs are best taken differentially to
avoid any common-mode noise that is present, but, if necessary,
can be taken single-ended from either output.
TRANSIMPEDANCE
AMPLIFIER
INHI
INLO
OPHI
OPLO
The output impedance is 20 ꢀ differential and can drive a range
of impedances from <20 ꢀ to >75 ꢀ. Back series terminations
can be used to pad the output impedance to a desired level.
Gm STAGE
If only a single output is used, it is still necessary to provide a
bias to the unused output pin and it is advisable to arrange a
reasonably equivalent ac load on the unused output. Differential
output can be taken via a 1:1 balun into a 50 Ω environment. In
virtually all cases, it is necessary to use dc blocking in the output
signal path.
GAIN
CONTROL
Figure 14. Simplified Schematic
A controlled input impedance of 50 Ω is achieved through
a combination of passive and active (feedback-derived)
termination techniques in an input Gm stage.
At high gain settings, the noise floor is set by the input stage,
in which case the noise figure (NF) of the device is essentially
independent of the gain setting. Below a certain gain setting,
however, the input stage noise that reaches the output of the
attenuator falls below the input-equivalent noise of the output
stage. In such a case, the output noise is dominated by the output
stage itself; therefore, the overall NF of the device gets worse
on a dB-per-dB basis as the gain is lowered, because the gain
is reduced below the critical value. Figure 7 through Figure 9
provide details of this behavior.
Note that the inputs of the Gm stage are internally biased to
a dc level and dc blocking capacitors are generally needed on
the inputs to avoid upsetting the operation of the device.
The currents from the Gm stage are then injected into a
balanced ladder attenuator at a deliberately diffused location
along the ladder, wherein the location of the centroid of the
injection region is dependent on the applied gain control
voltage. The steering of the current injection into the ladder
is accomplished by proprietary means to achieve linear-in-dB
gain control and low distortion.
Rev. 0 | Page 9 of 16
ADL5331
APPLICATIONS INFORMATION
VPOS
VPOS
C1
C3
0.1µF
0.1µF
GAIN
C2
C4
100pF
100pF
VPOS
C15
C16
L1
0.68µH
0.1µF 100pF
L2
0.68µH
VPS1
COM1
INHI
VPS2
C13
10nF
C5
10nF
COM2
OPHI
RFOUT
ADL5331
RFIN
INLO
COM1
VPS1
OPLO
C14
C6
10nF
COM2
VPS2
10nF
VPOS
C12
0.1µF 100pF
C11
C7
100pF
C8
0.1µF
C10
10nF
C9
10nF
VPOS
Figure 15. Basic Connections
To enable the ADL5331, the ENBL pin must be pulled high.
Taking ENBL low puts the ADL5331 in sleep mode, reducing
current consumption to 250 μA at an ambient temperature.
The voltage on ENBL must be greater than 1.7 V to enable the
device. When enabled, the device draws 100 mA at low gain to
215 mA at maximum gain.
BASIC CONNECTIONS
Figure 15 shows the basic connections for operating the
ADL5331. There are two positive supplies, VPS1 and VPS2,
which must be connected to the same potential. Connect COM1
and COM2 (common pins) to a low impedance ground plane.
Apply a power supply voltage between 4.75 V and 5.25 V to
VPS1 and VPS2. Connect decoupling capacitors with 100 pF
and 0.1 μF power supplies close to each power supply pin. The
VPS2 pins (Pins 13 and Pin 18 through Pin 22) can share a pair
of decoupling capacitors because of their proximity to each other.
The ADL5331 is primarily designed for differential signals;
however, there are several configurations that can be imple-
mented to interface the ADL5331 to single-ended applications.
Figure 16 and Figure 17 show options for differential-to-single-
ended interfaces. Both configurations use ac-coupling capacitors
at the input/output and RF chokes at the output.
+5V
The outputs of the ADL5331, OPHI and OPLO, are open
collectors that need to be pulled up to the positive supply
with 120 nH RF chokes. The ac-coupling capacitors and
the RF chokes are the principle limitations for operation at
low frequencies. For example, to operate down to 1 MHz,
use 0.1 μF ac coupling capacitors and 1.5 μH RF chokes. Note
that in some circumstances, the use of substantially larger
inductor values results in oscillations.
120nH
120nH
ADL5331
RF VGA
10nF
10nF
10nF
10nF
RFIN
INHI
OPHI
RFOUT
Because the differential outputs are biased to the positive
supply, ac-coupling capacitors (preferably 100 pF) are needed
between the ADL5331 outputs and the next stage in the system.
Similarly, the INHI and INLO input pins are at bias voltages of
about 3.3 V above ground.
INLO
OPLO
ETC1-1-13
ETC1-1-13
Figure 16. Differential Operation with Balun Transformers
Figure 16 illustrates differential balance at the input and output
using a transformer balun. Input and output baluns are recom-
mended for optimal performance. Much of the characterization
for the ADL5331 was completed using 1:1 baluns at the input
and output for a single-ended 50 Ω match. Operation using
M/A-COM ETC1-1-13 transmission line transformer baluns
is recommended for a broadband interface; however, narrow-
band baluns can be used for applications requiring lower
insertion loss over smaller bandwidths.
The nominal input and output impedance looking into each
individual RF input/output pin is 25 Ω. Consequently, the
differential impedance is 50 Ω.
Rev. 0 | Page 10 of 16
ADL5331
5V
Note that the ADL5331, because of its positive gain slope, in
an AGC application requires a detector with a negative VOUT
RFIN slope. As an example, the AD8319 in the example in
Figure 19 has a negative slope. The AD8362 rms detector,
however, has a positive slope. Extra circuitry is necessary to
compensate for this.
/
120nH
120nH
10nF
ADL5331
RF VGA
10nF
10nF
RFIN
INHI
INLO
OPHI
OPLO
RFOUT
To operate the ADL5331 in an AGC loop, a sample of the
output RF must be fed back to the detector (typically using
10nF
a directional coupler and additional attenuation). A setpoint
voltage is applied to the VSET input of the detector while VOUT
is connected to the GAIN pin of the ADL5331. Based on the
detector’s defined linear-in-dB relationship between VOUT
and the RFIN signal, the detector adjusts the voltage on the
GAIN pin (the detector’s VOUT pin is an error amplifier
output) until the level at the RF input corresponds to the applied
setpoint voltage. The VGAIN setting settles to a value that results
in the correct balance between the input signal level at the
detector and the setpoint voltage.
ETC1-1-13
Figure 17. Single-Ended Drive with Balanced Output
The device can be driven single-ended with similar perfor-
mance, as shown in Figure 17. The single-ended input interface
can be implemented by driving one of the input terminals and
terminating the unused input to ground. To achieve the optimal
performance, the output must remain balanced. In the case of
Figure 17, a transformer balun is used at the output.
GAIN CONTROL INPUT
When the VGA is enabled, the voltage applied to the GAIN pin
sets the gain. The input impedance of the GAIN pin is 1 MΩ.
The detector’s error amplifier uses CLPF, a ground-referenced
capacitor pin, to integrate the error signal (in the form of a
current). A capacitor must be connected to CLPF to set the
loop bandwidth and to ensure loop stability.
The gain control voltage range is between 0.1 V and 1.4 V,
which corresponds to a typical gain range between −15 dB and
+15 dB.
5V
5V
The 1 dB input compression point remains constant at 3 dBm
through the majority of the gain control range, as shown in
Figure 7 through Figure 9. The output compression point
increases decibel for decibel with increasing gain setting. The
noise floor is constant up to VGAIN = 1 V where it begins to rise.
VPOS
COMM
OPHI
RFIN
INHI
ADL5331
DIRECTIONAL
COUPLER
INLO
OPLO
GAIN
The bandwidth on the gain control pin is approximately 3 MHz.
Figure 10 shows the response time of a pulse on the VGAIN pin.
ATTENUATOR
VOUT
Although the ADL5331 provides accurate gain control, precise
regulation of output power can be achieved with an automatic
gain control (AGC) loop. Figure 18 shows the ADL5331 in an
AGC loop. The addition of a log amp or a TruPwr™ detector
(such as the AD8362) allows the AGC to have improved
temperature stability over a wide output power control range.
LOG AMP OR
TruPwr
DETECTOR
VSET
RFIN
DAC
CLPF
Figure 18. ADL5331 in AGC Loop
Rev. 0 | Page 11 of 16
ADL5331
+5V
+5V
RFIN
SIGNAL
RFOUT SIGNAL
120nH
10nF
120nH
VPOS
COMM
OPHI
10nF
10nF
INHI
ADL5331
10nF
10dB
INLO
OPLO
DIRECTIONAL
COUPLER
GAIN
390Ω
10dB
ATTENUATOR
+5V
1kΩ
SETPOINT
VOLTAGE
VOUT
VPOS
1nF
VSET
INHI
DAC
AD8319
LOG AMP
1nF
CLPF
INLO
220pF
COMM
Figure 19. AD8319 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5331
20
3.00
Figure 19 shows the basic connections for operating the AD8319
log detector in an automatic gain control (AGC) loop with the
ADL5331.
15
10
5
2.25
1.50
0.75
The gain of the ADL5331 is controlled by the output pin of the
AD8319. The voltage, VOUT, has a range of 0 V to near VPOS. To
avoid overdrive recovery issues, the AD8319 output voltage can
be scaled down using a resistive divider to interface with the
0.1 V to 1.4 V gain control range of the ADL5331.
+85°C
0
0
+25°C
–40°C
–0.75
–1.50
–2.25
–3.00
–5
–10
–15
–20
A coupler/attenuation of 21 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8319 (approximately −5 dBm
at 900 MHz).
0.6
0.7
0.8
0.9
1.0
1.1
(V)
1.2
1.3
1.4
1.5
1.6
V
SET
Figure 20 shows the transfer function of the output power vs.
the VSET voltage over temperature for a 100 MHz sine wave
with an input power of −1.5 dBm. Note that the power control
of the AD8319 has a negative sense. Decreasing VSET, which
corresponds to demanding a higher signal from the ADL5331,
increases gain.
Figure 20. ADL5331 Output Power vs. AD8319 Setpoint Voltage,
PIN = 0 dBm at 100 MHz
This AGC loop is capable of controlling signals of ~30 dB,
which is the gain range limitation on the ADL5331. Across
the top 25 dB range of output power, the linear conformance
error is within 0.5 dB over temperature.
Rev. 0 | Page 12 of 16
ADL5331
For the AGC loop to remain in equilibrium, the AD8319 must
track the envelope of the output signal of the ADL5331 and
provide the necessary voltage levels to the gain control input
of the ADL5331. Figure 21 shows an oscilloscope of the AGC
loop depicted in Figure 19. A 100 MHz sine wave with 50% AM
modulation is applied to the ADL5331. The output signal from the
VGA is a constant envelope sine wave with amplitude corres-
ponding to a setpoint voltage at the AD8319 of 1.3 V. The gain
control response of the AD8319 to the changing input envelope
is also shown in Figure 21.
CURS1 POS
4.48µs
CURS2 POS
2.4µs
t1: 4.48µs
t2: 2.4µs
Δt: –2.08µs
1/Δt: –480.8kHz
2
MEAN(C1) 440.3mV
AMPL(C1) 3.36V
AMPL(C2) 900mV
T
CH2 500mV
M 4.0µs 12.5MS/s 80.0ns/pt
CH1 150mV
AM MODULATED INPUT
T
CH3 200mV
Ω
A
Figure 22. Oscilloscope Showing theResponse Time of the AGC Loop
1
Response time and the amount of signal integration are con-
trolled by CLPF. This functionality is analogous to the feedback
capacitor around an integrating amplifier. While it is possible
to use large capacitors for CLPF, in most applications, values
under 1 nF provide sufficient filtering.
AD8319 OUTPUT
2
More information on the use of AD8319 in an AGC application
can be found in the AD8319 data sheet.
CMTS TRANSMIT APPLICATION
3
Interfacing to AD9789
Because of its broadband operating range, the ADL5331 VGA
can also be used in direct-launch cable modem termination
systems (CMTS) applications in the 50 MHz to 860 MHz cable
band. The ADL5331 makes an excellent choice as a post-DAC
VGA in a CMTS application when used with the Analog
Devices AD9789 wideband DAC. The AD9789 also contains
digital signal processing specifically designed to process
DOCSIS type CMTS signals. A typical AD9789-to-ADL5331
interface is shown in Figure 23.
ADL5331 OUTPUT
CH1 250mV Ω CH2 200mV
CH3 250mV Ω
M2.00ms
0.00000s
A CH4
1.80V
T
Figure 21. Oscilloscope Showing an AM Modulated Input Signal and the
Response from the AD8319
Figure 22 shows the response of the AGC RF output to a pulse
on VSET. As VSET decreases from 1.5 V to 0.4 V, the AGC loop
responds with an RF burst. In this configuration, the input signal to
the ADL5331 is a 1 GHz sine wave at a power level of −15 dBm.
SERIES
5V
VGA
TERMINATION
16mA
AD9789
50Ω
20Ω
70Ω
25Ω
DAC
16mA
55Ω
Figure 23. Block Diagram of AD9789 interface to ADL5331 in a DOCSIS Type Application
Rev. 0 | Page 13 of 16
ADL5331
quadrature modulators. These modulators can provide outputs
from 500 MHz to 4 GHz.
INTERFACING TO AN IQ MODULATOR
The basic connections for interfacing the ADL5331 with the
ADL5385 are shown in Figure 24. The ADL5385 is an RF
quadrature modulator with an output frequency range of
50 MHz to 2.2 GHz. It offers excellent phase accuracy and
amplitude balance, enabling high performance direct RF
modulation for communication systems.
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
chip’s ground. Solder the paddle to the low impedance ground
plane on the printed circuit board to ensure specified electrical
performance and to provide thermal relief. It is also recom-
mended that the ground planes on all layers under the paddle
be stitched together with vias to reduce thermal impedance.
The output of the ADL5385 is designed to drive 50 ꢀ loads and
easily interfaces with the ADL5331. The input to the ADL5331
can be driven single-ended, as shown in Figure 17. Similar
configurations are possible with the ADL537x family of
5V
68µH
5V
5V
68µH
VPOS COMM
IBBP
VPOS COMM
10nF
10nF
10nF
DAC
ADL5385
IQ MOD
ADL5331
RF VGA
IBBN
INHI
OPHI
RF OUTPUT
DIFFERENTIAL I/Q
BASEBAND INPUTS
VOUT
INLO
OPLO
QBBP
QBBN
DAC
10nF
ETC1-1-13
100pF
LO
100pF
GAIN CONTROL
Figure 24. ADL5385 Quadrature Modulator and ADL5331 Interface
Rev. 0 | Page 14 of 16
ADL5331
EVALUATION BOARD SCHEMATIC
VPS1A
VPS2A
GNDA
R17A
10kΩ
SW1A
TESTLOOP TESTLOOP TESTLOOP
BLUE RED BLACK
VPS1A
3
2
AGNDA
VPS2A
ENB_A
1
R1A
0Ω
VPS1A
VPS2A
AGNDA
ENBLA
C2
0.1µF
ENBLA
VPS1A
P1A
P1A
P1A
1
2
3
GAINA
R3A
1kΩ
AGNDA
AGNDA
R2A
0Ω
R14A
0Ω
C1A
100pF
GNA
R16A
0Ω
VPS2A
GAINA
IPBSA
OPBSA
VREFA
P1A
P1A
P1A
P1A
P1A
4
5
6
7
8
C17A
1000pF
AGNDA
VS2A
AGNDA
AGNDA
C8A
0.1µF
AGNDA
24 23
22 21 20
19
C7A
100pF
18
1
2
L1A
0.68µH
VPS2
VPS1A
VPS1
RSA
0Ω
17
16
AGNDA
AGNDA
COM1
INHI
COM2
C11A
10nF
C11A
C12A
T1A
2
T2A
3
4
5
6
INHIA
OPHIA
OPHI
3
1
4
1
3
5
4
R12A
0Ω
Z1A
15
14
ADL5331
VPS2A
2
5
INLO
OPLO
COM2
C13A
100pF
C14A
0.1µF
C12A
10nF
L2A
0.68µH
AGNDA
AGNDA
AGNDA
AGNDA
AGNDA
COM1
VPS1
R4A
0Ω
13
25
VPS1A
R6A
VPS2
EPAD
VS1A
0Ω
C3A
0.1µF
C4A
100pF
VPS2A
C10A
100pF
C9A
0.1µF
7
8
9
10
11
12
AGNDA
C16A
10nF
VS1A VS2A
R9A
0Ω
IPBSA
OPBSA
Figure 25. ADL5331 Single-Ended Input/Output Evaluation Board
Rev. 0 | Page 15 of 16
ADL5331
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
*
2.45
2.30 SQ
2.15
TOP
VIEW
3.75
BSC SQ
EXPOSED
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
12
7
0.23 MIN
0.80 MAX
0.65 TYP
1.00
0.85
0.80
2.50 REF
12° MAX
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
SECTION OF THIS DATA SHEET.
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Ordering
Quantity
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
ADL5331ACPZ-R71
ADL5331ACPZ-WP1
ADL5331-EVALZ1
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
ADL5331 Evaluation Board
CP-24-2
CP-24-2
1,500
250
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07593-0-5/09(0)
Rev. 0 | Page 16 of 16
相关型号：
ADL5336
An IQ Demodulator-Based IF-to-Baseband Receiver with IF and Baseband Variable Gain and Programmable Baseband Filtering
ADI
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