ADIS16080/PCBZ [ADI]
【80∑/sec Yaw Rate Gyro with SPI Interface; 【80Σ /秒偏航角速度陀螺仪，SPI接口
| 型号： | ADIS16080/PCBZ |
| 厂家： | 
ADI |
| 描述： | 【80∑/sec Yaw Rate Gyro with SPI Interface |
| 文件： | 总16页 (文件大小：606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FEATURES
GENERAL DESCRIPTION
Complete angular rate gyroscope
Z-axis (yaw rate) response
SPI digital output interface
High vibration rejection over wide frequency
2000 g powered shock survivability
Externally controlled self test
Internal temperature sensor output
Dual auxiliary 12-bit ADC inputs
Absolute rate output for precision applications
5 V single-supply operation
The ADIS16080 is a complete angular rate sensor (gyroscope)
that uses the Analog Devices, Inc. surface-micromachining
process to make a functionally complete angular rate sensor
with an integrated serial peripheral interface (SPI).
The digital data available at the SPI port is proportional to the
angular rate about the axis normal to the top surface of the
package (see Figure 19). A single external resistor can be used
to increase the measurement range. An external capacitor can
be used to lower the bandwidth.
8.2 mm × 8.2 mm × 5.2 mm package
RoHS-compliant
Access to an internal temperature sensor measurement is
provided, through the SPI, for compensation techniques.
Two pins are available for the user to input analog signals for
digitization. An additional output pin provides a precision
voltage reference. Two digital self-test inputs electro-
mechanically excite the sensor to test operation of the
sensor and the signal conditioning circuits.
APPLICATIONS
Platform stabilization
Image stabilization
Guidance and control
Inertial measurement units
Robotics
The ADIS16080 is available in an 8.2 mm × 8.2 mm × 5.2 mm
16-terminal, peripheral land grid array (LGA) package.
FUNCTIONAL BLOCK DIAGRAM
C
OUT
FILT
RATE
ADIS16080
±80°/s
SCLK
DIN
GYROSCOPE
4-CHANNEL
SPI
TEMPERATURE
SENSOR
MUX/ADC
CS
DOUT
AIN2
AIN1
REFERENCE
V
REF
ST1
ST2
V
COM
V
CC
5V
DRIVE
3V TO 5V
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADIS16080
TABLE OF CONTENTS
Features .............................................................................................. 1
Supply and Common Considerations ..................................... 11
Increasing Measurement Range ............................................... 11
Setting Bandwidth...................................................................... 11
Self-Test Function ...................................................................... 11
Continuous Self Test .................................................................. 11
Rate Sensitive Axis ..................................................................... 11
Control Register.............................................................................. 12
Serial Interface............................................................................ 13
Second-Level Assembly............................................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADIS16080
SPECIFICATIONS
TA = 25°C, VCC = VDRIVE = 5 V, angular rate = 0°/sec, COUT = 0 μF, ±± g, unless otherwise noted.
Table 1.
Parameter
SENSITIVITY
Dynamic Range2
Initial
Conditions
Min1
Typ
Max1
Unit
Full-scale range over specifications range
Clockwise rotation is positive output,
TA = −40°C to +±5°C
±±0
9.21
°/sec
LSB/°/sec
10.24
11.26
Change over Temperature3
Nonlinearity
Voltage Sensitivity
NULL
VCC = VDRIVE = 4.75 V to 5.25 V
Best fit straight line
VCC = VDRIVE = 4.75 V to 5.25 V
±5
0.15
0.7
%
% of FS
% of FS
Initial
1629
204±
±±5
35
2.05
±10.24
2466
LSB
LSB
ms
LSB/g
LSB/V
Change Over Temperature3
VCC = VDRIVE = 4.75 V to 5.25 V
Power on to ±ꢀ°/sec of final
Any axis
Turn-On Time
Linear Acceleration Effect
Voltage Sensitivity
NOISE PERFORMANCE
Total Noise
VCC = VDRIVE = 4.75 V to 5.25 V
0.1 Hz to 40 Hz; no averaging
@ 25°C
0.42
43
0.05
0.51
°/sec rms
LSB rms
°/sec /√Hz
LSB rms/√Hz
Rate Noise Density
FREQUENCY RESPONSE
3 dB Bandwidth (User-Selectable)4 COUT = 0 μF
Sensor Resonant Frequency
40
14
Hz
kHz
SELF-TEST INPUTS
ST1 RATEOUT Response5
ST2 RATEOUT Response5
Logic 1 Input Voltage
Logic 0 Input Voltage
Input Impedance
TEMPERATURE SENSOR
Reading at 29± K
ST1 pin from Logic 0 to Logic 1
−32±
+32±
3.3
−540
+540
−±19
+±19
LSB
LSB
V
V
kΩ
ST2 pin from Logic 0 to Logic 1
Standard high logic level definition
Standard low logic level definition
To common
1.7
50
204±
6.±±
LSB
LSB/K
Scale Factor
Proportional to absolute temperature
2.5 V REFERENCE
Voltage Value
Load Drive to Ground
Load Regulation
Power Supply Rejection
Temperature Drift
LOGIC INPUTS
2.45
2.5
100
5.0
1.0
5.0
2.55
V
μA
mV/mA
mV/V
mV
Source
0 μA < IOUT < 100 μA
VCC = VDRIVE = 4.75 V to 5.25 V
Delta from 25°C
0.7 × VDRIVE
−1
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
ANALOG INPUTS6
Resolution
Integral Nonlinearity6
Differential Nonlinearity
Offset Error
V
V
μA
pF
0.3 × VDRIVE
+1
Typically 10 nA
10
12
Bits
LSB
LSB
LSB
LSB
V
−2
−2
−±
−2
0
+2
+2
+±
+2
Gain Error
Input Voltage Range
VREF × 2
Rev. 0 | Page 3 of 16
ADIS16080
Parameter
Conditions
Min1
Typ
Max1
Unit
μA
Leakage Current
−1
+1
Input Capacitance
Full Power Bandwidth
DIGITAL OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
CONVERSION RATE
Conversion Time
20
8
pF
MHz
ISOURCE = 200 μA
ISINK = 200 μA
VDRIVE − 0.2
V
V
0.4
16 SCLK cycles with SCLK at 20 MHz
800
1
ns
MSPS
Throughput Rate
POWER SUPPLY7
VCC
VDRIVE
4.75
2.7
5
5.25
5.25
9.0
V
V
mA
μA
mW
VCC Quiescent Supply Current
VDRIVE Quiescent Supply Current
Power Dissipation
TEMPERATURE RANGE
Specified Performance
VCC @ 5 V, fSCLK = 50 kSPS
VDRIVE @ 5 V, fSCLK = 50 kSPS
VCC and VDRIVE @ 5 V, fSCLK = 50 kSPS
7.0
70
40
500
Tested to max and min specifications
−40
+85
°C
1 All minimum and maximum specifications are guaranteed. Typical specifications are neither tested nor guaranteed.
2 Dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 5 V
supplies.
3 Defined as the output change from ambient to maximum temperature or ambient to minimum temperature.
4 Frequency at which the response is 3 dB down from dc response. Bandwidth = 1/(2 × π × 180 kΩ × (22 nF + COUT)). For COUT = 0, bandwidth = 40 Hz. For COUT = 1 μF,
bandwidth = 0.87 Hz.
5 Self-test response varies with temperature.
6 For VIN < VCC.
7 All at TA = −40°C to +85°C.
Rev. 0 | Page 4 of 16
ADIS16080
TIMING SPECIFICATIONS
TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1
Table 2.
Parameter
VCC = VDRIVE = 5
Unit
Description
2
fSCLK
10
20
kHz min
MHz max
tCONVERT
tQUIET
t2
16 × tSCLK
50
ns min
ns min
ns max
ns max
ns min
ns min
ns min
Minimum quiet time required between CS rising edge and start of next conversion
CS to SCLK setup time
10
3
t3
30
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
3
t4
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
1
t5
t6
t7
4
t8
ns min/max SCLK falling edge to DOUT high impedance
t9
ns min
ns min
ns min
μs max
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
t10
t11
t12
Power-up time from full power-down/auto shutdown modes
1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans
from 4.75 V to 5.25 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 V × VDRIVE
.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
CS
tCONVERT
t2
t6
B
1
2
3
4
5
6
11
12
13
14
t5
15
16
t11
SCLK
t7
DB10
t3
t4
t8
DB0
tQUIET
ZERO
t9
ADD1
ADD0
DB11
DB4
DB3
DB2
DB1
DOUT
THREE-STATE
ZERO
THREE-STATE
2 IDENTIFICATION
BITS
t10
ADD0
DIN
WRITE
LOW
DONTC DONTC
ADD1
CODING DONTC DONTC
DONTC
DONTC
Figure 2. Gyroscope Serial Interface Timing Diagram
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 3. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 16
ADIS16080
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Acceleration (Any Axis, Unpowered, 0.5 ms)
Acceleration (Any Axis, Powered, 0.5 ms)
VCC to COM
2000 g
2000 g
−0.3 V to +6.0 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−0.3V to +7.0V
−0.3V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−55°C to +125°C
−65°C to +150°C
VDRIVE to COM
Analog Input Voltage to COM
Digital Input Voltage to COM
Digital Output Voltage to COM
STx Input Voltage to COM
Operating Temperature Range
Storage Temperature Range
Drops onto hard surfaces can cause shocks of greater than
2000 g and exceed the absolute maximum rating of the device.
Care should be exercised in handling to avoid damage.
ESD CAUTION
Rev. 0 | Page 6 of 16
ADIS16080
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
5
6
7
8
4
3
2
1
9
NC
DOUT
SCLK
DIN
AIN2
COM
ADIS16080
10
11
12
BOTTOM
VIEW
(Not to Scale)
V
REF
ST2
16
15
14
13
NC = NO CONNECT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
DIN
I
Data In. Data to be written to the control register is provided on this input and is clocked in on the
falling edge of the SCLK.
2
3
SCLK
I
Serial Clock. SCLK provides the serial clock for accessing data from the part and writing serial data
to the control registers. Also used as a clock source for the ADIS16080 conversion process.
Data Out. The data on this pin represents data being read from the control registers and is clocked
on the falling edge of the SCLK.
DOUT
O
4
5
6
7
NC
No Connect.
RATE
FILT
VDRIVE
O
I
S
Buffered Analog Output. Represents the angular rate signal.
External Capacitor Connection to Control Bandwidth.
Power to SPI. The voltage supplied to this pin determines the voltage at which the serial interface
operates.
8
9
AIN1
AIN2
I
I
External Analog Input Channel 1. Single-ended analog input multiplexed into the on-chip track-
and-hold, according to the setting of the ADD0 and ADD1 address bits (see Table 5).
External Analog Input Channel 2. Single-ended analog input multiplexed into the on-chip track-
and-hold, according to the setting of the ADD0 and ADD1 address bits (see Table 5).
10
11
12
13
14
15
16
COM
VREF
ST2
ST1
VCC
S
O
I
I
S
Common. Reference point for all circuitry in the ADIS16080.
Precision 2.5 V Reference.
Self-Test Input 2.
Self-Test Input 1.
Analog Power.
NC
CS
No Connect.
I
Chip Select. Active low. This input frames the serial data transfer and initiates the conversion
process.
1 I = input; O = output; S = power supply.
Rev. 0 | Page 7 of 16
ADIS16080
TYPICAL PERFORMANCE CHARACTERISTICS
70
60
50
40
30
20
10
0
25
AVERAGE = 2014.38
STD. DEVIATION = 99.3236
AVERAGE = 6.4mA
STD. DEVIATION = 0.2mA
20
15
10
5
0
1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
SUPPLY CURRENT (mA)
NULL (LSB)
Figure 8. Supply Current Histogram
Figure 5. Initial Null Histogram
20
18
16
14
12
10
8
2080
AVERAGE = –519.6 LSB
STD. DEVIATION = 21.892 LSB
–40°C
2070
2060
2050
2040
+25°C
2030
6
2020
4
+85°C
2010
2
0
2000
4.7
4.8
4.9
5.0
(V)
5.1
5.2
5.3
V
ST1 (LSB)
CC
Figure 9. Self Test 1 Histogram
Figure 6. Null Level vs. Supply Voltage
25
20
15
10
5
2080
30 PART AVERAGE, V
30 PART AVERAGE, V
30 PART AVERAGE, V
= 4.75V
= 5.00V
= 5.25V
AVERAGE = 522.47 LSB
STD. DEVIATION = 19.9086 LSB
CC
CC
CC
2070
2060
2050
2040
2030
2020
2010
2000
0
–50
–30
–10
10
30
50
70
90
110
TEMPERATURE (°C)
ST2 (LSB)
Figure 7. Null Level vs. Temperature
Figure 10. Self Test 2 Histogram
Rev. 0 | Page 8 of 16
ADIS16080
–400
–420
–440
–460
–480
–500
–520
–540
–560
–580
–600
600
580
560
540
520
500
480
460
440
420
400
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, V = 5.00V
30 PART AVERAGE, T = –40°C
CC
A
30 PART AVERAGE, V = 5.25V
CC
30 PART AVERAGE, T = +25°C
A
30 PART AVERAGE, T = +85°C
A
4.7
4.8
4.9
5.0
(V)
5.1
5.2
5.3
–50
–30
–10
10
30
50
70
90
110
V
CC
TEMPERATURE (°C)
Figure 11. Self Test 1 vs. Supply Voltage
Figure 14. Self Test 2 vs. Temperature
600
550
500
450
400
0
–0.5
–1.0
–1.5
–2.0
–2.5
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, T = +85°C
A
30 PART AVERAGE, V = 5.00V
CC
30 PART AVERAGE, V = 5.25V
CC
30 PART AVERAGE, T = +25°C
A
30 PART AVERAGE, T = –40°C
A
4.7
4.8
4.9
5.0
(V)
5.1
5.2
5.3
–50
–30
–10
10
30
50
70
90
110
V
CC
TEMPERATURE (°C)
Figure 12. Self Test 2 vs. Supply Voltage
Figure 15. ADC Offset vs. Temperature and Supply Voltage
–400
–420
–440
–460
–480
–500
–520
–540
–560
–580
1.0
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, V = 5.00V
CC
30 PART AVERAGE, V = 5.25V
CC
30 PART AVERAGE, V = 5.00V
CC
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
30 PART AVERAGE, V = 5.25V
CC
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
–50
–30
–10
10
30
50
70
90
110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Self Test 1 vs. Temperature
Figure 16. ADC Gain Error vs. Temperature (Excluding VREF)
Rev. 0 | Page 9 of 16
ADIS16080
2.486
2.485
2.484
2.483
2.482
2.481
2.480
2.479
1825
1820
1815
1810
1805
1800
30 PART AVERAGE, T = +25°C
A
30 PART AVERAGE, T = –40°C
A
30 PART AVERAGE, T = +85°C
A
0
1000 2000 3000 4000 5000 6000 7000 8000
4.7
4.8
4.9
5.0
(V)
5.1
5.2
5.3
000001110000010X
000001110000011X
3
19
V
CC
000001110000100X
000001110000101X
000001110000110X
000001110000111X
000001110001000X
000001110001001X
000001110001010X
000001110001011X
000001110001100X
000001110001101X
000001110001110X
000001110001111X
000001110010000X
000001110010010X
39
87
Figure 17. VREF vs. Supply Voltage
249
844
1136
1303
1702
1229
924
447
150
43
13
4
SAMPLES = 8192, MAX CODE = 1827, MIN CODE = 1796,
SPREAD = 32, STD DEV = 4.057, MEAN = 1811.803
Figure 18. Noise Histogram
Rev. 0 | Page 10 of 16
ADIS16080
THEORY OF OPERATION
The ADIS16080 operates on the principle of a resonator gyro.
Two polysilicon sensing structures each contain a dither frame,
which is electrostatically driven to resonance. This produces the
necessary velocity element to produce a Coriolis force during
angular rate. At two of the outer extremes of each frame,
orthogonal to the dither motion, are movable fingers that are
placed between fixed pickoff fingers to form a capacitive pickoff
structure that senses Coriolis motion. The resulting signal is fed
to a series of gain and demodulation stages that produce the
electrical rate signal output. The rate signal is then converted to
a digital representation of the output on the SPI pins. The dual-
sensor design rejects external g forces and vibration. Fabricating
the sensor with the signal conditioning electronics preserves
signal integrity in noisy environments.
SETTING BANDWIDTH
An external capacitor can be used in combination with an on-
chip resistor to create a low-pass filter to limit the bandwidth of
the ADIS16080 rate response.
The −3 dB frequency is defined as
fOUT =1/
2×π×ROUT
×
COUT + 0.022 μF
where ROUT represents an internal impedance that was trimmed
during manufacturing to 180 kΩ 1%.
Any external resistor applied between the RATE pin and the
FILT pin results in
ROUT
=
180 kꢀ× REXT
/
180 kꢀ + REXT
With COUT = 0 μF, a default −3 dB frequency response of 40 Hz
is obtained based upon an internal 0.022 μF capacitor
implemented on-chip.
The electrostatic resonator requires 14 V to 16 V for operation.
Because only 5 V is typically available in most applications,
a charge pump is included on-chip.
After the demodulation stage, there is a single-pole, low-pass filter
included on-chip that is used to limit high frequency artifacts
before final amplification. The frequency response is dominated
by the second low-pass filter, which is set at 40 Hz. For additional
bandwidth reduction options, see the Setting Bandwidth section.
SELF-TEST FUNCTION
The ADIS16080 includes a self-test feature that actuates each of
the sensing structures and associated electronics in the same
manner as if subjected to angular rate. It provides a simple
method for exercising the mechanical structure of the sensor,
along with the entire signal processing circuit. It is activated by
standard logic high levels applied to inputs ST1, ST2, or both.
ST1 causes a change in the digital output equivalent to typically
−540 LSB, and ST2 causes an opposite +540 LSB change. The self-
test response follows the viscosity temperature dependence of the
package atmosphere, approximately 0.25%/°C.
SUPPLY AND COMMON CONSIDERATIONS
Power supply noise and transient behaviors can influence the
accuracy and stability of any sensor-based measurement system.
When considering the power supply for the ADIS16080, it is
important to understand that the ADIS16080 provides 0.2 μF of
decoupling capacitance on the VCC pin. Depending on the level of
noise present in the system power supply, the ADIS16080 may not
require any additional decoupling capacitance for this supply.
The analog supply, VCC, and the digital drive supply, VDRIVE, are
segmented to allow multiple logic levels to be used in receiving the
digital output data. VDRIVE is intended for the down-stream logic
power supply and supports standard 3.3 V and 5 V logic families.
The VDRIVE supply does not have internal decoupling capacitors.
Activating both ST1 and ST2 simultaneously is not damaging.
Because ST1 and ST2 are not necessarily closely matched, actuating
both simultaneously can result in an apparent null bias shift.
CONTINUOUS SELF TEST
As an additional failure detection measure, power-on self test
can be performed. However, some applications can warrant
continuous self test while sensing rate.
INCREASING MEASUREMENT RANGE
RATE SENSITIVE AXIS
The full-scale measurement range of the ADIS16080 is increased
by placing an external resistor between the RATE pin and FILT pin,
which results in a parallel connection with the internal 180 kΩ,
1% resistor. For example, a 330 kΩ external resistor gives ~50%
increase in the full-scale range. This is effective for up to a 4×
increase in the full-scale range (minimum value of the parallel
resistor allowed is 45 kΩ). The internal circuitry headroom require-
ments prevent further increase in the linear full-scale output range.
This is a z-axis rate-sensing device that is also called a yaw rate
sensor. It produces a positive going output voltage for clockwise
rotation about the axis normal to the package top, that is,
clockwise when looking down at the package lid.
RATE
RATE
AXIS
V
= 5V
CC
LONGITUDINAL
AXIS
4.75V
2.5V
The trade-offs associated with increasing the full-scale range are
potential increase in output null drift (as much as 2°/sec over
temperature) and introducing initial null bias errors that must
be calibrated.
RATE IN
0.25V
A1
LATERAL AXIS
GND
Figure 19. Rate Signal Increases with Clockwise Rotation
Rev. 0 | Page 11 of 16
ADIS16080
CONTROL REGISTER
The control register on the ADIS16080 is a 12-bit, write-only
register. Data is loaded from the DIN pin on the falling edge of
SCLK. The data is transferred on the DIN line at the same time
that the conversion result is read from the part. The data
transferred on the DIN line dictates the configuration for the
next conversion.
MSB denotes the first bit in the data stream. The DIN Bit
Stream bit map shows the analog input channel selection
options.
Table 5. Channel Selection
Analog Input Channel
ADD1
ADD0
Gyroscope
Temperature Sensor
AIN1 Input
0
0
1
1
0
1
0
1
This requires 16 serial clocks for every data transfer. Only the
information provided on the first 12 falling clock edges (after
CS
falling edge) is loaded to the control register.
AIN2 Input
DIN Bit Stream
MSB (11)
LSB (0)
CODING
WRITE
LOW
DONTC
DONTC
ADD1
ADD0
HIGH
HIGH
DONTC
DONTC
LOW
Table 6. Analog Input Channel Selection Options
Bit
Mnemonic
Comments
11
WRITE
The value written to this bit of the control register determines whether the following 11 bits are loaded to the
control register or not. If this bit is a 1, the following 11 bits are written to the control register. If it is a 0, the
remaining 11 bits are not loaded to the control register, and it remains unchanged.
10
9, 8
7, 6
LOW
DONTC
ADD1, ADD0
This bit should be low.
Don’t care.
These two address bits are loaded at the end of the present conversion sequence and select which analog input
channel is to be converted in the next serial transfer. The selected input channel is decoded as shown in Table 5.
The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next
channel to be converted is selected by the mux on the 14th SCLK falling edge.
5, 4
3, 2
1
HIGH
DONTC
LOW
These bits should be high.
Don’t care.
This bit should be low.
0
CODING
This bit selects the type of output coding used for the conversion result. If this bit is set to 0, the output coding for
the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next
conversion).
Rev. 0 | Page 12 of 16
ADIS16080
SERIAL INTERFACE
CS
going low clocks out the first leading zero to be read in by
the system microcontroller or DSP on the first falling edge of
SCLK. The first falling edge of SCLK will also clock out the
second leading zero to be read in by the microcontroller or DSP
on the second SCLK falling edge, and so on.
Figure 2 shows the detailed timing diagram for the serial
CS
interface to the ADIS16080. The chip select signal, , frames
the entire data transfer, because it must be kept in a Logic 0
state to communicate with the ADIS16080. The serial clock,
SCLK, provides the conversion clock and controls the transfer
of information to and from the ADIS16080 during each
conversion cycle. The data input, DIN, provides access to
critical control parameters in the control register; and the
output signal, DOUT, provides access to the ADIS16080
output data.
The remaining two address bits and 12 bits are then clocked out
by subsequent SCLK falling edges, beginning with the first
address bit, ADD1; thus, the second falling clock edge on the
serial clock has the second leading 0 provided and also clocks
out Address Bit ADD1. The final bit in the data transfer is valid
on the 16th falling edge, having been clocked out on the previous
(15th) falling edge.
The ADIS16080 offers an efficient data transfer function by
supporting simultaneous READ and WRITE cycles. A data
After the 16th falling edge of SCLK, the DOUT line goes back
CS
transfer cycle is started when the
transitions to a Logic 0
CS
into a three-state mode. If the rising edge of
occurs before
state. If DIN is in a Logic 1 state during the first falling edge of
the SCLK, then the next 11 SCLK cycles fill the control register
with the contents on the DIN pin. The appropriate bit defini-
tions for DIN can be found in the DIN Bit Stream bit map and
Table 6. If DIN is in a Logic 0 state during the first falling edge
of the SCLK, then the contents of the control register remain
unchanged. Because the control register is only 12 bits wide,
the contents on the DIN pin during the last four SCLK cycles
are ignored.
16 SCLKs have elapsed, the DOUT line goes back into three-
state mode and the control register is not updated. Otherwise,
DOUT returns to a three-state mode on the 16th SCLK falling
edge, as shown in Figure 2.
CS
For the analog inputs, the
signal initiates the data transfer
CS
and conversion process. The falling edge of
put the track and
hold into hold mode and takes the bus out of the three-state.
The analog input is sampled at this point. The conversion is also
initiated at this point and requires 16 SCLK cycles to complete.
During this same cycle, the digital output data is clocked out on
the DOUT pin. The 12 bits of data are preceded by two leading
0s and two channel address bits, ADD1 and ADD0, identifying
to which channel the result corresponds (see the Reading DOUT
Bit Stream bit map and Table 7).
Reading DOUT Bit Stream
SCLK1
SCLK16
LOW
LOW
ADD1
ADD0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Table 7. DOUT Bit Functions
SCLK
1, 2
Mnemonic
LOW
Comments
The outputs are low for SCLK1 and SCLK2.
3, 4
ADD1, ADD0
The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data.
See Table 5 for the coding of these address bits.
5
DB11
DB10 to DB1
DB0
Data Bit 11 (MSB).
Data Bit 10 to Data Bit 1.
Data Bit 0 (LSB).
6 to 15
16
Rev. 0 | Page 13 of 16
ADIS16080
CRITICAL ZONE
TO T
T
tP
SECOND-LEVEL ASSEMBLY
L
P
T
P
RAMP-UP
The ADIS16080 can be attached to the second-level assembly
board using Sn63 (or equivalent) or an RoHS-compliant solder.
Figure 21 and Table 8 provide acceptable solder reflow profiles
for each solder type. Note that these profiles may not be the
optimum profile for the user’s application. In no case shall the
260°C limit be exceeded. It is recommended that the user develop
a reflow profile based upon the specific application. In general,
keep in mind the lowest peak temperature and shortest dwell
time above the melt temperature of the solder results in less
shock and stress to the product. In addition, evaluating the
cooling rate and peak temperature can result in a more reliable
assembly.
T
L
tL
T
SMAX
T
SMIN
tS
RAMP-DOWN
PREHEAT
t
25°C TO PEAK
TIME
Figure 21. Recommended Solder Reflow Profiles
Table 8.
Condition
6.873
2×
Profile Feature
Average Ramp Rate (TL to TP)
Preheat
Sn63/Pb37
Pb-Free
0.5 BSC
16×
3°C/sec max
3°C/sec max
Minimum Temperature (TSMIN
Maximum Temperature (TSMAX
)
100°C
150°C
150°C
200°C
0.67 BSC
12×
)
Time (TSMIN to TSMAX) (tS)
60 sec to
120 sec
60 sec to
150 sec
1 BSC
16×
TSMAX to TL
Ramp-Up Rate
3°C/sec
3°C/sec
0.9315
4×
Time Maintained Above
Liquidous (TL)
Liquidous Temperature (TL)
Time (tL)
183°C
60 sec to
150 sec
217°C
60 sec to
150 sec
0.9315
4×
Peak Temperature (TP)
240°C +
260°C +
0°C/–5°C
0°C/–5°C
Time Within 5°C of Actual Peak
Temperature (tP)
10 sec to
30 sec
20 sec to
40 sec
Figure 20. Second Level Assembly Pad Layout
Ramp-Down Rate
6°C/sec max
6 min max
6°C/sec max
8 min max
Time 25°C to Peak Temperature
Rev. 0 | Page 14 of 16
ADIS16080
OUTLINE DIMENSIONS
8.33
8.20 SQ
8.07
1.1585
BSC
PIN 1
INDICATOR
13
16
0.797
BSC
12
1
PIN 1
INDICATOR
0.873
BSC
4
9
8
5
TOP VIEW
7.00 TYP
BOTTOM VIEW
0.373
BSC
0.227
BSC
5.20
MAX
SIDE VIEW
Figure 22. 16-Terminal Land Grid Array [LGA]
(CC-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADIS16080ACCZ1
ADIS16080/PCBZ1
Temperature Range
−40°C to +85°C
Package Description
Package Option
CC-16-1
16-Terminal Land Grid Array (LGA)
Evaluation Board
1 Z = Pb-free part.
Rev. 0 | Page 15 of 16
ADIS16080
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06045-0-7/06(0)
Rev. 0 | Page 16 of 16
相关型号：
ADIS16100ACC
IC SPECIALTY ANALOG CIRCUIT, PBGA16, 8.20 X 8.20 MM, 5.20 MM HEIGHT, LGA-16, Analog IC:Other
ADI
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