ADIS16100 [ADI]
+-300∑/sec Yaw Rate Gyro with SPI Interface; + -300Σ /秒偏航角速度陀螺仪，SPI接口
| 型号： | ADIS16100 |
| 厂家： | 
ADI |
| 描述： | +-300∑/sec Yaw Rate Gyro with SPI Interface |
| 文件： | 总16页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
± ±330°/sec YacꢀYꢁscGyroc
aiꢁhcSPIcInꢁsrfYes
ADIS16133
cc
FEATURES
GENERAL DESCRIPTION
Complete angular rate gyroscope
Z-axis (yaw rate) response
SPI® digital output interface
High vibration rejection over wide frequency
2000 g powered shock survivability
Externally controlled self test
Internal temperature sensor output
Dual auxiliary 12-bit ADC inputs
Absolute rate output for precision applications
5 V single-supply operation
The ADIS16100 is a complete angular rate sensor (gyroscope)
that uses the Analog Devices surface-micromachining process
to make a functionally complete angular rate sensor with an
integrated serial peripheral interface (SPI).
The digital data available at the SPI port is proportional to the
angular rate about the axis normal to the top surface of the
package (see Figure 19). A single external resistor can be used to
increase the measurement range. An external capacitor can be
used to lower the bandwidth.
8.2 mm × 8.2 mm × 5.2 mm package
Access to an internal temperature sensor measurement is
provided, through the SPI, for compensation techniques.
Two pins are available to the user to input analog signals for
digitization. An additional output pin provides a precision
voltage reference. Two digital self-test inputs electro-
mechanically excite the sensor to test operation of the
sensor and the signal conditioning circuits.
APPLICATIONS
Platform stabilization
Image stabilization
Guidance and control
Inertial measurement units
The ADIS16100 is available in an 8.2 mm × 8.2 mm × 5.2 mm,
16-terminal, peripheral land grid array (LGA) package.
FUNCTIONAL BLOCK DIAGRAM
C
OUT
FILT
RATE
ADIS16100
±300°/s
GYROSCOPE
SCLK
DIN
4-CHANNEL
SPI
MUX/ADC
CS
DOUT
TEMP
SENSOR
AIN2
AIN1
V
REF
REF
COM
V
V
DRIVE
+3V TO +5V
CC
+5V
ST1
ST2
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADIS16133c
c
TABLEcOFcCONTENTSc
Features .............................................................................................. 1
Supply and Common Considerations ..................................... 11
Increasing Measurement Range ............................................... 11
Setting Bandwidth...................................................................... 11
Self-Test Function ...................................................................... 11
Continuous Self Test .................................................................. 11
Control Register ......................................................................... 12
Serial Interface............................................................................ 13
Rate Sensitive Axis ..................................................................... 13
Second-Level Assembly............................................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram ........................................................................... 4
Timing Specifications............................... ....................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
REVISION HISTORY
5/06—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 4
Changes to Setting Bandwidth Section........................................ 11
Changes to Table 9 and Table 10................................................... 13
1/06—Revision 0: Initial Version
Rev. A | Page 2 of 16
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ADIS16133
SPECIFICATIONSc
TA = 25°C, VCC = VDR = 5 V, angular rate = 0°/sec, COUT = 0 μF, 1 g, unless otherwise noted.
Table 1.
Parameter
Conditions
Min1
Typ
Max1
Unit
SENSITIVITY
Clockwise rotation is positive output
Full-scale range over specifications range
@ 25°C
VCC = VDRIVE = 4.75 V to 5.25 V
Best fit straight line
Dynamic Range2
±3ꢀꢀ
3.68
°/sec
LSB/°/sec
%
Initial
4.1
±1ꢀ
ꢀ.15
4.52
Change Over Temperature3
Nonlinearity
% of FS
NULL
Initial Null
1876
2ꢀ48
±2ꢀ5
75
ꢀ.82
4.1
22ꢀꢀ
LSB
LSB
ms
LSB/g
LSB/V
LSB rms
LSB rms/√Hz
Change Over Temperature3
VCC = VDR = 4.75 V to 5.25 V
Power on to ±±°/sec of final
Any axis
VCC = VDRIVE = 4.75 V to 5.25 V
ꢀ.1 Hz to 4ꢀ Hz
Turn-On Time
Linear Acceleration Effect
Voltage Sensitivity
NOISE PERFORMANCE
Rate Noise Density
FREQUENCY RESPONSE
3 dB Bandwidth (User-Selectable)4
Sensor Resonant Frequency
SELF-TEST INPUTS
ST1 RATEOUT Response5
ST2 RATEOUT Response5
Logic 1 Input Voltage
Logic ꢀ Input Voltage
Input Impedance
TEMPERATURE SENSOR
Reading at 298 K
3.25
ꢀ.43
f = 1ꢀꢀ Hz
COUT = ꢀ μF
4ꢀ
14
Hz
kHz
ST1 pin from Logic ꢀ to Logic 1
ST2 pin from Logic ꢀ to Logic 1
Standard high logic level definition
Standard low logic level definition
To common
−121
+121
3.3
−221
+221
−376
+376
LSB
LSB
V
V
kΩ
1.7
5ꢀ
2ꢀ48
6.88
LSB
LSB/K
Scale Factor
Proportional to absolute temperature
2.5 V REFERENCE
Voltage Value
Load Drive to Ground
Load Regulation
Power Supply Rejection
Temperature Drift
LOGIC INPUTS
2.45
2.5
1ꢀꢀ
5.ꢀ
1.ꢀ
5.ꢀ
2.55
V
μA
mV/mA
mV/V
mV
Source
ꢀ μA < IOUT < 1ꢀꢀ μA
VCC = VDRIVE = 4.75 V to 5.25 V
Delta from 25°C
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
ANALOG INPUTS6
Resolution
Integral Nonlinearity6
Differential Nonlinearity
Offset Error
ꢀ.7 × VDRIVE
−1
V
V
μA
pF
ꢀ.3 × VDRIVE
+1
Typically 1ꢀ nA
1ꢀ
12
All at TA = −4ꢀ°C to +85°C
Bits
LSB
LSB
LSB
%FSR
V
−2
−2
−8
−2
ꢀ
+2
+2
+8
+2
VREF × 2
+1
Gain Error
Input Voltage Range
Leakage Current
−1
μA
Input Capacitance
Full Power Bandwidth
2ꢀ
8
pF
MHz
Rev. A | Page 3 of 16
ADIS16133c
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Parameter
Conditions
Min1
Typ
Max1
Unit
DIGITAL OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
CONVERSION RATE
Conversion Time
Throughput Rate
POWER SUPPLY
ISOURCE = 2ꢀꢀ μA
ISINK = 2ꢀꢀ μA
VDRIVE − ꢀ.2
V
V
ꢀ.4
16 SCLK cycles with SCLK at 2ꢀ MHz
All at TA = −4ꢀ°C to +85°C
8ꢀꢀ
1
ns
MSPS
VCC
VDRIVE
4.75
2.7
5
5.25
5.25
9.ꢀ
V
V
mA
μA
mW
VCC Quiescent Supply Current
VDRIVE Quiescent Supply Current
Power Dissipation
VCC @ 5 V, fSCLK = 5ꢀ kSPS
VDRIVE @ 5 V, fSCLK = 5ꢀ kSPS
VCC and VDRIVE @ 5 V, fSCLK = 5ꢀ kSPS
7.ꢀ
7ꢀ
4ꢀ
5ꢀꢀ
1 All minimum and maximum specifications are guaranteed. Typical specifications are neither tested nor guaranteed.
2 Dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 5 V
supplies.
3 Defined as the output change from ambient to maximum temperature or ambient to minimum temperature.
4 Frequency at which the response is 3 dB down from dc response. Bandwidth = 1/(2 × π × 18ꢀ kΩ × (22 nF + COUT)). For COUT = ꢀ, bandwidth = 4ꢀ Hz. For COUT = 1 μF,
bandwidth = ꢀ.87 Hz.
5 Self-test response varies with temperature.
6 For VIN < VCC
.
TIMING DIAGRAM
CS
tCONVERT
6
t2
t6
B
1
2
3
4
5
11
12
13
14
t5
15
16
t11
SCLK
t7
DB10
t3
t4
t8
DB0
tQUIET
ZERO
t9
ADD1
ADD0
DB11
DB4
DB3
DB2
DB1
DOUT
THREE-STATE
THREE-STATE
2 IDENTIFICATION
BITS
ZERO
t10
ADD0
DIN
WRITE
LOW
DONTC DONTC
ADD1
CODING DONTC DONTC
DONTC
DONTC
Figure 2. Gyroscope Serial Interface Timing Diagram
The DIN bit functions are outlined in the following table (see the Control Register section for additional information).
Table 2. DIN Bit Functions
MSB (11)
LSB (0)
CODING
WRITE
LOW
DONTC
DONTC
ADD1
ADDꢀ
HIGH
HIGH
DONTC
DONTC
LOW
Rev. A | Page 4 of 16
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ADIS16133
TIMINGcSPECIFICATIONSc
TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1
Table 3.
Parameter
VCC = VDR = 5 Unit
Description
2
fSCLK
1ꢀ
kHz min
2ꢀ
MHz max
tCONVERT
tQUIET
t2
16 × tSCLK
5ꢀ
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
ꢁs max
Minimum quiet time required between CS rising edge and start of next conversion
CS to SCLK setup time
1ꢀ
3
t3
3ꢀ
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
3
t4
4ꢀ
ꢀ.4 × tSCLK
ꢀ.4 × tSCLK
1ꢀ
15/35
1ꢀ
5
2ꢀ
1
t5
t6
t7
4
t8
t9
t1ꢀ
t11
t12
Power-up time from full power-down/auto shutdown modes
1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (1ꢀ% to 9ꢀ% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans
from 4.75 V to 5.25 V.
2 Mark/Space ratio for the SCLK input is 4ꢀ/6ꢀ to 6ꢀ/4ꢀ.
3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross ꢀ.4 V or ꢀ.7 V × VDRIVE
.
4 t8 is derived from the measured time taken by the data outputs to change ꢀ.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 5ꢀ pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 3. Load Circuit for Digital Output Timing Specifications
Rev. A | Page 5 of 16
ADIS16133c
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ABSOLUTEcMAXIMUMcꢀATINGSc
Table 4.
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Acceleration (Any Axis, Unpowered, ꢀ.5 ms)
Acceleration (Any Axis, Powered, ꢀ.5 ms)
+VCC to COM
2ꢀꢀꢀ g
2ꢀꢀꢀ g
−ꢀ.3 V to +6.ꢀ V
−ꢀ.3 V to VCC + ꢀ.3 V
−ꢀ.3 V to VCC + ꢀ.3 V
−ꢀ.3V to +7.ꢀV
−ꢀ.3V to VCC + ꢀ.3 V
−ꢀ.3 V to VCC + ꢀ.3 V
−4ꢀ°C to +85°C
−65°C to +15ꢀ°C
+VDRIVE to COM
Analog Input Voltage to COM
Digital Input Voltage to COM
Digital Output Voltage to COM
STx Input Voltage to COM
Operating Temperature Range
Storage Temperature Range
Drops onto hard surfaces can cause shocks of greater than
2000 g and exceed the absolute maximum rating of the device.
Care should be exercised in handling to avoid damage.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4ꢀꢀꢀ V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 16
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ADIS16133
PINcCONFIGUꢀATIONcANDcFUNCTIONcDESCꢀIPTIONSc
5
6
7
8
4
3
2
1
9
NC
DOUT
SCLK
DIN
AIN2
COM
ADIS16100
10
11
12
BOTTOM
VIEW
(Not to Scale)
V
REF
ST2
14
13
16
15
NC = NO CONNECT
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
DIN
I
Data In. Data to be written to the control register is provided on this input and is clocked in on the
falling edge of the SCLK.
2
3
SCLK
I
Serial Clock. SCLK provides the serial clock for accessing data from the part and writing serial data
to the control registers. Also used as a clock source for the ADIS161ꢀꢀ conversion process.
Data Out. The data on this pin represents data being read from the control registers and is clocked
on the falling edge of the SCLK.
DOUT
O
4
5
6
7
NC
No Connect.
RATE
FILT
VDRIVE
O
I
S
Buffered analog output representing the angular rate signal.
External capacitor connection to control bandwidth.
Power to SPI. The voltage supplied to this pin determines the voltage at which the serial interface
operates.
8
9
AIN1
AIN2
I
I
External Analog Input Channel 1. Single-ended analog input multiplexed into the on-chip track-
and-hold according to the setting of the ADDꢀ and ADD1 address bits.
External Analog Input Channel 2. Single-ended analog input multiplexed into the on-chip track-
and-hold according to the setting of the ADDꢀ and ADD1 address bits.
1ꢀ
11
12
13
14
15
16
COM
VREF
ST2
ST1
VCC
S
O
I
I
S
Common. Reference point for all circuitry in the ADIS161ꢀꢀ.
Precision 2.5 V Reference.
Self Test Input 2.
Self Test Input 1.
Analog Power.
NC
CS
No Connect.
I
Chip Select. Active low. This input frames the serial data transfer and initiates the conversion
process.
1 I = Input; O = Output; S = Power supply.
Rev. A | Page 7 of 16
ADIS16133c
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T PICALcPEꢀFOꢀMANCEcCHAꢀACTEꢀISTICSc
30
60
50
40
30
20
10
0
25
20
15
10
5
0
1845 1895 1945 1995 2045 2095 2145 2195 2245
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.0
NULL (LSB)
SUPPLY CURRENT (mA)
Figure 5. Initial Null Histogram
Figure 8. Supply Current Histogram
2250
2200
2150
80
70
60
50
40
30
20
10
0
2100
+85°C
+25°C
2050
2000
1950
1900
1850
–40°C
4.7
4.8
4.9
5.0
(V)
5.1
5.2
5.3
–371 –346 –321 –296 –271 –246 –221 –196 –171 –146 –121
ST1 (LSB)
V
CC
Figure 9. Self Test 1 Histogram
Figure 6. Null Level vs. Supply Voltage
80
70
60
50
40
30
20
10
0
2040
2030
2020
2010
2000
1990
1980
1970
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, V = 5V
CC
30 PART AVERAGE, V = 5.25V
CC
121 146 171 196 221 246 271 296 321 346 371
ST2 (LSB)
–50
–20
10
40
70
100
TEMPERATURE (°C)
Figure 10. Self Test 2 Histogram
Figure 7. Null Level vs. Temperature
Rev. A | Page 8 of 16
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ADIS16133
0
–50
250
240
230
220
210
200
190
180
170
160
150
–100
–150
–200
–250
–300
–350
–400
–40°C
30 PART AVERAGE, V = 4.75V
CC
+25°C
30 PART AVERAGE, V = 5V
CC
+85°C
30 PART AVERAGE, V = 5.25V
CC
4.7
4.8
4.9
5.0
(V)
5.1
5.2
5.3
5.3
100
–50
–20
10
40
70
100
100
100
V
TEMPERATURE (°C)
CC
Figure 14. Self Test 2 vs. Temperature
Figure 11. Self Test 1 vs. Supply Voltage
3
2
400
350
300
250
200
150
100
50
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, V = 5V
CC
30 PART AVERAGE, V = 5.25V
CC
+85°C
+25°C
1
0
–40°C
–1
–2
–3
0
4.7
–50
–20
10
40
70
4.8
4.9
5.0
(V)
5.1
5.2
TEMPERATURE (°C)
V
CC
Figure 15. ADC Offset vs. Temperature and Supply Voltage
Figure 12. Self Test 2 vs. Supply Voltage
3
–150
–160
–170
–180
–190
–200
–210
–220
–230
–240
–250
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, V = 4.75V
CC
30 PART AVERAGE, V = 5V
CC
30 PART AVERAGE, V = 5V
CC
30 PART AVERAGE, V = 5.25V
CC
30 PART AVERAGE, V = 5.25V
CC
2
1
0
–1
–2
–3
–50
–20
10
40
70
–50
–20
10
40
70
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. ADC Gain Error vs. Temperature (Excluding VREF
)
Figure 13. Self Test 1 vs. Temperature
Rev. A | Page 9 of 16
ADIS16133c
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2060
2055
2050
2045
2040
2.500
2.499
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
+25°C
+85°C
–40°C
0
1000 2000 3000 4000 5000 6000 7000 8000
4.7
4.8
4.9
5.0
(V)
5.1
5.2
5.3
V
000001111111011X
000001111111100X
1
0
5
9
339
1307
4132
1996
387
12
3
CC
Figure 17. VREF vs. Supply Voltage
000001111111101X
000001111111110X
000001111111111X
000010000000000X
000010000000001X
000010000000010X
0000100000000 11X
000010000000100X
000010000000101X
000010000000 110X
1
SAMPLES = 8192, SPREAD = 23, STD DEV = 1.695,
MEAN = 2050.682
Figure 18. Noise Histogram
Rev. A | Page 1ꢀ of 16
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ADIS16133
THEOꢀ cOFcOPEꢀATIONc
The ADIS16100 operates on the principle of a resonator gyro.
Two polysilicon sensing structures each contain a dither frame,
which is electrostatically driven to resonance. This produces the
necessary velocity element to produce a Coriolis force during
angular rate. At two of the outer extremes of each frame, orthogo-
nal to the dither motion, are movable fingers that are placed
between fixed pickoff fingers to form a capacitive pickoff structure
that senses Coriolis motion. The resulting signal is fed to a series
of gain and demodulation stages that produce the electrical rate
signal output. The rate signal is then converted to a digital
representation of the output on the SPI pins. The dual-sensor
design rejects external g-forces and vibration. Fabricating the
sensor with the signal conditioning electronics preserves signal
integrity in noisy environments.
The trade-off associated with increasing the full-scale range are
potential increase in output null drift (as much as 2°/sec over
temperature) and introducing initial null bias errors that must
be calibrated.
SETTING BANDWIDTH
The ADIS16100 provides the ability to reduce the bandwidth.
This important feature enables a simple method for achieving
optimal bandwidth/noise trade-offs. An external capacitor can
be used in combination with an on-chip resistor to create a low-
pass filter to limit the bandwidth of the ADIS16100’s rate response.
The −3 dB frequency is defined as
fOUT =1/
2×π×ROUT
×
COUT + 0.022 μF
The electrostatic resonator requires 14 V to 16 V for operation.
Because only 5 V is typically available in most applications, a
charge pump is included on-chip.
where ROUT represents an internal impedance that was trimmed
during manufacturing to 180 kΩ 1ꢀ.
Any external resistor applied between the RATE pin and the
FILT pin results in
After the demodulation stage, there is a single-pole, low-pass
filter included on-chip that is used to limit high frequency
artifacts before final amplification. A second single-pole, low-
pass filter is set up via the bandwidth limit capacitor, COUT. This
pole acts as the primary filter within the system (see the Increasing
Measurement Range section).
ROUT
=
180 kꢁ× REXT
/
180 kꢁ + REXT
With COUT = 0 μF, a default −3 dB frequency response of 40 Hz
is obtained, based upon an internal 0.022 μF capacitor imple-
mented on-chip.
SUPPLY AND COMMON CONSIDERATIONS
SELF-TEST FUNCTION
Power supply noise and transient behaviors can influence the
accuracy and stability of any sensor-based measurement system.
When considering the power supply for the ADIS16100, it is
important to understand that the ADIS16100 provides 0.2 μF of
decoupling capacitance on the VCC pin. Depending on the level
of noise present in the system power supply, the ADIS16100
may not require any additional decoupling capacitance for this
supply. The analog supply, VCC, and the digital drive supply,
The ADIS16100 includes a self-test feature that actuates each of
the sensing structures and associated electronics in the same
manner, as if subjected to angular rate. It provides a simple
method for exercising the mechanical structure of the sensor,
along with the entire signal processing circuit. It is activated by
standard logic high levels applied to Input ST1, Input ST2, or
both. ST1 causes a change in the digital output equivalent to
typically −221 LSB, and ST2 causes an opposite +221 LSB
change. The self-test response follows the viscosity temperature
dependence of the package atmosphere, approximately
0.25ꢀ/°C.
VDRIVE, are segmented to allow multiple logic levels to be used in
receiving the digital output data. VDRIVE is intended for the
down-stream logic power supply and supports standard 3.3 V
and 5 V logic families. The VDRIVE supply does not have internal
decoupling capacitors.
Activating both ST1 and ST2 simultaneously is not damaging.
Because ST1 and ST2 are not necessarily closely matched,
actuating both simultaneously can result in an apparent null
bias shift.
INCREASING MEASUREMENT RANGE
The full-scale measurement range of the ADIS16100 is increased
by placing an external resistor between the RATE pin and the
FILT pin. This external resistor would be in parallel with an
internal 180 kΩ, 1ꢀ resistor. For example, a 330 kΩ external
resistor gives ~50ꢀ increase in the full-scale range. This is
effective for up to a 4× increase in the full-scale range
(minimum value of the parallel resistor allowed is 45 kΩ). The
internal circuitry headroom requirements prevent further
increase in the linear full-scale output range.
CONTINUOUS SELF TEST
As an additional failure detection measure, power-on self test
can be performed. However, some applications warrant a
continuous self test-while-sensing rate.
Rev. A | Page 11 of 16
ADIS16133c
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CONTROL REGISTER
The control register on the ADIS16100 is a 12-bit, write-only
register. Data is loaded from the DIN pin on the falling edge of
SCLK. The data is transferred on the DIN line at the same time
that the conversion result is read from the part. The data
transferred on the DIN line dictates the configuration for the
next conversion. This requires 16 serial clocks for every data
transfer. Only the information provided on the first 12 falling
Table 6. Channel Selection
ADD1
ADD0
Analog Input Channel
ꢀ
ꢀ
1
1
ꢀ
1
ꢀ
1
Gyroscope
Temperature sensor
AIN1 input
AIN2 input
CS
clock edges (after
register.
falling edge) is loaded to the control
MSB denotes the first bit in the data stream. Table 8 shows the
analog input channel selection options.
Table 7. The DIN Bit Stream
MSB (11)
LSB (0)
CODING
WRITE
LOW
DONTC
DONTC
ADD1
ADDꢀ
HIGH
HIGH
DONTC
DONTC
LOW
Table 8. Analog Input Channel Selection Options
Bit
Mnemonic
Comment
11
WRITE
The value written to this bit of the control register determines whether the following 11 bits are loaded to the
control register or not. If this bit is a 1, the following 11 bits are written to the control register. If it is a ꢀ, the
remaining 11 bits are not loaded to the control register, and it remains unchanged.
1ꢀ
9, 8
7, 6
LOW
DONTC
ADD1, ADDꢀ
This bit should be held low.
Don’t care.
These two address bits are loaded at the end of the present conversion sequence and select which analog input
channel is to be converted in the next serial transfer. The selected input channel is decoded as shown in Table 6.
The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next
channel to be converted is selected by the mux on the 14th SCLK falling edge.
5, 4
HIGH
These pins should be held high.
3, 2
1
DONTC
LOW
Don’t care.
This bit should be held low.
ꢀ
CODING
This bit selects the type of output coding used for the conversion result. If this bit is set to ꢀ, the output coding for
the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next
conversion).
Rev. A | Page 12 of 16
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ADIS16133
During this same cycle, the digital output data is clocked out on
the DOUT pin, with the bit transitions occurring shortly after
the SCLK falling edges. The DOUT bit sequence is character-
ized in Table 9 and Table 10. On the 16th falling edge of SCLK, the
DOUT line goes back into a three-state mode. If the rising edge of
SERIAL INTERFACE
Figure 2 shows the detailed timing diagram for the serial
interface to the ADIS16100. The chip select signal, , frames
CS
the entire data transfer, because it must be kept in a Logic 0
state to communicate with the ADIS16100. The serial clock,
SCLK, provides the conversion clock and controls the transfer
of information to and from the ADIS16100 during each conver-
sion cycle. The data input, DIN, provides access to critical
control parameters in the control register, and the output signal,
DOUT, provides access to the output data of the ADIS16100.
CS
occurs before 16 SCLKs have elapsed, the DOUT line goes
back into three-state mode and the control register is not updated.
Otherwise, DOUT returns to a three-state mode on the 16th
SCLK falling edge, as shown in Figure 2.
RATE SENSITIVE AXIS
The ADIS16100 offers an efficient data transfer function by
supporting simultaneous READ and WRITE cycles. A data
This is a z-axis rate-sensing device that is also called a yaw rate
sensing device. It produces a positive going output voltage for
clockwise rotation about the axis normal to the package top,
that is, clockwise when looking down at the package lid.
CS
transfer cycle is started when the
transitions to a Logic 0
state. If DIN is in Logic 1 state during the first falling edge of
the SCLK, then the next 11 SCLK cycles fill the control register
with the contents on the DIN pin. The appropriate bit definitions
for DIN can be found in Table 7 and Table 8. If the DIN is in
a Logic 0 state during the first falling edge of the SCLK, then
contents of the control register remain unchanged. Because the
control register is only 12-bits wide, the contents on the DIN
pin during the last four SCLK cycles are ignored.
RATE
RATE
AXIS
V
= 5V
CC
LONGITUDINAL
AXIS
4.75V
2.5V
RATE IN
0.25V
A1
LATERAL AXIS
GND
Figure 19. Rate Signal Increases with Clockwise Rotation
Table 9. DOUT Bit Stream
SCLK1
SCLK16
LOW
LOW
ADD1
ADDꢀ
DB11
DB1ꢀ
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBꢀ
Table 10. DOUT Bit Functions
SCLK
Mnemonic
Comment
1, 2
LOW
The outputs are low for SCLK1 and SCLK2.
3, 4
ADD1, ADDꢀ
The address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data.
See Table 6 for the coding of these address bits.
5
DB11
DB1ꢀ to DB1
DBꢀ
Data Bit 11 (MSB).
Data Bit 1ꢀ to Data Bit 1.
Data Bit ꢀ (LSB).
6 to 15
16
Rev. A | Page 13 of 16
ADIS16133c
c
SECOND-LEVEL ASSEMBLY
CRITICAL ZONE
TO T
The recommended pad geometries for the ADIS16100 are
displayed in Figure 20. The ADIS16100 can be attached to
printed circuit boards using Sn63 or an equivalent solder.
Figure 21 and Table 11 provide recommended solder reflow
profiles for each solder type. Note: These profiles may not be
the optimum profile for the user’s application. In no case should
the temperature exceed 260°C. It is recommended that the user
develop a reflow profile based upon the specific application.
In general, keep in mind that the lowest peak temperature and
shortest dwell time above the melt temperature of the solder
results in less shock and stress to the product. In addition,
evaluating the cooling rate and peak temperature can result in
a more reliable assembly.
T
tP
L
P
T
P
RAMP-UP
T
L
tL
T
SMAX
T
SMIN
tS
RAMP-DOWN
PREHEAT
t
25°C TO PEAK
TIME
Figure 21. Recommended Solder Reflow Profiles
Table 11. Solder Profile Characteristics
Profile Feature
6.873
2×
Sn63/Pb37
Average Ramp Rate (TL to TP)
Preheat
3°C/sec max
0.5 BSC
16×
Minimum Temperature (TSMIN
Maximum Temperature (TSMAX
Time (TSMIN to TSMAX) (tS)
TSMAX to TL
Ramp-Up Rate
Time Maintained Above Liquidous (TL)
Liquidous Temperature (TL)
Time (tL)
)
)
1ꢀꢀ°C
15ꢀ°C
6ꢀ sec to 12ꢀ sec
0.67 BSC
12×
3°C/sec
1 BSC
16×
183°C
0.9315
4×
6ꢀ sec to 15ꢀ sec
24ꢀ°C + ꢀ°C/–5°C
1ꢀ sec to 3ꢀ sec
Peak Temperature (TP)
Time Within 5°C of Actual Peak
Temperature (tp)
Ramp-Down Rate
Time 25°C to Peak Temperature
6°C/sec max
6 min max
0.9315
4×
Figure 20. Second Level Assembly Pad Layout
Rev. A | Page 14 of 16
ADIS16100
OUTLINE DIMENSIONS
8.33
8.20 SQ
8.07
1.1585
BSC
PIN 1
INDICATOR
13
16
0.797
BSC
12
1
PIN 1
INDICATOR
0.873
BSC
4
9
8
5
TOP VIEW
7.00 TYP
BOTTOM VIEW
0.373
BSC
0.227
BSC
5.20
MAX
SIDE VIEW
Figure 22. 16-Terminal Land Grid Array [LGA]
(CC-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADIS16100ACC
ADIS16100/PCB
Temperature Range
−40°C to +85°C
Package Description
Package Option
CC-16-1
16-Terminal Land Grid Array (LGA)
Evaluation Board
Rev. A | Page 15 of 16
ADIS16133c
NOTESc
c
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05461-0-5/06(A)
Rev. A | Page 16 of 16
相关型号：
ADIS16100ACC
IC SPECIALTY ANALOG CIRCUIT, PBGA16, 8.20 X 8.20 MM, 5.20 MM HEIGHT, LGA-16, Analog IC:Other
ADI
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