ADG852BCPZ-REEL7 [ADI]
0.8 Ω CMOS, 1.8V to 5.5V, SPDT/2:1 Mux Mini LFCSP;
| 型号： | ADG852BCPZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 0.8 Ω CMOS, 1.8V to 5.5V, SPDT/2:1 Mux Mini LFCSP 光电二极管 输出元件 |
| 文件： | 总16页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.8 Ω CMOS, 1.8 V to 5.5 V,
SPDT/2:1 Mux Mini LFCSP
Data Sheet
ADG852
FEATURES
FUNCTIONAL BLOCK DIAGRAM
0.8 Ω typical on resistance
Less than 1 Ω maximum on resistance at 85°C
ADG852
S1
1.8 V to 5.5 V single supply
D
High current carrying capability: 300 mA continuous
Rail-to-rail switching operation
S2
Fast-switching times: <17 ns
IN
Typical power consumption: <0.1 µW
1.30 mm × 1.60 mm, 10-lead mini LFCSP
NOTES
1. SWITCHES SHOWN
FOR A LOGIC 1 INPUT.
APPLICATIONS
Cellular phones
PDAs
Figure 1.
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. <1 Ω over full temperature range of −40°C to +85°C.
2. Single 1.8 V to 5.5 V operation.
The ADG852 is a low voltage CMOS single-pole, double-throw
(SPDT) switch. This device offers ultralow on resistance of less
than 1 Ω over the full temperature range. The ADG852 is fully
specified for 5.5 V and 3.3 V supply operation.
3. Compatible with 1.8 V CMOS logic.
4. High current handling capability (300 mA continuous
current per channel).
Each switch conducts equally well in both directions when on,
and has an input signal range that extends to the supplies. The
ADG852 exhibits break-before-make switching action.
5. Low THD + N: 0.08% typical.
6. 1.30 mm × 1.60 mm, 10-lead mini LFCSP.
The ADG852 is available in a 1.30 mm × 1.60 mm 10-lead
mini L F C S P.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that mayresult from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
ADG852
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Pin Configuration and Function Description ...............................6
Typical Performance Characteristics ..............................................7
Test Circuits..................................................................................... 10
Terminology.................................................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
5/12—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 13
10/08—Rev. 0 to Rev. A
Change to Title.................................................................................. 1
Changes to Features Section............................................................ 1
Changes to Product Highlights Section......................................... 1
8/08—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADG852
SPECIFICATIONS
VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
+25°C −40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
1
V
0.8
0.85
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 16
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA
On Resistance Match Between Channels, ∆RON 0.02
0.04
On Resistance Flatness, RFLAT (ON)
0.17
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA
0.23
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
VDD = 5.5 V
10
30
pA typ
pA typ
VS = 0.6 V/4.2 V, VD = 4.2 V/0.6 V; see Figure 17
VS = VD = 0.6 V or 4.2 V; see Figure 18
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.002
2.5
µA typ
µA max
pF typ
VIN = VGND or VDD
0.05
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
tON
17
23
6
8.5
14
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
%
RL = 50 Ω, CL = 35 pF
VS = 3 V/0 V; see Figure 19
RL = 50 Ω, CL = 35 pF
VS = 3 V; see Figure 19
28
9.2
8
tOFF
Break-Before-Make Time Delay, tBBM
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 20
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 23
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion, THD + N
Insertion Loss
−3 dB Bandwidth
CS (Off)
CD, CS (On)
30
−75
−73
0.08
−0.6
100
19.5
50
dB typ
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 23
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
0.002
µA typ
1.0
µA max
1 Guaranteed by design, not subject to production test.
Rev. B | Page 3 of 16
ADG852
Data Sheet
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
+25°C −40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
1.7
V
1.3
1.5
0.03
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VDD = 2.7 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 16
VDD = 2.7 V, VS = 0.6 V, IDS = 100 mA
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
0.05
0.48
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA
0.66
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
VDD = 3.6 V
10
30
pA typ
pA typ
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 17
VS = VD = 0.6 V or 3.3 V; see Figure 18
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
1.35
0.7
V min
V max
IINL or IINH
0.002
4
µA typ
µA max
pF typ
VIN = VGND or VDD
0.05
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
tON
25
37
7
7.4
22
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
%
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/0 V; see Figure 19
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1 V; see Figure 20
VS = 1.5 V, RS = 0 V, CL = 1 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 23
43
8
tOFF
Break-Before-Make Time Delay, tBBM
13
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion, THD
Insertion Loss
23
−75
−73
0.15
−0.07
100
20
dB typ
–3 dB Bandwidth
CS (Off)
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 23
pF typ
CD, CS (On)
52
pF typ
POWER REQUIREMENTS
IDD
VDD = 3.6 V
Digital inputs = 0 V or 3.6 V
0.002
µA typ
1.0
µA max
1 Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 16
Data Sheet
ADG852
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to GND
Analog Inputs1
Digital Inputs1
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V or 10 mA,
whichever occurs first
Only one absolute maximum rating can be applied at any
one time.
Peak Current, S or D Pins
500 mA (pulsed at 1 ms,
10% duty cycle max)
Continuous Current, S or D Pins 300 mA
Operating Temperature Range −40°C to +85°C
ESD CAUTION
Storage Temperature Range
Junction Temperature
Mini LFCSP
−65°C to +150°C
150°C
θJA Thermal Impedance,
3-Layer Board
131.6°C/W
Reflow Soldering, Pb-Free
Peak Temperature
260(+0/−5)°C
Time at Peak Temperature
10 sec to 40 sec
1 Overvoltages at the IN, S, or D pins are clamped by internal diodes. Current
should be limited to the maximum ratings given.
Rev. B | Page 5 of 16
ADG852
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTION
ADG852
8
7
NC
NC
D
2
3
S2
TOP VIEW
(Not to scale)
NC = NO CONNECT
Figure 2. Pin Configurations
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
S1
D
S2
IN
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Logic Control Input.
5, 6
7, 8, 9
10
VDD
N/C
GND
Most Positive Power Supply Potential.
No Connect.
Ground (0 V) Reference.
Table 5. ADG852 Truth Table
Logic
Switch 1
Off
On
Switch 2
0
1
On
Off
Rev. B | Page 6 of 16
Data Sheet
ADG852
TYPICAL PERFORMANCE CHARACTERISTICS
0.9
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 3.3V
T
= 25°C
DD
A
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= +85°C
= +25°C
A
T
A
T
= –40°C
A
V
V
V
V
= 4.2V
= 4.5V
= 5.0V
= 5.5V
DD
DD
DD
DD
0
1
3
4
5
6
0
0.5
1.0
1.5
V , V (V)
D
2.0
2.5
3.0
2
V
, V (V)
D
S
S
Figure 3. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V
Figure 6. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.1
V
= 5V
T
= 25°C
DD
A
0.9
0.7
I
I
I
I
I
(ON) ++
(OFF) +–
(ON) – –
(OFF) –+
D,
S
I
D,
D,
D,
S
I
S
I
0.5
S
V
V
V
V
= 2.7V
= 3.0V
= 3.3V
= 3.6V
DD
DD
DD
DD
0.3
0.1
–0.1
0
0.5
1.0
1.5
2.0
, V (V)
2.5
3.0
3.5
4.0
10
20
30
40
50
60
70
80
V
TEMPERATURE (°C)
D
S
Figure 4. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V
Figure 7. Leakage Current vs. Temperature, VDD = 5 V
0.9
0.8
0.6
0.4
0.2
0
V
= 5V
V
= 3.3V
DD
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= +85°C
= +25°C
A
I
I
I
I
I
(ON) ++
(OFF) +–
(ON) – –
(OFF) –+
D,
D,
D,
D,
S
T
A
I
S
I
S
I
S
T
= –40°C
A
–0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
20
30
40
50
60
70
80
V
, V (V)
S
TEMPERATURE (°C)
D
Figure 8. Leakage Current vs. Temperature, VDD = 3.3 V
Figure 5. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V
Rev. B | Page 7 of 16
ADG852
Data Sheet
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
V
= 25°C
A
V
= 5V
DD
= 5V, 3.3V
DD
V
= 3V
DD
V
= 2.5V
DD
0
0
1
2
3
4
5
6
0.1
1
10
100
1k
FREQUENCY (MHz)
SOURCE VOLTAGE (V)
Figure 9. Charge Injection vs. Source Voltage
Figure 12. Off isolation vs. Frequency
35
30
25
20
15
10
5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25°C
A
= 5V, 3.3V
DD
S1 to S2
tON (3.3V)
tON (5V)
tOFF (5V)
tOFF (3.3V)
0
–60
–40
–20
0
20
40
60
80
100
0.1
1
10
100
1k
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 10. tON/tOFF Times vs. Temperature
Figure 13. Crosstalk vs. Frequency
0.25
0.20
0.15
0.10
0.05
0
0
–2
–4
V
= 3.6V
DD
–6
–8
V
V
= 4.2V
= 5.5V
DD
–10
–12
–14
DD
T
V
= 25°C
A
= 5V, 3.3V
DD
–16
0.1
100
1k
FREQUENCY (Hz)
10k
100k
1
10
100
1k
FREQUENCY (MHz)
Figure 14. Total Harmonic Distortion + Noise (THD+N) vs. Frequency
Figure 11. Bandwidth
Rev. B | Page 8 of 16
Data Sheet
ADG852
0
T
= 25°C
A
V
= 5V, 3.3V
DD
–20
–40
–60
–80
–100
–120
–140
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 15. PSSR vs. Frequency
Rev. B | Page 9 of 16
ADG852
Data Sheet
TEST CIRCUITS
I
DS
V1
I
(OFF)
A
I
(OFF)
A
S
D
S
D
V
V
D
S
S
D
V
R
= V1/I
S
ON DS
Figure 17. Off Leakage
Figure 16. On Resistance
I
(ON)
D
S
D
NC
A
V
D
Figure 18. On Leakage
V
V
DD
0.1µF
DD
S1B
S1A
V
S
V
L
50%
50%
OUT
D
V
IN
R
L
C
IN
35pF
50Ω
90%
90%
V
OUT
GND
tON
tOFF
Figure 19. Switching Times, tON, tOFF
V
V
DD
DD
0.1µF
50%
50%
0V
V
V
IN
S1B
S1A
V
S
V
L
OUT
OUT
D
80%
80%
R
L
C
IN
35pF
50Ω
tBBM
tBBM
GND
Figure 20. Break-Before-Make Time Delay, tBBM
V
DD
SWITCH ON
SWITCH OFF
V
V
IN
S1B
S1A
NC
D
V
S
V
OUT
1nF
IN
OUT
ΔV
OUT
GND
Q
= C × ΔV
L OUT
INJ
Figure 21. Charge Injection
Rev. B | Page 10 of 16
Data Sheet
ADG852
V
V
V
V
DD
DD
DD
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
DD
S1
V
OUT
50Ω
R
L
S1B
S1A
50Ω
NC
50Ω
V
S
D
S2
R
L
D
50Ω
50Ω
V
OUT
R
50Ω
L
V
S
GND
GND
V
OUT
OFF ISOLATION = 20 log
V
OUT
V
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
S
V
S
Figure 24. Channel-to-Channel Crosstalk (S1 toS2)
Figure 22. Off Isolation
V
V
DD
0.1µF
NETWORK
ANALYZER
DD
50Ω
S1B
S1A
V
S
D
V
OUT
R
L
50Ω
GND
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 23. Bandwidth
Rev. B | Page 11 of 16
ADG852
Data Sheet
TERMINOLOGY
CD, CS (On)
IDD
On switch capacitance. Measured with reference to ground.
Positive supply current.
CIN
VD (VS)
Digital input capacitance.
Analog voltage on Terminal D and Terminal S.
RON
tON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Ohmic resistance between Terminal D and Terminal S.
RFLAT (On)
tOFF
The difference between the maximum and minimum values of
on resistance as measured on the switch.
Delay time between the 50% and 90% points of the digital input
and switch off condition.
∆RON
tBBM
On resistance match between any two channels.
On or off time measured between the 80% points of both
switches when switching from one to another.
IS (Off)
Source leakage current with the switch off.
Charge Injection
Measure of the glitch impulse transferred from the digital input
to the analog output during on/off switching.
ID (Off)
Drain leakage current with the switch off.
Off Isolation
ID, IS (On)
Measure of unwanted signal coupling through an off switch.
Channel leakage current with the switch on.
Crosstalk
VINL
Measure of unwanted signal that is coupled from one channel to
another as a result of parasitic capacitance.
Maximum input voltage for Logic 0.
VINH
−3 dB Bandwidth
Minimum input voltage for Logic 1.
Frequency at which the output is attenuated by 3 dB.
Insertion Loss
I
INL (IINH)
Input current of the digital input.
The loss due to the on resistance of the switch.
THD + N
CS (Off)
Off switch source capacitance. Measured with reference
to ground.
Ratio of the harmonics amplitude plus noise of a signal to the
fundamental.
Rev. B | Page 12 of 16
Data Sheet
ADG852
OUTLINE DIMENSIONS
0.55
0.40
0.30
0.20 DIA
TYP
1.30
PIN 1
IDENTIFIER
9
6
1
4
1.60
0.35
0.30
0.25
0.40
BSC
BOTTOM VIEW
TOP VIEW
0.20 BSC
0.60
0.55
0.50
0.05 MAX
0.02 NOM
SEATING
PLANE
Figure 25. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
1.30 mm × 1.60 mm Body, Ultrathin Quad
(CP-10-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
−40°C to +85°C 10-Lead Lead Frame Chip Scale Package (LFCSP_UQ)
Package Option Branding
ADG852BCPZ-REEL7
1Z = RoHS Compliant Part.
CP-10-10
F
Rev. B | Page 13 of 16
ADG852
NOTES
Data Sheet
Rev. B | Page 14 of 16
Data Sheet
NOTES
ADG852
Rev. B | Page 15 of 16
ADG852
NOTES
Data Sheet
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07461-0-5/12(B)
Rev. B | Page 16 of 16
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