ADG858BCPZ-REEL1 [ADI]
0.58 ヘ CMOS, 2.3 V to 5.5 V, Quad SPDT/2:1 Mux in Mini LFCSP; 0.58ヘCMOS ， 2.3 V至5.5 V ，四通道SPDT / 2 ： 1多路复用器在小型LFCSP
| 型号： | ADG858BCPZ-REEL1 |
| 厂家： | 
ADI |
| 描述： | 0.58 ヘ CMOS, 2.3 V to 5.5 V, Quad SPDT/2:1 Mux in Mini LFCSP |
| 文件： | 总16页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.58 Ω CMOS, 2.3 V to 5.5 V,
Quad SPDT/2:1 Mux in Mini LFCSP
ADG858
FEATURES
FUNCTIONAL BLOCK DIAGRAM
0.58 Ω typical on resistance
ADG858
0.82 Ω maximum on resistance at 85°C
2.3 V to 5.5 V single supply
High current carrying capability: 250 mA continuous
Rail-to-rail switching operation
Fast-switching times: <20 ns
S1A
D1
S1B
S2A
D2
S2B
IN1
Typical power consumption: <0.1 μW
2.1 mm × 2.1 mm mini LFCSP
S3A
APPLICATIONS
D3
S3B
Cellular phones
PDAs
S4A
MP3 players
Power routing
D4
S4B
Battery-powered systems
PCMCIA cards
IN2
Modems
Audio and video signal routing
Communication systems
SWITCHES SHOWN FOR
A LOGIC 1 INPUT
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG858 is a low voltage CMOS device containing four
single-pole, double-throw (SPDT) switches. This device offers
ultralow on resistance of less than 0.82 Ω over the full temperature
range. The ADG858 is fully specified for 4.2 V to 5.5 V and 2.7 V
to 3.6 V supply operation.
1. <0.82 Ω over the full temperature range of −40°C to +85°C.
2. Single 2.3 V to 5.5 V operation.
3. Compatible with 1.8 V CMOS logic.
4. High current handling capability (250 mA continuous
current per channel).
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG858 exhibits break-before-make switching action.
5. Low THD + N: 0.06% typical.
6. 2.1 mm × 2.1 mm, 16-lead mini LFCSP.
The ADG858 is available in a 2.1 mm × 2.1 mm, 16-lead mini
LFCSP. This tiny package makes the part ideal for space-
constrained applications, such as handsets, PDAs, and MP3s.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADG858
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Test Circuits..................................................................................... 10
Terminology.................................................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADG858
SPECIFICATIONS
VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
+25°C −40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 to VDD
0.82
V
0.58
0.72
0.04
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VDD = 4.2 V, VS = 0 V to VDD, IS = 100 mA, see Figure 16
VDD = 4.2 V, VS = 2 V, IS = 100 mA
On-Resistance Match Between Channels, ΔRON
On-Resistance Flatness, RFLAT (ON)
0.14
0.12
VDD = 4.2 V, VS = 0 V to VDD
IS = 100 mA
0.26
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
VDD = 5.5 V
10
10
pA typ
pA typ
VS = 0.6 V/4.2 V, VD = 4.2 V/0.6 V, see Figure 17
VS = VD = 0.6 V or 4.2 V, see Figure 18
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.004
2
μA typ
μA max
pF typ
VIN = VGND or VDD
0.05
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
20
27
8
12
14
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
RL = 50 Ω, CL = 35 pF
VS = 3 V/0 V, see Figure 19
RL = 50 Ω, CL = 35 pF
VS = 3 V, see Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V, see Figure 20
VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 22
S1A to S2A/S1B to S2B/S3A to S4A/S3B to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25
36
13
9
tOFF
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
45
−67
−85
−67
dB typ
S1A to S1B/S2A to S2B/S3A to S3B/S4A to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 24
Total Harmonic Distortion, THD + N
0.06
−0.05
70
%
dB typ
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p
RL = 50 Ω, CL = 5 pF, see Figure 23
Insertion Loss
−3 dB Bandwidth
CS (Off)
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 23
pF typ
25
CD, CS (On)
75
pF typ
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
0.003
μA typ
1
μA max
1 Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 16
ADG858
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
+25°C −40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 to VDD
1.5
V
1
1.35
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VDD = 2.7 V, VS = 0 V to VDD, IS = 100 mA, see Figure 16
VDD = 2.7 V, VS = 0.7 V, IS = 100 mA
VDD = 2.7 V, VS = 0 V to VDD, IS = 100 mA
VDD = 3.6 V
On-Resistance Match Between Channels, ΔRON 0.05
0.15
On-Resistance Flatness, RFLAT (ON)
0.35
0.79
LEAKAGE CURRENTS
Source Off Leakage IS (Off)
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
10
10
pA typ VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V, see Figure 17
pA typ VS = VD = 0.6 V or 3.3 V, see Figure 18
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
1.35
0.8
V min
V max
IINL or IINH
0.004
2
μA typ VIN = VGND or VDD
μA max
pF typ
0.05
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
30
50
9
14
25
ns typ
ns max VS = 1.5 V/0 V, see Figure 19
ns typ RL = 50 Ω, CL = 35 pF
ns max VS = 1.5 V, see Figure 19
ns typ RL = 50 Ω, CL = 35 pF
RL = 50 Ω, CL = 35 pF
59
15
11
tOFF
Break-Before-Make Time Delay, tBBM
ns min VS1 = VS2 = 1.5 V, see Figure 20
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
35
−67
−85
pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 21
dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 22
dB typ S1A to S2A/S1B to S2B/S3A to S4A/S3B to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25
−67
dB typ S1A to S1B/S2A to S2B/S3A to S3B/S4A to S4B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 24
Total Harmonic Distortion, THD + N
0.1
−0.06
70
%
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
Insertion Loss
−3 dB Bandwidth
CS (Off)
dB typ RL = 50 Ω, CL = 5 pF, see Figure 23
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 23
pF typ
25
CD, CS (On)
75
pF typ
POWER REQUIREMENTS
IDD
VDD = 3.6 V
μA typ Digital inputs = 0 V or 3.6 V
μA max
0.003
1
1 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 16
ADG858
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VDD to GND
Analog Inputs1
Digital Inputs1
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD or 10 mA,
whichever occurs first
500 mA (pulsed at 1 ms,
10% duty cycle max)
250 mA
−40°C to +85°C
−65°C to +150°C
150°C
Peak Current, S or D
Only one absolute maximum rating can be applied at any one time.
Continuous Current, S or D
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD CAUTION
16-Lead Mini LFCSP
θJA Thermal Impedance, 3-Layer Board 84.9°C/W
Reflow Soldering, Pb-Free
PeakTemperature
Time at PeakTemperature
260(+0/−5)°C
10 sec to 40 sec
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. 0 | Page 5 of 16
ADG858
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13 S4B
12 D4
S1A
D1
1
2
3
4
5
ADG858
S1B
S2A
D2
11 S4A
10 S3B
TOP VIEW
(Not to Scale)
9
D3
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 3, 4, 6, 8, 10, 11, 13
2, 5, 9, 12
7
S1A, S1B, S2A, S2B, S3A, S3B, S4A, S4B
D1, D2, D3, D4
GND
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Ground (0 V) Reference.
14, 16
15
IN1, IN2
VDD
Logic Control Input.
Most Positive Power Supply Potential.
Table 5. ADG858 Truth Table
Logic (IN1/IN2)
Switch A (S1A/S2A/S3A/S4A)
Switch B (S1B/S2B/S3B/S4B)
0
1
Off
On
On
Off
Rev. 0 | Page 6 of 16
ADG858
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
V
= 3.3V
DD
A
0.5
0.4
0.3
0.2
0.1
0
V
V
V
V
= 4.2V
= 4.5V
= 5.0V
= 5.5V
DD
DD
DD
DD
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
0
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
V , V (V)
D
2.5
3.0
3.5
V
, V (V)
D
S
S
Figure 3. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V
Figure 6. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
7
T
= 25°C
A
I
I
I
I
(OFF)+–
(OFF)–+
,I (ON)++
S
S
S
D
D
6
5
,I (ON)––
S
4
3
2
V
V
V
V
= 2.7V
= 3.0V
= 3.3V
= 3.6V
DD
DD
DD
DD
1
0
–1
–2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
25
50
75
100
125
V
, V (V)
S
TEMPERATURE (°C)
D
Figure 7. Leakage Current vs. Temperature, VDD = 5 V
Figure 4. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V
7
6
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
DD
I
I
I
I
(OFF)+–
(OFF)–+
S
S
D
D
,I (ON)++
S
5
,I (ON)––
S
4
3
2
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
1
0
–1
0
25
50
75
100
125
0
1
2
3
4
5
6
TEMPERATURE (°C)
V
, V (V)
S
D
Figure 5. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V
Figure 8. Leakage Current vs. Temperature, VDD = 3.3 V
Rev. 0 | Page 7 of 16
ADG858
160
140
120
100
80
0
–2
T
= 25°C
A
T
V
= 25°C
A
= 5V, 3.3V
DD
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
V
= 5V
60
DD
40
V
= 3V
DD
20
0
0
1
2
3
4
5
6
0.1
1
10
100
1k
FREQUENCY (MHz)
SOURCE VOLTAGE (V)
Figure 9. Charge Injection vs. Source Voltage
Figure 11. Bandwidth
40
35
30
25
20
15
10
5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
V
= 25°C
A
= 5V, 3.3V
DD
tON (3.3V)
tON (5V)
tOFF (5V)
tOFF (3.3V)
0
–60
–40
–20
0
20
40
60
80
100
0.1
1
10
100
1k
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 10. tON/tOFF Times vs. Temperature
Figure 12. Off Isolation vs. Frequency
Rev. 0 | Page 8 of 16
ADG858
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–20
T
V
= 25°C
T
V
= 25°C
A
A
= 5V, 3.3V
= 5V, 3.3V
DD
DD
S1A TO S1B
S1A TO S2A
–40
–60
–80
–100
–120
0.1
1
10
FREQUENCY (MHz)
100
1k
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
1G
Figure 13. Crosstalk vs. Frequency
Figure 15. PSSR vs. Frequency
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
V
= 3.6V
DD
V
= 5V
10k
DD
100
1k
FREQUENCY (Hz)
100k
Figure 14. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
Rev. 0 | Page 9 of 16
ADG858
TEST CIRCUITS
I
DS
V1
S
D
I
(ON)
A
D
S
D
NC
V
R
= V1/I
S
ON DS
V
D
Figure 16. On Resistance
Figure 18. On Leakage
I
(OFF)
A
I
(OFF)
A
S
D
S
D
V
V
S
D
Figure 17. Off Leakage
V
V
DD
DD
0.1µF
S1B
S1A
V
S
V
L
50%
50%
OUT
D
V
IN
R
L
C
IN
35pF
50Ω
90%
90%
V
OUT
GND
tON
tOFF
Figure 19. Switching Times, tON, tOFF
V
V
DD
DD
0.1µF
50%
50%
0V
V
V
IN
S1B
S1A
V
S
V
L
OUT
OUT
D
80%
80%
R
C
L
IN
35pF
50Ω
tBBM
tBBM
GND
Figure 20. Break-Before-Make Time Delay, tBBM
V
DD
SW ON
SW OFF
V
V
IN
S1B
S1A
NC
D
V
S
V
OUT
1nF
IN
OUT
ΔV
OUT
GND
Q
= CL × ΔV
OUT
INJ
Figure 21. Charge Injection
Rev. 0 | Page 10 of 16
ADG858
V
V
V
V
DD
DD
DD
DD
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
S1A
V
OUT
50Ω
R
L
S1B
S1A
50Ω
NC
50Ω
V
S
D
S1B
R
L
50Ω
D
50Ω
V
OUT
R
50Ω
L
V
S
GND
GND
V
OUT
VS
OFF ISOLATION = 20 log
V
OUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 24. Channel-to-Channel Crosstalk (S1A to S1B)
Figure 22. Off Isolation
V
V
DD
DD
0.1µF
NETWORK
ANALYZER
OUT
NETWORK
ANALYZER
V
D2
D1
S2A
S2B
NC
50Ω
50Ω
S1B
S1A
V
S
D
S1A
S1B
50Ω
V
OUT
R
50Ω
L
NC
V
S
50Ω
GND
V
OUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 23. Bandwidth
Figure 25. Channel-to-Channel Crosstalk (S1A to S2A)
Rev. 0 | Page 11 of 16
ADG858
TERMINOLOGY
CD, CS (On)
IDD
On switch capacitance. Measured with reference to ground.
Positive supply current.
CIN
VD (VS)
Digital input capacitance.
Analog voltage on Terminal D and Terminal S.
tON
RON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
tOFF
The difference between the maximum and minimum values of
on resistance as measured on the switch.
Delay time between the 50% and 90% points of the digital input
and switch off condition.
ΔRON
tBBM
On resistance match between any two channels.
On or off time measured between the 80% points of both
switches when switching from one to another.
IS (Off)
Source leakage current with the switch off.
Charge Injection
Measure of the glitch impulse transferred from the digital input
to the analog output during on/off switching.
ID (Off)
Drain leakage current with the switch off.
Off Isolation
ID, IS (On)
Measure of unwanted signal coupling through an off switch.
Channel leakage current with the switch on.
Crosstalk
VINL
Measure of unwanted signal that is coupled from one channel to
another because of parasitic capacitance.
Maximum input voltage for Logic 0.
VINH
−3 dB Bandwidth
Frequency at which the output is attenuated by 3 dB.
Minimum input voltage for Logic 1.
I
INL (IINH)
On Response
Frequency response of the on switch.
Input current of the digital input.
CS (Off)
Insertion Loss
The loss due to the on resistance of the switch.
Off switch source capacitance. Measured with reference to
ground.
THD + N
CD (Off)
Ratio of the harmonics amplitude plus noise of a signal to the
fundamental.
Off switch drain capacitance. Measured with reference to
ground.
Rev. 0 | Page 12 of 16
ADG858
OUTLINE DIMENSIONS
0.35
0.30
0.25
2.10 SQ
0.20 DIA
TYP
PIN 1
IDENTIFIER
1
5
13
9
0.55
0.40
0.30
0.40
BSC
BOTTOM VIEW
TOP VIEW
0.60
0.55
0.50
0.05 MAX
0.02 NOM
0.25
0.20
0.15
SEATING
PLANE
Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
2.10 mm × 2.10 mm Body, Ultra Thin Quad
(CP-16-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG858BCPZ-REEL1
ADG858BCPZ-REEL71
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-16-15
CP-16-15
Branding
16-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
11
11
1 Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
ADG858
NOTES
Rev. 0 | Page 14 of 16
ADG858
NOTES
Rev. 0 | Page 15 of 16
ADG858
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07090-0-8/08(0)
Rev. 0 | Page 16 of 16
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