ADG5204BCPZ-RL7 [ADI]
High Voltage, Latch-Up Proof, 4-Channel Multiplexer Automatic test equipment; 高电压，闭锁证明， 4通道多路复用器自动测试设备
| 型号： | ADG5204BCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | High Voltage, Latch-Up Proof, 4-Channel Multiplexer Automatic test equipment |
| 文件： | 总20页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, Latch-Up Proof,
4-Channel Multiplexer
ADG5204
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Latch-up proof
ADG5204
3 pF off source capacitance
S1
26 pF off drain capacitance
S2
D
−0.6 pC charge injection
S3
Low leakage: 0.4 nA maximum at 85°C
9 V to 22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at 15 V, 20 V, +12 V, and +36 V
S4
1 OF 4
DECODERS
A0
A1 EN
Figure 1.
V
SS to VDD analog signal range
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5204 is a complementary metal oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels.
1. Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors,
thereby preventing latch-up even under severe overvoltage
conditions.
2. Ultralow Capacitance and <1 pC Charge Injection.
3. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5204 can be operated from dual supplies up to 22 V.
4. Single-Supply Operation.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed together with high signal bandwidth make
the ADG5204 suitable for video signal switching.
The ADG5204 is designed on a trench process, which guards
against latch-up. A dielectric trench separates the P and N
channel transistors, thereby preventing latch-up even under
severe overvoltage conditions.
For applications where the analog signal is unipolar, the
ADG5204 can be operated from a single rail power supply
up to 40 V.
The ADG5204 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch con-
ducts equally well in both directions when on, and each switch
has an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action.
5. 3 V Logic-Compatible Digital Inputs.
V
INH = 2.0 V, VINL = 0.8 V.
6. No VL Logic Power Supply Required.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADG5204
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions............................9
Truth Table .....................................................................................9
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 14
Terminology.................................................................................... 16
Trench Isolation.............................................................................. 17
Applications Information.............................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
20 V Dual Supply ....................................................................... 4
12 V Single Supply........................................................................ 5
36 V Single Supply........................................................................ 6
Continuous Current per Channel, Sx or D............................... 7
REVISION HISTORY
5/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG5204
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
280
V max
160
200
4.5
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −1 mA, see Figure 24
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
250
On-Resistance Match
Between Channels, ∆RON
8
38
50
9
10
70
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 10 V, IS = −1 mA
65
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.01
nA typ
VS = VS = 10 V, VD = ∓10 V, see Figure 23
0.1
0.01
0.2
0.4
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = VS = 10 V, VD = ∓10 V, see Figure 23
0.1
0.4
0.5
1.2
1.2
nA max
nA typ
nA max
Channel On Leakage, ID, IS (On)
0.02
0.2
VS = VD = 10 V, see Figure 26
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
175
230
155
205
150
175
80
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 30
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 32
RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28
RL = 50 Ω, CL = 5 pF, see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
VS = 0 V, f = 1 MHz
285
255
200
320
285
215
30
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
CS (Off)
−0.6
−80
−80
136
−6.8
3
CD (Off)
CD, CS (On)
26
30
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
45
55
0.001
μA typ
μA max
μA typ
μA max
70
ISS
Digital inputs = 0 V or VDD
1
VDD/VSS
9/ 22
V min/max GND = 0 V
1 Guaranteed by design; not subject to production test.
Rev. 0 | Page 3 of 20
ADG5204
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = −20 V 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
25°C
−40°C to +85°C
−40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
230
V max
140
160
4.5
Ω typ
Ω max
Ω typ
VS = 15 V, IS = −1 mA, see Figure 24
VDD = +18 V, VSS = −18 V
VS = 15 V, IS = −1 mA
200
On-Resistance Match
Between Channels, ∆RON
8
33
45
9
10
60
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 15 V, IS = −1 mA
55
LEAKAGE CURRENTS
VDD = +22 V, VSS = −22 V
Source Off Leakage, IS (Off)
0.01
nA typ
VS = 15 V, VD = ∓15 V, see Figure 23
0.1
0.01
0.2
0.4
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 15 V, VD = ∓15 V, see Figure 23
0.1
0.02
0.2
0.4
0.5
1.2
1.2
nA max
nA typ
nA max
Channel On Leakage, ID, IS (On)
VS = VD = 15 V, see Figure 26
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
160
215
150
185
150
175
75
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 30
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 32
RL = 50 Ω, CL = 5 pF, f = 100 kHz,
see Figure 25
260
225
195
290
255
210
30
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
−0.6
−80
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
−80
150
−6
3
26
30
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28
RL = 50 Ω, CL = 5 pF, see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
50
μA typ
70
0.001
110
μA max
μA typ
ISS
Digital inputs = 0 V or VDD
GND = 0 V
1
μA max
V min/max
VDD/VSS
9/ 22
1 Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 20
ADG5204
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
700
V max
340
500
5
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA, see Figure 24
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
610
On-Resistance Match
Between Channels, ∆RON
20
145
280
21
22
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 0 V to 10 V, IS = −1 mA
335
370
LEAKAGE CURRENTS
VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.01
0.1
0.01
0.1
0.02
0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 23
0.2
0.4
0.5
0.4
1.2
1.2
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 23
VS = VD = 1 V/10 V, see Figure 26
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
240
350
250
335
160
195
140
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 30
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28
RL = 50 Ω, CL = 5 pF, see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
VS = 6 V, f = 1 MHz
445
420
220
515
485
240
60
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
CS (Off)
−1.2
−80
−80
106
−11
3.5
CD (Off)
CD, CS (On)
29
33
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 13.2 V
Digital inputs = 0 V or VDD
40
μA typ
65
μA max
VDD
9/40
V min/max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 20
ADG5204
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
25°C
−40°C to +85°C
−40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
245
V max
150
170
4.5
Ω typ
Ω max
Ω typ
VS = 0 V to 30 V, IS = −1 mA, see Figure 24
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −1 mA
215
On-Resistance Match
Between Channels, ∆RON
8
35
50
9
10
65
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT(ON)
VS = 0 V to 30 V, IS = −1 mA
60
LEAKAGE CURRENTS
VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.01
0.1
0.01
0.1
0.02
0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 23
0.2
0.4
0.5
0.4
1.2
1.2
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 23
VS = VD = 1 V/30 V, see Figure 26
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
180
250
170
220
170
210
80
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 31
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V, see Figure 30
VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28
RL = 50 Ω, CL = 5 pF, see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
VS = 18 V, f = 1 MHz
275
251
215
305
285
220
30
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
CS (Off)
−0.6
−80
−80
136
−6.7
3
CD (Off)
CD, CS (On)
26
30
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 39.6 V
Digital inputs = 0 V or VDD
85
μA typ
100
130
9/40
μA max
V min/max
VDD
GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
Rev. 0 | Page 6 of 20
ADG5204
CONTINUOUS CURRENT PER CHANNEL, Sx OR D
Table 5.
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR D PINS
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
24.5
35.7
7.5
7.7
2.8
2.8
mA max
mA max
26
37
7.5
7.7
2.8
2.8
mA max
mA max
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
18
28
7
7.7
2.8
2.8
mA max
mA max
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
30
41
7.7
7.7
2.8
2.8
mA max
mA max
Rev. 0 | Page 7 of 20
ADG5204
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
81 mA (pulsed at 1 ms,
Digital Inputs1
Only one absolute maximum rating can be applied at any
one time.
Peak Current, Sx or D Pins
10% duty cycle maximum)
ESD CAUTION
Continuous Current, Sx or D2
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Data + 15%
−40°C to +125°C
−65°C to +150°C
150°C
Thermal Impedance, θJA
16-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance (4-Layer Board)
112.6°C/W
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1 Overvoltages at the Sx and D pins are clamped by internal diodes. Limit
current to the maximum ratings given.
2 See Table 5.
Rev. 0 | Page 8 of 20
ADG5204
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
A0
EN
A1
GND
V
V
DD
SS
12 GND
11
10 S3
S4
V
1
2
3
4
SS
ADG5204
ADG5204
TOP VIEW
(Not to Scale)
S1
S3
S4
NC
NC
NC
S1
S2
V
TOP VIEW
DD
(Not to Scale)
S2
D
9
8
NC
NC = NO CONNECT
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, V
.
SS
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
Mnemonic
Description
1
2
15
16
A0
EN
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
3
4
5
6
1
3
4
6
VSS
S1
S2
D
NC
S4
S3
VDD
Most Negative Power Supply Potential.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
No Connect. These pins are open.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
7 to 9
10
11
12
13
14
N/A1
2, 5, 7, 8, 13
9
10
11
12
14
EP
GND
A1
Exposed Pad
Logic Control Input.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder
joints and maximum thermal capability, it is recommended that the pad be soldered to the
substrate, VSS.
1 N/A means not applicable.
TRUTH TABLE
Table 8.
EN
A1
X1
0
0
1
A0
X1
0
1
0
S1
S2
S3
S4
0
1
1
1
Off
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
On
1
1
1
1 X is don’t care.
Rev. 0 | Page 9 of 20
ADG5204
TYPICAL PERFORMANCE CHARACTERISTICS
160
160
140
120
100
80
T
= 25°C
T
= 25°C
A
A
V
V
= 32.4V
= 0V
DD
SS
140
120
100
80
V
V
= +18V
= –18V
DD
SS
V
V
= 39.6V
= 0V
DD
SS
V
V
= 36V
= 0V
DD
SS
V
V
= +20V
= –20V
DD
SS
V
V
= +22V
= –22V
DD
SS
60
60
40
40
20
20
0
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
0
5
10
15
20
V , V (V)
25
30
35
40
V , V (V)
S
D
S
D
Figure 4. RON as a Function of VD or VS, Dual Supply
Figure 7. RON as a Function of VD or VS, Single Supply
250
200
150
100
50
250
200
150
100
50
T
= 25°C
V
V
= +15V
= –15V
A
V
V
= +9V
= –9V
DD
SS
DD
SS
T
= +125°C
= +85°C
A
T
A
T
T
= +25°C
= –40°C
A
V
V
= +13.2V
= –13.2V
DD
SS
A
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +15V
= –15V
DD
SS
0
0
–20
–15
–10
–5
0
5
10
15
20
–15
–10
–5
0
5
10
15
V , V (V)
V
V (V)
S, D
S
D
Figure 5. RON as a Function of VD or VS, Dual Supply
Figure 8. RON as a Function of VD or VS, for Different Temperatures,
15 V Dual Supply
200
180
160
500
450
400
350
300
250
200
150
100
50
T
= 25°C
V
V
= 9V
= 0V
A
DD
SS
V
V
= 10.8V
= 0V
DD
SS
T
= +125°C
= +85°C
A
V
V
= 12V
= 0V
DD
SS
140
120
100
80
T
A
V
= 13.2V
= 0V
DD
V
SS
T
T
= +25°C
= –40°C
A
A
60
40
20
V
V
= +20V
= –20V
DD
SS
0
0
–20
–15
–10
–5
0
5
10
15
20
0
2
4
6
8
10
12
14
V
V (V)
D
V , V (V)
S,
S
D
Figure 6. RON as a Function of VD or VS, Single Supply
Figure 9. RON as a Function of VD or VS, for Different Temperatures,
20 V Dual Supply
Rev. 0 | Page 10 of 20
ADG5204
500
450
400
340
300
250
200
150
100
50
100
50
I
(OFF) – +
D
I
I
(ON) + +
S
D,
(OFF) + –
I
S
T
= +125°C
= +85°C
A
T
A
0
I
(OFF) – +
S
T
T
= +25°C
= –40°C
A
–50
–100
–150
–200
I
(OFF) + –
A
D
I
I (ON) – –
S
D,
V
V
V
= +20V
= –20V
DD
SS
V
V
= 12V
= 0V
DD
SS
= +15V/–15V
BIAS
0
0
2
4
6
8
10
12
0
20
40
60
80
100
120
V
V (V)
D
TEMPERATURE (°C)
S,
Figure 10. RON as a Function of VD or VS for Different Temperatures,
12 V Single Supply
Figure 13. Leakage Current vs. Temperature, 20 V Dual Supply
40
250
V
V
= 36V
= 0V
DD
SS
I
(OFF) + –
S
I
(OFF) – +
D
20
0
200
150
100
50
I
(OFF) – +
S
T
= +125°C
= +85°C
A
–20
–40
–60
–80
–100
–120
T
I
I (ON) + +
D, S
A
T
T
= +25°C
= –40°C
A
I
(OFF) + –
D
A
I
I (ON) – –
S
D,
V
V
V
= 12V
= 0V
DD
SS
= 1V/10V
BIAS
0
0
20
40
60
80
100
120
0
5
10
15
20
25
30
35
TEMPERATURE (°C)
V
V
(V)
D
S,
Figure 11. RON as a Function of VD or VS for Different Temperatures,
36 V Single Supply
Figure 14. Leakage Current vs. Temperature, 12 V Single Supply
10
50
I
(OFF) – +
I
I
(ON) + +
I
S
(OFF) + –
D
D,
S
I
(OFF) + –
S
I
(OFF) – +
D
I
, I (ON) + +
S
D
0
–10
–20
–30
–40
–50
–60
–70
0
–50
I
(OFF) – +
S
I
(OFF) + –
D
I
(OFF) – +
S
I
I (ON) – –
S
D,
–100
–150
–200
–250
I
(OFF) + –
D
I
, I (ON) – –
S
D
V
V
V
= +15V
= –15V
V
V
V
= 36V
= 0V
DD
DD
SS
SS
= +10V/–10V
= 1V/30V
BIAS
BIAS
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, 15 V Dual Supply
Figure 15. Leakage Current vs. Temperature, 36 V Single Supply
Rev. 0 | Page 11 of 20
ADG5204
0
350
300
250
200
150
100
50
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
–20
–40
V
V
= +36V
= 0V
V
V
= +12V
= 0V
DD
SS
DD
SS
–60
V
V
= +15V
= –15V
DD
SS
–80
V
V
= +20V
= –20V
DD
SS
–100
–120
0
10k
100k
1M
10M
100M
1G
1G
40
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 16. Off Isolation vs. Frequency, 15 V Dual Supply
Figure 19. Transition Time vs. Temperature
0
–20
0
–20
T
V
V
= 25°C
= +15V
= –15V
T
= 25°C
= +15V
= –15V
A
A
V
V
DD
SS
DD
SS
–40
–40
NO DECOUPLING CAPACITORS
BETWEEN S1 AND S2
–60
–60
–80
–80
BETWEEN S1 AND S4
–100
–120
–100
–120
DECOUPLING CAPACITORS
10k
100k
1M
10M
100M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 17. Crosstalk vs. Frequency, 15 V Dual Supply
Figure 20. ACPSRR vs. Frequency, 15 V Dual Supply
40
35
30
25
20
15
10
5
2.5
2.0
T
= 25°C
T = 25°C
A
V
V
A
V
V
= +20V
= –20V
DD
= +15V
= –15V
DD
SS
SS
1.5
SOURCE/DRAIN ON
DRAIN OFF
1.0
0.5
V
= +15V
= –15V
DD
V
V
= +36V
= 0V
DD
V
0
SS
V
= +12V
= 0V
DD
SS
V
SS
–0.5
–1.0
–1.5
–2.0
–2.5
SOURCE OFF
0
–15
–10
–5
0
5
10
15
–20
–10
0
10
(V)
20
30
V
(V)
V
S
S
Figure 21. Capacitance vs. Source Voltage, Dual Supply
Figure 18. Charge Injection vs. Source Voltage
Rev. 0 | Page 12 of 20
ADG5204
0
–2
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
–4
–6
–8
–10
–12
–14
–16
–18
–20
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 22. Bandwidth
Rev. 0 | Page 13 of 20
ADG5204
TEST CIRCUITS
I
(OFF)
A
I
(OFF)
A
I
(ON)
A
S
D
D
Sx
D
Sx
D
NC
V
V
D
V
D
S
NC = NO CONNECT
Figure 23. Off Leakage
Figure 26. On Leakage
V
V
SS
DD
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
SS
DD
50Ω
Sx
V
S
D
V
V
OUT
R
L
50Ω
GND
Sx
D
I
DS
V
S
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 27. Bandwidth
Figure 24. On Resistance
V
V
DD
SS
V
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
S1
DD
SS
V
OUT
50Ω
R
L
50Ω
D
Sx
50Ω
S2
R
L
V
S
50Ω
D
V
OUT
V
S
R
L
GND
50Ω
GND
V
V
V
OUT
OUT
OFF ISOLATION = 20 log
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
S
Figure 25. Off Isolation
Figure 28. Channel-to-Channel Crosstalk
Rev. 0 | Page 14 of 20
ADG5204
V
V
V
V
DD
DD
SS
0.1µF
0.1µF
3V
0V
ADDRESS
DRIVE (V
50%
50%
SS
)
IN
S1
V
A1
S1
S2
S3
S4
A0
V
IN
90%
V
S4
V
OUT
90%
2.4V
EN
V
D
OUT
GND
R
C
L
tTRANSITION
L
300Ω
35pF
tTRANSITION
Figure 29. Address to Output Switching Times
V
V
V
DD
DD
SS
0.1µF
0.1µF
3V
V
SS
S1
ADDRESS
DRIVE (V
V
A1
S1
)
IN
0V
S2
S3
S4
A0
V
IN
300Ω
80%
80%
V
2.4V
EN
D
OUT
V
OUT
GND
C
35pF
R
300Ω
L
L
tD
Figure 30. Break-Before-Make Time Delay, tD
V
V
V
DD
DD
SS
SS
0.1µF
0.1µF
3V
ENABLE
50%
50%
V
DRIVE (V )
IN
0V
V
S1
A1
S
S2
S3
S4
A0
V
OUT
0.9V
OUT
OUTPUT
0.1V
OUT
V
OUT
EN
D
0V
GND
R
C
L
L
V
IN
300Ω
300Ω
35pF
tON (EN)
tOFF (EN)
Figure 31. Enable-to-Output Switching Delay
V
V
V
SS
SS
DD
V
OUT
∆V
OUT
V
DD
Q
= C × ∆V
OUT
INJ
L
R
S
Sx
D
V
V
OUT
IN
SW OFF
SW OFF
SW OFF
C
1nF
L
V
S
SW ON
DECODER
GND
SW OFF
V
IN
A1 A2
EN
Figure 32. Charge Injection
Rev. 0 | Page 15 of 20
ADG5204
TERMINOLOGY
IDD
The positive supply current.
CIN
The digital input capacitance.
ISS
tTRANSITION
The negative supply current.
The delay time between the 50% and 90% points of the digital
input and switch-on condition when switching from one address
state to another.
VD, VS
The analog voltage on Terminal D and Terminal S.
t
ON (EN)
RON
The delay between applying the digital control input and the
output switching on. See Figure 31.
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
t
OFF (EN)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range.
The delay between applying the digital control input and the
output switching off. See Figure 31.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (Off)
The source leakage current with the switch off.
ID (Off)
Off Isolation
The drain leakage current with the switch off.
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
Crosstalk
The channel leakage current with the switch on.
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
The maximum input voltage for Logic 0.
Bandwidth
VINH
The frequency at which the output is attenuated by 3 dB.
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
I
INL, IINH
The input current of the digital input.
Insertion Loss
The loss due to the on resistance of the switch.
CS (Off)
The off switch source capacitance, which is measured with
reference to ground.
ACPSRR (AC Power Supply Rejection Ratio)
The ratio of the amplitude of signal on the output to the amplitude
of the modulation. This is a measure of the ability of the device
to avoid coupling noise and spurious signals that appear on the
supply voltage pins to the output of the switch. The dc voltage on
the device is modulated by a sine wave of 0.62 V p-p.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
CD (On), CS (On)
The on switch capacitance, which is measured with reference to
ground.
Rev. 0 | Page 16 of 20
ADG5204
TRENCH ISOLATION
NMOS
PMOS
In the ADG5204, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. By using trench isolation, this diode is removed, and
the result is a latch-up proof switch.
P WELL
N WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 33. Trench Isolation
Rev. 0 | Page 17 of 20
ADG5204
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5204 high voltage multiplexer allows
single-supply operation from 9 V to 40 V and dual-supply
operation from 9 V to 22 V.
Rev. 0 | Page 18 of 20
ADG5204
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 34. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5204BRUZ
ADG5204BRUZ-RL7
ADG5204BCPZ-RL7
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-14
RU-14
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-16-17
1 Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADG5204
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09768-0-5/11(0)
Rev. 0 | Page 20 of 20
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