ADG5206BRUZ [ADI]
High Voltage, Latch-Up Proof, 8-/16-Channel Multiplexers; 高电压闩锁防， 8位/ 16通道多路复用器
| 型号： | ADG5206BRUZ |
| 厂家： | 
ADI |
| 描述： | High Voltage, Latch-Up Proof, 8-/16-Channel Multiplexers |
| 文件： | 总28页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, Latch-Up Proof,
8-/16-Channel Multiplexers
Data Sheet
ADG5206/ADG5207
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
ADG5206
3.5 pF off source capacitance
Off drain capacitance
S1
ADG5206: 64 pF
D
ADG5207: 33 pF
0.35 pC typical charge injection
0.02 nA on channel leakage
Low on resistance: 155 Ω typical
9 V to 22 V dual-supply operation
9 V to 40 V single-supply operation
S16
1-OF-16
DECODER
V
SS to VDD analog signal range
A0 A1 A2 A3 EN
Human body model (HBM) ESD rating
ADG5206: 8 kV all pins
Figure 1.
ADG5207: 8 kV I/O port to supplies
ADG5207
S1A
APPLICATIONS
DA
S8A
Automatic test equipment
Data acquisition
Instrumentation
S1B
DB
Avionics
Battery monitoring
Communication systems
S8B
1-OF-8
DECODER
A0 A1 A2 EN
Figure 2.
GENERAL DESCRIPTION
The ADG5206 and ADG5207 are monolithic CMOS analog
multiplexers comprising 16 single channels and 8 differential
channels, respectively. The ADG5206 switches one of sixteen
inputs to a common output, as determined by the 4-bit binary
address lines, A0, A1, A2, and A3. The ADG5207 switches one
of eight differential inputs to a common differential output, as
determined by the 3-bit binary address lines, A0, A1, and A2.
The ADG5206/ADG5207 do not have VL pins; instead, an on-chip
voltage generator generates the logic power supply internally.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up. A dielectric trench
separates the P and N channel transistors to prevent latch-up
even under severe overvoltage conditions.
2. Optimal switch design for low charge injection, low switch
capacitance, and low leakage currents.
3. The ADG5206 achieves 8 kV HBM ESD specification on
all external pins, while the ADG5207 achieves 8 kV on the
I/O port to supply pins, 2 kV on the I/O port to I/O port
pins, and 8 kV on all other pins.
4. Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5206/ADG5207 can be operated
from dual supplies of up to 22 V.
5. Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5206/ADG5207 can be
operated from a single rail power supply of up to 40 V.
An EN input on both devices enables or disables the device. When
EN is low, the device is disabled and all channels switch off. The
ultralow capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make these
devices suitable for video signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
Rev. A
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ADG5206/ADG5207
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions......................... 12
Typical Performance Characteristics ........................................... 16
Test Circuits..................................................................................... 21
Terminology.................................................................................... 23
Applications Information .............................................................. 24
Trench Isolation.......................................................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
20 V Dual Supply ....................................................................... 4
12 V Single Supply........................................................................ 6
36 V Single Supply........................................................................ 8
Continuous Current per Channel, Sx, D, or Dx..................... 10
REVISION HISTORY
5/13—Rev. 0 to Rev. A
Added 32-Lead LFCSP .......................................................Universal
Changes to Features Section and Product Highlights Section..........1
Moved Continuous Current per Channel, Sx, D, or Dx Section,
Table 5, and Table 6 .........................................................................10
Changes to Table 7...........................................................................11
Changes to Figure 3.........................................................................12
Changes to Figure 5.........................................................................13
Changes to Figure 30, Figure 32, and Figure 33..........................22
7/12—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
ADG5206/ADG5207
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
−40°C to −40°C to −40°C to
Parameter
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
155
Ω typ
VS = 10 V, IS = −1 mA;
see Figure 32
200
4
225
250
285
Ω max
Ω typ
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
On Resistance Match Between Channels,
ΔRON
12
48
65
13
73
14
80
15
90
Ω max
Ω typ
Ω max
On Resistance Flatness, RFLAT (ON)
VS = 10 V, IS = −1 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.005
nA typ
VS = 10 V, VD =
see Figure 33
10 V;
0.1
0.01
0.15
0.2
0.4
0.015
nA max
nA typ
Match Between Channels, ΔLeakage,
IS (Off)1
Drain Off Leakage, ID (Off)
VS = 10 V, VD =
10 V
VS = 10 V, VD =
see Figure 33
10 V;
ADG5206
0.02
nA typ
nA max
nA typ
nA max
nA typ
0.1
0.02
0.1
0.25
0.25
0.6
0.4
3.3
ADG5207
1.7
0.015
Match Between Channels, ΔLeakage,
ID (Off), ADG5207 Only
0.015
VS = 10 V, VD =
10 V
Channel On Leakage, ID (On), IS (On)
ADG5206
VS = VD = 10 V; see Figure 34
0.02
0.1
0.02
0.1
nA typ
nA max
nA typ
nA max
nA typ
0.25
0.2
0.6
0.4
3.3
ADG5207
1.7
0.03
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01
VS = VD = 10 V
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION
200
260
180
245
140
200
85
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 37
300
260
220
320
270
240
360
285
270
27
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Rev. A | Page 3 of 28
ADG5206/ADG5207
Data Sheet
−40°C to −40°C to −40°C to
Parameter
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
Charge Injection, QINJ
0.35
pC typ
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
1.8
−90
2
pC typ
dB typ
VS = 10 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
−76
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
RL = 50 Ω, CL = 5 pF;
see Figure 41
ADG5206
ADG5207
Insertion Loss
60
140
6.4
MHz typ
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
CS (Off)
3.5
pF typ
VS = 0 V, f = 1 MHz
CD (Off)
ADG5206
ADG5207
64
33
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
CD (On), CS (On)
ADG5206
ADG5207
68
36
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
45
55
0.001
µA typ
µA max
µA typ
µA max
70
ISS
Digital inputs = 0 V or VDD
1
VDD/VSS
9/ 22
V min/V max GND = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = +10 V and VD = −10 V, or VS = −10 V and VD = +10 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = +10 V, or VS = VD = −10 V.
3 Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = −20 V 10%, GND = 0 V, unless otherwise noted.
Table 2.
−40°C to −40°C to −40°C to
Parameter
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
130
Ω typ
VS = 15 V, IS = −1 mA;
see Figure 32
160
4
12
35
50
180
13
200
14
230
15
Ω max
Ω typ
Ω max
Ω typ
VDD = +18 V, VSS = −18 V
VS = 15 V, IS = −1 mA
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
VS = 15 V, IS = −1 mA
58
65
75
Ω max
Rev. A | Page 4 of 28
Data Sheet
ADG5206/ADG5207
−40°C to −40°C to −40°C to
Parameter
25°C
0.005
0.1
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
VDD = +22 V, VSS = −22 V
nA typ
VS = 15 V, VD =
see Figure 33
15 V;
0.15
0.2
0.4
nA max
nA typ
Match Between Channels, ΔLeakage, IS (Off )1 0.01
Drain Off Leakage, ID (Off)
0.015
VS = 15 V, VD =
see Figure 33
15 V;
ADG5206
ADG5207
0.02
nA typ
nA max
nA typ
nA max
nA typ
0.1
0.02
0.1
0.25
0.25
0.6
0.4
3.3
1.7
0.015
Match Between Channels, ΔLeakage,
ID (Off), ADG5207 Only
0.015
Channel On Leakage, ID (On), IS (On)
VS = VD = 15 V;
see Figure 34
ADG5206
0.02
0.1
0.02
0.1
nA typ
nA max
nA typ
nA max
nA typ
0.25
0.2
0.6
0.4
3.3
ADG5207
1.7
0.03
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION
185
240
175
230
135
185
75
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 37
270
245
205
290
255
220
320
270
245
27
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
0.45
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
4
−90
4
pC typ
dB typ
VS = 10 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF,
Off Isolation
f = 1 MHz; see Figure 39
Channel-to-Channel Crosstalk
−3 dB Bandwidth
−76
dB typ
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 40
RL = 50 Ω, CL = 5 pF;
see Figure 41
ADG5206
ADG5207
Insertion Loss
65
145
5.6
MHz typ
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 41
CS (Off)
3.3
pF typ
VS = 0 V, f = 1 MHz
Rev. A | Page 5 of 28
ADG5206/ADG5207
Data Sheet
−40°C to −40°C to −40°C to
Parameter
CD (Off)
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
ADG5206
ADG5207
62
32
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
CD (On), CS (On)
ADG5206
ADG5207
67
35
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
50
70
0.001
µA typ
µA max
µA typ
µA max
110
ISS
Digital inputs = 0 V or VDD
1
VDD/VSS
9/ 22
V min/V max GND = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = +15 V and VD = −15 V, or VS = −15 V and VD = +15 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = +15 V, or VS = VD = −15 V.
3 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
−40°C to −40°C to −40°C to
Parameter
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
V
350
Ω typ
VS = 0 V to 10 V, IS = −1 mA;
see Figure 32
500
5
560
610
700
Ω max
Ω typ
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
On-Resistance Match Between
Channels, ∆RON
20
170
280
21
22
24
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −1 mA
VDD = +13.2 V, VSS = 0 V
310
335
370
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.005
nA typ
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 33
0.1
0.01
0.15
0.2
0.4
0.015
nA max
nA typ
Match Between Channels, ΔLeakage,
IS (Off)1
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 1 V/10 V;
see Figure 33
ADG5206
0.02
nA typ
nA max
nA typ
nA max
nA typ
0.1
0.02
0.1
0.25
0.25
0.6
0.4
3.3
ADG5207
1.7
0.015
Match Between Channels, ΔLeakage,
ID (Off), ADG5207 Only
0.015
Channel On Leakage, ID (On), IS (On)
ADG5206
VS = VD = 1 V/10 V; see Figure 34
0.02
0.1
0.02
0.1
nA typ
nA max
nA typ
nA max
nA typ
0.25
0.2
0.6
0.4
3.3
ADG5207
1.7
0.03
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01
Rev. A | Page 6 of 28
Data Sheet
ADG5206/ADG5207
−40°C to −40°C to −40°C to
Parameter
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION
290
290
230
290
230
315
170
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 37
440
320
360
480
340
390
550
370
450
45
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
0.25
VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
0.6
−90
0.7
pC typ
dB typ
VS = 0 V to 10 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
Off Isolation
Channel-to-Channel Crosstalk
−76
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
−3 dB Bandwidth
ADG5206
ADG5207
RL = 50 Ω, CL = 5 pF; see Figure 41
50
105
8.55
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
CS (Off)
3.6
pF typ
VS = 6 V, f = 1 MHz
CD (Off)
ADG5206
ADG5207
71
36
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
CD (On), CS (On)
ADG5206
ADG5207
75
40
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
POWER REQUIREMENTS
IDD
40
50
µA typ
µA max
Digital inputs = 0 V or VDD
65
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = 1 V and VD = 10 V, or VS = 10 V and VD = 1 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = 1 V, or VS = VD = 10 V.
3 Guaranteed by design; not subject to production test.
Rev. A | Page 7 of 28
ADG5206/ADG5207
Data Sheet
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
−40°C to −40°C to −40°C to
Parameter
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
V
140
Ω typ
VS = 0 V to 30 V, IS = −1 mA;
see Figure 32
170
4
12
40
55
195
13
215
14
245
15
Ω max
Ω typ
Ω max
Ω typ
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −1 mA
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 30 V, IS = −1 mA
63
70
80
Ω max
LEAKAGE CURRENTS
VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.005
0.1
nA typ
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 33
0.15
0.2
0.4
0.015
nA max
nA typ
Match Between Channels, ΔLeakage, IS (Off )1 0.01
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 33
ADG5206
ADG5207
0.02
nA typ
nA max
nA typ
nA max
nA typ
0.1
0.02
0.1
0.25
0.25
0.6
0.4
3.3
1.7
0.015
Match Between Channels, ΔLeakage,
ID (Off), ADG5207 Only
0.015
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/30 V;
see Figure 34
ADG5206
0.02
0.1
0.02
0.1
nA typ
nA max
nA typ
nA max
nA typ
0.25
0.2
0.6
0.4
3.3
ADG5207
1.7
0.03
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION
225
290
215
265
170
215
90
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 37
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
VS = 0 V to 30 V, RS = 0 Ω,
CL = 1 nF
310
285
230
320
285
245
350
295
270
28
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
0.7
3
3
pC typ
Rev. A | Page 8 of 28
Data Sheet
ADG5206/ADG5207
−40°C to −40°C to −40°C to
Parameter
25°C
+60°C
+85°C
+125°C
Unit
Test Conditions/Comments
Off Isolation
−90
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
Channel-to-Channel Crosstalk
−3 dB Bandwidth
−76
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
RL = 50 Ω, CL = 5 pF;
see Figure 41
ADG5206
ADG5207
Insertion Loss
55
115
5.65
MHz typ
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
CS (Off)
3.4
pF typ
VS = 18 V, f = 1 MHz
CD (Off)
ADG5206
ADG5207
62
32
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
CD (On), CS (On)
ADG5206
ADG5207
66
35
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
POWER REQUIREMENTS
IDD
80
µA typ
Digital inputs = 0 V or VDD
100
130
µA max
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = 1 V and VD = 30 V, or VS = 30 V and VD = 1 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = 1 V, or VS = VD = 30 V.
3 Guaranteed by design; not subject to production test.
Rev. A | Page 9 of 28
ADG5206/ADG5207
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx
Table 5. ADG5206
Parameter
25°C
60°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 12 V, VSS = 0 V
44
62
32
42
23
28
12
13
mA maximum
mA maximum
47
66
33
44
24
29
12
13
mA maximum
mA maximum
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 36 V, VSS = 0 V
31
45
24
33
19
24
11
12
mA maximum
mA maximum
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
46
65
33
43
24
28
12
13
mA maximum
mA maximum
Table 6. ADG5207
Parameter
25°C
60°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 12 V, VSS = 0 V
33
48
25
34
19
24
11
12
mA maximum
mA maximum
35
51
27
36
20
25
11
12
mA maximum
mA maximum
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
VDD = 36 V, VSS = 0 V
23
34
19
26
15
20
12
12
mA maximum
mA maximum
TSSOP (θJA = 67.7°C/W)
LFCSP (θJA = 27.27°C/W)
34
50
26
35
20
25
11
12
mA maximum
mA maximum
Rev. A | Page 10 of 28
Data Sheet
ADG5206/ADG5207
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
Rating
VDD to VSS
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Only one absolute maximum rating can be applied at any
one time.
Peak Current, Sx, D, or Dx Pins
ADG5206
ESD CAUTION
140 mA (pulsed at 1 ms, 10%
duty cycle maximum)
ADG5207
105 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx, D, or Dx
Pins2
Data + 15%
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
28-Lead TSSOP (4-Layer Board)
32-Lead LFCSP (4-Layer Board)
−40°C to +125°C
−65°C to +150°C
150°C
67.7°C/W
27.27°C/W
Reflow Soldering Peak
Temperature, Pb Free
As per JEDEC J-STD-020
HBM ESD
(ESDA/JEDEC JS-001-2011)
ADG5206
All Pins
8 kV
ADG5207
I/O Port to Supplies
I/O Port to I/O Port
All Other Pins
8 kV
2 kV
8 kV
1 Overvoltages at the Ax, EN, Sx, D, and Dx pins are clamped by internal
diodes. Limit current to the maximum ratings given.
2 See Table 5 and Table 6.
Rev. A | Page 11 of 28
ADG5206/ADG5207
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
D
DD
NC
NC
V
SS
3
S8
S7
S6
S5
S4
S3
S2
S1
EN
A0
A1
A2
S16
S15
S14
S13
S12
S11
S10
S9
1
2
3
4
5
6
7
8
24 S8
23 S7
22 S6
21 S5
20 S4
19 S3
18 S2
17 S1
4
S16
S15
S14
S13
S12
S11
S10
S9
ADG5206
TOP VIEW
(Not to Scale)
5
6
ADG5206
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
13
14
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
GND
NC
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
A3
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, V
.
SS
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
Figure 4. ADG5206 Pin Configuration (LFCSP)
Figure 3. ADG5206 Pin Configuration (TSSOP)
Table 8. ADG5206 Pin Function Descriptions
Pin No.
TSSOP LFCSP
31
2, 3, 13 12, 13, 26, 27,
28, 30, 32
Mnemonic Description
1
VDD
NC
Most Positive Power Supply Potential.
No Connect. Not internally connected.
4
5
6
7
8
9
10
11
12
14
15
16
17
18
1
2
3
4
5
6
7
8
S16
S15
S14
S13
S12
S11
S10
S9
GND
A3
A2
A1
A0
Source Terminal 16. This pin can be an input or an output.
Source Terminal 15. This pin can be an input or an output.
Source Terminal 14. This pin can be an input or an output.
Source Terminal 13. This pin can be an input or an output.
Source Terminal 12. This pin can be an input or an output.
Source Terminal 11. This pin can be an input or an output.
Source Terminal 10. This pin can be an input or an output.
Source Terminal 9. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Logic Control Input.
9
10
11
14
15
16
EN
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned
off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1
S2
S3
S4
S5
S6
S7
S8
VSS
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
28
29
D
Drain Terminal. This pin can be an input or an output.
NA
Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Rev. A | Page 12 of 28
Data Sheet
ADG5206/ADG5207
Table 9. ADG5206 Truth Table
A3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Rev. A | Page 13 of 28
ADG5206/ADG5207
Data Sheet
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DA
DD
DB
NC
V
SS
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
1
2
3
4
5
6
7
8
24 S8A
3
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
EN
23 S7A
22 S6A
21 S5A
20 S4A
19 S3A
18 S2A
17 S1A
4
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
ADG5207
TOP VIEW
(Not to Scale)
5
6
ADG5207
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
13
14
NOTES
A0
1. NO CONNECT. NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
A1
NC
A2
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, V
.
SS
NOTES
1. NO CONNECT. NOT INTERNALLY CONNECTED.
Figure 5. ADG5207 Pin Configuration (TSSOP)
Figure 6. ADG5207 Pin Configuration (LFCSP)
Table 10. ADG5207 Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic Description
1
2
29
31
VDD
DB
NC
Most Positive Power Supply Potential.
Drain Terminal B. This pin can be an input or an output.
No Connect. Not internally connected.
3, 13,
14
11, 12, 12, 26,
28, 30, 32
4
5
6
7
8
9
10
11
12
15
16
17
18
1
2
3
4
5
6
7
8
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
A2
Source Terminal 8B. This pin can be an input or an output.
Source Terminal 7B. This pin can be an input or an output.
Source Terminal 6B. This pin can be an input or an output.
Source Terminal 5B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Ground (0 V) Reference.
9
10
14
15
16
Logic Control Input.
Logic Control Input.
Logic Control Input.
A1
A0
EN
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned
off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Source Terminal 5A. This pin can be an input or an output.
Source Terminal 6A. This pin can be an input or an output.
Source Terminal 7A. This pin can be an input or an output.
Source Terminal 8A. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
28
27
DA
Drain Terminal A. This pin can be an input or an output.
NA
Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Rev. A | Page 14 of 28
Data Sheet
ADG5206/ADG5207
Table 11. ADG5207 Truth Table
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
X
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch Pair
None
1
2
3
4
5
6
7
8
1
1
1
1
Rev. A | Page 15 of 28
ADG5206/ADG5207
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
140
150
140
130
120
110
100
90
32.4V
36V
±18V
±20V
±22V
T
= 25°C
T
= 25°C
A
A
130
120
110
100
90
39.6V
80
80
70
70
60
60
–22.0 –16.5 –11.0
–5.5
0
5.5
11.0
16.5
22.0
0
5
10
15
20
V , V (V)
25
30
35
V , V (V)
S
D
S
D
Figure 7. RON as a Function of VS, VD
(
20 V Dual Supply)
Figure 10. RON as a Function of VS, VD (36 V Single Supply)
160
200
±13.5V
±15V
+125°C
+85°C
+60°C
+25°C
–40°C
T
= 25°C
V
V
= +15V
= –15V
A
DD
SS
150
140
130
120
110
100
90
180
160
140
120
100
80
±16.5V
80
70
60
60
–17.00 –12.75 –8.50 –4.25
0
4.25
8.50
12.75
17.0
–15
–10
–5
0
5
10
15
V , V (V)
V , V (V)
S D
S
D
Figure 8. RON as a Function of VS, VD
(
15 V Dual Supply)
Figure 11. RON as a Function of VS, VD for Different Temperatures,
15 V Dual Supply
360
160
10.8V
12V
+125°C
+85°C
+60°C
+25°C
–40°C
T
= 25°C
V
V
= +20V
= –20V
A
DD
SS
150
140
130
120
110
100
90
13.2V
310
260
210
160
110
60
80
70
60
0
2
4
6
8
10
12
–20
–15
–10
–5
0
5
10
15
20
V , V (V)
V , V (V)
S D
S
D
Figure 9. RON as a Function of VS, VD (12 V Single Supply)
Figure 12. RON as a Function of VS, VD for Different Temperatures,
20 V Dual Supply
Rev. A | Page 16 of 28
Data Sheet
ADG5206/ADG5207
410
360
310
260
210
160
110
150
100
50
V
V
= 12V
= 0V
DD
SS
0
–50
–100
–150
–200
–250
–300
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
S
D
S
D
+125°C
+85°C
+60°C
+25°C
–40°C
V
V
V
= +20V
= –20V
DD
SS
I , I (ON) + +
S
D
I , I (ON) – –
= +15V/–15V
S
D
BIAS
60
0
2
4
6
8
10
12
0
20
40
60
80
100
120
V , V (V)
TEMPERATURE (°C)
S
D
Figure 13. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Figure 16. Leakage Currents vs. Temperature, 20 V Dual Supply
180
50
0
+125°C
+85°C
+60°C
+25°C
–40°C
V
V
= 36V
= 0V
DD
SS
160
140
120
100
80
–50
–100
–150
–200
–250
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
S
D
S
D
–300
–350
–400
–450
V
V
V
= 12V
= 0V
DD
SS
I , I (ON) + +
S
D
I , I (ON) – –
= 1V/10V
S
D
BIAS
60
0
5
10
15
20
25
30
35
0
20
40
60
80
100
120
V , V (V)
TEMPERATURE (°C)
S
D
Figure 14. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
Figure 17. Leakage Currents vs. Temperature, 12 V Single Supply
20
0
100
50
–20
–40
–60
–80
0
–50
–100
–150
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
S
D
S
D
S
D
S
D
–100
–120
–140
–160
–200
–250
–300
–350
V
V
V
= +15V
= –15V
V
V
V
= 36V
= 0V
DD
SS
DD
I , I (ON) + +
I , I (ON) + +
S D
S
D
SS
I , I (ON) – –
I , I (ON) – –
S D
= +10V/–10V
= 1V/30V
S
D
BIAS
BIAS
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 18. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. A | Page 17 of 28
ADG5206/ADG5207
Data Sheet
0
0
–20
T
V
V
= 25°C
T = 25°C
A
A
= +15V
= –15V
V
= +15V
DD
SS
DD
SS
V
= –15V
–20
–40
–40
NO DECOUPLING
CAPACITORS
–60
–60
ADG5206
ADG5207
–80
–80
DECOUPLING
CAPACITORS
–100
–120
–140
–100
–120
–140
10k
100k
1M
10M
100M
1G
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 19. Off Isolation vs. Frequency, 15 V Dual Supply
Figure 22. ACPSRR vs. Frequency, 15 V Dual Supply
0
–5
–6
BETWEEN S1A AND S2A
BETWEEN S16 AND S1
BETWEEN S1A AND S8B
–20
–40
–7
–8
ADG5207
–60
–9
–80
–10
–11
–12
–13
–14
–15
ADG5206
–100
–120
–140
–160
T
V
V
= 25°C
T = 25°C
A
A
= +15V
= –15V
V
V
= +15V
= –15V
DD
SS
DD
SS
10k
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. Crosstalk vs. Frequency, 15 V Dual Supply
Figure 23. Bandwidth
45
40
35
30
25
20
15
10
5
8
7
6
5
4
3
2
1
0
V
V
V
V
= +15V, V = –15V
SS
= +20V, V = –20V
SS
= +12V, V = 0V
SS
= +36V, V = 0V
SS
V
V
V
V
= +15V, V = –15V
SS
= +20V, V = –20V
SS
= +12V, V = 0V
SS
= +36V, V = 0V
SS
DD
DD
DD
DD
DD
DD
DD
DD
–1
T
= 25°C
A
T
= 25°C
A
DEMUX (DRAIN TO SOURCE)
MUX (SOURCE TO DRAIN)
0
–20
–2
–20
–10
0
10
(V)
20 30 40
–10
0
10
(V)
20 30 40
V
V
S
S
Figure 21. Charge Injection vs. Source Voltage, Drain to Source
Figure 24. Charge Injection vs. Source Voltage, Source to Drain
Rev. A | Page 18 of 28
Data Sheet
ADG5206/ADG5207
3.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40°C
–40°C
+25°C
+85°C
+125°C
MUX (SOURCE TO DRAIN)
MUX (SOURCE TO DRAIN)
+25°C
+85°C
+125°C
2.5
2.0
1.5
1.0
0.5
0
–0.2
–0.4
–0.6
–0.5
–1.0
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
1
2
3
4
5
6
7
8
9
10
V
(V)
V (V)
S
S
Figure 25. QINJ as a Function of VS for Different Temperatures, 15 V Dual Supply
Figure 28. QINJ as a Function of VS for Different Temperatures, 12 V Single Supply
6
3.0
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
MUX (SOURCE TO DRAIN)
MUX (SOURCE TO DRAIN)
2.5
5
4
2.0
1.5
1.0
3
2
0.5
1
0
0
–0.5
–1.0
–1.5
–1
–2
–15
–10
–5
0
5
10
15
0
5
10
15
(V)
20
25
30
V
(V)
V
S
S
Figure 26. QINJ as a Function of VS for Different Temperatures, 20 V Dual Supply
Figure 29. QINJ as a Function of VS for Different Temperatures, 36 V Single Supply
450
V
V
V
V
= +12V, V = 0V
SS
DD
DD
DD
DD
= +36V, V = 0V
SS
400
350
300
250
200
150
100
50
= +15V, V = –15V
SS
= +20V, V = –20V
SS
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 27. tTRANSITION Time vs. Temperature
Rev. A | Page 19 of 28
ADG5206/ADG5207
Data Sheet
100
60
50
40
30
20
10
0
T
V
V
= 25°C
= +15V
T
V
V
= 25°C
= +15V
A
A
DD
DD
= –15V
= –15V
SS
SS
80
60
40
20
0
SOURCE/DRAIN ON
DRAIN OFF
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
SOURCE OFF
–15
–10
–5
0
5
10
15
–15
–10
–5
0
5
10
15
V
(V)
V (V)
S
S
Figure 30. ADG5206 Capacitance vs. Source Voltage, 15 V Dual Supply
Figure 31. ADG5207 Capacitance vs. Source Voltage, 15 V Dual Supply
Rev. A | Page 20 of 28
Data Sheet
ADG5206/ADG5207
TEST CIRCUITS
I
(ON)
A
D
V
S1
S2
D
NC
S
D
I
DS
V
S
R
= V/I
DS
S16
ON
NC = NO CONNECT
V
V
D
D
Figure 32. On Resistance
Figure 34. On Leakage
I
(OFF)
A
I
(OFF)
A
S
D
S1
D
S16
A
V
V
D
S
Figure 33. Off Leakage
V
V
V
DD
SS
3V
ADDRESS
t
t
< 20ns
< 20ns
r
f
V
DD
SS
50%
50%
DRIVE (V
)
A0
A1
A2
A3
IN
S1
S2
V
S
0V
V
IN
50Ω
tTRANSITION
tTRANSITION
S3 TO S16
ADG52061
90%
OUTPUT
3V
EN
D
OUTPUT
GND
300Ω
35pF
90%
0V
1
SIMILAR CONNECTION FOR ADG5207.
Figure 35. Address to Output Switching Times, tTRANSITION
V
V
V
DD
SS
3V
V
DD
SS
A0
A1
A2
A3
ENABLE
DRIVE (V
50%
50%
)
S1
S2 TO S16
V
IN
S
0V
ADG52061
tON (EN)
tOFF (EN)
OUTPUT
0.9V
D
EN
OUT
OUTPUT
0V
V
35pF
IN
50Ω
GND
300Ω
0.1V
OUT
1
SIMILAR CONNECTION FOR ADG5207.
Figure 36. Enable Delay, tON (EN), tOFF (EN)
Rev. A | Page 21 of 28
ADG5206/ADG5207
Data Sheet
V
V
V
V
DD
SS
3V
DD
SS
ADDRESS
A0
A1
A2
A3
DRIVE (V
)
IN
S1
V
S
V
IN
50Ω
0V
S2 TO S15
S16
ADG52061
80%
80%
OUTPUT
OUTPUT
D
3V
EN
GND
300Ω
35pF
tBBM
1
SIMILAR CONNECTION FOR ADG5207.
Figure 37. Break-Before-Make Time Delay, tD
V
V
V
V
DD
DD
SS
SS
A0
A1
A2
A3
3V
V
IN
ADG52061
0V
R
S
Sx
D
V
OUT
V
OUT
ΔV
OUT
EN
C
1nF
L
GND
V
Q
= C × ΔV
S
INJ
L
OUT
V
IN
1
SIMILAR CONNECTION FOR ADG5207.
Figure 38. Charge Injection
V
V
V
V
DD
SS
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
V
DD
SS
DD
SS
50Ω
Sx
50Ω
Sx
50Ω
V
S
V
S
D
D
V
V
OUT
OUT
R
50Ω
R
50Ω
L
L
GND
GND
V
V
V
WITH SWITCH
OUT
OUT
OFF ISOLATION = 20 log
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
S
OUT
Figure 39. Off Isolation
Figure 41. Bandwidth
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
S1
V
OUT
R
L
50Ω
D
S2
R
L
50Ω
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 40. Channel-to-Channel Crosstalk
Rev. A | Page 22 of 28
Data Sheet
ADG5206/ADG5207
TERMINOLOGY
IDD
CIN
IN represents digital input capacitance.
ON (EN)
ON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
OFF (EN)
OFF (EN) represents the delay time between the 50% and 90%
I
DD represents the positive supply current.
C
ISS
t
t
I
SS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
t
t
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal D and
tTRANSITION
Terminal S.
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
Break-Before-Make Time Delay (tD)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to another.
RFLAT (ON)
RFLAT (ON) is the flatness defined as the difference between the
maximum and the minimum value of on resistance measured
over the specified analog signal range.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
Crosstalk
ID (On), IS (On)
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
Bandwidth
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH represent the low and high input currents of the
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
V
On Response
I
I
On response is the frequency response of the on switch.
AC Power Supply Rejection Ratio (ACPSRR)
digital inputs.
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin to
the output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. A | Page 23 of 28
ADG5206/ADG5207
Data Sheet
APPLICATIONS INFORMATION
NMOS
PMOS
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persist until the power supply is turned
off. The ADG5206/ADG5207 high voltage switches allow single-
supply operation from 9 V to 40 V and dual-supply operation
from 9 V to 22 V.
P WELL
N WELL
TRENCH ISOLATION
In the ADG5206/ADG5207, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed and the result is a latch-
up proof switch.
Figure 42. Trench Isolation
Rev. A | Page 24 of 28
Data Sheet
ADG5206/ADG5207
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 43. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
*
3.75
EXPOSED
PAD
3.60 SQ
3.55
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 44. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 × 5 mm Body, Very Very Thin Quad (CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
Package Description
Package Option
RU-28
RU-28
CP-32-12
RU-28
RU-28
ADG5206BRUZ
ADG5206BRUZ-RL7
ADG5206BCPZ-RL7
ADG5207BRUZ
ADG5207BRUZ-RL7
ADG5207BCPZ-RL7
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
CP-32-12
1 Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
ADG5206/ADG5207
NOTES
Data Sheet
Rev. A | Page 26 of 28
Data Sheet
NOTES
ADG5206/ADG5207
Rev. A | Page 27 of 28
ADG5206/ADG5207
NOTES
Data Sheet
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10714-0-5/13(A)
Rev. A | Page 28 of 28
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