ADG5208 [ADI]
High Voltage, Latch-Up Proof; 高电压，闭锁证明
| 型号： | ADG5208 |
| 厂家： | 
ADI |
| 描述： | High Voltage, Latch-Up Proof |
| 文件： | 总24页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, Latch-Up Proof,
4-/8-Channel Multiplexers
Data Sheet
ADG5208/ADG5209
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
ADG5208
ADG5209
5.5 pF off source capacitance
52 pF off drain capacitance
0.4 pC charge injection
Low on resistance: 160 Ω typical
9 V to 22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at 15 V, 20 V, +12 V, and +36 V
S1
S1A
DA
DB
S4A
S1B
D
S4B
S8
1-OF-8
DECODER
1-OF-4
DECODER
V
SS to VDD analog signal range
Human body model (HBM) ESD rating
4 kV I/O port to supplies
1 kV I/O port to I/O port
4 kV all other pins
A0 A1 A2 EN
A0 A1 EN
Figure 1.
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
The ADG5208/ADG5209 do not have VL pins; instead, the logic
power supply is generated internally by an on-chip voltage
generator.
GENERAL DESCRIPTION
The ADG5208/ADG5209 are monolithic CMOS analog multi-
plexers comprising eight single channels and four differential
channels, respectively. The ADG5208 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2. The ADG5209 switches one of
four differential inputs to a common differential output, as
determined by the 2-bit binary address lines, A0 and A1.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors
to prevent latch-up even under severe overvoltage conditions.
2. 0.4 pC Charge Injection.
An EN input on both devices enables or disables the device.
When EN is disabled, all channels switch off. The ultralow
capacitance and charge injection of these switches make them
ideal solutions for data acquisition and sample-and-hold appli-
cations, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make
these devices suitable for video signal switching.
3. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5208/ADG5209 can be operated from dual supplies
of up to 22 V.
4. Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5208/ADG5209 can be operated from a single rail
power supply of up to 40 V.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
5. 3 V Logic-Compatible Digital Inputs.
V
INH = 2.0 V, VINL = 0.8 V.
6. No VL Logic Power Supply Required.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADG5208/ADG5209
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................9
ESD Caution...................................................................................9
Pin Configurations and Function Descriptions......................... 10
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 16
Terminology.................................................................................... 19
Trench Isolation.............................................................................. 20
Applications Information .............................................................. 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
20 V Dual Supply ....................................................................... 4
12 V Single Supply........................................................................ 5
36 V Single Supply........................................................................ 6
Continuous Current per Channel, Sx or Dx............................. 8
REVISION HISTORY
3/12—Rev. 0 to Rev. A
Added 16-Lead LFCSP.......................................................Universal
Changes to Ordering Guide ...........................................................22
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADG5208/ADG5209
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
280
V
160
200
3.5
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −1 mA; see Figure 28
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
250
On-Resistance Match Between
Channels, ∆RON
8
40
50
9
10
70
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 10 V, IS = −1 mA
65
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.005
0.1
0.005
0.1
0.01
0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 10 V, VD =
10 V; see Figure 30
0.2
0.4
0.5
0.4
1.4
1.4
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
VS = 10 V, VD =
10 V; see Figure 30
VS = VD = 10 V; see Figure 27
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
3
170
205
145
185
120
145
65
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 34
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
245
220
165
275
245
180
30
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
0.4
−90
−90
dB typ
dB typ
Channel-to-Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
−3 dB Bandwidth
ADG5208
ADG5209
RL = 50 Ω, CL = 5 pF; see Figure 32
54
133
−6.4
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 32
CS (Off)
5.5
pF typ
VS = 0 V, f = 1 MHz
CD (Off)
ADG5208
ADG5209
52
26
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Rev. A | Page 3 of 24
ADG5208/ADG5209
Data Sheet
Parameter
CD (On), CS (On)
ADG5208
25°C
−40°C to +85°C −40°C to +125°C Unit
pF typ
Test Conditions/Comments
58
31
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADG5209
pF typ
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
45
55
0.001
µA typ
µA max
µA typ
µA max
70
1
ISS
Digital inputs = 0 V or VDD
VDD/VSS
9/ 22
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = −20 V 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
230
V
140
160
3.5
Ω typ
Ω max
Ω typ
VS = 15 V, IS = −1 mA; see Figure 28
VDD = +18 V, VSS = −18 V
VS = 15 V, IS = −1 mA
200
On-Resistance Match Between
Channels, ∆RON
8
34
45
9
10
60
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 15 V, IS = −1 mA
VDD = +22 V, VSS = −22 V
55
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.005
0.1
0.005
0.1
0.01
0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 15 V, VD =
15 V; see Figure 30
0.2
0.4
0.5
0.4
1.4
1.4
Drain Off Leakage, ID (Off)
VS = 15 V, VD =
15 V; see Figure 30
Channel On Leakage, ID (On), IS (On)
VS = VD = 15 V; see Figure 27
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
3
160
195
145
170
120
140
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 34
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
225
200
155
255
225
170
30
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD 55
Charge Injection, QINJ
Off Isolation
0.3
−90
−90
dB typ
dB typ
Channel-to-Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
Rev. A | Page 4 of 24
Data Sheet
ADG5208/ADG5209
Parameter
−3 dB Bandwidth
ADG5208
25°C
−40°C to +85°C −40°C to +125°C Unit
MHz typ
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF; see Figure 32
60
ADG5209
Insertion Loss
130
−5.6
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
CS (Off)
5.5
pF typ
VS = 0 V, f = 1 MHz
CD (Off)
ADG5208
ADG5209
51
26
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
CD (On), CS (On)
ADG5208
ADG5209
57
31
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
50
70
0.001
µA typ
µA max
µA typ
µA max
110
1
ISS
Digital inputs = 0 V or VDD
VDD/VSS
9/ 22
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
700
V
350
Ω typ
VS = 0 V to 10 V, IS = −1 mA; see
Figure 28
VDD = 10.8 V, VSS = 0 V
500
5
610
Ω max
Ω typ
On-Resistance Match Between
Channels, ∆RON
VS = 0 V to 10 V, IS = −1 mA
20
160
280
22
24
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −1 mA
VDD = 13.2 V, VSS = 0 V
335
370
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.005
nA typ
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 30
0.1
0.005
0.2
0.4
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 30
0.1
0.01
0.2
0.4
0.5
1.4
1.4
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V; see Figure 27
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
3
Rev. A | Page 5 of 24
ADG5208/ADG5209
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
25°C
−40°C to +85°C −40°C to +125°C Unit
ns typ
Test Conditions/Comments
210
270
215
275
115
140
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 34
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
330
345
160
380
400
175
70
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD 135
Charge Injection, QINJ
Off Isolation
0.3
−90
−90
dB typ
dB typ
Channel-to-Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
−3 dB Bandwidth
ADG5208
ADG5209
RL = 50 Ω, CL = 5 pF; see Figure 32
60
120
−8.8
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
CS (Off)
6
pF typ
VS = 6 V, f = 1 MHz
CD (Off)
ADG5208
ADG5209
56
28
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
CD (On), CS (On)
ADG5208
ADG5209
63
35
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
POWER REQUIREMENTS
IDD
40
50
µA typ
µA max
Digital inputs = 0 V or VDD
65
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
25°C
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
245
V
150
Ω typ
VS = 0 V to 30 V, IS = −1 mA; see
Figure 28
VDD = 32.4 V, VSS = 0 V
170
3.5
215
Ω max
Ω typ
On-Resistance Match Between
Channels, ∆RON
VS = 0 V to 30 V, IS = −1 mA
8
35
55
9
10
70
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 30 V, IS = −1 mA
VDD = 39.6 V, VSS = 0 V
65
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.005
0.1
nA typ
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 30
0.2
0.4
nA max
Rev. A | Page 6 of 24
Data Sheet
ADG5208/ADG5209
Parameter
25°C
0.005
−40°C to +85°C −40°C to +125°C Unit
nA typ
Test Conditions/Comments
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 30
0.1
0.01
0.2
0.4
0.5
1.4
1.4
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/30 V; see Figure 27
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
185
230
170
210
125
180
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 34
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
245
230
180
259
255
180
35
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD 70
Charge Injection, QINJ
Off Isolation
0.4
−90
−90
dB typ
dB typ
Channel-to-Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
−3 dB Bandwidth
ADG5208
ADG5209
RL = 50 Ω, CL = 5 pF; see Figure 32
65
130
−6
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
CS (Off)
5.5
pF typ
VS = 18 V, f = 1 MHz
CD (Off)
ADG5208
ADG5209
51
25
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
CD (On), CS (On)
ADG5208
ADG5209
57
32
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
POWER REQUIREMENTS
IDD
80
µA typ
Digital inputs = 0 V or VDD
100
130
µA max
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
Rev. A | Page 7 of 24
ADG5208/ADG5209
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx
Table 5. ADG5208
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
40
69
24
37
14.5
18
mA maximum
mA maximum
42
75
26.5
40
14.5
18
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
28
40
19
25
12
14.5
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
40
72
26
39
14.5
18
mA maximum
mA maximum
Table 6. ADG5209
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
29
51
19
30
12
16
mA maximum
mA maximum
30
55
20
32
12.5
17
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
20
29
14
20
10
12.5
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
30
54
20
31
12.5
17
mA maximum
mA maximum
Rev. A | Page 8 of 24
Data Sheet
ADG5208/ADG5209
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
Rating
VDD to VSS
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Only one absolute maximum rating can be applied at any
one time.
Peak Current, Sx, D, or Dx Pins
ADG5208
ESD CAUTION
126 mA (pulsed at 1 ms, 10%
duty cycle maximum)
ADG5209
92 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx, D, or
Dx Pins2
Data + 15%
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
−40°C to +125°C
−65°C to +150°C
150°C
16-Lead TSSOP (4-Layer
Board)
16-Lead LFCSP (4-Layer
Board)
112.6°C/W
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
HBM ESD
I/O Port to Supplies
I/O Port to I/O Port
All Other Pins
4 kV
1 kV
4 kV
1 Overvoltages at the Ax, EN, Sx, D, and Dx pins are clamped by internal
diodes. Limit current to the maximum ratings given.
2 See Table 5 and Table 6.
Rev. A | Page 9 of 24
ADG5208/ADG5209
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A0
EN
1
2
3
4
5
6
7
8
16 A1
15 A2
V
14 GND
SS
ADG5208
V
1
12 GND
SS
S1
13 V
DD
TOP VIEW
S1 2
S2 3
11 V
DD
ADG5208
TOP VIEW
(Not to Scale)
(Not to Scale)
S2
S3
S4
D
12 S5
11 S6
10 S7
10 S5
4
9
S6
S3
9
S8
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, V
.
SS
Figure 2. ADG5208 Pin Configuration (TSSOP)
Figure 3. ADG5208 Pin Configuration (LFCSP)
Table 8. ADG5208 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
15
16
Mnemonic
Description
1
2
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high, the
Ax logic inputs determine the on switches.
3
1
VSS
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG5208 Truth Table
A2
X1
0
0
0
0
1
1
1
A1
X1
0
0
1
1
0
0
1
A0
X1
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
1
1
1
1
1 X is don’t care.
Rev. A | Page 10 of 24
Data Sheet
ADG5208/ADG5209
A0
EN
1
2
3
4
5
6
7
8
16 A1
15 GND
V
14 V
DD
SS
ADG5209
V
1
12 V
DD
S1A
13 S1B
12 S2B
11 S3B
10 S4B
SS
TOP VIEW
(Not to Scale)
S2A
S3A
S4A
DA
S1A 2
S2A 3
11 S1B
10 S2B
ADG5209
TOP VIEW
(Not to Scale)
4
9
S3B
S3A
9
DB
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, V
.
SS
Figure 4. ADG5209 Pin Configuration (TSSOP)
Figure 5. ADG5209 Pin Configuration (LFCSP)
Table 10. ADG5209 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic
Description
1
2
15
16
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine the on switches.
3
1
VSS
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
S1A
S2A
S3A
S4A
DA
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Drain Terminal A. This pin can be an input or an output.
Drain Terminal B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Most Positive Power Supply Potential.
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
Ground (0 V) Reference.
Logic Control Input.
Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 11. ADG5209 Truth Table
A1
X1
0
0
1
A0
X1
0
1
0
EN
0
1
1
1
On Switch Pair
None
1
2
3
4
1
1
1
1 X is don’t care.
Rev. A | Page 11 of 24
ADG5208/ADG5209
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
160
160
140
120
100
80
T
= 25°C
T
= 25°C
A
A
V
V
= 32.4V
= 0V
DD
SS
140
120
100
80
V
V
= +18V
= –18V
DD
SS
V
V
= 39.6V
= 0V
DD
SS
V
V
= 36V
= 0V
DD
SS
V
V
= +20V
= –20V
DD
SS
V
V
= +22V
= –22V
DD
SS
60
60
40
40
20
20
0
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
20
14
0
5
10
15
20
V , V (V)
25
30
35
40
V , V (V)
S
D
S
D
Figure 9. RON as a Function of VS, VD (36 V Single Supply)
Figure 6. RON as a Function of VS, VD
( 20 V Dual Supply)
250
200
150
100
50
250
200
150
100
50
T
= 25°C
V
V
= +15V
= –15V
A
V
V
= +9V
= –9V
DD
SS
DD
SS
T
= +125°C
= +85°C
A
T
A
T
T
= +25°C
= –40°C
A
V
V
= +13.2V
= –13.2V
DD
SS
A
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +15V
= –15V
DD
SS
0
0
–15
–10
–5
0
5
10
15
–20
–15
–10
–5
0
5
10
15
V
V (V)
D
V , V (V)
S,
S
D
Figure 10. RON as a Function of VS, VD for Different Temperatures,
15 V Dual Supply
Figure 7. RON as a Function of VS, VD
( 15 V Dual Supply)
200
180
160
500
450
400
350
300
250
200
150
100
50
T
= 25°C
V
V
= 9V
= 0V
A
DD
SS
V
V
= 10.8V
= 0V
DD
SS
T
= +125°C
= +85°C
A
V
V
= 12V
= 0V
V
DD
SS
140
120
100
80
T
A
= 13.2V
= 0V
DD
V
SS
T
T
= +25°C
= –40°C
A
A
60
40
20
V
V
= +20V
= –20V
DD
SS
0
0
–20
–15
–10
–5
0
5
10
15
20
0
2
4
6
8
10
12
V
V (V)
D
V , V (V)
S,
S
D
Figure 11. RON as a Function of VS, VD for Different Temperatures,
20 V Dual Supply
Figure 8. RON as a Function of VS, VD (12 V Single Supply)
Rev. A | Page 12 of 24
Data Sheet
ADG5208/ADG5209
500
450
400
350
300
250
200
150
100
50
100
50
I
(OFF) + –
I
(OFF) + –
S
D
I
(OFF) – +
D
T
= +125°C
= +85°C
A
T
A
0
I
(OFF) – +
S
T
T
= +25°C
= –40°C
A
–50
–100
–150
–200
A
I
, I (ON) + +
S
D
I
, I (ON) – –
S
D
V
V
V
= +20V
= –20V
DD
SS
V
V
= 12V
= 0V
DD
SS
= +15V/–15V
BIAS
0
0
2
4
6
8
10
12
0
25
50
75
100
125
V
V (V)
D
TEMPERATURE (°C)
S,
Figure 15. Leakage Currents vs. Temperature, 20 V Dual Supply
Figure 12. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
100
250
I
(OFF) – +
I (OFF) – +
S
V
V
= 36V
= 0V
D
DD
SS
0
–100
–200
–300
–400
–500
–600
–700
200
150
100
50
I
, I (ON) + +
S
D
I
(OFF) + –
S
T
= +125°C
= +85°C
A
T
A
T
T
= +25°C
= –40°C
A
A
I
(OFF) + –
D
V
V
V
= 12V
= 0V
DD
SS
I
, I (ON) – –
S
D
= 1V/10V
BIAS
0
0
25
50
75
100
125
0
5
10
15
20
25
30
35
TEMPERATURE (°C)
V
V
(V)
D
S,
Figure 13. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply
50
200
I
(OFF) + –
S
I
, I (ON) + +
S
I
(OFF) – +
D
I (OFF) + –
S
S
0
–50
0
–200
–400
–600
–800
–1000
I
(OFF) – +
S
I
, I (ON) + +
S
D
I
(OFF) – +
D
I
(OFF) + –
D
I
(OFF) – +
–100
–150
–200
–250
D
I
, I (ON) – –
S
D
I
(OFF) + –
D
V
V
V
= +15V
= –15V
V
V
V
= 36V
= 0V
DD
SS
DD
SS
I
, I (ON) – –
S
D
= +10V/–10V
= 1V/30V
BIAS
BIAS
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. A | Page 13 of 24
ADG5208/ADG5209
Data Sheet
0
0
–20
T
V
V
= 25°C
T = 25°C
A
A
= +15V
= –15V
V
= +15V
DD
SS
DD
SS
V
= –15V
–20
–40
–40
NO DECOUPLING
CAPACITORS
–60
–60
–80
–80
–100
–120
–140
DECOUPLING
CAPACITORS
–100
–120
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. ACPSRR vs. Frequency, 15 V Dual Supply
Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply
–6
–7
0
–20
T
V
V
= 25°C
T
V
V
= 25°C
= +15V
A
A
= +15V
DD
SS
DD
= –15V
= –15V
SS
–40
–8
BETWEEN S1 AND S2
ADG5208
ADG5209
–60
–9
–80
–10
–11
–12
–100
–120
–140
BETWEEN S1 AND S8
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Bandwidth
Figure 19. Crosstalk vs. Frequency, 15 V Dual Supply
6
5
16
14
12
10
8
T
= 25°C
V
V
= +20V
= –20V
T
= 25°C
A
DD
SS
A
MUX (SOURCE TO DRAIN)
DEMUX (DRAIN TO SOURCE)
V
V
= +20V
= –20V
DD
SS
4
V
V
= +15V
= –15V
V
V
= +36V
= 0V
DD
DD
SS
SS
3
V
V
= +15V
= –15V
DD
SS
2
V
V
= +12V
= 0V
V
V
= +36V
= 0V
DD
SS
DD
SS
1
6
0
4
V
V
= +12V
= 0V
DD
SS
–1
2
–2
0
–20
–10
0
10
(V)
20
30
40
–20
–10
0
10
(V)
20
30
40
V
V
S
S
Figure 23. Charge Injection vs. Source Voltage, Source to Drain
Figure 20. Charge Injection vs. Source Voltage, Drain to Source
Rev. A | Page 14 of 24
Data Sheet
ADG5208/ADG5209
350
300
250
200
150
100
50
80
70
60
50
40
30
20
10
0
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
SOURCE/DRAIN ON
DRAIN OFF
V
V
= +12V
= 0V
DD
SS
V
V
= +36V
= 0V
DD
SS
V
= +15V
= –15V
V
V
= +20V
= –20V
DD
SS
DD
SS
V
SOURCE OFF
0
–40
–20
0
20
40
60
80
100
120
–15
–10
–5
0
5
10
15
TEMPERATURE (°C)
V
(V)
S
Figure 24. tTRANSITION Times vs. Temperature
Figure 26. ADG5208 Capacitance vs. Source Voltage, 15 V Dual Supply
40
35
30
25
20
15
10
5
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
0
–15
–10
–5
0
5
10
15
V
(V)
S
Figure 25. ADG5209 Capacitance vs. Source Voltage, 15 V Dual Supply
Rev. A | Page 15 of 24
ADG5208/ADG5209
TEST CIRCUITS
Data Sheet
I
(OFF)
A
I
(OFF)
A
I
(ON)
A
S
D
D
Sx
D
Sx
D
NC
V
V
D
V
D
S
NC = NO CONNECT
Figure 30. Off Leakage
Figure 27. On Leakage
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
50Ω
Sx
50Ω
I
DS
V
S
D
V
OUT
V1
R
L
50Ω
GND
Sx
D
V
S
V
V
OUT
OFF ISOLATION = 20 log
R
= V1/I
ON
DS
S
Figure 28. On Resistance
Figure 31. Off Isolation
V
V
V
DD
SS
V
V
0.1µF
0.1µF
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
NETWORK
ANALYZER
DD
SS
S1
V
V
DD
SS
V
OUT
R
L
50Ω
D
Sx
50Ω
S2
R
L
V
S
50Ω
D
V
OUT
V
S
R
50Ω
L
GND
GND
V
WITH SWITCH
V
OUT
WITHOUT SWITCH
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
INSERTION LOSS = 20 log
V
V
S
OUT
Figure 29. Channel-to-Channel Crosstalk
Figure 32. Bandwidth
Rev. A | Page 16 of 24
Data Sheet
ADG5208/ADG5209
V
V
V
V
DD
SS
3V
tr < 20ns
tf < 20ns
DD
SS
ADDRESS
DRIVE (V
50%
50%
A0
A1
A2
)
IN
S1
V
S1
0V
V
IN
50Ω
S2 TO S7
tTRANSITION
tTRANSITION
90%
S8
V
S8
ADG5208*
OUTPUT
D
2.0V
EN
OUTPUT
GND
300Ω
35pF
90%
*
SIMILAR CONNECTION FOR ADG5209.
Figure 33. Address to Output Switching Times, tTRANSITION
V
V
V
DD
SS
3V
V
DD
SS
ADDRESS
A0
A1
A2
DRIVE (V
)
IN
S1
V
S
V
IN
50Ω
0V
S2 TO S7
S8
80%
80%
ADG5208*
OUTPUT
OUTPUT
D
2.0V
EN
GND
300Ω
35pF
tD
*SIMILAR CONNECTION FOR ADG5209.
Figure 34. Break-Before-Make Time Delay, tD
V
V
V
V
DD
SS
SS
3V
DD
A0
A1
A2
ENABLE
DRIVE (V
50%
50%
)
S1
S2 TO S8
V
IN
S
0V
ADG5208*
tON (EN)
tOFF (EN)
OUTPUT
0.9V
D
EN
OUT
OUTPUT
V
35pF
IN
50Ω
GND
300Ω
0.1V
OUT
*SIMILAR CONNECTION FOR ADG5209.
Figure 35. Enable Delay, tON (EN), tOFF (EN)
Rev. A | Page 17 of 24
ADG5208/ADG5209
Data Sheet
V
V
V
V
DD
SS
DD
SS
3V
A0
A1
A2
V
V
IN
ADG5208*
R
S
S
D
OUT
V
OUT
ΔV
OUT
EN
C
1nF
L
V
Q
= C × ΔV
OUT
S
INJ
L
GND
V
IN
*SIMILAR CONNECTION FOR ADG5209.
Figure 36. Charge Injection
Rev. A | Page 18 of 24
Data Sheet
ADG5208/ADG5209
TERMINOLOGY
IDD
CIN
IN represents digital input capacitance.
ON (EN)
ON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
OFF (EN)
OFF (EN) represents the delay time between the 50% and 90%
I
DD represents the positive supply current.
C
ISS
t
t
I
SS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
t
t
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal D and
tTRANSITION
Terminal S.
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
Break-Before-Make Time Delay (tD)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range is represented by RFLAT (ON)
.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Charge Injection
ID (Off)
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
VINL
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH represent the low and high input currents of the
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
V
I
I
On Response
On response is the frequency response of the on switch.
digital inputs.
AC Power Supply Rejection Ratio (ACPSRR)
CD (Off)
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of signal on the output to the amplitude of the
modulation is the ACPSRR.
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. A | Page 19 of 24
ADG5208/ADG5209
Data Sheet
TRENCH ISOLATION
NMOS
PMOS
In the ADG5208/ADG5209, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and the
result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
P WELL
N WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 37. Trench Isolation
Rev. A | Page 20 of 24
Data Sheet
ADG5208/ADG5209
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persist until the power supply is
turned off. The ADG5208/ADG5209 high voltage switches
allow single-supply operation from 9 V to 40 V and dual-supply
operation from 9 V to 22 V.
Rev. A | Page 21 of 24
ADG5208/ADG5209
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 39. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-16
RU-16
CP-16-17
CP-16-17
RU-16
ADG5208BRUZ
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
ADG5208BRUZ-RL7
ADG5208BCPZ-RL7
ADG5209BCPZ-RL7
ADG5209BRUZ
ADG5209BRUZ-RL7
RU-16
1 Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
Data Sheet
NOTES
ADG5208/ADG5209
Rev. A | Page 23 of 24
ADG5208/ADG5209
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09917-0-3/12(A)
Rev. A | Page 24 of 24
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