ADG513BRZ [ADI]
LC2MOS Precision 5V/3V Quad SPST Switches;型号: | ADG513BRZ |
厂家: | ADI |
描述: | LC2MOS Precision 5V/3V Quad SPST Switches 开关 |
文件: | 总11页 (文件大小:127K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LC2MOS
a
Precision 5 V/3 V Quad SPST Switches
ADG511/ADG512/ADG513
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
+3 V, +5 V or ؎5 V Power Supplies
Ultralow Power Dissipation (<0.5 W)
Low Leakage (<100 pA)
Low On Resistance (<50 ⍀)
Fast Switching Times
Low Charge Injection
TTL/CMOS Compatible
16-Lead DIP or SOIC Package
S1
S1
S1
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
D1
S2
D2
S3
D2
S3
D2
S3
ADG511
ADG512
ADG513
D3
S4
D3
S4
D3
S4
APPLICATIONS
Battery Powered Instruments
Single Supply Systems
D4
D4
D4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Remote Powered Equipment
+5 V Supply Systems
Computer Peripherals such as Disk Drives
Precision Instrumentation
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Sample Hold Systems
Communication Systems
Compatible with ؎5 V Supply DACs and ADCs such as
AD7840/8, AD7870/1/2/4/5/6/8
The ADG511, ADG512 and ADG513 contain four indepen-
dent SPST switches. The ADG511 and ADG512 differ only in
that the digital control logic is inverted. The ADG511 switch is
turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG512. The ADG513
contains two switches whose digital control logic is similar to
that of the ADG511 while the logic is inverted in the remaining
two switches.
PRODUCT HIGHLIGHTS
1. +5 Volt Single Supply Operation
GENERAL DESCRIPTION
The ADG511/ADG512/ADG513 offers high performance,
including low on resistance and wide signal range, fully
specified and guaranteed with +3 V, ±5 V as well as +5 V
supply rails.
The ADG511, ADG512 and ADG513 are monolithic CMOS
ICs containing four independently selectable analog switches.
These switches feature low, well-controlled on resistance and
wide analog signal range, making them ideal for precision
analog signal switching.
2. Ultralow Power Dissipation
CMOS construction ensures ultralow power dissipation.
These switch arrays are fabricated using Analog Devices’
advanced linear compatible CMOS (LC2MOS) process which
offers the additional benefits of low leakage currents, ultralow
power dissipation and low capacitance for fast switching speeds
with minimum charge injection. These features make the
ADG511, ADG512 and ADG513 the optimum choice for a
wide variety of signal switching tasks in precision analog signal
processing and data acquisition systems.
3. Low RON
4. Break-Before-Make Switching
Switches are guaranteed to have break-before-make opera-
tion. This allows multiple outputs to be tied together for
multiplexer applications without the possibility of momentary
shorting between channels.
The ability to operate from single +3 V, +5 V or ±5 V bipolar
supplies make the ADG511, ADG512 and ADG513 perfect for
use in battery-operated instruments, 4–20 mA loop systems and
with the new generation of DACs and ADCs from Analog
Devices. The use of 5 V supplies and reduced operating currents
give much lower power dissipation than devices operating from
±15 V supplies.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
ADG511/ADG512/ADG513–SPECIFICATIONS1
Dual Supply(VDD = +5 V ؎ 10%, VSS = –5 V ؎ 10%, GND = 0 V, unless otherwise noted)
B Versions
–40؇C to
T Versions
–55؇C to
Parameter
+25؇C
+85؇C
+25؇C
+125؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
VDD to VSS
50
VDD to VSS
50
V
30
30
Ω typ
Ω max
VD = ±3.5 V, IS = –10 mA;
VDD = +4.5 V, VSS = –4.5 V
LEAKAGE CURRENTS
VDD = +5.5 V, VSS = –5.5 V
Source OFF Leakage IS (OFF)
±0.025
±0.1
±0.025
±0.1
±0.05
±0.2
±0.025
±0.1
±0.025
±0.1
±0.05
±0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = ±4.5 V, VS = ϯ4.5 V;
Test Circuit 2
VD = ±4.5 V, VS = ϯ4.5 V;
Test Circuit 2
VD = VS = ±4.5 V;
Test Circuit 3
±2.5
±2.5
±5
±2.5
±2.5
±5
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
0.005
0.005
µA typ
VIN = VINL or VINH
±0.1
±0.1
µA max
DYNAMIC CHARACTERISTICS2
tON
200
120
100
11
200
120
100
11
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω. CL = 35 pF;
VS = ±3 V; Test Circuit 4
RL = 300 Ω. CL = 35 pF;
VS = ±3 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +3 V; Test Circuit 5
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
375
150
375
150
tOFF
Break-Before-Make Time
Delay, tD (ADG513 Only)
Charge Injection
pC typ
dB typ
dB typ
OFF Isolation
68
68
Channel-to-Channel Crosstalk
85
85
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
VDD
VSS
IDD
+4.5/5.5
–4.5/–5.5
+4.5/5.5
–4.5/–5.5
V min/max
V min/max
µA typ
µA max
µA typ
0.0001
0.0001
0.0001
0.0001
VDD = +5.5 V, VSS = –5.5 V
Digital Inputs = 0 V or 5 V
1
1
1
1
ISS
µA max
NOTES
1Temperature ranges are as follows: B Versions –40°C to +85°C; T Versions –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. B
ADG511/ADG512/ADG513
(VDD = +5 V ؎ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
Single Supply
B Versions
–40؇C to
T Versions
–55؇C to
Parameter
+25؇C
+85؇C
+25؇C
+125؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
0 V to VDD
75
0 V to VDD
75
V
Ω typ
Ω max
45
45
VD = +3.5 V, IS = –10 mA;
VDD = +4.5 V
LEAKAGE CURRENTS
VDD = +5.5 V
Source OFF Leakage IS (OFF)
±0.025
±0.1
±0.025
±0.1
±0.05
±0.2
±0.025
±0.1
±0.025
±0.1
±0.05
±0.2
nA typ
VD = 4.5/1 V, VS = 1ր4.5 V;
Test Circuit 2
VD = 4.5/1 V, VS = 1ր4.5 V;
Test Circuit 2
VD = VS = +4.5 V/+1 V;
Test Circuit 3
±2.5
±2.5
±5
±2.5
±2.5
±5
nA max
nA typ
nA max
nA typ
nA max
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
0.005
0.005
µA typ
VIN = VINL or VINH
±0.1
±0.1
µA max
DYNAMIC CHARACTERISTICS2
tON
250
50
250
50
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF;
VS = +2 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = +2 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +2 V; Test Circuit 5
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 6
500
100
500
100
tOFF
Break-Before-Make Time
Delay, tD (ADG513 Only)
Charge Injection
200
16
200
16
pC typ
dB typ
dB typ
OFF Isolation
68
68
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Channel-to-Channel Crosstalk
85
85
Test Circuit 8
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
VDD
IDD
+4.5/5.5
1
+4.5/5.5
1
V min/max
µA typ
µA max
0.0001
0.0001
VDD = +5.5 V
Digital Inputs = 0 V or 5 V
NOTES
1Temperature ranges are as follows: B Versions –40°C to +85°C; T Versions –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
–3–
ADG511/ADG512/ADG513–SPECIFICATIONS1
(VDD = +3.3 V ؎ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
Single Supply
B Versions
0؇C to
+70؇C
Parameter
+25؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
0 V to VDD
500
V
200
Ω typ
Ω max
VD = +1.5 V, IS = –1 mA;
VDD = +3 V
LEAKAGE CURRENTS
VDD = +3.6 V
Source OFF Leakage IS (OFF)
±0.025
±0.1
±0.025
±0.1
±0.05
±0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 2.6/1 V, VS = 1ր2.6 V;
Test Circuit 2
VD = 2.6/1 V, VS = 1ր2.6 V;
Test Circuit 2
VD = VS = +2.6 V/+1 V;
Test Circuit 3
±2.5
±2.5
±5
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
µA typ
VIN = VINL or VINH
±0.1
µA max
DYNAMIC CHARACTERISTICS2
tON
600
100
500
11
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF;
VS = +1 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = +1 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +1 V; Test Circuit 5
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
1200
160
tOFF
Break-Before-Make Time
Delay, tD (ADG513 Only)
Charge Injection
pC typ
dB typ
dB typ
OFF Isolation
68
Channel-to-Channel Crosstalk
85
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
VDD
IDD
3/3.6
1
V min/max
µA typ
µA max
0.0001
VDD = +3.6 V
Digital Inputs = 0 V or 3 V
NOTES
1Temperature ranges are as follows: B Versions –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. B
ADG511/ADG512/ADG513
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
V
DD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
Analog, Digital Inputs2 . . . . . . . . . . . VSS –2 V to VDD + 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . +300°C
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG511/ADG512/ADG513 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss
of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model1
Temperature Range2
Package Option3
ADG511BN
ADG511BR
ADG511ABR4
ADG511TQ4
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16A
R-16A
Q-16
ADG512BN
ADG512BR
ADG512ABR4
ADG512TQ4
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16A
R-16A
Q-16
ADG513BN
ADG513BR
ADG513ABR4
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
R-16A
NOTES
1For availability of MIL-STD-883, Class B processed parts, contact factory.
23.3 V specifications apply over 0°C to +70°C temperature range.
3N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.
4Trench isolated latch-up proof parts. See Trench Isolation section.
REV. B
–5–
ADG511/ADG512/ADG513
TERMINOLOGY
PIN CONFIGURATION
(DIP/SOIC)
VDD
VSS
Most positive power supply potential.
Most negative power supply potential in
dual supplies. In single supply applications,
it may be connected to GND.
IN1
D1
S1
IN2
D2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADG511
ADG512
ADG513
GND
S
D
IN
RON
IS (OFF)
Ground (0 V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
Ohmic resistance between D and S.
Source leakage current with the switch
“OFF.”
V
V
DD
SS
TOP VIEW
(Not to Scale)
GND
NC
S3
S4
D4
D3
IN3
IN4
NC = NO CONNECT
ID (OFF)
Drain leakage current with the switch
“OFF.”
Truth Table (ADG511/ADG512)
ID, IS (ON)
Channel leakage current with the switch
“ON.”
Analog voltage on terminals D, S.
“OFF” switch source capacitance.
“OFF” switch drain capacitance.
“ON” switch capacitance.
ADG511
In
ADG512
In
Switch
Condition
VD (VS)
CS (OFF)
0
1
1
0
ON
OFF
C
D (OFF)
CD, CS (ON)
tON
Delay between applying the digital control
input and the output switching on.
Truth Table (ADG513)
Switch
1, 4
Switch
2, 3
tOFF
tD
Delay between applying the digital control
input and the output switching off.
“OFF” or “ON” time measured between the
90% points of both switches when switching
from one address state to another.
Logic
0
1
OFF
ON
ON
OFF
Crosstalk
A measure of unwanted signal which is
coupled through from one channel to an-
other as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” switch.
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
–6–
REV. B
Typical Performance Graphs–ADG511/ADG512/ADG513
50
40
30
20
10mA
V
V
= +5V
= –5V
DD
SS
T
= +25؇C
A
1mA
100A
10A
V
V
= +3V
= –3V
DD
SS
I–, I+
1A
100nA
10nA
V
V
= +5V
= –5V
1 SW
4 SW
DD
SS
10
0
0
–5
–4
–3
–2
–1
1
2
3
4
5
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
Figure 4. Supply Current vs. Input Switching Frequency
Figure 1. On Resistance as a Function of VD (VS) Dual
Supplies
10
50
V
V
V
V
= +5V
= –5V
= ؎5V
= ؎5V
DD
SS
V
V
= +5V
= –5V
DD
SS
S
D
I
(OFF)
D
40
30
20
1
0.1
+125؇C
+85؇C
+25؇C
I
(ON)
D
0.01
0.001
10
0
I
(OFF)
45
S
25
35
55
65
75
85
95
105 115 125
0
–5
–4
–3
–2
–1
1
2
3
4
5
TEMPERATURE – ؇C
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
Figure 5. Leakage Currents as a Function of Temperature
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures
120
90
T
= +25؇C
A
V
V
= +5V
= –5V
DD
SS
80
70
60
50
40
30
20
V
V
= +3V
= 0V
DD
SS
100
80
V
V
= +5V
= 0V
DD
SS
60
40
100
1k
10k
100k
1M
10M
0
1
2
3
4
5
FREQUENCY – Hz
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
Figure 6. Off Isolation vs. Frequency
Figure 3. On Resistance as a Function of VD (VS)
Single Supply
REV. B
–7–
ADG511/ADG512/ADG513
network RC and CC. This compensation network also reduces
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the ±3 V input range.
The acquisition time is 2.5 µs while the settling time is 1.85 µs.
0.008
V
V
= +5V
= –5V
= +25؇C
DD
SS
I
(ON)
0.004
0.002
D
T
A
I
(OFF)
(OFF)
D
+5V
0.000
I
2200pF
S
+5V
SW2
–0.002
–0.004
–0.006
+5V
AD845
–5V
S
S
D
D
C
C
1000pF
R
V
OUT
C
OP07
–5V
V
IN
SW1
75⍀
C
H
2200pF
–5
–4
–3
–2
–1
0
1
2
3
4
5
ADG511
ADG512
ADG513
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
Figure 7. Leakage Currents as a Function of VD (VS)
–5V
Figure 9. Accurate Sample-and-Hold
110
V
V
= +5V
= –5V
DD
SS
TRENCH ISOLATION
100
90
80
70
60
The MOS devices that make up the ADG511A/ADG512A/
ADG513A are isolated from each other by an oxide layer
(trench) (see Figure 10). When the NMOS and PMOS devices
are not electrically isolated from each other, there exists the
possibility of “latch-up” caused by parasitic junctions between
CMOS transistors. Latch-up is caused when P-N junctions that
are normally reverse biased, become forward biased, causing
large currents to flow. This can be destructive.
CMOS devices are normally isolated from each other by
Junction Isolation. In Junction Isolation the N and P wells of the
CMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR)-type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With Trench Isolation, this diode is removed; the
result is a latch-up-proof circuit.
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 8. Crosstalk vs. Frequency
APPLICATION
Figure 9 illustrates a precise sample-and-hold circuit. An AD845
is used as the input buffer while the output operational amplifier
is an OP07. During the track mode, SW1 is closed and the
output VOUT follows the input signal VIN. In the hold mode,
SW1 is opened and the signal is held by the hold capacitor CH.
V
V
G
G
V
V
V
V
D
S
D
S
T
P-CHANNEL
T
N-CHANNEL
T
+
+
+
+
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG511/ADG512/
ADG513 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 15 µV/µs.
P
N
P
N
N
R
E
N
C
H
R
E
N
C
H
R
E
N
C
H
–
–
P
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp OP07, which will minimize charge
injection effects. Pedestal error is also reduced by the compensation
Figure 10. Trench Isolation
–8–
REV. B
ADG511/ADG512/ADG513
Test Circuits
I
DS
V1
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
D
S
S
D
S
D
S
D
V
V
V
V
D
S
D
S
V
S
R
= V1/I
DS
ON
1. On Resistance
2. Off Leakage
3. On Leakage
V
V
DD
0.1F
3V
ADG511
DD
V
50%
50%
50%
50%
IN
S
D
V
OUT
3V
ADG512
V
R
C
L
IN
L
V
S
35pF
300⍀
IN
90%
90%
V
V
OUT
GND
SS
0.1F
tON
tOFF
V
SS
4. Switching Times
V
V
DD
0.1F
3V
V
IN
50%
50%
DD
0V
0V
S1
D1
D2
V
V
S1
OUT1
90%
90%
V
V
OUT1
R
C
L1
35pF
L1
V
OUT2
S2
300⍀
V
S2
R
C
L2
35pF
IN1, IN2
L2
300⍀
90%
V
90%
GND
SS
V
OUT2
IN
0V
tD
tD
0.1F
V
SS
5. Break-Before-Make Time Delay
V
V
DD
3V
DD
V
R
IN
S
S
D
V
OUT
C
10nF
L
V
S
IN
V
OUT
⌬V
OUT
V
V
GND
SS
Q
= C
؋
⌬V L OUT
INJ
SS
6. Charge Injection
–9–
REV. B
ADG511/ADG512/ADG513
Test Circuits (continued)
V
V
DD
DD
V
V
DD
DD
0.1F
0.1F
50⍀
S
D
S
D
V
OUT
V
IN1
R
50⍀
L
V
S
V
IN2
IN
V
V
S
IN
D
S
V
OUT
NC
V
V
GND
SS
GND
SS
R
L
50⍀
CHANNEL TO CHANNEL
CROSSTALK = 20
؋
LOG V /V 0.1F
0.1F
S
OUT
V
V
SS
SS
7. Off Isolation
8. Channel-to-Channel Crosstalk
–10–
REV. B
ADG511/ADG512/ADG513
OUTLINE DIMENSIONS
Dimensions are shown in inches and (mm).
16-Lead Plastic DIP
(N-16)
0.840 (21.34)
0.745 (18.92)
16
1
9
0.280 (7.11)
0.240 (6.10)
8
0.325 (8.26)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
PLANE
0.045 (1.15)
16-Lead Cerdip
(Q-16)
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.310 (7.87)
0.220 (5.59)
8
1
0.320 (8.13)
0.290 (7.37)
PIN 1
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
15°
0°
0.030 (0.76)
16-Lead SOIC
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
16
9
8
0.1574 (4.00)
0.2440 (6.20)
0.2284 (5.80)
1
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45؇
0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. B
–11–
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