ADG3248BKS-REEL [ADI]
2.5 V/ 3.3 V, 2 :1 Multiplexer/ Demultiplexer Bus Switch; 2.5 V / 3.3 V ， 2 ： 1多路复用器/多路解复用器总线开关
| 型号： | ADG3248BKS-REEL |
| 厂家： | 
ADI |
| 描述： | 2.5 V/ 3.3 V, 2 :1 Multiplexer/ Demultiplexer Bus Switch |
| 文件： | 总12页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch
ADG3248
FEATURES
FUNCTIONAL BLOCK DIAGRAM
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.244 Gbps
ADG3248
A0
2.5 V/3.3 V Supply Operation
Level Translation
B
A1
3.3 V to 2.5 V
2.5 V to 1.8 V
IN
Small Signal Bandwidth 610 MHz
6-Lead SC70 Package
SWITCHES SHOWN FOR A LOGIC 0 INPUT
APPLICATIONS
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Docking Stations
Memory Switching
Analog Switch Applications
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3248 is a 2.5 V or 3.3 V, high performance 2:1 multi-
plexer/demultiplexer. It is designed on a low voltage CMOS
process, which provides low power dissipation yet gives high
switching speed and very low on resistance. This allows the input
to be connected to the output without additional propagation
delay or generating additional ground bounce noise.
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Tiny SC70 package.
Each switch of the ADG3248 conducts equally well in both direc-
tions when on. The ADG3248 exhibits break-before-make
switching action, preventing momentary shorting when switch-
ing channels.
The ADG3248 is available in a tiny 6-lead SC70 package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless
ADG3248–SPECIFICATIONS1 otherwise noted.)
B Version
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
VINL
VINL
II
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
µA
µA
µA
V
Input Low Voltage
0.8
0.7
1
1
1
Input Leakage Current
0.01
0.01
0.01
2.5
OFF State Leakage Current
ON State Leakage Current
Maximum Pass Voltage
IOZ
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = 3.3 V, IO = –5 µA
VA/VB = VCC = 2.5 V, IO= –5 µA
VP
2.0
1.5
2.9
2.1
1.8
V
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
CA OFF
CB OFF
CA, CB ON f = 1 MHz
f = 1 MHz
f = 1 MHz
3.5
4.5
8.5
4
pF
pF
pF
pF
CIN
f = 1 MHz
SWITCHING CHARACTERISTICS3
4
Propagation Delay A to B or B to A, tPD
tPHL, tPLH
CL = 50 pF, VCC = 3 V
0.225 ns
Propagation Delay Matching5
Transition Time
5
ps
tTRANS
tBBM
RL = 510 Ω, CL = 50 pF
RL = 510 Ω, CL = 50 pF
VCC = 3.3 V; VA/VB = 2 V
16
10
1.244
45
29
ns
ns
Gbps
ps p-p
Break-before-Make Time
Maximum Data Rate
Channel Jitter
5
V
CC = 3.3 V; VA/VB = 2 V
DIGITAL SWITCH
On Resistance
RON
VCC = 3 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, VA = 1.7 V, IBA = 8 mA
4.5
12
5
9
0.1
8
28
9
18
0.5
Ω
Ω
Ω
Ω
Ω
V
CC = 2.3 V, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, VA = 0 V, IA = 8 mA
On Resistance Matching
⌬RON
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
2.3
3.6
1
V
µA
ICC
Digital Inputs = 0 V or VCC
0.01
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Typical values are at 25°C, unless otherwise stated.
3Guaranteed by design, not subject to production test.
4The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
Specifications subject to change without notice.
–2–
REV. 0
ADG3248
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
PIN CONFIGURATION
6-Lead SC70
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel
Operating Temperature Range
1
2
3
IN
V
A0
6
5
4
ADG3248
TOP VIEW
(Not to Scale)
GND
A1
CC
B
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Table I. Pin Function Descriptions
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 332°C/W
Pin No.
Mnemonic
Description
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
1
2
3
4
5
6
A0
GND
A1
Port A0, Input or Output
Ground Reference
Port A1, Input or Output
Port B, Input or Output
Positive Power Supply Voltage
Channel Select
B
VCC
IN
Table II. Truth Table
IN
Function
L
H
B = A0
B = A1
ORDERING GUIDE
Temperature
Range
Package
Description
Model
Package Branding
ADG3248BKS-R2
ADG3248BKS-REEL
ADG3248BKS-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
SC70 (Thin Shrink Small Outline Transistor Package)
SC70 (Thin Shrink Small Outline Transistor Package)
SC70 (Thin Shrink Small Outline Transistor Package)
KS-6
KS-6
KS-6
SMA
SMA
SMA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3248 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–
ADG3248
TERMINOLOGY
VCC
GND
VINH
VINL
II
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
IOZ
IOL
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
VP
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
RON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬RON
CX OFF
CX ON
CIN
ON Resistance Match between Any Two Channels, i.e., RON max – RON min.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of IN.
ICC
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
t
PLH, tPHL
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON × CL, where CL is the load capacitance.
tBBM
On or Off time measured between the 90% points of both switches when switching from one to another.
tTRANS
Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the
OUT signal.
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
–4–
REV. 0
Typical Performance Characteristics–ADG3248
40
35
30
25
40
35
30
25
20
15
10
5
20
T
= 25؇C
A
T
= 25؇C
= 3.3V
CC
V
A
V
= 3V
V
= 2.3V
CC
CC
15
10
5
V
= 3.3V
V
= 2.5V
= 2.7V
CC
CC
20
15
10
5
؉85؇C
V
CC
V
= 3.6V
CC
؉25؇C
؊40؇C
0
0
0
0
0.5
1.0
1.5
2.0
/V (V
2.5
3.0 3.5
1.0
V /V (V)
A
2.0
0
0.5
1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
)
V
/V (V)
A
B
B
A
B
TPC 1. On Resistance vs.
Input Voltage
TPC 2. On Resistance vs.
Input Voltage
TPC 3. On Resistance vs. Input
Voltage for Different Temperatures
2.5
15
10
5
3.0
2.5
V
= 3.6V
T = 25؇C
A
O
CC
V
= 2.5V
T
= 25؇C
= –5A
CC
A
V
= 2.7V
= 2.5V
CC
I
= –5A
I
O
2.0
1.5
1.0
0.5
2.0
1.5
V
= 3.3V
CC
؉85؇C
V
CC
V
= 3V
CC
V
= 2.3V
CC
1.0
0.5
0
؊40؇C
؉25؇C
0
0
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0 2.5
/V (V)
3.0 3.5
0
0.5
V
1.0
1.2
V
V
A
B
A
B
/V (V)
A
B
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
TPC 5. Pass Voltage vs. VCC
TPC 6. Pass Voltage vs. VCC
3.0
3.0
2.5
2.0
1.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
T
= 25؇C
T
V
= 25؇C
= 0V
T
V
= 25؇C
= V
CC
A
A
A
ON = OFF
= 1nF
A
A
2.5
2.0
1.5
1.0
C
V
= 2.5V
L
CC
V
= 3.3V
CC
V
= 2.5V
CC
1.0
V
= 2.5V
CC
V
= 3.3V
CC
0.5
0
0.5
0
V
= 3.3V
CC
0
0.02
0.04
0.06
(A)
0.08
0.10
–0.10 –0.08
–0.06
–0.04
(A)
–0.02
0
0
0.5
1.0
1.5
V
2.0
/V (V)
2.5
3.0
3.5
I
I
O
A
B
O
TPC 7. Output Low Characteristic
TPC 8. Output High Characteristic
TPC 9. Charge Injection vs.
Source Voltage
REV. 0
–5–
ADG3248
1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
V
= 25؇C
T = 25؇C
A
A
0
= 3.3V/2.5V
V
= 3.3V/2.5V
CC
CC
= 0dBm
V = 0dBm
IN
IN
–1
–2
–3
–4
N/W ANALYZER:
R
N/W ANALYZER:
= R = 50⍀
R
= R = 50⍀
L
S
L
S
T
= 25؇C
A
–5
–6
–7
–8
V
V
= 3.3V/2.5V
= 0dBm
CC
IN
N/W ANALYZER:
R
= R = 50⍀
L
S
0.03 0.1
1.0
10
100
1000
0.03 0.1
1.0
10
100
1000
0.03 0.1
1.0
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 10. Bandwidth vs. Frequency
TPC 11. Crosstalk vs. Frequency
TPC 12. Off Isolation vs.
Frequency
25
100
100
V
= 3.3V
CC
90
80
70
60
50
40
30
20
10
0
95
90
85
80
75
V
= 1.5V p-p
A
V
= 3.3V
= 1.5V p-p
CC
V
= 2.5V
20dB ATTENUATION
CC
20
15
10
5
V
A
20dB ATTENUATION
V
= 3.3V
CC
70
65
60
55
50
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD)
؋
100% 0
–40
–20
0
20
40
60
80 85
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
DATA RATE (Gbps)
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
TEMPERATURE (؇C)
DATA RATE (Gbps)
TPC 13. Transition Time vs.
Temperature
TPC 14. Jitter vs. Data Rate;
PRBS 31
TPC 15. Eye Width vs. Data Rate;
PRBS 31
V
V
= 3.3V
20dB
ATTENUATION
T = 25؇C
A
V
V
= 2.5V
20dB
ATTENUATION
T = 25؇C
A
CC
CC
38.7mV/DIV
133.7ps/DIV
20mV/DIV
166.3ps/DIV
= 2V p-p
= 1V p-p
IN
IN
TPC 16. Eye Pattern; 1.244 Gbps,
VCC = 3.3 V, PRBS 31
TPC 17. Eye Pattern; 1 Gbps,
VCC = 2.5 V, PRBS 31
–6–
REV. 0
ADG3248
V
BUS SWITCH APPLICATIONS
OUT
3.3V SUPPLY
Mixed Voltage Operation, Level Translation
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3248 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly
to 2.5 V.
2.5V
V
IN
0V
SWITCH
INPUT
3.3V
Figure 1 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V toler-
ant inputs, therefore placing the ADG3248 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
Figure 3. 3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Translation
When VCC is 2.5 V and the input signal range is 0 V to VCC, the
maximum output signal will, as before, be clamped to within a
voltage threshold below the VCC supply. In this case, the output
will be limited to approximately 1.8 V, as shown in Figure 5.
3.3V
3.3V
2.5V
2.5V
2.5V
3.3V ADC
MICROPROCESSOR
ADG3248
2.5V
1.8V
Figure 1. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
Figure 4. 2.5 V to 1.8 V Voltage Translation
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to within a voltage
threshold below the VCC supply.
V
OUT
2.5V SUPPLY
1.8V
In this case, the output will be limited to 2.5 V, as shown in
Figure 3. This device can be used for translation from 2.5 V to
3.3 V devices and also between two 3.3 V devices.
3.3V
V
IN
0V
SWITCH
INPUT
2.5V
3.3V
2.5V
2.5V
2.5V
Figure 5. 2.5 V to 1.8 V Voltage Translation
Analog Switching
ADG3248
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
Figure 2. 3.3 V to 2.5 V Voltage Translation
REV. 0
–7–
ADG3248
Multiplexing
MEMORY
ADDRESS
DATA
MEMORY
BANK A
Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common prob-
lems faced by designers of these systems include
MEMORY
BANK B
•
•
Large delays caused by capacitive loading of the bus
Noise due to simultaneous switching of the address and data
bus signals
MEMORY
BANK C
Figure 6 shows an array of memory banks in which each address
and data signal is loaded by the sum of the individual loads. If
a bus switch is used as shown in Figure 7, the output load on
the memory address and data bits is halved. The speed at which
the selected bank’s data can flow is much improved
MEMORY
BANK D
Figure 6. All Memory Banks Are Permanently
Connected to the Bus
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.
MEMORY
BANK A
MEMORY
ADDRESS
DATA
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
Figure 7. ADG3248 Used to Reduce Both Access
Time and Noise
–8–
REV. 0
ADG3248
OUTLINE DIMENSIONS
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
2.00 BSC
6
5
2
4
3
2.10 BSC
1.25 BSC
1
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
1.10 MAX
0.22
0.08
0.46
0.36
0.26
8؇
4؇
0؇
0.30
0.15
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB
REV. 0
–9–
–10–
–11–
–12–
相关型号：
©2020 ICPDF网 联系我们和版权申明