ADG3249BRJ-REEL7 [ADI]
2.5 V/3.3 V, 2:1 Multiplexer/ Demultiplexer Bus Switch; 2.5 V / 3.3 V ， 2 ： 1多路复用器/多路解复用器总线开关
| 型号： | ADG3249BRJ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 2.5 V/3.3 V, 2:1 Multiplexer/ Demultiplexer Bus Switch |
| 文件： | 总12页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch
ADG3249
FEATURES
FUNCTIONAL BLOCK DIAGRAM
225 ps Propagation Delay through the Switch
4.5 ꢀ Switch Connection between Ports
Data Rate 1.244 Gbps
ADG3249
A0
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
B
A1
CONTROL
LOGIC
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
IN EN
Small Signal Bandwidth 610 MHz
8-Lead SOT-23 Package
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Docking Stations
Memory Switching
Analog Switch Applications
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3249 is a 2.5 V or 3.3 V, high performance 2:1 multi-
plexer/demultiplexer bus switch. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
input to be connected to the output without additional propaga-
tion delay or generating additional ground bounce noise.
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Tiny SOT-23 package.
Each switch of the ADG3249 conducts equally well in both direc-
tions when on. The ADG3249 exhibits break-before-make
switching action, preventing momentary shorting when switch-
ing channels.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from
3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device
is operated from 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition, a level
translating pin (SEL) is included. When SEL is low, VCC is
reduced internally, allowing for level translating between 3.3 V
inputs and 1.8 V outputs.
The ADG3249 is available in a tiny 8-lead SOT-23 package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX
,
ADG3249–SPECIFICATIONS1 unless otherwise noted.)
B Version
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
VINL
VINL
II
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
µA
µA
µA
V
V
V
Input Low Voltage
0.8
0.7
1
1
1
2.9
2.1
2.1
Input Leakage Current
0.01
0.01
0.01
2.5
1.8
1.8
OFF State Leakage Current
ON State Leakage Current
Maximum Pass Voltage
IOZ
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = SEL = 3.3 V, IO = –5 µA
VA/VB = VCC = SEL = 2.5 V, IO= –5 µA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA
VP
2.0
1.5
1.5
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
CA OFF
f = 1 MHz; EN = VCC
f = 1 MHz; EN = VCC
3.5
4.5
8.5
4
pF
pF
pF
pF
pF
C
B OFF
CA, CB ON f = 1 MHz
CIN, CSEL
CEN
f = 1 MHz
f = 1 MHz
6.5
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD
4
tPHL, tPLH
CL = 50 pF, VCC = SEL = 3 V
0.225 ns
Propagation Delay Matching5
Bus Enable Time EN to A or B6
Bus Disable Time EN to A or B6
Bus Enable Time EN to A or B6
Bus Disable Time EN to A or B6
Bus Enable Time EN to A or B6
Bus Disable Time EN to A or B6
Break-before-Make Time
5
ps
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
tBBM
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = 2.3 V to 2.7 V; SEL = VCC
RL = 510 Ω, CL = 50 pF
1
1
1
1
1
1
5
3.5
5.5
3.2
4.5
3.5
4
4.8
8.2
4.5
7.7
4.6
5.8
ns
ns
ns
ns
ns
ns
10
ns
Transition Time
tTRANS
RL = 510 Ω, CL = 50 pF; SEL = VCC
RL = 510 Ω, CL = 50 pF; SEL = 0 V
VCC = SEL = 3.3 V; VA/VB = 2 V
VCC = SEL = 3.3 V; VA/VB = 2 V
16
15
1.244
45
29
22
ns
ns
Gbps
ps p-p
Maximum Data Rate
Channel Jitter
DIGITAL SWITCH
On Resistance
RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
4.5
12
5
9
5
12
0.1
0.1
8
28
9
18
8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
V
CC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V VA = 0 V, IBA = 8 mA
V
CC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
On Resistance Matching
⌬RON
VCC = 3 V, SEL = VCC, VA = 0 V, IA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IA = 8 mA
0.5
0.5
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
2.3
3.6
1
0.2
8
V
ICC
Digital Inputs = 0 V or VCC; SEL = VCC
Digital Inputs = 0 V or VCC; SEL = 0 V
VCC = 3.6 V, EN = 3.0 V; SEL = VCC; IN = VCC
0.01
0.1
0.15
µA
mA
µA
Increase in ICC per Input7
NOTES
⌬ICC
1Temperature range is as follows: B Version: –40°C to +85°C.
2Typical values are at 25°C, unless otherwise stated.
3Guaranteed by design, not subject to production test.
4The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6See Timing Measurement Information section.
7This current applies to the control pin EN only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. 0
ADG3249
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
PIN CONFIGURATION
8-Lead SOT-23
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel
Operating Temperature Range
1
2
3
4
EN
8
7
6
5
V
CC
ADG3249
SEL
IN
A0
A1
TOP VIEW
(Not to Scale)
GND
B
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Table I. Pin Function Descriptions
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206°C/W
Pin No.
Mnemonic
Description
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
1
2
3
4
5
6
7
8
EN
A0
A1
GND
B
IN
Enable (Active Low)
Port A0, Input or Output
Port A1, Input or Output
Ground Reference
Port B, Input or Output
Channel Select
SEL
VCC
Level Translation Select
Positive Power Supply Voltage
Table II. Truth Table
SEL* FUNCTION
EN
IN
H
L
L
L
L
X
L
L
H
H
X
L
H
L
Disconnect
A0 = B; 3.3 V to 1.8 V Level Shifting
A0 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
A1 = B; 3.3 V to 1.8 V Level Shifting
H
A1 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
*SEL = 0 V only when VDD = 3.3 V ꢁ 10%
ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Branding
ADG3249BRJ-R2
ADG3249BRJ-REEL
ADG3249BRJ-REEL7 –40°C to +85°C
–40°C to +85°C
–40°C to +85°C
SOT-23 (Small Outline Transistor Package)
SOT-23 (Small Outline Transistor Package)
SOT-23 (Small Outline Transistor Package)
RJ-8
RJ-8
RJ-8
SHA
SHA
SHA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3249 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–
ADG3249
TERMINOLOGY
VCC
GND
VINH
VINL
II
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
IOZ
IOL
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
VP
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
RON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬RON
CX OFF
CX ON
ON Resistance Match between Any Two Channels, i.e., RON max to RON min.
OFF Switch Capacitance.
ON Switch Capacitance.
CIN, CSEL, CEN Control Input Capacitance. This consists of IN, SEL, and EN.
ICC
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
⌬ICC
Extra power supply current component for the EN control input when the input is not driven at the supplies.
t
t
t
PLH, tPHL
PZH, tPZL
PHZ, tPLZ
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON × CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, EN.
Bus Disable Times. These are the time taken to place the switch in the high impedance OFF state in response to the
control signal. They are measured as the time taken for the output voltage to change by V⌬ from the original
quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable
and disable times.)
tBBM
On or Off Time. Measured between the 90% points of both switches when switching fom one to another.
tTRANS
Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the
OUT signal.
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
–4–
REV. 0
Typical Performance Characteristics–ADG3249
40
35
30
25
40
35
30
25
20
15
10
5
40
V = 3V
CC
V
= 3V
V
= 2.3V
CC
T
= 25ꢂC
CC
T
= 25ꢂC
A
T
= 25ꢂC
35
30
25
20
15
10
5
A
A
SEL = 0V
SEL = V
SEL = V
CC
CC
V
= 3.3V
= 3.6V
V
= 3.3V
V
= 2.5V
= 2.7V
CC
CC
CC
20
15
10
5
V
CC
V
CC
V
= 3.6V
CC
0
0
0
0
0.5
1.0
1.5
2.0
)
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
/V (V
2.5
3.0 3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
/V (V
V
)
A
B
V
/V (V)
A
B
A
B
TPC 1. On Resistance vs.
Input Voltage
TPC 3. On Resistance vs.
Input Voltage
TPC 2. On Resistance vs.
Input Voltage
3.0
2.5
20
15
10
5
15
10
5
V
= 3.6V
T
= 25ꢂC
CC
V
= 3.3V
A
CC
V
= 2.5V
CC
SEL = V
CC
= –5ꢅA
SEL = V
CC
SEL = V
I
CC
O
2.0
1.5
V
= 3.3V
CC
ꢃ85ꢂC
V
= 3V
CC
ꢃ85ꢂC
1.0
0.5
0
ꢄ40ꢂC
ꢃ25ꢂC
ꢃ25ꢂC
ꢄ40ꢂC
0
0
0
0.5
1.0
1.5
2.0 2.5
/V (V)
3.0 3.5
1.0
/V (V)
2.0
0
0.5
1.5
0
0.5
V
1.0
1.2
V
V
A
B
A
B
/V (V)
A
B
TPC 4. On Resistance vs. Input
TPC 5. On Resistance vs. Input
TPC 6. Pass Voltage vs. VCC
Voltage for Different Temperatures
Voltage for Different Temperatures
2.5
2.5
300
250
200
150
100
50
T
= 25ꢂC
A
T
= 25ꢂC
T
= 25ꢂC
A
A
V
= 2.7V
= 2.5V
V
= 3.6V
CC
CC
SEL = V
SEL = 0V
= –5ꢅA
CC
= –5ꢅA
2.0
1.5
1.0
0.5
2.0
1.5
1.0
0.5
I
I
O
O
V
= SEL = 3.3V
CC
V
= 3.3V
CC
V
CC
SEL = 0V
V
= 3.3V
CC
V
= 2.3V
V
= 3V
CC
CC
V
= SEL = 2.5V
CC
0
0
0
0
0.5
1.0
1.5
2.0
/V (V)
2.5
3.0 3.5
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
0
5
10 15 20 25 30 35 40 45 50
ENABLE FREQUENCY (MHz)
V
V
A
B
A
B
TPC 7. Pass Voltage vs. VCC
TPC 8. Pass Voltage vs. VCC
TPC 9. ICC vs. Enable Frequency
REV. 0
–5–
ADG3249
3.0
3.0
2.5
2.0
1.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
T
= 25ꢂC
T
V
= 25ꢂC
T = 25ꢂC
A
A
A
V
= 0V
= V
SEL = V
CC
A
A CC
2.5
2.0
1.5
1.0
ON = OFF
= INF.
V
= 2.5V
EN = 0
EN = 0
CC
C
L
V
= SEL = 3.3V
CC
V
= 3.3V; SEL = 0V
CC
V
= SEL = 3.3V
CC
1.0
V
= SEL = 2.5V
CC
V
= 3.3V
CC
0.5
0
0.5
0
V
= 3.3V; SEL = 0V
CC
V
= SEL = 2.5V
CC
0
0.02
0.04
0.06
(A)
0.08
0.10
–0.10 –0.08
–0.06
–0.04
I (A)
O
–0.02
0
0
0.5
1.0
1.5
V
2.0
/V (V)
2.5
3.0
3.5
I
O
A
B
TPC 11. Output High Characteristic
TPC 10. Output Low Characteristic
TPC 12. Charge Injection vs.
Source Voltage
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
0
T
V
= 25ꢂC
T
V
= 25ꢂC
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 3.3V/2.5V
= 3.3V/2.5V
CC
CC
SEL = V
V
N/W ANALYZER:
R
SEL = V
V
N/W ANALYZER:
R
CC
CC
–1
–2
–3
–4
= 0dBm
= 0dBm
IN
IN
= R = 50ꢀ
= R = 50ꢀ
L
S
L
S
T
V
= 25ꢂC
A
–5
–6
–7
–8
= 3.3V/2.5V
CC
SEL = V
V
N/W ANALYZER:
R
CC
= 0dBm
IN
= R = 50ꢀ
L
S
0.03 0.1
1.0
10
100
1000
0.03 0.1
1.0
10
100
1000
0.03 0.1
1.0
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 13. Bandwidth vs. Frequency
TPC 14. Crosstalk vs. Frequency
TPC 15. Off Isolation vs.
Frequency
6
4.0
100
90
80
70
60
50
40
30
20
10
0
V
= SEL = 3.3V
CC
3.5
DISABLE
DISABLE
5
V
= 1.5V p-p
IN
V
= SEL = 3.3V
V
= SEL = 2.5V
CC
CC
20dB ATTENUATION
3.0
2.5
2.0
1.5
1.0
0.5
0
DISABLE
ENABLE
4
3
2
1
ENABLE
V
= 3.3V, SEL = 0V
CC
ENABLE
0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
DATA RATE (Gbps)
TEMPERATURE (ꢂC)
TEMPERATURE (ꢂC)
TPC 16. Enable/Disable Time
vs. Temperature
TPC 17. Enable/Disable Time
vs. Temperature
TPC 18. Jitter vs. Data Rate;
PRBS 31
–6–
REV. 0
ADG3249
100
95
90
85
80
75
V
= SEL = 3.3V
= 1.5V p-p
CC
V
IN
20dB ATTENUATION
70
65
60
55
50
V
= 3.3V
20dB
ATTENUATION
V
= 2.5V
20dB
ATTENUATION
T = 25ꢂC
A
CC
SEL = 3.3V
= 2V p-p
CC
SEL = 2.5V
= 1V p-p
38.7mV/DIV
133.7ps/DIV
20mV/DIV
166.3ps/DIV
V
T
= 25ꢂC
V
IN
A
IN
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) ꢆ 100%
TPC 20. Eye Pattern; 1.244 Gbps,
VCC = 3.3 V, PRBS 31
TPC 21. Eye Pattern; 1 Gbps,
VCC = 2.5 V, PRBS 31
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
DATA RATE (Gbps)
TPC 19. Eye Width vs. Data
Rate; PRBS 31
REV. 0
–7–
ADG3249
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that is used is VIN and VOUT where
VIN = VA and VOUT = VB or VIN = VB and VOUT = VA
V
V
IH
CC
2 ꢆ V
CC
SW1
CONTROL
INPUT EN
V
T
0V
GND
tPLH
tPLH
R
L
V
V
H
T
V
V
OUT
IN
V
PULSE
GENERATOR
OUT
DUT
V
L
R
R
C
L
L
T
Figure 2. Propagation Delay
NOTES
PULSE GENERATOR FOR ALL PULSES: t
FREQUENCY 10MHz.
2.5ns, t
2.5ns,
R
F
C
R
INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
ISTHETERMINATION RESISTOR, SHOULD BE EQUALTO Z
OFTHE PULSE GENERATOR.
L
T
OUT
Figure 1. Load Circuit
Test Conditions
Symbol
VCC = 3.3 V 0.3 V (SEL = VCC
)
VCC = 2.5 V 0.2 V (SEL = VCC
)
VCC = 3.3 V 0.3 V (SEL = 0 V) Unit
RL
V⌬
CL
VT
500
300
50
500
150
30
500
150
30
Ω
mV
pF
V
1.5
0.9
0.9
DISABLE
ENABLE
V
INH
V
CONTROL INPUT EN
T
Table III. Switch Position
0V
tPZL
tPLZ
Test
S1
V
CC
V
CC
V
OUT
V
tPLZ, tPZL
tPHZ, tPZH
2 × VCC
GND
V
= 0V
= V
T
IN
V
V
+V
ꢇ
L
L
SW1 @ 2V
CC
tPZH
tPHZ
V
V
H
V
OUT
V
–V
V
IN
CC
H
ꢇ
T
SW1 @ GND
0V
0V
Figure 3. Enable and Disable Times
–8–
REV. 0
ADG3249
BUS SWITCH APPLICATIONS
2.5 V to 1.8 V Translation
Mixed Voltage Operation, Level Translation
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3249 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly
to 2.5 V.
When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to VCC, the maximum output signal will, as before, be clamped
to within a voltage threshold below the VCC supply. In this case,
the output will be limited to approximately 1.8 V, as shown
in Figure 8.
2.5V
Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V toler-
ant inputs, therefore placing the ADG3249 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
ADG3249
2.5V
1.8V
Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC
3.3V
3.3V
2.5V
V
OUT
2.5V SUPPLY
SEL = 2.5V
2.5V
1.8V
3.3V ADC
MICROPROCESSOR
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
V
IN
0V
SWITCH
INPUT
2.5V
3.3 V to 2.5 V Translation
When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to VCC, the maximum output signal will be clamped to
within a voltage threshold below the VCC supply. In this case,
the output will be limited to 2.5 V, as shown in Figure 6. This
device can be used for translation from 2.5 V to 3.3 V devices
and also between two 3.3 V devices.
Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3 V to 1.8 V Translation
The ADG3249 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin. The SEL pin is an active low control pin. SEL acti-
vates internal circuitry in the ADG3242 that allows voltage
translation between 3.3 V devices and 1.8 V devices.
3.3V
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
3.3V
2.5V
2.5V
2.5V
ADG3249
SEL is unused, it should be tied directly to VCC
.
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
3.3V
ADG3249
1.8V
V
OUT
3.3V SUPPLY
SEL = 3.3V
2.5V
Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
V
V
IN
OUT
3.3V SUPPLY
SEL = 0V
0V
SWITCH
INPUT
3.3V
1.8V
Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
V
IN
0V
SWITCH
INPUT
3.3V
Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
REV. 0
–9–
ADG3249
Analog Switching
MEMORY
ADDRESS
DATA
MEMORY
BANK A
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
MEMORY
BANK B
MEMORY
BANK C
Multiplexing
MEMORY
BANK D
Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common prob-
lems faced by designers of these systems include
Figure 11. All Memory Banks Are Permanently
Connected to the Bus
•
•
Large delays caused by capacitive loading of the bus
Noise due to simultaneous switching of the address and data
bus signals
MEMORY
BANK A
MEMORY
ADDRESS
DATA
Figure 11 shows an array of memory banks in which each ad-
dress and data signal is loaded by the sum of the individual
loads. If a bus switch is used as shown in Figure 12, the output
load on the memory address and data bits is halved. The speed
at which the selected bank’s data can flow is much improved
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
High Impedance during Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, EN should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
Figure 12. ADG3249 Used to Reduce Both Access
Time and Noise
–10–
REV. 0
ADG3249
OUTLINE DIMENSIONS
8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
PIN 1
2.80 BSC
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8ꢂ
4ꢂ
0ꢂ
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178BA
REV. 0
–11–
–12–
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