ADG3248BKS-REEL7 [ROCHESTER]
2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO6, MO-203AB, SC-70, 6 PIN;
| 型号： | ADG3248BKS-REEL7 |
| 厂家： | 
Rochester Electronics |
| 描述： | 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO6, MO-203AB, SC-70, 6 PIN 光电二极管 |
| 文件： | 总13页 (文件大小：1224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch
ADG3248
FUNCTIONAL BLOCK DIAGRAM
FEATURES
225 ps propagation delay through the switch
4.5 Ω switch connection between ports
Data rate 1.244 Gbps
2.5 V/3.3 V supply operation
Level translation
ADG3248
A0
B
A1
IN
3.3 V to 2.5 V
2.5 V to 1.8 V
NOTES
Small signal bandwidth 610 MHz
6-lead SC70 package
1. SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 1.
APPLICATIONS
3.3 V to 2.5 V voltage translation
2.5 V to 1.8 V voltage translation
Bus switching
Docking stations
Memory switching
Analog switch applications
GENERAL DESCRIPTION
Table 1. ADG3248 Truth Table
IN Pin Logic Level Function
The ADG3248 is a 2.5 V or 3.3 V, high performance 2:1
multiplexer/demultiplexer. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. The low on
resistance allows the input to be connected to the output
without additional propagation delay or generating additional
ground bounce noise.
Low (L)
High (H)
B = A0
B = A1
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Tiny SC70 package.
Each switch of the ADG3248 conducts equally well in both
directions when on. The ADG3248 exhibits break-before-make
switching action, preventing momentary shorting when
switching channels.
The ADG3248 is available in a tiny 6-lead SC70 package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
ADG3248
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................5
Typical Performance Characteristics ..............................................6
Terminology.......................................................................................9
Bus Switch Applications ................................................................ 10
Mixed Voltage Operation, Level Translation.......................... 10
Analog Switching ....................................................................... 10
Multiplexing................................................................................ 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
REVISION HISTORY
10/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 1............................................................................ 1
Changes to Table 3,........................................................................... 4
Changes to Ordering Guide .......................................................... 12
10/03—Revision 0: Initial Version
Rev. A | Page 2 of 12
ADG3248
SPECIFICATIONS
VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
B Version
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
VINL
VINL
II
IOZ
IOL
VP
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
μA
μA
μA
V
Input Low Voltage
0.8
0.7
1
1
1
Input Leakage Current
Off State Leakage Current
On State Leakage Current
Maximum Pass Voltage
0.01
0.01
0.01
2.5
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = 3.3 V, IO = −5 μA
VA/VB = VCC = 2.5 V, IO= −5 μA
2.0
1.5
2.9
2.1
1.8
V
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD
Propagation Delay Matching5
Transition Time
CA Off
CB Off
CA, CB On
CIN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
3.5
4.5
8.5
4
pF
pF
pF
pF
4
tPHL, tPLH
CL = 50 pF, VCC = 3 V
0.225
5
29
ns
ps
ns
ns
Gbps
ps p-p
tTRANS
tBBM
RL = 510 Ω, CL = 50 pF
RL = 510 Ω, CL = 50 pF
VCC = 3.3 V; VA/VB = 2 V
VCC = 3.3 V; VA/VB = 2 V
16
10
1.244
45
Break-Before-Make Time
Maximum Data Rate
Channel Jitter
5
DIGITAL SWITCH
On Resistance
RON
VCC = 3 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, VA = 0 V, IA = 8 mA
4.5
12
5
9
0.1
8
28
9
18
0.5
Ω
Ω
Ω
Ω
Ω
On-Resistance Matching
POWER REQUIREMENTS
VCC
ΔRON
2.3
3.6
1
V
μA
Quiescent Power Supply Current
ICC
Digital inputs = 0 V or VCC
0.01
1 Temperature range is as follows for B Version: −40°C to +85°C.
2 Typical values are at 25°C, unless otherwise stated.
3 Guaranteed by design, not subject to production test.
4 The digital switch contributes no propagation delay other than the resistance-capacitance (RC) delay of the typical RON of the switch and the load capacitance when
driven by an ideal voltage source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to
the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with
the load on the driven side.
5 Propagation delay matching between channels is calculated from the on-resistance matching and load capacitance of 50 pF.
Rev. A | Page 3 of 12
ADG3248
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
VCC to GND
Digital Inputs to GND
DC Input Voltage
Rating
−0.5 V to +4.6 V
−0.5 V to +4.6 V
−0.5 V to +4.6 V
25 mA per channel
DC Output Current
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
Lead Soldering
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
332°C/W
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature
Pb-Free Soldering
300°C
220°C
Reflow, Peak Temperature
Time at Peak Temperature
260(+0/−5)°C
20 sec to 40 sec
Rev. A | Page 4 of 12
ADG3248
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A0
GND
A1
1
2
3
6
5
4
IN
ADG3248
V
TOP VIEW
CC
(Not to Scale)
B
Figure 2. 6-Lead SC70
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
A0
GND
A1
B
VCC
IN
Port A0, Input or Output.
Ground Reference.
Port A1, Input or Output.
Port B, Input or Output.
Positive Power Supply Voltage.
Channel Select.
Rev. A | Page 5 of 12
ADG3248
TYPICAL PERFORMANCE CHARACTERISTICS
40
15
10
5
T
= 25°C
V
= 2.5V
A
CC
35
30
+85°C
V
= 3V
CC
25
20
V
V
= 3.3V
= 3.6V
+25°C
CC
CC
15
10
5
–40°C
0
0
0
0
0
0.5
1.0
1.5
2.0
/V (V)
2.5
3.0
3.5
3.0
2.0
0
0.5
1.0
1.2
V
V /V (V)
A B
A
B
Figure 3. On Resistance vs. Input Voltage
Figure 6. On Resistance vs. Input Voltage for Different Temperatures
3.0
40
35
30
T
= 25°C
= 5µA
T
= 25°C
A
A
V
= 3.6V
CC
I
O
2.5
2.0
1.5
1.0
V
= 3.3V
V
= 2.5V
CC
CC
25
20
V
= 3V
CC
V
= 2.3V
CC
15
10
5
V
= 2.7V
CC
0.5
0
0
0
0.5
1.0
1.5
V
2.0
/V (V)
2.5
3.0
3.5
0.5
1.0
1.5
/V (V)
2.0
2.5
V
A
B
A
B
Figure 7. Pass Voltage vs. VCC
Figure 4. On Resistance vs. Input Voltage
2.5
2.0
1.5
1.0
0.5
0
20
15
10
5
V
= 3.3V
T
= 25°C
CC
A
V
= 2.7V
CC
I
= 5µA
O
V
= 2.5V
CC
V
= 2.3V
CC
+85°C
+25°C
–40°C
0
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
0.5
1.0
/V (V)
B
1.5
V
V
A
B
A
Figure 5. On Resistance vs. Input Voltage for Different Temperatures
Figure 8. Pass Voltage vs. VCC
Rev. A | Page 6 of 12
ADG3248
1
0
3.0
2.5
2.0
1.5
1.0
T
V
= 25°C
= 0V
A
A
–1
–2
–3
–4
V
= 2.5V
CC
–5
–6
T
= 25°C
A
V
V
= 3.3V/2.5V
CC
= 0dBm
IN
0.5
0
N/W ANALYZER:
= R = 50Ω
–7
–8
V
= 3.3V
R
CC
L
S
0.03
0.1
1.0
10
100
1k
0
0.02
0.04
0.06
0.08
0.10
I
(A)
FREQUENCY (MHz)
O
Figure 12. Bandwidth vs. Frequency
Figure 9. Output Low Characteristic
0
–10
–20
–30
–40
–50
–60
–70
3.0
2.5
2.0
1.5
1.0
T
V
= 25°C
= V
CC
T
A
= 25°C
= 3.3V/2.5V
= 0dBm
A
V
A
CC
V
IN
N/W ANALYZER:
= R = 50Ω
R
L
S
V
= 3.3V
CC
–80
V
= 2.5V
CC
0.5
0
–90
–100
0.03
0.1
1.0
10
100
1k
–0.10
–0.08
–0.06
–0.04
–0.02
0
FREQUENCY (MHz)
I
(A)
O
Figure 13. Crosstalk vs. Frequency
Figure 10. Output High Characteristic
0
–10
–20
–30
–40
–50
–60
–70
0
T
= 25°C
T = 25°C
A
A
ON = OFF
= 1nF
V
V
= 3.3V/2.5V
= 0dBm
CC
V
= 2.5V
–0.2
CC
C
L
IN
N/W ANALYZER:
R = R = 50Ω
L
–0.4
–0.6
–0.8
S
V
= 3.3V
CC
–1.0
–1.2
–1.4
–80
–90
–100
0.03
0.1
1.0
10
100
1k
0
0.5
1.0
1.5
V
2.0
/V (V)
2.5
3.0
3.5
FREQUENCY (MHz)
A
B
Figure 14. Off Isolation vs. Frequency
Figure 11. Charge Injection vs. Input Voltage
Rev. A | Page 7 of 12
ADG3248
25
20
15
10
5
V
= 2.5V
CC
V
= 3.3V
CC
0
–40
V
= 3.3V
20dB
–20
0
20
40
60
80 85
CC
38.7mV/DIV
133.7ps/DIV
ATTENUATION
TA = 25°C
TEMPERATURE (°C)
V
= 2V p-p
IN
Figure 18. Eye Pattern; 1.244 Gbps, VCC = 3.3 V, PRBS 31
Figure 15. Transition Time vs. Temperature
100
V
V
= 3.3V
= 1.5V p-p
CC
90
80
70
60
50
40
30
A
20dB ATTENUATION
20
10
0
V
= 2.5V
20dB
ATTENUATION
TA = 25°C
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
CC
20mV/DIV
166.3ps/DIV
DATA RATE (Gbps)
V
= 1V p-p
IN
Figure 19. Eye Pattern; 1 Gbps, VCC = 2.5 V, PRBS 31
Figure 16. Jitter vs. Data Rate; PRBS 31
100
95
90
85
80
75
70
65
V
V
= 3.3V
CC
= 1.5V p-p
A
20dB ATTENUATION
60
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) × 100%
55
50
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
DATA RATE (Gbps)
Figure 17. Eye Width vs. Data Rate; PRBS 31
Rev. A | Page 8 of 12
ADG3248
TERMINOLOGY
CX Off
Off switch capacitance.
VCC
Positive power supply voltage.
CX On
On switch capacitance.
GND
Ground (0 V) reference.
CIN
VINH
Control input capacitance. CIN consists of IN.
Minimum input voltage for Logic 1.
ICC
VINL
Quiescent power supply current. ICC represents the leakage
current between the VCC and ground pins and is measured
when all control inputs are at a logic high or logic low level and
the switches are off.
Maximum input voltage for Logic 0.
II
Input leakage current at the control inputs.
IOZ
t
PLH, tPHL
Off state leakage current. IOZ is the maximum leakage current at
the switch pin in the off state.
Data propagation delay through the switch in the on state.
Propagation delay is related to the RC time constant RON × CL,
where CL is the load capacitance.
IOL
On state leakage current. IOL is the maximum leakage current at
the switch pin in the on state.
tBBM
On or off time measured between the 90% points of both
switches when switching from one to another.
VP
Maximum pass voltage. VP relates to the clamped output voltage
of an NMOS device when the switch input voltage is equal to
the supply voltage.
tTRANS
Time taken to switch from one channel to the other, measured
from 50% of the in signal to 90% of the out signal.
RON
Maximum Data Rate
Maximum rate at which data can be passed through the switch.
Ohmic resistance offered by a switch in the on state. RON is
measured at a given voltage by forcing a specified amount of
current through the switch.
Channel Jitter
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
ΔRON
On resistance match between any two channels, that is,
RON max − RON min.
Rev. A | Page 9 of 12
ADG3248
BUS SWITCH APPLICATIONS
MIXED VOLTAGE OPERATION, LEVEL
TRANSLATION
V
OUT
3.3V SUPPLY
2.5V
Bus switches can provide an ideal solution for interfacing between
mixed voltage systems. The ADG3248 is suitable for applications
in which voltage translation from 3.3 V technology to a lower
voltage technology is needed. This device can translate from 2.5 V
to 1.8 V or bidirectionally from 3.3 V directly to 2.5 V.
V
IN
0V
3.3V
SWITCH
INPUT
Figure 20 shows a block diagram of a typical application in
which a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V
tolerant inputs; therefore, placing the ADG3248 between the
two devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
Figure 22. 3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Translation
When VCC is 2.5 V and the input signal range is 0 V to VCC, the
maximum output signal is, as before, clamped to within a voltage
threshold below the VCC supply. In this case, the output is limited
to approximately 1.8 V, as shown in Figure 24.
2.5V
3.3V
3.3V
2.5V
2.5V
3.3V ADC
MICROPROCESSOR
ADG3248
2.5V
1.8V
Figure 20. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
Figure 23. 2.5 V to 1.8 V Voltage Translation
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal is clamped to within a voltage threshold
below the VCC supply.
V
OUT
2.5V SUPPLY
1.8V
In this case, the output is limited to 2.5 V, as shown in Figure 22.
This device can be used for translation from 2.5 V to 3.3 V
devices and also between two 3.3 V devices.
3.3V
V
IN
0V
2.5V
SWITCH
INPUT
3.3V
2.5V
2.5V
2.5V
Figure 24. 2.5 V to 1.8 V Voltage Translation
ADG3248
ANALOG SWITCHING
Bus switches can be used in many analog switching applica-
tions, for example, video graphics. Bus switches can have lower
on resistance, smaller on and off channel capacitance, and thus
better frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see Figure 3 for a typical
plot) but, in many cases, this does not present an issue.
Figure 21. 3.3 V to 2.5 V Voltage Translation
Rev. A | Page 10 of 12
ADG3248
MEMORY
ADDRESS
MULTIPLEXING
DATA
MEMORY
BANK A
Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common problems
faced by designers of these systems include
MEMORY
BANK B
•
•
Large delays caused by capacitive loading of the bus
MEMORY
BANK C
Noise due to simultaneous switching of the address and
data bus signals
MEMORY
BANK D
Figure 25 shows an array of memory banks in which each
address and data signal is loaded by the sum of the individual
loads. If a bus switch is used as shown in Figure 26, the output
load on the memory address and data bits is halved. The speed
at which data from the selected bank can flow is much improved
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.
Figure 25. All Memory Banks Are Permanently Connected to the Bus
MEMORY
BANK A
MEMORY
ADDRESS
DATA
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
Figure 26. ADG3248 Used to Reduce Both Access Time and Noise
Rev. A | Page 11 of 12
ADG3248
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.46
0.36
0.26
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Branding
SMA
SMA
SMA
S1W
ADG3248BKS-R2
ADG3248BKS-REEL
ADG3248BKS-REEL7
ADG3248BKSZ-REEL71
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
KS-6
KS-6
KS-6
KS-6
1 Z = RoHS Compliant Part.
©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04404-0-10/07(A)
Rev. A | Page 12 of 12
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