ADF4193BCPZ-RL7 [ADI]
Low Phase Noise, Fast Settling PLL Frequency Synthesizer; 低相位噪声，快速建立PLL频率合成器
| 型号： | ADF4193BCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Low Phase Noise, Fast Settling PLL Frequency Synthesizer |
| 文件： | 总28页 (文件大小：595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Phase Noise, Fast Settling PLL
Frequency Synthesizer
ADF4193
FEATURES
GENERAL DESCRIPTION
New, fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
by 20 μs
0.5° rms phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
The ADF4193 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture
is specifically designed to meet the GSM/EDGE lock time
requirements for base stations. It consists of a low noise, digital
phase frequency detector (PFD), and a precision differential
charge pump. There is also a differential amplifier to convert
the differential charge pump output to a single-ended voltage
for the external voltage-controlled oscillator (VCO).
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
Loop filter design possible using ADI SimPLL
The Σ-Δ based fractional interpolator, working with the N
divider, allows programmable modulus fractional-N division.
Additionally, the 4-bit reference (R) counter and on-chip
frequency doubler allow selectable reference signal (REFIN)
frequencies at the PFD input. A complete phase-locked loop
(PLL) can be implemented if the synthesizer is used with an
external loop filter and a VCO. The switching architecture
ensures that the PLL settles inside the GSM time slot guard
period, removing the need for a second PLL and associated
isolation switches. This decreases cost, complexity, PCB area,
shielding, and characterization on previous ping-pong GSM
PLL architectures.
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment
FUNCTIONAL BLOCK DIAGRAM
SDV
DV
1
DV
2
DV
3
AV
1
V 1
V 2
V 3
R
SET
DD
DD
×2
DD
DD
DD
P
P
P
REFERENCE
SW1
CP
4-BIT R
COUNTER
/2
DIVIDER
+
PHASE
+
REF
CHARGE
PUMP
OUT+
IN
FREQUENCY
DETECTOR
DOUBLER
CP
–
OUT–
–
SW2
CMR
V
DD
DGND
HIGH Z
LOCK DETECT
DIFFERENTIAL
AMPLIFIER
AIN–
AIN+
–
+
OUTPUT
MUX
MUX
OUT
R
N
DIV
DIV
A
OUT
N COUNTER
SW3
FRACTIONAL
INTERPOLATOR
RF
RF
IN+
IN–
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION
REG
MODULUS
REG
INTEGER
REG
ADF4193
A
1
A
2
D
1
D
2
D
3
SD
GND
SW
GND
GND
GND
GND
GND
GND
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADF4193
TABLE OF CONTENTS
Features .............................................................................................. 1
Function Register (R3) .............................................................. 18
Charge Pump Register (R4)...................................................... 19
Power-Down Register (R5)....................................................... 20
Mux Register (R6) ...................................................................... 21
Programming.................................................................................. 22
Worked Example ........................................................................ 22
Spur Mechanisms ....................................................................... 22
Power-Up Initialization ............................................................. 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Reference Input Section............................................................. 11
RF Input Stage............................................................................. 11
Register Map.................................................................................... 14
FRAC/INT Register (R0)........................................................... 15
MOD/R Register (R1)................................................................ 16
Phase Register (R2) .................................................................... 17
Changing the Frequency of the PLL and the Phase Look-Up
Table ............................................................................................. 23
Applications..................................................................................... 25
Local Oscillator for A GSM Base Station................................ 25
Interfacing ................................................................................... 27
PCB Design Guidelines for Chip Scale Package .................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
Changes to the 8-Bit INT Value Section ..................................... 15
Changes to Figure 33...................................................................... 19
Replaced Figure 35 ......................................................................... 21
Changes to the Σ-Δ and Lock Detect Modes Section................ 21
Changes to the Power-Up Initialization Section........................ 23
Changes to Table 8.......................................................................... 23
Changes to the Local Oscillator for a GSM
Base Station Section ....................................................................... 25
Changes to the Timer Values for Rx Section .............................. 25
Changes to Figure 36...................................................................... 26
Updates to the Outline Dimensions ............................................ 28
Changes to the Ordering Guide ................................................... 28
6/06—Rev A. to Rev. B
Changes to Table 1............................................................................ 3
Changes to Figure 32...................................................................... 18
Changes to Power-Up Initialization Section............................... 23
Changes to Timer Values for Tx Section and Timer Values for
Rx Section........................................................................................ 25
11/05—Rev 0. to Rev. A
Updated Format..................................................................Universal
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 3
Changes to Reference Input Section ............................................ 11
Changes to RF N Divider Section ................................................ 11
Changes to the Lock Detect Section ............................................ 13
Changes to Figure 29...................................................................... 15
4/05—Revision 0: Initial Version
Rev. B | Page 2 of 28
ADF4193
SPECIFICATIONS
AVDD = DVDD = SDVDD = 3 V 10ꢀ, VP1, VP2 = 5 V 10ꢀ, VP3 = 5.35 V 5ꢀ, AGND = DGND = GND = 0 V, RSET = 2.4 kΩ, dBm
referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
B Version1
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Sensitivity
Maximum Allowable Prescaler Output Frequency2
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Edge Slew Rate
0.4/3.5
–10/0
470
GHz min/max
dBm min/max
MHz max
See Figure 21 for input circuit
300
300
0.7/VDD
0 to VDD
10
MHz max
V/μs min
V p-p min/max
V max
pF max
μA max
For f > 120 MHz, set REF/2 bit = 1
REFIN Input Sensitivity
AC-coupled
CMOS-compatible
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
100
26
MHz max
ICP Up/Down
High Value
Low Value
6.6
104
5
1/4
1
0.1
1
1
mA typ
μA typ
% typ
kΩ min/max
nA typ
% typ
With RSET = 2.4 kΩ
With RSET = 2.4 kΩ
Absolute Accuracy
RSET Range
ICP Three-State Leakage
ICP Up vs. Down Matching
ICP vs. VCP
ICP vs. Temperature
DIFFERENTIAL AMPLIFIER
Input Current
Nominally RSET = 2.4 kΩ
0.75 V ≤ VCP ≤ VP – 1.5 V
0.75 V ≤ VCP ≤ VP – 1.5 V
0.75 V ≤ VCP ≤ VP – 1.5 V
% typ
% typ
1
nA typ
Output Voltage Range
VCO Tuning Range
Output Noise
1.4/(VP3 − 0.3)
1.8/(VP3 − 0.8)
7
V min/max
V min/max
nV/√Hz typ
@ 20 kHz offset
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP1, VP2
VP3
IDD (AVDD + DVDD + SDVDD)
IDD (VP1 + VP2)
1.4
0.7
1
V min
V max
μA max
pF max
10
VDD – 0.4
0.4
V min
V max
IOH = 500 μA
IOL = 500 μA
2.7/3.3
AVDD
4.5/5.5
5.0/5.65
27
V min/V max
V min/V max
V min/V max
mA max
AVDD ≤ VP1, VP2 ≤ 5.5 V
VP1, VP2 ≤ VP3 ≤ 5.65 V
22 mA typ
27
mA max
22 mA typ
IDD (VP3)
30
mA max
24 mA typ
IDD Power-Down
10
μA typ
Rev. B | Page 3 of 28
ADF4193
Parameter
B Version1
Unit
Test Conditions/Comments
SW1, SW2, and SW3
RON (SW1 and SW2)
RON SW3
65
75
Ω typ
Ω typ
NOISE CHARACTERISTICS
900 MHz Output3
1800 MHz Output4
Phase Noise Figure of Merit5
–108
–102
–216
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 5 kHz offset and 26 MHz PFD frequency
@ 5 kHz offset and 13 MHz PFD frequency
@ VCO output with dither off
1 Operating temperature range is from –40°C to +85°C.
2 The prescaler value is chosen to ensure that the RF input is divided down to a frequency that is less than this value.
3 fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop BW = 40 kHz.
4 fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1850 MHz; loop BW = 60 kHz.
5 Calculated from the phase noise measured at 5 kHz with a 60 kHz loop BW. Increased noise contribution from the differential amplifier if the loop BW is reduced.
TIMING CHARACTERISTICS
AVDD = DVDD = 3 V 10ꢀ, VP1, VP2 = 5 V 10ꢀ, VP3 = 5.35 V 5ꢀ, AGND = DGND = GND = 0 V, RSET = 2.4 kΩ, dBm referred to
50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit (B Version)1
Unit
Test Conditions/Comments
LE setup time
t1
t2
t3
t4
t5
t6
t7
10
10
10
15
15
10
15
ns min
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
1 Operating temperature is from −40°C to +85°C.
t4
t5
CLK
t2
t3
DB23
(MSB)
DB1
DB0 (LSB)
DATA
LE
DB22
DB2
(CONTROL BIT C2)
(CONTROL BIT C1)
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. B | Page 4 of 28
ADF4193
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AVDD to GND
AVDD to DVDD, SDVDD
VP to GND
–0.3 V to +3.6 V
–0.3 V to +0.3 V
–0.3 V to +5.8 V
–0.3 V to +5.8 V
–0.3 V to VDD + 0.3 V
–0.3 V to VP + 0.3 V
–0.3 V to VDD + 0.3 V
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFIN+, RFIN− to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
need to be taken for handling and assembly.
–40°C to +85°C
–65°C to +125°C
150°C
Transistor Count
LFCSP θJA Thermal Impedance
(Paddle Soldered)
27.3°C/W
75,800 (MOS), 545 (BJT)
Reflow Soldering
Peak Temperature
Time at Peak Temperature
260°C
40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 5 of 28
ADF4193
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 V 2
CMR
1
2
P
PIN 1
A
23
22
21
R
A
D
OUT
SET
GND
GND
INDICATOR
SW3
3
4
2
3
A
1
GND
ADF4193
RF
RF
5
6
7
8
20 V 1
IN–
P
TOP VIEW
19 LE
18 DATA
17 CLK
IN+
1
AV
DD
DV
1
DD
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
CMR
Common-Mode Reference Voltage for the Differential Amplifier’s Output Voltage Swing. Internally biased to
three-fifths of VP3. Requires a 0.1 μF capacitor to ground.
2
3
4
5
AOUT
SW3
Differential Amplifier Output to Tune the External VCO.
Fast-Lock Switch 3. Closed while SW3 timeout counter is active.
Analog Ground. This is the ground return pin for the differential amplifier and the RF section.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
AGND1
RFIN−
6
7
RFIN+
AVDD1
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Power Supply Pin for the RF Section. Nominally 3 V. A 100 pF decoupling capacitor to the ground plane should be
placed as close as possible to this pin.
8
DVDD1
Power Supply Pin for the N Divider. Should be the same voltage as AVDD1. A 0.1 μF decoupling capacitor to ground
should be placed as close as possible to this pin.
9
DGND1
Ground Return Pin for DVDD1.
10
DVDD2
Power Supply Pin for the REFIN Buffer and R Divider. Nominally 3 V. A 0.1 μF decoupling capacitor to ground
should be placed as close as possible to this pin.
11
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ (see Figure 15). This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
12
13
14
15
DGND
2
Ground Return Pin for DVDD2 and DVDD3.
Power Supply Pin for the Serial Interface Logic. Nominally 3 V.
Ground Return Pin for the Σ-Δ Modulator.
Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. A 0.1 μF decoupling capacitor to the ground plane
should be placed as close as possible to this pin.
DVDD3
SDGND
SDVDD
16
17
18
19
20
MUXOUT
CLK
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally (see Figure 35).
Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is
selected by the three LSBs.
DATA
LE
VP1
Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, should be at the same voltage at VP2.
A 0.1 μF decoupling capacitor to ground should be placed as close as possible to this pin.
21
22
DGND
3
Ground Return Pin for VP1.
Ground Return Pin for VP2.
AGND2
Rev. B | Page 6 of 28
ADF4193
Pin No. Mnemonic Description
23
RSET
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at
the RSET pin is 0.55 V. The relationship between ICP and RSET is
ICP = 0.25/RSET
So, with RSET = 2.4 kΩ, ICP = 104 μA.
24
VP2
Power Supply Pin for the Charge Pump. Nominally 5 V, should be at the same voltage at VP1. A 0.1 μF decoupling
capacitor to ground should be placed as close as possible to this pin.
25
26
27
28
29
30
31
32
AIN−
CPOUT−
SW2
SWGND
SW1
CPOUT+
AIN+
VP3
Differential Amplifier’s Negative Input Pin.
Differential Charge Pump’s Negative Output Pin. Should be connected to AIN− and the loop filter.
Fast Lock Switch 2. This switch is closed to SWGND while the SW1/2 timeout counter is active.
Common for SW1 and SW2 Switches. Should be connected to the ground plane.
Fast Lock Switch 1. This switch is closed to SWGND while the SW1/2 timeout counter is active.
Differential Charge Pump’s Positive Output Pin. Should be connected to AIN+ and the loop filter.
Differential Amplifier’s Positive Input Pin.
Power Supply Pin for the Differential Amplifier. This can range from 5.0 V to 5.5 V. A 0.1 μF decoupling capacitor to
ground should be placed as close as possible to this pin. Also requires a 10 μF decoupling capacitor to ground.
Rev. B | Page 7 of 28
ADF4193
TYPICAL PERFORMANCE CHARACTERISTICS
0
–5
FREQ. UNIT GHz KEYWORD
R
PARAM TYPE S
DATA FORMAT
IMPEDANCE 50
MA
FREQ.
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
MAGS11 ANGS11
FREQ.
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
MAGS11 ANGS11
4/5 PRESCALER
0.8897
–16.6691
–19.9279
–23.561
–26.9578
–30.8201
–34.9499
–39.0436
–42.3623
–46.322
–50.3484
–54.3545
–57.3785
–60.695
0.67107
0.66556
0.6564
0.6333
0.61406
0.5977
–75.8206
–77.6851
–80.3101
–82.5082
–85.5623
–87.3513
–89.7605
–93.0239
–95.9754
–99.1291
–102.208
–106.794
–111.659
–117.986
–125.62
0.87693
0.85834
0.85044
0.83494
0.81718
0.80229
0.78917
0.77598
0.75578
0.74437
0.73821
0.7253
–10
–15
–20
–25
–30
–35
8/9 PRESCALER
0.5655
0.5428
0.51733
0.49909
0.47309
0.45694
0.44698
0.43589
0.42472
0.41175
0.41055
0.40983
0.71365
0.70699
0.7038
0.69284
0.67717
–63.9152
–66.4365
–68.4453
–70.7986
–73.7038
–133.291
–140.585
–147.97
0
1000
2000
3000
4000
5000
RF FREQUENCY (MHz)
IN
Figure 4. S Parameter Data for the RF Input
Figure 7. RF Input Sensitivity
–30
–40
–30
–40
DCS1800 Tx SETUP, 60kHz LOOP BW, DITHER OFF
RF = 1842.6MHz, F = 13MHz, MOD = 65
DSB INTEGRATED PHASE ERROR = 0.46° RMS
GSM900 Rx SETUP, 40kHz LOOP BW, DITHER OFF
RF = 1092.8MHz, F
N = 42 4/130
= 26MHz, MOD = 130
REF
REF
–50
–50
SIRENZA 1843T VCO
INTEGER BOUNDARY SPUR: –103dBc @ 800kHz
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. SSB Phase Noise Plot at 1092.8 MHz (GSM900 Rx Setup) vs.
Free Running VCO Noise
Figure 8. SSB Phase Noise Plot at 1842.6 MHz (DCS1800 Tx Setup)
–60
–60
DCS1800 Tx SETUP WITH DITHER OFF,
60kHz LOOP BW, 13MHz PFD.
MEASURED ON EVAL-ADF4193-EB1 BOARD
DCS1800 Tx SETUP WITH DITHER OFF,
60kHz LOOP BW, 13MHz PFD.
MEASURED ON EVAL-ADF4193-EB1 BOARD
–70
–70
–80
400kHz SPURS @ 25°C
–80
–90
600kHz SPURS @ 25°C
–90
–100
–110
–120
–100
–110
400kHz SPURS @ 85°C
600kHz SPURS @ 85°C
–120
1846
1859
1872
1846
1859
FREQUENCY (MHz)
1872
FREQUENCY (MHz)
Figure 6. 400 kHz Fractional Spur Levels Across All DCS1800 Tx Channels over
Two-Integer Multiples of the PFD Reference
Figure 9. 600 kHz Fractional Spur Levels Across All DCS1800 Tx Channels over
Two-Integer Multiples of the PFD Reference
Rev. B | Page 8 of 28
ADF4193
5
4
3
2
1
0
5
4
3
2
1
0
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 5μs.
V
TUNE
CP
V
OUT–
CP
CP
OUT+
OUT–
TUNE
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 4
CP
OUT+
μs.
–1
0
1
2
3
4
5
6
7
8
9
–1
0
1
2
3
4
5
6
7
8
9
TIME (
μ
s)
TIME (μs)
Figure 10. VTUNE Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz with Sirenza 1843T VCO
Figure 13. VTUNE Settling Transient for a 75 MHz Jump Down from 1893 MHz to
1818 MHz, the Bottom of the Allowed Tuning Range with the Sirenza 1843T VCO
50
50
DCS1800 Tx SETUP, 60kHz LOOP BW.
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
MEASURED ON EVAL-ADF4193-EB1
40
40
EVALUATION BOARD WITH AD8302
EVALUATION BOARD WITH AD8302
PHASE DETECTOR.
PHASE DETECTOR.
30
20
30
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
+25
°
C
+25°C
PEAK PHASE ERROR < 5
PEAK PHASE ERROR < 5° @ 17.8μs
° @ 19.2μs
20
10
10
0
0
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
+85
°
C
+85°C
–40
°
C
–40°C
–5
0
5
10
15
20
TIME (
25
30
35
40
45
–5
0
5
10
15
20
TIME (μs)
25
30
35
40
45
μ
s)
Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz (VTUNE 1.8 V to 3.7 V with Sirenza 1843T VCO)
Figure 14. Phase Settling Transient for a 75 MHz Jump from 1893 MHz to
1818 MHz (VTUNE = 3.7 V to 1.8 V with Sirenza 1843T VCO)
8
6
2.0
ICP
+ P, ICP
– P
OUT
OUT
V 1 = V 2 = 5V
P
P
5
4
3
2
1
0
V 3 = 5.5V
1.5
P
A
(= V
)
V
= 3.3V
OUT
TUNE
CMR
I
I
= | ICP
+ P | + | ICP
– N |
UP
OUT
OUT
4
1.0
= | ICP
– P | + | ICP
+ N |
DOWN
OUT
OUT
2
0.5
CHARGE PUMP MISMATCH (%)
0
0
CP
(= AIN+)
OUT+
–2
–4
–6
–8
–0.5
–1.0
–1.5
–2.0
NORMAL OPERATING RANGE
CP
(= AIN–)
OUT–
ICP
+ N, ICP
2.5
– N
OUT
2.0
OUT
0
0.5
1.0
1.5
CP
3.0
3.5
4.0
4.5
5.0
1780 1800 1820 1840 1860 1880 1900 1920 1940
+ / CP
– VOLTAGE (V)
FREQUENCY (MHz)
OUT
OUT
Figure 15. Tuning Range with a Sirenza 1843T VCO and a 5.5 V Differential
Amplifier Power Supply Voltage
Figure 12. Differential Charge Pump Output Compliance Range and
Charge Pump Mismatch with VP1 = VP2 = 5 V
Rev. B | Page 9 of 28
ADF4193
1000
1.8
1.5
1.2
0.9
0.6
0.3
0
MEASURED USING AD8302 PHASE DETECTOR
Y-AXIS SCALE: 10mV/DEGREE
RF = 1880MHz, PFD = 26MHz, MOD = 130
X-AXIS SCALE: 2.77°/STEP
100
10
7nV/ Hz @ 20kHz
1
1k
10k
100k
1M
10M
0
13
26
39
52
65
78
91
104 117 130
FREQUENCY (Hz)
PHASE CODE
Figure 16. Voltage Noise Density Measured at the Differential Amplifier Output
Figure 18. Detected RF Output Phase for Phase Code Sweep from 0 to MOD
100
ADF4193
104MHz
5dBm
EVAL BOARD
SW3
90
REF
IN
+85°C
SW1/
RF
OUT
80
SW2
1805 1880MHz
+85°C
+25°C
70
60
+25°C
–40°C
INPA
AGILENT
TEKTRONIX
TDS714L
OSCILLOSCOPE
HP8663A
VPHS
50
SIG. GEN.
–40°C
TUNING VOLTAGE RANGE
40
30
20
AD8302
EVB
INPB
R&S
10MHz
EXT REF
1880MHz
SMT03
10
0
SIG. GEN.
0
1
2
3
4
5
INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD
REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS
DRAIN VOLTAGE (V)
Figure 19. Test Setup for Phase Lock Time Measurement
Figure 17. On Resistance of Loop Filter Switches SW1/SW2 and SW3
Rev. B | Page 10 of 28
ADF4193
THEORY OF OPERATION
The ADF4193 is targeted at GSM base station requirements,
specifically to eliminate the need for ping-pong solutions. It
works based on fast lock, using a wide loop bandwidth during a
frequency change and narrowing the loop bandwidth once
frequency lock is achieved. Widening the loop bandwidth is
achieved by increasing the charge pump current. Switches are
included to change the loop filter component values to maintain
stability with the changing charge pump current. The narrow
loop bandwidth ensures that phase noise and spur specifications
are met. A differential charge pump and loop filter topology are
used to ensure that the fast lock time benefit from widening the
loop bandwidth is maintained when the loop is restored to
narrow bandwidth mode for normal operation.
RF INPUT STAGE
The RF input stage is shown in Figure 21. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler. Two prescaler options are selectable: a
4/5 and an 8/9. The 8/9 prescaler is selected for N divider values
greater than 80.
AV
DD
1.6V
BIAS
GENERATOR
500Ω
500Ω
RF
RF
IN+
IN–
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 20. Switches S1 and
S2 are normally closed, and S3 is normally open. During power-
down, S3 is closed, and S1 and S2 are opened to ensure that
there is no loading of the REFIN pin. The falling edge of REFIN is
the active edge at the positive edge triggered PFD.
AGND
Figure 21. RF Input Stage
RF N Divider
The RF N divider allows a fractional division ratio in the PLL
feedback path. The integer and fractional parts of the division
are programmed using separate registers, as shown in Figure 22
and described in the INT, FRAC, and MOD Relationship
section. Integer division ratios from 26 to 255 are allowed and a
third-order, Σ-Δ modulator interpolates the fractional value
between the integer steps.
POWER-DOWN
CONTROL
100kΩ
NC
S2
TO R COUNTER
REF
IN
NC
BUFFER
S1
S3
NO
Figure 20. Reference Input Stage
RF N DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
R Counter and Doubler
N COUNTER
The 4-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). A toggle flip-flop can be optionally
inserted after the R counter to give a further divide-by-2. Using
this option has the additional advantage of ensuring that the
PFD reference clock has a 50/50 mark-space ratio. This ratio
gives the maximum separation between the fast lock timer
clock, which is generated off the falling edge of the PFD
reference, and the rising edge, which is the active edge in the
PFD. It is recommended that this toggle flip-flop be enabled for
all even R divide values greater than 2. It must be enabled if
dividing down a REFIN frequency that is greater than 120 MHz.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
MOD
REG
FRAC
VALUE
Figure 22. Fractional-N Divider
INT, FRAC, and MOD Relationship
The INT, FRAC, and MOD values, programmed through the
serial interface, make it possible to generate RF output frequencies
that are spaced by fractions of the PFD reference frequency.
The N divider value, shown inside the brackets of the following
equation for the RF VCO frequency (RFOUT), is made up of an
integer part (INT) and a fractional part (FRAC/MOD):
An optional doubler before the 4-bit R counter can be used for
low REFIN frequencies, up to 20 MHz. With these programmable
options, reference division ratios from 0.5 to 30 between REFIN
and the PFD are possible.
RFOUT = FPFD × [INT + (FRAC/MOD)]
where:
RFOUT is the output frequency of the external VCO.
FPFD is the PFD reference frequency.
Rev. B | Page 11 of 28
ADF4193
The value of MOD is chosen to give the desired channel step
with the available reference frequency. Thereafter, program the
INT and FRAC words for the desired RF output frequency. See
the Worked Example section for more information.
To pump up, the up switches are on and PMOS current is
sourced out through CPOUT+; this increases the voltage on the
external loop filter capacitors connected to CPOUT+. Similarly,
the NMOS current sink on CPOUT− decreases the voltage on the
external loop filter capacitors connected to CPOUT−. Therefore,
the differential voltage between CPOUT+ and CPOUT− increases.
To pump down, PMOS current sources out through CPOUT− and
NMOS current sinks in through CPOUT+, which decreases the
(CPOUT+, CPOUT−) differential voltage. The charge pump up/
down matching is improved by an order of magnitude over the
conventional single-ended charge pump that depended on the
matching of two different device types. The up/down matching
in this structure depends on how a PMOS matches a PMOS and
an NMOS matches an NMOS.
PFD and Charge Pump
The PFD takes inputs from the R divider and N divider and
produces up and down outputs with a pulse width difference
proportional to the phase difference between the inputs. The
charge pump outputs a net up or down current pulse of a width
equal to this difference, to pump up or pump down the voltage
that is integrated onto the loop filter, which in turn increases or
decreases the VCO output frequency. If the N divider phase lags
the R divider phase, a net up current pulse is produced that
increases the VCO frequency (and thus the phase). If the
N divider phase leads the R divider edge, then a net down pulse
is produced to reduce the VCO frequency and phase. Figure 23
is a simplified schematic of the PFD and charge pump. The
charge pump is made up of an array of 64 identical cells, each of
which is fully differential. All 64 cells are active during fast lock,
but only one is active during normal operation. Because a
single-ended control voltage is required to tune the VCO, an
on-chip, differential-to-single-ended amplifier is provided for
this purpose. In addition, because the phase-lock loop only
controls the differential voltage generated across the charge
pump outputs, an internal common-mode feedback (CMFB)
loop biases the charge pump outputs at a common-mode
voltage of approximately 2 V.
V
P
BIAS
P
P
UP
DOWN
CP
C
POUT–
OUT+
DOWN
UP
V
N
BIAS
N
N
Figure 24. Differential Charge Pump Cell with External Loop Filter Components
CP
Fast Lock Timeout Counters
D
Q
OUT+
R DIVIDER
Timeout counters, clocked at one quarter the PFD reference
frequency, are provided to precisely control the fast locking
operation (see Figure 25). Whenever a new frequency is
programmed, the fast lock timers start and the PLL locks into
wide BW mode with the 64 identical 100 μA charge pump cells
active (6.4 mA total). When the ICP counter times out, the
charge pump current is reduced to 1× by deselecting cells in
binary steps over the next six timer clock cycles, until just one
100 μA cell is active. The charge pump current switching from
6.4 mA to 100 μA equates to an 8-to-1 change in loop band-
width. The loop filter must be changed to ensure stability when
this happens. That is the job of the SW1, SW2, and SW3 switches.
The application circuit (shown in Figure 36) shows how they
can be used to reconfigure the loop filter time constants. The
application circuits close to short out external loop filter resistors
during fast lock and open when their counters time out to restore
the filter time constants to their normal values for the 100 μA
charge pump current. Because it takes six timer clock cycles to
reduce the charge pump current to 1×, it is recommended that
both switch timers be programmed to the value of the ICP
timer + 7.
CLR
CLR
CHARGE
PUMP
CMFB
ARRAY
[64:1]
CP
D
Q
OUT–
N DIVIDER
EN[64:1]
Figure 23. PFD and Differential Charge Pump Simplified Schematic
Differential Charge Pump
The charge pump cell (see Figure 24) has a fully differential
design for best up-to-down current matching. Good matching
is essential to minimize the phase offset created when switching
the charge pump current from its high value (in fast lock mode)
to its nominal value (in normal mode).
Rev. B | Page 12 of 28
ADF4193
START
WRITE
TO R0
MUXOUT and Lock Detect
The output multiplexer on the ADF4193 allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M4 to M1 in the MUX register. Figure 35 shows
the full truth table. Figure 27 shows the MUXOUT section in
block diagram form.
ICP
SW1/SW2
TIMEOUT
COUNTER
SW3
TIMEOUT
COUNTER
TIMEOUT
COUNTER
F
÷4
PFD
SW3
CHARGE PUMP
ENABLE LOGIC
A
OUT
DV
DD
SW1
SW2
LOGIC LOW
SERIAL DATA OUTPUT
R DIVIDER OUTPUT
N DIVIDER OUTPUT
THREE-STATE OUTPUT
TIMER OUTPUTS
EN[64:1]
SW
GND
Figure 25. Fast Lock Timeout Counters
MUX
MUX
CONTROL
OUT
Differential Amplifier
DIGITAL LOCK DETECT
LOGIC HIGH
The internal, low noise, differential-to-single-ended amplifier is
used to convert the differential charge pump output to a single-
ended control voltage for the tuning port of the VCO. Figure 26
shows a simplified schematic of the differential amplifier. The
output voltage is equal to the differential voltage, offset by the
voltage on the CMR pin, according to
D
GND
NOTE:
NOT ALL MUXOUT MODES SHOWN REFER TO MUX REGISTER
Figure 27. MUXOUT Circuit
Lock Detect
V
AOUT = (VAIN+ − VAIN−) + VCMR
MUXOUT can be programmed to provide a digital lock detect
signal. Digital lock detect is active high. Its output goes high if
there are 40 successive PFD cycles with an input error of less
than 3 ns. For reliable lock detect operation with RF frequencies
<2 GHz, it is recommended that this threshold be increased to
10 ns by programming Register R6. The digital lock detect goes
low again when a new channel is programmed or when the
error at the PFD input exceeds 30 ns for one or more cycles.
The CMR offset voltage is internally biased to three-fifths of
VP3, the differential amplifier power supply voltage, as shown in
Figure 26. Connect a 0.1 μF capacitor to ground to the CMR pin
to roll off the thermal noise of the biasing resistors.
As can be seen in Figure 15, the differential amplifier output
voltage behaves according to the previous equation over a 4 V
range from approximately 1.2 V minimum up to VP3 − 0.3 V.
However, fast settling is guaranteed only over a tuning voltage
range from 1.8 V up to VP3 − 0.8 V. This is to allow sufficient
room for overshoot in the PLL frequency settling transient.
Input Shift Register
The ADF4193 serial interface section includes a 24-bit input
shift register. Data is clocked in MSB first on each rising edge
of CLK. Data from the shift register is latched into one of eight
control registers, R0 to R7, on the rising edge of latch enable
(LE). The destination register is determined by the state of
the three control bits (Control Bit C3, Control Bit C2, and
Control Bit C1) in the shift register. The three LSBs are Bit DB2,
Bit DB1, and Bit DB0, as shown in the timing diagram of Figure 2.
The truth table for these bits is shown in Table 5. Figure 28
shows a summary of how the registers are programmed.
Noise from the differential amplifier is suppressed inside the
PLL bandwidth. For loop bandwidths >20 kHz, the 1/f noise has
a negligible effect on the PLL output phase noise. Outside the
loop bandwidth, the differential amplifier’s noise FM modulates
the VCO. The passive filter network following the differential
amplifier, shown in Figure 36, suppresses this noise contribution to
below the VCO noise from offsets of 400 kHz and above. This
network has a negligible effect on lock time because it is
bypassed when SW3 is closed while the loop is locking.
Table 5. C3, C2, and C1 Truth Table
Control Bits
AIN–
C3
0
0
C2
0
0
C1
0
1
Name
Register
R0
R1
FRAC/INT
MOD/R
500Ω
500Ω
AOUT
0
0
1
1
1
1
0
0
0
1
0
1
Phase
R2
R3
R4
R5
V 3
P
AIN+
Function
Charge Pump
Power-Down
Mux
20kΩ
CMR
500Ω
500Ω
C EXT =
0.1µF
30kΩ
1
1
0
R6
1
1
1
Test Mode
R7
Figure 26. Differential Amplifier Block Diagram
Rev. B | Page 13 of 28
ADF4193
REGISTER MAP
FRAC/INT REGISTER (R0)
CONTROL
BITS
8-BIT RF INT VALUE
12-BIT RF FRAC VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F6
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
0
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
C3 (0) C2 (0) C1 (0)
MOD/R REGISTER (R1)
DBB DBB
DBB
DBB
DBB
4-BIT RF R
COUNTER
CONTROL
BITS
12-BIT MODULUS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F5 F4 F2 F1 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7
DB8
M6
DB7
M5
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
0
C3 (0) C2 (0) C1 (1)
PHASE REGISTER (R2)
DBB
CONTROL
BITS
12-BIT PHASE
DB15 DB14 DB13 DB12 DB11 DB10 DB9
P12 P11 P10 P9 P8 P7
DB8
P6
DB7
P5
DB6
P4
DB5
P3
DB4
P2
DB3
P1
DB2
DB1
DB0
0
C3 (0) C2 (1) C1 (0)
FUNCTION REGISTER (R3)
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
1
DB5
F3
DB4
1
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
C3 (0) C2 (1) C1 (1)
CHARGE PUMP REGISTER (R4)
TIMER
CONTROL
BITS
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
C9 C8 C7 C6 C5
9-BIT TIMEOUT COUNTER
SELECT
DB8
C4
DB7
C3
DB6
C2
DB5
C1
DB4
F2
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
C3 (1) C2 (0) C1 (0)
POWER-DOWN REGISTER (R5)
CONTROL
BITS
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
C3 (1) C2 (0) C1 (1)
MUX REGISTER (R6)
SIGMA-DELTA
AND
LOCK DETECT MODES
CONTROL
BITS
RESERVED
MUX
OUT
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
M13
M12
M11
M10
0
0
0
C3 (1) C2 (1) C1 (0)
TEST MODE REGISTER (R7)
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
DB1
DB0
0
0
0
0
0
0
0
C3 (1) C2 (1) C1 (1)
DBB = DOUBLE BUFFERED BIT(S)
Figure 28. Register Map
Rev. B | Page 14 of 28
ADF4193
FRAC/INT REGISTER (R0)
CONTROL
BITS
8-BIT RF INT VALUE
12-BIT RF FRAC VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F6
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
0
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
C3 (0) C2 (0) C1 (0)
F12
F11
F10
F3
F2
F1
FRACTIONAL VALUE (FRAC)
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
4092
4093
4094
4095
0 = < FRAC < MOD
N8
N7
N6
N5
N4
N3
N2
N1
INTEGER VALUE (INT)
0
.
0
.
0
.
1
.
1
.
0
.
1
.
0
.
26
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
255
Figure 29. FRAC/INT Register (R0)
Control Bits
R0, the FRAC/INT register, is used to program the synthesizer
output frequency. On the next PFD cycle following a write to
R0, the N divider section is updated with the new INT and
FRAC values. At the same time, the PLL automatically enters
fast lock mode and the charge pump current is increased to its
maximum value and stays at this value until the ICP timeout
counter times out, and switches SW1, SW2, and SW3 closed
and remains closed until the SW1, SW2, and SW3 timeout
counters time out.
The three LSBs, Control Bit C3, Control Bit C2, and Control Bit C1,
should be set to 0, 0, 0, respectively, to select R0, the FRAC/INT
register.
Reserved Bit
Bit DB23 is reserved and must be set to 0.
8-Bit INT Value
These eight bits set the INT value, which determines the integer
part of the feedback division factor. All integer values from 26
to 255 are allowed. See the Worked Example section.
Once all registers are programmed during the initialization
sequence (see Table 8), all that is required thereafter to program
a new channel is a write to R0. However, as described in the
Programming section, it can also be desirable to program R1
and R2 register settings on a channel-by-channel basis. These
settings are double buffered by the write to R0. This means that
while the data is loaded through the serial interface on the
respective R1 and R2 write cycles, the synthesizer is not updated
with their data until the next write to Register R0.
12-Bit FRAC Value
The 12 FRAC bits set the numerator of the fraction that is input
to the Σ-Δ modulator. This, along with INT, specifies the new
frequency channel that the synthesizer locks to, as shown in the
Worked Example section. FRAC values from 0 to MOD − 1
cover channels over a frequency range equal to the PFD
reference frequency.
Rev. B | Page 15 of 28
ADF4193
MOD/R REGISTER (R1)
4-BIT RF
R COUNTER
CONTROL
BITS
12-BIT MODULUS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
M6
DB7
M5
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
F5
F4
0
F2
F1
R4
R3
R2
R1
M12
M11
M10
M9
M8
M7
C3 (0) C2 (0) C1 (1)
F4 REF/2
0
1
DISABLE
ENABLE
F2 PRESCALER
F1 DOUBLER ENABLE
M12
M11
M10
M3
M2
M1
INTERPOLATOR MODULUS VALUE (MOD)
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
..........
1
1
1
.
.
.
1
1
1
1
0
1
1
.
.
.
0
0
1
1
1
0
1
.
.
.
0
1
0
1
13
14
15
.
.
.
4092
4093
4094
4095
0
1
4/5
8/9
0
1
DOUBLER DISABLED
DOUBLER ENABLED
..........
..........
..........
..........
..........
..........
..........
..........
..........
F5 CP ADJ
0
1
NOMINAL
ADJUSTED
R4
R3
R2
R1
RF R COUNTER DIVIDE RATIO
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
12
13
14
15
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Figure 30. MOD/R Register (R1)
Reserved Bit
This register is used to set the PFD reference frequency and the
channel step size, which is determined by the PFD frequency
divided by the fractional modulus. Note that the MOD, R
counter, REF/2, CP ADJ, and doubler enable bits are double
buffered. They do not take effect until the next write to R0
(FRAC/INT register) is complete.
Reserved Bit DB21 must be set to 0.
Doubler Enable
Setting this bit to 1 inserts a frequency doubler between REFIN
and the 4-bit R counter. Setting this bit to 0 bypasses the
doubler.
Control Bits
4-Bit RF R Counter
With C3, C2, and C1 set to 0, 0, 1, respectively, the MOD/R
register (R1) is programmed.
It allows the REFIN frequency to be divided down to produce the
reference clock to the PFD. All integer values from 1 to 15 are
allowed. See the Worked Example section.
CP ADJ
When this bit is set to 1, the charge pump current is scaled up
25ꢀ from its nominal value on the next write to R0. When this
bit is set to 0, the charge pump current stays at its nominal value
on the next write to R0. See the Programming section for more
information on how this feature can be used.
12-Bit Interpolator Modulus
For a given PFD reference frequency, the fractional denomina-
tor or modulus sets the channel step resolution at the RF
output. All integer values from 13 to 4095 are allowed. See the
Programming section for additional information and guidelines
for selecting the value of MOD.
REF/2
Setting this bit to 1 inserts a divide-by-2, toggle flip-flop
between the R counter and PFD, which extends the maximum
REFIN input rate.
Rev. B | Page 16 of 28
ADF4193
PHASE REGISTER (R2)
CONTROL
BITS
12-BIT PHASE
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
P6
DB7
P5
DB6
P4
DB5
P3
DB4
P2
DB3
P1
DB2
DB1
DB0
0
P12
P11
P10
P9
P8
P7
C3 (0) C2 (1) C1 (0)
1
P12
P11
P10
P3
P2
P1
PHASE VALUE
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
.
.
.
1
1
1
1
0
0
1
.
.
.
0
0
1
1
0
1
0
.
.
.
0
1
0
1
0
1
2
.
.
.
4092
4093
4094
4095
1
0 = < PHASE VALUE < MOD
Figure 31. Phase Register (R2)
12-Bit Phase
If it is desired to keep the output at the same phase offset with
respect to the reference, each time that particular output
frequency is programmed, then the interval between writes to
R0 must be an integer multiple of MOD reference cycles.
The phase word sets the seed value of the Σ-Δ modulator. It can
be programmed to any integer value from 0 to MOD. As the
phase word is swept from 0 to MOD, the phase of the VCO
output sweeps over a 360° range in steps of 360°/MOD.
If it is desired to keep the outputs of two ADF4193-based
synthesizers phase coherent with each other, but not necessarily
with their common reference, then it is only required to ensure
that the write to R0 on both chips is performed during the same
reference cycle. The interval between R0 writes in this case does
not have to be an integer multiple of the MOD cycles.
Note that the phase bits are double buffered. They do not take
effect until the LE of the next write to R0 (FRAC/INT register).
Therefore, if it is desired to change the phase of the VCO output
frequency, it is necessary to rewrite the INT and FRAC values to
R0, following the write to R2.
Reserved Bit
The output of a fractional-N PLL can settle to any one of the
MOD possible phase offsets with respect to the reference, where
MOD is the fractional modulus.
The reserved bit, Bit DB15, should be set to 0.
Rev. B | Page 17 of 28
ADF4193
FUNCTION REGISTER (R3)
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
1
DB5
F3
DB4
1
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
C3 (0) C2 (1) C1 (1)
F1 PFD POLARITY
0
1
NEGATIVE
POSITIVE
F3 CPO GND
0
1
CPO/CPO GND
NORMAL
Figure 32. Function Register (R3)
PFD Polarity
R3, the function register (C3, C2, C1 set to 0, 1, 1, respectively),
only needs to be programmed during the initialization sequence
(see Table 8).
This bit should be set to 1 for positive polarity and set to 0 for
negative polarity.
CPO GND
Reserved Bits
When the CPO GND bit is low, the charge pump outputs are
internally pulled to ground. This is invoked during the
initialization sequence to discharge the loop filter capacitors.
For normal operation, this bit should be high.
The Bit DB15 to Bit DB6 are reserved bits and should be
programmed to hex code 001, and Reserved Bit DB4 should be
set to 1.
Rev. B | Page 18 of 28
ADF4193
CHARGE PUMP REGISTER (R4)
TIMER
SELECT
CONTROL
BITS
RESERVED
9-BIT TIMEOUT COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
C4
DB7
C3
DB6
C2
DB5
C1
DB4
F2
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
C9
C8
C7
C6
C5
C3 (1) C2 (0) C1 (0)
F2 F1 TIMER SELECT
0
0
1
1
0
1
0
1
SW1/SW2
SW3
ICP
NOT USED
1
C9
C8
C7
C3
C2
C1
TIMEOUT COUNTER xPFD CYCLES
DELAY µs
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
508
509
510
511
0
4
8
12
.
.
.
2032
2036
2040
2044
0
0.15
0.30
0.46
.
.
.
78.15
78.30
78.46
78.61
1
DELAY WITH 26MHz PFD
Figure 33. Charge Pump Register (R4)
Table 6. Recommended Values for a GSM Tx LO
Time (μs) with
Value PFD = 13 MHz
Reserved Bits
Bit DB23 to Bit DB14 are reserved and should be set to hex
code 001 for normal operation.
Timer Select
Timeout Counter
10
01
00
ICP
SW1/2
SW3
28
35
35
8.6
10.8
10.8
9-Bit Timeout Counter
These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency, therefore, their time delay scales with the PFD
frequency according to
On each write to R0, the timeout counters start. Switch SW3
closes until the SW3 counter times out. Similarly, switches
SW1/SW2 close until the SW1/SW2 counter times out. When
the ICP counter times out, the charge pump current is ramped
down from 64× to 1× in six binary steps. It is recommended
that the SW1, SW2, and SW3 timeout counter values are set
equal to the ICP timeout counter value plus 7, as in the example
of Table 6.
Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)
For example, if 35 were loaded with timer select (00) with a
13 MHz PFD, then SW1/SW2 would be switched after
(35 × 4)/13 MHz = 10.8 μs
Timer Select
These two address bits select the timeout counter to be
programmed. Note that to set up the ADF4193 correctly
requires setup of these three timeout counters; therefore, three
writes to this register are required in the initialization sequence.
Table 6 shows example values for a GSM Tx synthesizer with a
60 kHz final loop BW. See the Applications section for more
information.
Rev. B | Page 19 of 28
ADF4193
POWER-DOWN REGISTER (R5)
PD
DIFF AMP
CONTROL
BITS
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
C3 (1) C2 (0) C1 (1)
F1
COUNTER RESET
0
1
NORMAL OPERATION
COUNTER RESET
CHARGE PUMP
F2 3-STATE
0
1
NORMAL OPERATION
3-STATE ENABLED
CHARGE PUMP
F3 POWER-DOWN
0
1
DISABLED
ENABLED
DIFF AMP
F5 F4 POWER-DOWN
0
1
0
1
DISABLED
ENABLED
Figure 34. Power-Down Register (R5)
R5, the power-down register (C3, C2, C1 set to 1, 0, 1,
For normal operation, Bit DB5 should be set to 0, followed by a
write to R0.
respectively) can be used to software power down the PLL and
differential amplifier sections. After power is initially applied,
there must be writes to R5 to clear the power-down bits and to
R2, R1, and R0 before the ADF4193 comes out of power-down.
CP Three-State
When this bit is set high, the charge pump outputs are put into
three-state. With the bit set low, the charge pump outputs are
enabled.
Power-Down Differential Amplifier
When Bit DB6 and Bit DB7 are set high, the differential
amplifier is put into power-down. When Bit DB6 and Bit DB7
are set low, normal operation is resumed.
Counter Reset
When this bit is set to 1, the counters are held in reset. For
normal operation, this bit should be 0, followed by a write to R0.
Power-Down Charge Pump
Setting Bit DB5 high activates a charge pump power-down and
the following events occur:
• All active dc current paths are removed, except for the
differential amplifier.
• The R and N divider counters are forced to their load state
conditions.
• The charge pump is powered down with its outputs in three-
state mode.
• The digital lock detect circuitry is reset.
• The RFIN input is debiased.
• The reference input buffer circuitry is disabled.
• The serial interface remains active and capable of loading and
latching data.
Rev. B | Page 20 of 28
ADF4193
MUX REGISTER (R6)
SIGMA-DELTA
AND
LOCK DETECT MODES
CONTROL
BITS
RESERVED
MUX
OUT
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
M13
M12
M11
M10
0
0
0
C3 (1) C2 (1) C1 (0)
SIGMA-DELTA MODES
M13
0
M12
M11
M10
0
M4 M3 M2 M1 MUX
OUT
0
0
INIT STATE, DITHER OFF,
3ns LOCK DETECT THRESHOLD
DITHER ON
10ns LOCK DETECT THRESHOLD
RESERVED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3-STATE
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
LOGIC HIGH
0
1
0
0
1
0
1
1
R COUNTER
RESERVED
ALL OTHER STATES
SERIAL DATA OUT
LOGIC LOW
R DIVIDER/2 OUTPUT
N DIVIDER/2 OUTPUT
RESERVED
RESERVED
ICP TIMEOUT SIGNAL
SW1/2 TIMEOUT SIGNAL
SW3 TIMEOUT SIGNAL
RESERVED
Figure 35. MUX Register (R6)
MUXOUT Modes
With C3, C2, and C1 set to 1, 1, 0, respectively, the MUX
register is programmed.
These bits control the on-chip multiplexer. See Figure 35 for the
truth table. This pin is useful for diagnosis because it allows the
user to look at various internal points of the chip, such as the
R divider and INT divider outputs.
Σ-Δ and Lock Detect Modes
Bit DB15 to Bit DB12 are used to reconfigure certain PLL
operating modes. In the initialization sequence after power is
applied to the chip, the four bits must first be programmed to
all zeros. This initializes the PLL to a known state with dither
off in the Σ-Δ modulator and a 3 ns PFD error threshold in the
lock detect circuit.
In addition, it is possible to monitor the programmed timeout
counter intervals on MUXOUT. For example, if the ICP timeout
counter was programmed to 65 (with a 26 MHz PFD), then
following the next write to R0, a pulse width of 10 μs would be
observed on the MUXOUT pin.
To turn on dither in the Σ-Δ modulator, an additional write
should be made to Register R6 to program bits [DB15:DB12] =
[0011]. However, for lowest noise operation, it is best to leave
dither off.
Digital lock detect is available via the MUXOUT pin.
To change the lock detect threshold from 3 ns to 10 ns, a
separate write to R6 should be performed to program bits
[DB15:DB12] = [1001]. This should be done for reliable lock
detect operation when the RF frequency is <2 GHz.
A write to R6 that programs bits [DB15:DB12] = [0000] returns
operation to the default state with both dither off and a 3 ns
lock detect threshold.
Reserved Bits
The reserved bits must all be set to 0 for normal operation.
Rev. B | Page 21 of 28
ADF4193
PROGRAMMING
The ADF4193 can synthesize output frequencies with a channel
step or resolution that is a fraction of the input reference frequency.
For a given input reference frequency and a desired output
frequency step, the first choice to make is the PFD reference
frequency and the MOD. Once these are chosen, the desired
output frequency channels are set by programming the INT
and FRAC values.
SPUR MECHANISMS
The Fractional Spurs, Integer Boundary Spurs, and Reference
Spurs sections describe the three different spur mechanisms
that arise with a fractional-N synthesizer and how the ADF4193
can be programmed to minimize them.
Fractional Spurs
The fractional interpolator in the ADF4193 is a third-order, Σ-Δ
modulator (SDM) with a modulus (MOD) that is programmable to
any integer value from 13 to 4095. If dither is enabled, then the
minimum allowed value of MOD is 50. The SDM is clocked at
the PFD reference rate (fPFD) that allows PLL output frequencies
to be synthesized at a channel step resolution of fPFD/MOD.
WORKED EXAMPLE
In this example of a GSM900 RX system, it is required to
generate RF output frequencies with channel steps of 200 kHz.
A 104 MHz reference frequency input (REFIN) is available. The
R divider setting that set the PFD reference is shown in
Equation 1.
With dither turned off, the quantization noise from the Σ-Δ
modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order modulator
used in the ADF4193, the repeat length depends on the value of
MOD, as shown in Table 7.
F
PFD = REFIN × [(1 + D)/(R × (1 + T))]
(1)
where:
REFIN is the input reference frequency.
D is the doubler enable bit (0 or 1).
R is the 4-bit R counter code (0…15).
T is the REF/2 bit (0 or 1).
Table 7. Fractional Spurs with Dither Off
Condition (Dither Off)
Repeat Length
Spur Interval
The maximum PFD reference frequency of 26 MHz is chosen
and the following settings are programmed to give an R divider
value of 4:
If MOD is divisible by 2,
but not 3
2 × MOD
Channel step/2
If MOD is divisible by 3,
but not 2
3 × MOD
Channel step/3
Doubler enable = 0
R = 2
If MOD is divisible by 6
Otherwise
6 × MOD
MOD
Channel step/6
Channel step
REF/2 = 1
With dither enabled, the repeat length is extended to 221 cycles,
regardless of the value of MOD, which makes the quantization
error spectrum look like broadband noise. This can degrade the
in-band phase noise at the PLL output by as much as 10 dB.
Therefore, for the lowest noise, dither off is a better choice,
particularly when the final loop BW is low enough to attenuate
even the lowest frequency fractional spur. The wide loop
bandwidth range available with the ADF4193 makes this
possible in most applications.
Next, the modulus is chosen to allow fractional steps of 200 kHz.
MOD = 26 MHz/200 kHz = 130
(2)
Once the channel step is defined, the following equation shows
how output frequency channels are programmed:
RFOUT = [INT + (FRAC/MOD] × [FPFD
]
(3)
where:
RFOUT is the desired RF output frequency.
INT is the integer part of the division.
Integer Boundary Spurs
Another mechanism for fractional spur creation involves
interactions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related, spur
sidebands appear on the VCO output spectrum at an offset
frequency that corresponds to the beat note or difference
frequency between an integer multiple of the reference and the
VCO frequency.
FRAC is the numerator part of the fractional division.
MOD is the modulus or denominator part of the fractional
division.
For example, the frequency channel at 962.4 MHz is synthesized
by programming the following values:
INT = 37
FRAC = 2
Rev. B | Page 22 of 28
ADF4193
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the refer-
ence where the difference frequency can be inside the loop
bandwidth, thus the name integer boundary spurs.
Table 8. Power-Up Initialization Sequence
Register Hex
Step
Bits
Codes
Description
1
2
R5 [7:0]
R3 [15:0] 005B
FD
Set all power-down bits.
PD polarity = 1, ground CPOUT+
/
The 8:1 loop bandwidth switching ratio of the ADF4193 makes
it possible to attenuate all spurs to sufficiently low levels for
most applications. The final loop BW can be chosen to ensure
that all spurs are far enough out of band while meeting the lock
time requirements with the 8× bandwidth boost.
CPOUT–.
Allow time for loop filter
capacitors to discharge.
Clear test modes.
Initialize PLL modes, digital lock
detect on MUXOUT
Wait
10 ms
3
4
R7 [15:0] 0007
R6 [15:0] 000E
.
The ADF4193’s programmable modulus and R divider can also
be used to avoid integer boundary channels. This option is
described in the Avoiding Integer Boundary Channels section.
5
R6 [15:0] 900E
10 ns lock detect threshold,
digital lock detect on MUXOUT
.
6
7
8
R4 [23:0] 004464 SW1/SW2 timer = 10.8 μs.
R4 [23:0] 00446C SW3 timer = 10.8 μs.
R4 [23:0] 004394 ICP timer = 8.6 μs.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers as the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such
mechanism is feedthrough of low levels of on-chip reference
switching noise out through the RFIN pin back to the VCO,
resulting in reference spur levels as high as –90 dBc. These
spurs can be suppressed below –110 dBc by inserting sufficient
reverse isolation, for example, through an RF buffer between
the VCO and RFIN pin. In addition, care should be taken in the
PCB layout to ensure that the VCO is well separated from the
input reference to avoid a possible feedthrough path on the board.
9
10
R2 [15:0] 00D2
R1 [23:0] 520209 8/9 prescaler, doubler disabled,
R = 4, toggle FF on, MOD = 65.
R0 [23:0] 480140 INT = 144, FRAC = 40 for
1880 MHz output frequency.
R3 [15:0] 007B
Phase = 26.
11
12
PD polarity = 1, release CPOUT+/
CPOUT–.
Clear all power-down bits.
13
14
R5 [7:0] 05
R0 [23:0] 480140 INT = 144, FRAC = 40 for
1880 MHz output frequency.
The ADF4193 powers up after Step 13. It locks to the
programmed channel frequency after Step 14.
POWER-UP INITIALIZATION
CHANGING THE FREQUENCY OF THE PLL AND THE
PHASE LOOK-UP TABLE
After applying power to the ADF4193, a 14-step sequence is
recommended, as described in Table 8.
Once the ADF4193 is initialized, a write to Register R0 is all
that is required to program a new output frequency. The N
divider is updated with the values of INT and FRAC on the next
PFD cycle following the LE edge that latches in the R0 word.
However, the settling time and spurious performance of the
synthesizer can be further optimized by modifying R1 and R2
register settings on a channel-by-channel basis. These settings
are double buffered by the write to R0. This means that while
the data is loaded in through the serial interface on the
respective R1 and R2 write cycles, the synthesizer is not
updated with their data until the next write to Register R0.
The divider and timer setting used in the example in Table 8 is
for a DCS1800 Tx synthesizer with a 104 MHz REFIN frequency.
The R2 register can be used to digitally adjust the phase of the
VCO output relative to the reference edge. The phase can be
adjusted over the full 360° range at RF with a resolution of
360°/MOD. In most frequency synthesizer applications, the
actual phase offset of the VCO output with respect to the
reference is unknown and does not matter. In such applications,
the phase adjustment capability of the R2 register can instead be
used to optimize the settling time performance, as described in
the Phase Look-Up Table section.
Rev. B | Page 23 of 28
ADF4193
Phase Look-Up Table
Avoiding Integer Boundary Channels
The ADF4193’s fast lock sequence is initiated following the
write to Register R0. The fast lock timers are programmed so
that after the PLL has settled in wide BW mode, the charge
pump current is reduced and loop filter resistor switches are
opened to reduce the loop BW. The reference cycle on which
these events occur is determined by the values preprogrammed
into the timeout counters.
A further option when programming a new frequency involves
a write to Register R1 to avoid integer boundary spurs. If it is
found that the integer boundary spur level is too high, an
option is to move the integer boundary away from the desired
channel by reprogramming the R divider to select a different
PFD frequency. For example, if REFIN = 104 MHz and R = 4 for
a 26 MHz PFD reference and MOD = 130 for 200 kHz steps, the
frequency channel at 910.2 MHz has a 200 kHz integer
Figure 10 and Figure 13 show that the lock time to final phase is
dominated by the phase swing that occurs when the BW is
reduced. Once the PLL has settled to final frequency and phase,
in wide BW mode, this phase swing is the same, regardless of
the size of the synthesizer’s frequency jump. The amplitude of
the phase swing is related to the current flowing through the
loop filter zero resistors on the PFD reference cycle that the
SW1/SW2 switches are opened. In an integer-N PLL, this
current is zero once the PLL has settled. In a fractional-N PLL,
the current is zero on average but varies from one reference
cycle to the next, depending on the quantization error sequence
output from the digital Σ-Δ modulator. Because the Σ-Δ
modulator is all digital logic, clocked at the PFD reference rate,
for a given value of MOD, the actual quantization error on any
given reference cycle is determined by the value of FRAC and
the PHASE word that the modulator is seeded with, following
the write to R0. By choosing an appropriate value of PHASE,
corresponding to the value of FRAC, that is programmed on the
next write to R0, the size of the error current on the PFD
reference cycle the SW1/SW2 switches opened, and thus the
phase swing that occurs when the BW is reduced can be
minimized.
boundary spur because it is 200 kHz offset from 35 × 26 MHz.
An alternative way to synthesize this channel is to set R = 5 for a
20.8 MHz PFD reference and MOD = 104 for 200 kHz steps.
The 910.2 MHz channel is now 5 MHz offset from the nearest
integer multiple of 20.8 MHz and the 5 MHz beat note spurs are
well attenuated by the loop. Setting double buffered Bit R1 [23] = 1
(CP ADJ bit) increases the charge pump current by 25ꢀ, which
compensates for the 25ꢀ increase in N with the change to the
20.8 MHz PFD frequency. This maintains constant loop
dynamics and settling time performance for jumps between the
two PFD frequencies. The CP ADJ bit should be cleared again
when jumping back to 26 MHz-based channels.
The Register R1 settings necessary for integer boundary spur
avoidance are all double buffered and do not become active on
the chip until the next write to Register R0. Register R0 should
always be the last register written to when programming a new
frequency.
Serial Interface Activity
The serial interface activity when programming the R2 or R1
registers causes no noticeable disturbance to the synthesizers
settled phase or degradation in its frequency spectrum.
Therefore, in a GSM application, it can be performed during
the active part of the data burst. Because it takes just 10.2 μs to
program the three registers, R2, R1, and R0, with the 6.5 MHz
serial interface clock rate typically used, this programming can
also be performed during the previous guard period with the
LE edge to latch in the R0 data delayed until it’s time to switch
frequency.
With dither off, the fractional spur pattern due to the SDM’s
quantization noise also depends on the phase word the modulator
is seeded with. Tables of optimized FRAC and phase values for
popular SW1/SW2 and ICP timer settings can be down-loaded
from the ADF4193 product page. If making use of a phase table,
first write phase to double buffered Register R2, then write the
INT and FRAC to R0.
Rev. B | Page 24 of 28
ADF4193
APPLICATIONS
LOCAL OSCILLATOR FOR A GSM BASE STATION
Timer Values for Tx
To comply with the GSM spectrum due to switching require-
ments, the Tx synthesizer should not switch frequency until the
PA output power has ramped down by at least 50 dB. If it takes
10 μs to ramp down to this level, then only the last 20 μs of the
30 μs guard period is available for the Tx synthesizer to lock to
final frequency and phase.
Figure 36 shows the ADF4193 being used with a VCO to
produce the LO for a GSM1800 base station. For GSM, the
REFIN signal can be any integer multiple of 13 MHz, but the
main requirement is that the slew rate is at least 300 V/μs.
The 5 dBm, 104 MHz input sine wave shown satisfies this
requirement.
In fast lock mode, the Tx loop BW is widened by a factor-of-8
to 480 kHz, and therefore, the PLL achieves frequency lock for a
jump across the entire band in <6 μs. After this, the PA power
can start to ramp up again, and the loop BW can be restored to
the final value. With the ICP timer = 28, the charge pump
current reduction begins at ~8.6 μs. When SW1, SW2, and SW3
timers = 35, the current reaches its final value before the loop
filter switches open at ~10.8 μs.
Recommended parameters for the various GSM/PCS/DCS
synthesizers are given in Table 9.
Table 9. Recommended Setup Parameters
GSM900
DCS1800/PCS1900
Parameter
Loop BW
PFD (MHz)
MOD
Dither
Prescaler
ICP Timer
Tx
Rx
Tx
Rx
60 kHz
13
65
Off
4/5
28
40 kHz
26
130
Off
4/5
78
60 kHz
13
65
Off
8/9
28
40 kHz
13
65
Off
8/9
38
With these timer values, the phase disturbance created when
the bandwidth is reduced settles back to its final value by 20 μs,
in time for the start of the active part of the GSM burst. If faster
phase settling is desired with the 60 kHz BW setting, then the timer
values can be reduced further but should not be brought less than
the 6 μs it takes to achieve frequency lock in wide BW mode.
SW1, SW2,
35
85
35
45
SW3 Timers
VCO KV
18 MHz/V 18 MHz/V 38 MHz/V 38 MHz/V
Timer Values for Rx
Loop BW and PFD Frequency
The 40 kHz Rx loop BW is increased by a factor-of-8 to
approximately 320 kHz during fast lock. With the Rx timer
values shown, the BW is reduced after ~12 μs, which allows
sufficient time for the phase disturbance to settle back before
the start of the active part of the Rx time slot at 30 μs. As in the
Tx case, faster Rx settling can be achieved by reducing these
timer values, their lower limit being determined by the time it
takes to achieve frequency lock in wide BW mode. In addition,
the PCS and DCS Rx synthesizers have relaxed 800 kHz blocker
specifications and thus can tolerate a wider loop BW, which
allows correspondingly faster settling.
A 60 kHz loop BW is narrow enough to attenuate the PLL phase
noise and spurs to the required level for a Tx low. A 40 kHz BW
is necessary to meet the GSM900 Rx synthesizer’s particularly
tough phase noise and spur requirements at 800 kHz offsets.
To get the lowest spur levels at 800 kHz offsets for Rx, the Σ-Δ
modulator should be run at the highest oversampling rate
possible. Therefore, for GSM900 Rx, a 26 MHz PFD frequency
is chosen and MOD = 130 is required for 200 kHz steps.
Because this value of MOD is divisible by two, certain FRAC
channels have a 100 kHz fractional spur. This is attenuated by
the 40 kHz loop filter and therefore is not a concern. However,
the 60 kHz loop filter recommended for Tx has a closed-loop
response that peaks close to 100 kHz. Therefore, a 13 MHz PFD
with MOD = 65, which avoids the 100 kHz spur, is the best
choice for a Tx synthesizer.
VCO KV
In general, the VCO gain, KV, should be set as low as possible to
minimize the reference and integer boundary spur levels that arise
due to feedthrough mechanisms. When deciding on the optimum
VCO KV, a good choice is to allow 2 V to tune across the desired
band, centered on the available tuning range. With VP3 regulated
to 5.5 V 100 mV, the tuning range available is 2.8 V.
Dither
Dither off should be selected for the lowest rms phase error.
Prescaler
Loop Filter Components
The 8/9 prescaler should be selected for the PCS and DCS
bands. The 4/5 prescaler allows an N divider range low enough
to cover the GSM900 Tx and Rx bands with either a 13 MHz or
26 MHz PFD frequency.
It is important for good settling performance that capacitors
with low dielectric absorption are used in the loop filter.
Ceramic NPO COG capacitors are a good choice for this
application. A 2ꢀ tolerance is recommended for loop filter
capacitors and 1ꢀ for resistors. A 10ꢀ tolerance is adequate
for the inductor, L1.
Rev. B | Page 25 of 28
ADF4193
ADI SimPLL SUPPORT
Also available is a technical note (ADF4193-TN-001) that
outlines a loop filter design procedure that takes full advantage
of the new degree of freedom in the filter design that the
differential amplifier and loop filter switches provide.
The ADF4193 loop filter design is supported on ADI SimPLL
v2.7 or later. Example files for popular applications are available
for download from the applications section of the ADF4193
product page.
10pF
100pF
18Ω 18Ω
18Ω
RF OUT
5V
+
10µF
3V
5.5V
100nF
+
10µF
100nF
100nF
15
SVD V
100nF
8, 10, 13
100nF
20
100pF
24
7
32
V 3
DV
V
1
V 2
AV
DD
DD
DD
P
P
P
+
10µF
30
CP
OUT+
SW1
C1A
100pF
C2A
6
5
120pF
1.20nF
RFIN+
RFIN–
INTEGRATED
R1A2
820Ω
DIFFERENTIAL
AMPLIFIER
100nF
51Ω
R3
29
62Ω
3
2
R1A2
6.20kΩ
SW3
AIN+
100pF
R2
1.80kΩ
ADF4193
31
25
28
27
SW
AIN–
A
GND
L1
2.2mH
C3
470pF
Ct
30pF
OUT
R1B2
6.20kΩ
1nF
1nF
11
REF
LE
IN
CMR
1
SW2
51Ω
REFERENCE
104MHz, +5dBm
R1B1
820Ω
C2B
1.20nF
SIRENZA VCO190-1843T
38MHz/V
19
18
17
100nF
DATA
CLK
26
16
CP
OUT–
C1B
120pF
23
R
MUX
OUT
SET
R
SET
SD
A
D
GND
GND
GND
2.40kΩ
LOCK DETECT OUT
14
4, 22
9, 12, 21
Figure 36. Local Oscillator for DCS1800 Tx Using the ADF4193
Rev. B | Page 26 of 28
ADF4193
ADSP-21xx Interface
INTERFACING
Figure 38 shows the interface between the ADF4193 and the
ADSP-21xx digital signal processor. The ADF4193 needs a
24-bit serial word for some writes. The easiest way to accom-
plish this using the ADSP-21xx family is to use the autobuffered
transmit mode of operation with alternate framing. This
provides a means for transmitting an entire block of serial data
before an interrupt is generated. Set up the word length for
eight bits and use three memory locations for each 24-bit word.
To program each 24-bit word, store the three 8-bit bytes, enable
the autobuffered mode, and then write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
The ADF4193 has a simple SPI®-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that have been clocked
into the input register on each rising edge of CLK are latched
into the appropriate register. See Figure 2 for the timing
diagram and Table 5 for the register address table.
The maximum allowable serial clock rate is 33 MHz.
ADuC812 Interface
Figure 37 shows the interface between the ADF4193 and the
ADuC812 MicroConverter®. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Some registers of the ADF4193
require a 24-bit programming word. This is accomplished by
writing three 8-bit bytes from the MicroConverter to the device.
When the third byte is written, the LE input should be brought
high to complete the transfer.
ADSP-21xx
ADF4193
SCLK
CLK
DT
DATA
LE
TFS
MUX
I/O FLAGS
OUT
(LOCK DETECT)
An I/O port line on the ADuC812 can also be used to detect
lock (MUXOUT configured as lock detect and polled by the
port input).
Figure 38. ADSP-21xx to ADF4193 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
ADuC812
ADF4193
The lands on the chip scale package (CP-32-3) are rectangular.
The printed circuit board (PCB) pad for these should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The land should be centered on
the pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
SCLOCK
CLK
MOSI
DATA
LE
I/O PORTS
MUX
OUT
(LOCK DETECT)
The thermal pad on the PCB should be at least as large as the
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Figure 37. ADuC812 to ADF4193 Interface
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
should be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter should be between 0.3 mm and 0.33 mm, and
the via barrel should be plated with one ounce copper to plug
the via.
The user should connect the PCB thermal pad to AGND
.
Rev. B | Page 27 of 28
ADF4193
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
EXPOSED
PAD
(BOTTOM VIEW)
3.45
3.30 SQ
3.15
TOP
VIEW
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
CP-32-3
CP-32-3
ADF4193BCPZ1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board (GSM 1800)
ADF4193BCPZ-RL1
ADF4193BCPZ-RL71
EVAL-ADF4193EB1
EVAL-ADF4193EB2
CP-32-3
Evaluation Board (No VCO or Loop Filter)
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05328-0-6/06(B)
Rev. B | Page 28 of 28
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