ADF4207 [ADI]
Dual RF PLL Frequency Synthesizers; 双射频锁相环频率合成器
| 型号： | ADF4207 |
| 厂家： | 
ADI |
| 描述： | Dual RF PLL Frequency Synthesizers |
| 文件： | 总20页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Dual RF PLL Frequency Synthesizers
ADF4206/ADF4207/ADF4208
GENERAL DESCRIPTION
FEATURES
The ADF4206 family of dual frequency synthesizers can be
used to implement local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
Each synthesizer consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, programmable A and B counters and a dual-
modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit)
counters, in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter), allows selectable REFIN frequen-
cies at the PFD input. The on-chip oscillator circuitry allows
the reference input to be derived from crystal oscillators.
ADF4206: 550 MHz/550 MHz
ADF4207: 1.1 GHz/1.1 GHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Selectable Charge Pump Currents
On-Chip Oscillator Circuit
Selectable Dual Modulus Prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode
A complete PLL (Phase-Locked Loop) can be implemented if
the synthesizers are used with an external loop filter and VCOs
(Voltage Controlled Oscillators).
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
V
1
V
2
V 1
V 2
P
DD
DD
P
N = BP + A
ADF4206/ADF4207/ADF4208
11-BIT RF2
B-COUNTER
PHASE
COMPARATOR
RF2
A
B
IN
RF2
PRESCALER
RF2
CHARGE
PUMP
IN
CP
RF2
6-BIT RF2
A-COUNTER
RF2
LOCK
DETECT
OSC
IN
OSCILLATOR
OSC
OUT
14-BIT RF2
R-COUNTER
OUTPUT
MUX
MUXOUT
CLOCK
DATA
LE
22-BIT
DATA
REGISTER
SDOUT
RF1
14-BIT RF1
R-COUNTER
LOCK
DETECT
N = BP + A
CHARGE
PUMP
CP
RF1
11-BIT RF1
B-COUNTER
PHASE
COMPARATOR
RF1
A
B
IN
RF1
PRESCALER
RF1
IN
6-BIT RF1
A-COUNTER
AGND
RF1
DGND
RF2
AGND
RF2
DGND
RF1
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001
ADF4206/ADF4207/ADF4208–SPECIFICATIONS1
(VDD1 = VDD2 = 3 V ؎ 10%, 5 V ؎ 10%;
VDD1, VDD2 Յ VP1, VP2 Յ 6.0 V; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX unless otherwise noted, dBm referred to 50 ⍀.)
Parameter
B Version
B Chips2 Unit
Test Conditions/Comments
RF/IF CHARACTERISTICS (3 V)
See Figure 2 for input circuit.
RF1 Input Frequency (RF1IN
)
Use a square wave for frequencies lower than fMIN.
ADF4206
ADF4207
ADF4208
RF Input Sensitivity
0.05/0.55
0.08/1.1
0.08/2.0
–15/+4
0.05/0.55 GHz min/max
0.08/1.1
0.08/2.0
–15/+4
GHz min/max
GHz min/max
dBm min/max
IF Input Frequency (RF2IN
ADF4206
ADF4207/ADF4208
IF Input Sensitivity
)
0.05/0.55
0.08/1.1
–15/+4
165
0.05/0.55 GHz min/max
0.08/1.1
–15/+4
165
GHz min/max
dBm min/max
MHz max
Maximum Allowable Prescaler Output
Frequency3
RF CHARACTERISTICS (5 V)
RF1 Input Frequency (RF1IN
)
Use a square wave for frequencies lower than fMIN.
ADF4206
ADF4207
ADF4208
RF Input Sensitivity
0.05/0.55
0.08/1.1
0.08/2.0
–10/+4
0.05/0.55 GHz min/max
0.08/1.1
0.08/2.0
–10/+4
GHz min/max
GHz min/max
dBm min/max
MHz min/max
IF Input Frequency (RF2IN
)
ADF4206
ADF4207/ADF4208
IF Input Sensitivity
0.05/0.55
0.08/1.1
–10/+4
200
0.05/0.55 GHz min/max
0.08/1.1
–10/+4
200
GHz min/max
dBm min/max
MHz max
Maximum Allowable Prescaler Output
Frequency3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity4
5/40
–2
5/40
–2
MHz min/max For f < 5 MHz Use Square Wave 0 to VDD
dBm min
AC-Coupled. When DC-Coupled,
0 to VDD Max (CMOS-Compatible)
REFIN Input Capacitance
REFIN Input Current
10
100
10
100
pF max
µA max
PHASE DETECTOR
Phase Detector Frequency5
55
55
MHz max
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
ICP Three-State Leakage Current
5
5
mA typ
mA typ
% typ
1.25
2.5
1
1.25
2.5
1
nA typ
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
0.8 × VDD
0.8 × VDD V min
0.2 × VDD V max
0.2 × VDD
1
10
1
µA max
10
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
VDD – 0.4
0.4
VDD – 0.4 V min
IOH = 500 µA
IOL = 500 µA
0.4
V max
POWER SUPPLIES
VDD
VDD
VP
1
2
2.7/5.5
2.7/5.5
VDD1
VDD1/6.0
V min/V max
V min/V max
VDD1
VDD1/6.0
VDD1, VDD2 Յ VP1, VP2 Յ 6.0 V
IDD (IDD1 + IDD2)6
ADF4206
14
16.5
21
14
16.5
21
mA max
mA max
mA max
9.5 mA Typical at VDD = 3 V, TA = 25°C
11 mA Typical at VDD = 3 V, TA = 25°C
14 mA Typical at VDD = 3 V, TA = 25°C
ADF4207
ADF4208
IDD
1
ADF4206
ADF4207
ADF4208
8
9
14
8
9
14
mA max
mA max
mA max
5.5 mA Typical at VDD = 3 V, TA = 25°C
6 mA Typical at VDD = 3 V, TA = 25°C
9 mA Typical at VDD = 3 V, TA = 25°C
IDD
2
ADF4206
ADF4207
ADF4208
IP (IP1 + IP2)
Low-Power Sleep Mode
7.5
8.5
9
1
0.5
7.5
8.5
9
1
0.5
mA max
mA max
mA max
mA max
µA typ
5 mA Typical at VDD = 3 V, TA = 25°C
5.5 mA Typical at VDD = 3 V, TA = 25°C
5.5 mA Typical at VDD = 3 V, TA = 25°C
TA = 25°C
–2–
REV. 0
ADF4206/ADF4207/ADF4208
Parameter
B Version
B Chips2 Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Phase Noise Floor (RF1)7
ADF4206
–169
–171
–173
–160
–162
–164
–169
–171
–173
–160
–162
–164
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 25 kHz PFD Frequency
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 540 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
@ 836 MHz, 30 kHz at PFD
@ 1750 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
@ 1750 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
ADF4207
ADF4208
ADF4206
ADF4207
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
ADF4208
Phase Noise Performance8
ADF4206 (RF1, RF2)
ADF4207 (RF1, RF2)
ADF4207 (RF1, RF2)9
ADF4208 (RF1)
–92
–90
–81
–85
–91
–66
–89
–92
–90
–81
–85
–91
–66
–89
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
ADF4208 (RF1)
ADF4208 (RF1)10
ADF4208 (RF2)
Spurious Signals
RF1, RF2 (20 kHz Loop B/W)
RF1, RF2 (1 kHz Loop B/W)
–80/–84
–65/–73
–80/–84
–65/–73
dB typ
dB typ
@ 200 kHz/400 kHz and 200 kHz PFD
@10 kHz/20 kHz and 10 kHz PFD
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2The B Chip specifications are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is
less than this value.
4VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels.
5Guaranteed by design. Sample tested to ensure compliance.
6Typical values apply for VDD = 3 V; P = 32; RF1IN1/RF2IN2 for ADF4206 = 540 MHz; RF1IN1/RF2IN2 for ADF4207 = 900 MHz; RF1IN1/RF2IN2 for ADF4208 = 900 MHz.
7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8The phase noise is measured at a 1 kHz unless otherwise noted. The phase noise is measured with the EVAL-ADF4206/ADF4207EB or the EVAL-AD4208EB Evaluation
Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
9fREFIN = 10 MHz; fPFD = 30 kHz; Offset Frequency = 300 Hz; fRF/IF = 836 MHz; N = 27866; Loop B/W = 3 kHz.
10
f
= 10 MHz; fPFD = 10 kHz; Offset Frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
REFIN
Specifications subject to change without notice.
–3–
REV. 0
ADF4206/ADF4207/ADF4208
(VDD1 = VDD2 = 3 V ؎ 10%, 5 V ؎ 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V; AGNDRF1 = DGNDRF1
=
TIMING CHARACTERISTICS
AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX unless otherwise noted, dBm referred to 50 ⍀.)
Limit at
TMIN to TMAX
(B Version)
Parameter
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.
t4
t3
CLOCK
t1
t2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB21 (MSB)
DATA
DB20
DB2
t6
LE
LE
t5
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2
CSP θJA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W
CSP θJA (Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
(TA = 25°C unless otherwise noted.)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP1, VP2 to VDD . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
V
1
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
OSCIN, OSCOUT, RF1IN (A, B),
RF2IN (A, B) to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RFINA to RFINB (RF1, RF2) . . . . . . . . . . . . . . . . . . 320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
3GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option*
ADF4206BRU
ADF4207BRU
ADF4208BRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
RU-16
RU-16
RU-20
*Contact the factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4206/ADF4207/ADF4208 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
ADF4206/ADF4207/ADF4208
PIN FUNCTION DESCRIPTIONS
Mnemonic
ADF4206/
ADF4207
Pin
No.
ADF4208
Function
1
VDD
1
VDD
1
Positive Power Supply for the RF1 Section. A 0.1 µF capacitor should be connected between
this pin and the RF1 ground pin, DGNDRF1. VDD1 should have a value of between 2.7 V and
5.5 V. VDD1 must have the same potential as VDD2.
2
3
VP1
CPRF1
VP1
CPRF1
Power Supply for the RF1 Charge Pump. This should be greater than or equal to VDD.
Output from the RF1 Charge Pump. This is normally connected to a loop filter which, in
turn, drives the input to an external VCO.
4
5
6
DGNDRF1
RF1IN
OSCIN
DGNDRF1
RF1INA
RFINB
Ground Pin for the RF1 Digital Circuitry.
Input to the RF1 Prescaler. This low-level input signal is normally taken from the RF1 VCO.
Complementary Input to the RF1 Prescaler of the ADF4208. This point should be decoupled to
the ground plane with a small bypass capacitor.
7
8
OSCOUT
MUXOUT
AGNDRF1
OSCIN
Ground Pin for the RF1 Analog Circuitry.
Oscillator Input. It has a VDD/2 threshold and can be driven from an external CMOS or TTL
logic gate.
9
CLK
OSCOUT
Oscillator Output.
10
DATA
MUXOUT
This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled
Reference Frequency to be accessed externally. See Table V.
11
LE
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 22-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
12
13
RF2IN
DATA
LE
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected using the control bits.
DGNDRF2
14
15
CPRF2
VP2
AGNDRF2
RF2INB
Ground Pin for the RF2 Analog Circuitry.
Complementary Input to the RF2 Prescaler. This point should be decoupled to the ground
plane with a small bypass capacitor.
16
V
DD2
RF2INA
Input to the RF2 Prescaler. This low-level input signal is normally ac-coupled to the
external VCO.
17
18
DGNDRF2
CPRF2
Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives
the input to an external VCO.
19
20
VP2
Power Supply for the RF2 Charge Pump. This should be greater than or equal to VDD.
VDD2
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 µF capacitor
should be connected between this pin and the RF2 ground Pin, DGNDRF2. VDD2 should
have a value between 2.7 V and 5.5 V. VDD2 must have the same potential as VDD1.
PIN CONFIGURATIONS
TSSOP
TSSOP
V
1
1
2
V
2
20
1
1
DD
16
15
14
13
12
11
10
9
V
2
V
DD
DD
DD
19 V 2
P
2
3
4
5
6
7
8
V 1
P
V 2
P
V 1
P
ADF4206/
ADF4207
3
18
CP
CP
CP
CP
RF1
RF2
RF2
RF1
4
17
16
15
14
DGND
DGND
DGND
DGND
RF2
RF1
RF2
RF1
ADF4208
5
RF2
RF2
A
B
RF1
I
A
N
RF1
RF2
IN
N
N
I
I
N
I
TOP VIEW
(Not to Scale)
6
OSC
RF1
I
B
N
LE
IN
7
TOP VIEW
(Not to Scale)
AGND
DATA
CLK
AGND
OSC
RF2
RF1
OUT
8
13 LE
12
OSC
MUXOUT
IN
9
OSC
DATA
OUT
10
MUXOUT
11
CLK
–5–
REV. 0
–Typical Performance Characteristics
ADF4206/ADF4207/ADF4208
0
V
I
= 3V, V = 5V
P
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE – OHMS
DD
= 5mA
GHz
S
MA
R
50
–10
CP
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
REFERENCE LEVEL =
–4.2dBm
FREQ MAGS11
ANGS11
FREQ MAGS11
ANGS11
–20
–30
–40
–50
–60
0.0
0.957111193 –3.130429321 1.35
0.963546793 –6.686426265 1.45
0.953621785 –11.19913586 1.55
0.953757706 –15.35637483 1.65
0.816886959 –51.80711782
0.825983016 –56.20373378
0.791737125 –61.21554647
0.770543186 –61.88187496
0.793897072 –65.39516615
0.745765233 –69.24884474
0.15
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
1.15
1.25
0.929831379 –20.3793432
1.75
0.908459709 –22.69144845 1.85
0.897303634 –27.07001443 1.95
0.876862863 –31.32240763 2.05
0.849338092 –33.68058163 2.15
0.858403269 –38.57674885 2.25
0.841888714 –41.48606772 2.35
0.840354983 –45.97597958 2.45
0.822165839 –49.19163116 2.55
0.7517547
–71.21608147
0.745594889 –75.93169947
0.713387801 –78.8391674
0.711578577 –81.71934806
0.698487131 –85.49067481
0.669871818 –88.41958754
0.668353367 –91.70921678
–70
–90.2dBc/Hz
–80
–90
–100
–200k
900M
FREQUENCY – Hz
200k
400k
–400k
TPC 1. S-Parameter Data for the AD4208 RF1 Input
(Up to 2.5 GHz)
TPC 4. ADF4208 RF1 Reference Spurs (900 MHz,
200 kHz, 20 kHz)
0
–40
V
V
= 5V
DD
= 5V
10dB/DIVISION
P
–50
–5
–10
–15
–20
–25
–30
–35
R
= –40dBc/Hz
L
rms NOISE = 0.52؇
–60
–70
–80
T
= +85؇C
A
0.52؇ rms
–90
–100
–110
–120
T
= –40؇C
A
T
= +25؇C
–130
–140
A
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
100Hz
1kHz
10kHz
100kHz
1MHz
RF INPUT SENSITIVITY – GHz
FREQUENCY OFFSET FROM 900MHz CARRIER
TPC 2. Input Sensitivity for the ADF4208 (RF1)
TPC 5. ADF4208 RF1 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz)
0
–40
V
I
= 3V, V = 5V
P
DD
= 5mA
10dB/DIVISION
–10
–50
CP
R
= –40dBc/Hz
L
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
REFERENCE LEVEL =
–4.2dBm
rms NOISE = 0.62؇
–20
–30
–40
–50
–60
–60
–70
–80
0.62؇ rms
–90
–100
–110
–120
–70
–90.5dBc/Hz
–80
–90
–130
–140
–100
–2k
–1k
900M
FREQUENCY – Hz
1k
2k
100Hz
1kHz
10kHz
100kHz
1MHz
FREQUENCY OFFSET FROM 900MHz CARRIER
TPC 3. ADF4208 RF1 Phase Noise (900 MHz, 200 kHz,
20 kHz)
TPC 6. ADF4208 RF1 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz)
–6–
REV. 0
ADF4206/ADF4207/ADF4208
0
0
V
I
= 3V, V = 5V
P
DD
= 5mA
V
I
= 3V, V = 5V
P
DD
= 5mA
–10
–10
CP
CP
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 35kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
REFERENCE LEVEL =
–4.2dBm
REFERENCE LEVEL =
–5.7dBm
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 3Hz
VIDEO BANDWIDTH = 3Hz
SWEEP = 255 SECONDS
POSITIVE PEAK
–20
–30
–40
–50
–60
–20
–30
–40
–50
–60
DETECT MODE
–79.6dBc
–70
–70
–89.3dBc
–80
–90
–80
–90
–100
–100
–200k
1750M
FREQUENCY – Hz
40k
80k
–400k
–200k
200k
400k
–400k
900M
FREQUENCY – Hz
TPC 7. ADF4208 RF1 Reference Spurs (900 MHz,
200 kHz, 35 kHz)
TPC 10. ADF4208 RF1 Reference Spurs (1750 MHz,
30 kHz, 3 kHz)
–120
0
V
V
= 3V
V
I
= 3V, V = 5V
P
= 5mA
DD
P
DD
= 5V
–10
CP
–130
–140
–150
–160
–170
–180
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 10kHz
VIDEO BANDWIDTH = 10kHz
SWEEP = 477ms
REFERENCE LEVEL =
–8.0dBm
–20
–30
–40
–50
–60
AVERAGES = 10
ADF4206
ADF4207
ADF4208
–70
–75.2dBc/Hz
–80
–90
–100
1
10
100
1000
10000
–200
1750M
200
400
–400
PHASE DETECTOR FREQUENCY – kHz
FREQUENCY – Hz
TPC 11. ADF4208 RF1 Phase Noise vs. PFD Frequency
TPC 8. ADF4208 RF1 Phase Noise (1750 MHz, 30 kHz, 3 kHz)
–60
–40
10dB/DIVISION
–50
V
V
= 3V
= 3V
DD
R
= –40dBc/Hz
L
P
–60
–70
–80
–70
–80
–90
1.6؇ rms
–100
–110
–120
–90
–130
–140
–100
–40
–20
0
20
40
60
80
100
100Hz
1kHz
10kHz
100kHz
1MHz
TEMPERATURE – ؇C
FREQUENCY OFFSET FROM 1750MHz CARRIER
TPC 12. ADF4208 RF1 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
TPC 9. ADF4208 RF1 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
–7–
REV. 0
ADF4206/ADF4207/ADF4208
–60
3.0
2.5
V
V
= 3V
= 3V
DD
P
V
V
= 3V
= 5V
DD
P
–70
–80
2.0
1.5
1.0
0.5
0
–90
–100
–40
–20
0
20
40
60
80
100
0
50
100
150
200
TEMPERATURE – ؇C
PRESCALER OUTPUT FREQUENCY – MHz
TPC 13. ADF4208 RF1 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
TPC 16 DIDD vs. Prescaler Output Frequency (All Models,
RF1 and RF2)
10
–5
–15
9
V
V
= 3V
ADF4208
DD
= 5V
P
8
7
6
–25
–35
–45
–55
–65
–75
–85
–95
–105
ADF4207
5
4
ADF4206
3
2
1
0
32/33
64/65
0
1
2
3
4
5
TUNING VOLTAGE – V
PRESCALER VALUE
TPC 14. ADF4208 RF1 Reference Spurs vs. VTUNE
(900 MHz, 200 kHz, 20 kHz)
TPC 17. ADF4206/ADF4207/ADF4208 AIDD vs. Prescaler
Value (RFI)
–120
V
V
= 3V
DD
= 5V
P
–130
–140
–150
–160
–170
–180
ADF4206
ADF4207
ADF4208
1
10
100
1000
10000
PHASE DETECTOR FREQUENCY – kHz
TPC 15. ADF4208 RF2 Phase Noise vs. PFD Frequency
–8–
REV. 0
ADF4206/ADF4207/ADF4208
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2
are opened. Typical recommended external components are
shown in Figure 2.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 200 MHz or less.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
POWER-DOWN
CONTROL
f
VCO = [(P × B) + A] × fREFIN/R
NC
100k⍀
SW2
fVCO = Output frequency of external voltage controlled
TO R
COUNTER
OSC
OSC
NC
IN
oscillator (VCO).
BUFFER
30pF
30pF
SW1
P
= Preset modulus of dual modulus prescaler
(32/33, 64/65).
SW3
NO
B
A
= Preset Divide Ratio of binary 11-bit counter
(1 to 2047).
OUT
18k⍀
= Preset Divide Ratio of binary 6-bit A counter
(0 to 63).
Figure 2. RF Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplifier to generate the CML clock levels needed
for the prescaler.
fREFIN = Output frequency of the external reference frequency
oscillator.
R
= Preset divide ratio of binary 14-bit programmable
reference counter (1 to 16383).
1.6V
R COUNTER
BIAS
GENERATOR
AV
DD
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
2k⍀
2k⍀
RF
A
B
IN
N = BP + A
RF
11-BIT B
TO PFD
IN
COUNTER
LOAD
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
LOAD
AGND
MODULUS
CONTROL
6-BIT A
COUNTER
Figure 3. RF Input Stage
N DIVIDER
PRESCALER
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the RF input stage and divides it down to a man-
ageable frequency for the CMOS A and B counters. It is based
on a synchronous 4/5 core.
Figure 4. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic.
The prescaler is selectable. Both RF1 and RF2 can be set to
either 32/33 or 64/65. DB20 of the AB counter latch selects
the value. See Tables IV and VI.
–9–
REV. 0
ADF4206/ADF4207/ADF4208
DV
DD
V
P
CHARGE
PUMP
UP
HI
RF2 ANALOG LOCK DETECT
RF2 R COUNTER OUTPUT
RF2 N COUNTER OUTPUT
RF2/RF1 ANALOG LOCK DETECT
RF1 R COUNTER OUTPUT
RF1 N COUNTER OUTPUT
D1
Q1
U1
MUXOUT
MUX
CONTROL
R DIVIDER
CLR1
RF1 ANALOG LOCK DETECT
DELAY
ELEMENT
CP
U3
DGND
Figure 6. MUXOUT Circuit
Lock Detect
CLR2
U2
DOWN
MUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 kΩ nominal. When lock
has been detected it is high with narrow low-going pulses.
HI
D2
Q2
N DIVIDER
CPGND
INPUT SHIFT REGISTER
The functional block diagram for the ADF4206 family is shown
on Page 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and an 17-bit N counter, comprising a 6-bit
A counter and an 11-bit B counter. Data is clocked into the 22-bit
shift register on each rising edge of CLK. The data is clocked
in MSB first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination latch is
determined by the state of the two control bits (C2, C1) in the
shift register. These are the two LSBs DB1, DB0, as shown in
the timing diagram of Figure 1. The truth table for these bits is
shown in Table I.
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 5. PFD Simplified Schematic and Timing (In Lock)
The PFD includes a delay element which sets the width of the
antibacklash phase. The typical value for this is in the ADF4206
family is 3 ns. The pulse ensures that there is no deadzone in
the PFD transfer function and minimizes phase noise and refer-
ence spurs.
Table I. C2, C1 Truth Table
Control Bits
MUXOUT AND LOCK DETECT
C2
C1
Data Latch
The output multiplexer on the ADF4206 family allows the
user to access various internal points on the chip. The state
of MUXOUT is controlled by P3, P4, P11, and P12. See
Tables III and V. Figure 6 shows the MUXOUT section in
block diagram form.
0
0
1
1
0
1
0
1
RF2 R Counter
RF2 AB Counter (and Prescaler Select)
RF1 R Counter
RF1 AB Counter (and Prescaler Select)
–10–
REV. 0
ADF4206/ADF4207/ADF4208
Table II. ADF4206 Family Latch Summary
RF2 REFERENCE COUNTER LATCH
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
P1 R14 R13 R12 R11 R10 R9 R8
DB8
R7
DB7
R6
DB6 DB5 DB4 DB3 DB2
R5 R4 R3 R2 R1
DB1
DB0
C2 (0) C1 (0)
P4
P3
P2
P5
RF2 AB COUNTER LATCH
CONTROL
BITS
6-BIT A COUNTER
11-BIT B COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
DB8
DB7
A6
DB6 DB5 DB4 DB3 DB2
A5 A4 A3 A2 A1
DB1
DB0
C2 (0) C1 (0)
RF1 REFERENCE COUNTER LATCH
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
R14 R13 R12 R11 R10 R9 R8
DB8
R7
DB7
R6
DB6 DB5 DB4 DB3 DB2
R5 R4 R3 R2 R1
DB1
DB0
C1 (0)
P11 P10
P13
P9
P12
C2 (1)
RF1 AB COUNTER LATCH
CONTROL
BITS
11-BIT B COUNTER
6-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
A6
DB6 DB5 DB4 DB3 DB2
A5 A4 A3 A2 A1
DB1
DB0
P16
P14
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
C2 (1) C1 (1)
–11–
REV. 0
ADF4206/ADF4207/ADF4208
Table III. RF2 Reference Counter Latch Map
RF2 REFERENCE COUNTER LATCH
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
R7
DB7
R6
DB6 DB5 DB4 DB3 DB2
R5 R4 R3 R2 R1
DB1
DB0
DB16
P4
R13
R12
R11
R10
R9
R8
C2 (0) C1 (0)
P3
P2
R14
P5
P1
R14
R13
R12
..........
R3
R2
0
1
1
0
.
R1
DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
0
16380
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
16381
16382
16383
P1
0
PD POLARITY
NEGATIVE
POSITIVE
1
P5
I
CP
0
1
1.25 mA
4.375 mA
P2
CHARGE PUMP
OUTPUT
0
1
NORMAL
THREE-STATE
P12
P11
FROM RF1 R LATCH
P4
0
0
1
1
0
0
0
0
P3
0
1
0
1
0
1
0
1
MUXOUT
LOGIC LOW STATE
RF2 ANALOG LOCK DETECT
RF2 REFERENCE DIVIDER OUTPUT
RF2 N DIVIDER OUTPUT
RF1 ANALOG LOCK DETECT
RF1/RF2 ANALOG LOCK DETECT
RF1 REFERENCE DIVIDER
RF1 N DIVIDER
FAST LOCK OUTPUT SWITCH ON
AND CONNECTED TO MUXOUT
RF2 COUNTER RESET
RF1 COUNTER RESET
RF2 AND RF1 COUNTER RESET
0
0
0
0
0
0
1
1
1
0
0
X
X
1
1
X
X
0
1
0
1
1
1
0
1
1
1
1
1
1
0
1
–12–
REV. 0
ADF4206/ADF4207/ADF4208
Table IV. RF2 AB Counter Latch Map
RF2 AB COUNTER LATCH
CONTROL
BITS
6-BIT A COUNTER
11-BIT B COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
A6
DB6 DB5 DB4 DB3 DB2
DB1
C2 (0)
DB0
A5
A4
A3
A2
A1
P7
P6
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
C1 (1)
A COUNTER
DIVIDE RATIO
A6
A5
X
X
X
X
.
A4
0
0
0
0
.
A3
A2
0
0
1
1
.
A1
X
X
X
X
.
0
0
0
0
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
.
X
X
X
X
1
1
1
1
1
1
0
1
14
15
B11
B10
B9
0
0
0
0
.
B3
B2
B1
B COUNTER DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
0
0
1
1
.
0
1
0
1
.
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
0
2044
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
2045
2046
2047
P6
0
RF2 PRESCALER
64/65
1
32/33
P7
RF2 SECTION
0
1
NORMAL OPERATION
POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER
THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES
2
OF Nx F
, N
IS (P – P).
REF
MIN
–13–
REV. 0
ADF4206/ADF4207/ADF4208
Table V. RF1 Reference Counter Latch Map
RF1 REFERENCE COUNTER LATCH
14-BIT REFERENCE COUNTER, R
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
R7
DB7
R6
DB6 DB5 DB4 DB3 DB2
R5 R4 R3 R2 R1
DB1
C2 (1)
DB0
P12
P9
R14
R13
R12
R11
R10
R9
R8
C1 (0)
P11 P10
P13
R14
R13
R12
..........
R3
R2
0
1
1
0
.
R1
DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
0
16380
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
16381
16382
16383
P9
0
PD POLARITY
NEGATIVE
POSITIVE
1
P13
0
I
CP
1.25 mA
1
4.375 mA
P10
0
CHARGE PUMP OUTPUT
NORMAL
1
THREE-STATE
P4
P3
P12
P11
0
0
X
X
1
FROM RF2 R LATCH
MUXOUT
LOGIC LOW STATE
RF2 ANALOG LOCK DETECT
RF2 REFERENCE DIVIDER OUTPUT
RF2 N DIVIDER OUTPUT
RF1 ANALOG LOCK DETECT
RF1/RF2 ANALOG LOCK DETECT
RF1 REFERENCE DIVIDER
RF1 N DIVIDER
FAST LOCK OUTPUT SWITCH ON
AND CONNECTED TO MUXOUT
RF2 COUNTER RESET
RF1 COUNTER RESET
RF2 AND RF1 COUNTER RESET
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
X
X
0
1
1
1
0
1
1
1
1
1
1
0
1
–14–
REV. 0
ADF4206/ADF4207/ADF4208
Table VI. RF1 AB Counter Latch Map
RF1 AB COUNTER LATCH
CONTROL
BITS
11-BIT B COUNTER
6-BIT A COUNTER
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
A6
DB6 DB5 DB4 DB3 DB2
DB1
DB0
DB21
P16
P14 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1
C2 (1) C1 (1)
A COUNTER
A6
0
0
0
0
.
A5
A4
0
0
0
0
.
A3
A2
A1
DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
0
1
62
63
B11
B10
B9
B3
B2
B1
B COUNTER DIVIDE RATIO
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
.
.
1
0
1
1
0
.
.
.
0
1
0
1
0
.
1
2
3
3
.
.
.
.
.
0
2044
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
2045
2046
2047
P14
RF1 PRESCALER
0
1
64/65
32/33
P16
RF1 SECTION
0
1
NORMAL OPERATION
POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER
THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF
2
N, N
MIN
IS (P – P).
–15–
REV. 0
ADF4206/ADF4207/ADF4208
PROGRAM MODES
Asynchronous RF1 Power-Down
Table III and Table V show how to set up the Program Modes
in the ADF420x family. The following should be noted:
If P10 of the ADF420x family has been set to “1” (three-state
the RF1 charge pump), and P16 is subsequently set to “1,” an
asynchronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the “1” to
the RF1 power-down bit (P16).
1. RF2 and RF1 Analog Lock Detect indicate when the PLL
is in lock. When the loop is locked and either RF2 or RF1
Analog Lock Detect is selected, the MUXOUT pin will show a
logic high with narrow low-going pulses. When the RF2/RF1
Analog Lock Detect is chosen, the locked condition is indi-
cated only when both RF2 and RF1 loops are locked.
Activation of either synchronous or asynchronous power-down
forces the RF2/RF1 loop’s R and N dividers to their load
state conditions and the RF2/RF1 input section is debiased to
a high impedance state.
2. The RF2 Counter Reset mode resets the R and AB counters
in the RF2 section and also puts the RF2 charge pump into
three-state. The RF1 Counter Reset mode resets the R and AB
counters in the RF1 section and also puts the RF1 charge
pump into three-state. The RF2 and RF1 Counter Reset
mode does both of the above.
The reference oscillator circuit is only disabled if both the RF2
and RF1 power-downs are set.
The input register and latches remain active and are capable of
loading and latching data during all the power-down modes.
The RF2/RF1 section of the devices will return to normal pow-
ered up operation immediately upon LE latching a “0” to the
appropriate power-down bit.
Upon removal of the reset bits, the AB counter resumes count-
ing in close alignment with the R counter (maximum error is
one prescaler output cycle).
3. The Fastlock mode uses MUXOUT to switch a second loop
filter damping resistor to ground during Fastlock operation.
Activation of Fastlock occurs whenever RF1 CP Gain in the
RF1 Reference counter is set to one.
IF SECTION (RF2)
Programmable RF2 Reference (R) Counter
If control bits (C2, C1) are (0, 0), the data is transferred from
the input shift register to the 14-bit RF2 R counter. Table III
shows the input shift register data format for the RF2 R counter
and the divide ratios possible.
POWER-DOWN
It is possible to program the ADF420x family for either syn-
chronous or asynchronous power-down on either the RF2 or
RF1 side.
RF2 Phase Detector Polarity
P1 sets the RF2 Phase Detector Polarity. When the RF2 VCO
characteristics are positive, this should be set to “1.” When they
are negative, it should be set to “0.” See Table III.
Synchronous RF2 Power-Down
Programming a “1” to P7 of the ADF420x family will initiate a
power-down. If P2 of the ADF420x family has been set to “0”
(normal operation), a synchronous power-down is conducted.
The device will automatically put the charge pump into three-
state and then complete the power-down.
RF2 Charge Pump Three-State
P2 puts the RF2 charge pump into three-state mode when pro-
grammed to a “1.” It should be set to “0” for normal operation.
See Table III.
RF2 Program Modes
Table III and Table V show how to set up the Program Modes
in the ADF420x family.
Asynchronous RF2 Power-Down
If P2 of the ADF420x family has been set to “1” (three-state
the RF2 charge pump), and P7 is subsequently set to “1,” an
asynchronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the “1” to
the RF2 power-down bit (P7).
RF2 Charge Pump Currents
Bit P5 programs the current setting for the RF2 charge pump.
See Table III.
Programmable RF2 AB Counter
Synchronous RF1 Power-Down
If control bits (C2, C1) are (0, 1), the data in the input register is
used to program the RF2 AB counter. The AB counter consists of
a 6-bit swallow counter (A counter) and 11-bit programmable
counter (B counter). Table IV shows the input register data
format for programming the RF2 AB counter and the divide
ratios possible.
Programming a “1” to P16 of the ADF420x family will initiate
a power-down. If P10 of the ADF420x family has been set to
“0” (normal operation), a synchronous power-down is conducted.
The device will automatically put the charge pump into three-
state and then complete the power-down.
RF2 Prescaler Value
P6 in the RF2 AB counter latch sets the RF2 prescaler value. See
Table IV.
RF2 Power-Down
P7 in Table IV is the power-down bit for the RF2 side.
–16–
REV. 0
ADF4206/ADF4207/ADF4208
RF SECTION (RF1)
Programmable RF1 AB Counter
Programmable RF1 Reference (R) Counter
If control bits (C2, C1) are (1, 0), the data is transferred from
the input shift register to the 14 Bit RF1 R counter. Table V
shows the input shift register data format for the RF1 R counter
and the divide ratios possible.
If control bits (C2, C1) are (1, 1), then the data in the input
register is used to program the RF1 AB counter. The AB
counter consists of a 6-bit swallow counter (A counter) and
11-bit programmable counter (B counter). Table VI shows
the input register data format for programming the RF1 AB
counter and the divide ratios possible. See Table VI.
RF1 Phase Detector Polarity
P9 sets the RF1 Phase Detector Polarity. When the RF1 VCO
characteristics are positive this should be set to “1.” When they
are negative it should be set to “0.” See Table V.
RF1 Prescaler Value
P14 in the RF1 A, B counter latch set the RF1 prescaler value.
See Table VI.
RF1 Charge Pump Three-State
RF1 Power-Down
P10 puts the RF1 charge pump into three-state mode when
programmed to a “1.” It should be set to “0” for normal opera-
tion. See Table V.
Setting P16 in the RF1 AB counter high powers down RF1 side.
RF Fastlock
The fastlock feature can improve the lock time of the PLL. It
increases charge pump current to a maximum for a period of
time. Fastlock of the ADF420x family is activated by setting
P13 in the reference counter high and setting the fastlock switch
on using MUXOUT. Switching in an external resistor using
MUXOUT compensates the loop dynamics for the effect of
increasing charge pump current. Setting P13 low removes the
PLL from fastlock mode.
RF1 Program Modes
Table III and Table V show how to set up the Program Modes
in the ADF420x family.
RF1 Charge Pump Currents
Replaced with a P13 programs the current setting for the RF1
charge pump. See Table V.
IF
OUT
V
V
V
RF
P
P
DD
OUT
100pF
100pF
VCO190-1068U
100pF
V
V
CC
CC
18⍀
18⍀
V
2
V
V 2
P
1
V 1
P
VCO190-125T
100pF
DD
3.3k⍀
DD
18⍀
18⍀
CP
CP
RF1
RF2
2.7k⍀
18⍀
18⍀
1.3nF
620pF
13nF
ADF4207
MUXOUT
LOCK DETECT
100pF
100pF
RF2
RF1
IN
IN
51⍀
OSC
51⍀
IN
CLK
DATA
LE
30pF
30pF
10MHz
18k⍀
OSC
OUT
DECOUPLING CAPACITORS (22F/10pF) ON V , V OF
DD
P
THE ADF4207, AND ON V OF THE VCOs HAVE BEEN
CC
OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4207
–17–
REV. 0
ADF4206/ADF4207/ADF4208
APPLICATIONS SECTION
The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.
Local Oscillator for GSM Handset Receiver
Figure 7 shows the ADF4207 being used in a classic superhet-
erodyne receiver to provide the required LOs (Local Oscillators).
Local Oscillator for WCDMA Receiver
In this circuit, the reference input signal is applied to the circuit
at OSCIN and is being generated by a 10 MHz Crystal Oscillator.
This is a low-cost solution and for better performance over tem-
perature, a TCXO (Temperature Controlled Crystal Oscillator)
may be used instead.
Figure 8 shows the ADF4208 being used to generate the local
oscillator frequencies for a Wideband CDMA (WCDMA) system.
The RF output range needed is 1720 MHz to 1780 MHz. The
VCO190–1750T will accomplish this. Channel spacing is
200 kHz with a 20 kHz loop bandwidth. VCO sensitivity is
32 MHz/V. Charge pump current of 4.375 mA is used and
the desired phase margin for the loop is 45°.
In order to have a channel spacing of 200 kHz (the GSM stan-
dard), the reference input must be divided by 50, using the
on-chip reference counter.
The IF output is fixed at 200 MHz. The VCO190–200T is used.
It has a sensitivity of 10 MHz/V. Channel spacing and loop
bandwidth is chosen to be the same as the RF side.
The RF output frequency range is 1050 MHz to 1086 MHz. Loop
filter component values are chosen so that the loop bandwidth is
20 kHz. The synthesizer is set up for a charge pump current of
4.375 mA and the VCO sensitivity is 15.6 MHz/V.
IF
OUT
V
V
V
RF
OUT
P
P
DD
100pF
100pF
100pF
V
V
CC
CC
18⍀
18⍀
V
2
V
V 2
P
1
V 1
P
VCO190-200T
VCO190-1750T
100pF
DD
3.3k⍀
DD
18⍀
18⍀
CP
CP
RF1
RF2
2.7k⍀
18⍀
18⍀
1.3nF
620pF
13nF
ADF4208
MUXOUT
LOCK DETECT
100pF
100pF
RF2
IN
RF1
IN
51⍀
OSC
51⍀
IN
CLK
DATA
LE
30pF
30pF
10MHz
18k⍀
OSC
OUT
DECOUPLING CAPACITORS (22F/10pF) ON V , V OF
DD
P
THE ADF4208, AND ON V OF THE VCOs HAVE BEEN
CC
OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 8. Local Oscillator for WCDMA Receiver Using the ADF4208
–18–
REV. 0
ADF4206/ADF4207/ADF4208
INTERFACING
ADSP-2181 Interface
The ADF4206/ADF4207/ADF4208 family has a simple SPI-
compatible serial interface for writing to the device. SCLK,
SDATA, and LE (Latch Enable) control the data transfer. When
LE goes high, the 22 bits that have been clocked into the input
register on each rising edge of SCLK will be transferred to the
appropriate latch. See Figure 1 for the Timing Diagram and
Table I for the Latch Truth Table.
Figure 10 shows the interface between the ADF420x family and
the ADSP-21xx Digital Signal Processor. As previously noted,
the ADF420x family needs a 22-bit serial word for each latch
write. The easiest way to accomplish this using the ADSP21-xx
family is to use the Autobuffered Transmit Mode of operation
with Alternate Framing. This provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 22-bit word. To program each 22-bit latch,
store the three 8-bit bytes, enable the Autobuffered mode and
then write to the transmit register of the DSP. This last opera-
tion initiates the autobuffer transfer.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 ms. This is certainly more than
adequate for systems that will have typical lock times in hun-
dreds of microseconds.
ADuC812 Interface
Figure 10 shows the interface between the ADF420x family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF420x family
needs a 22-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
SCLOCK
DT
SCLK
SDATA
ADF4206/
ADF4207/
ADF4208
TFS
LE
ADSP-21xx
MUXOUT
(LOCK DETECT)
I/O FLAG
On first applying power to the ADF420x family, it requires four
writes (one each to the R counter latch and the AB counter latch
for both RF1 and RF2 side) for the output to become active.
Figure 10. ADSP-21xx to ADF420x Family Interface
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be about
180 kHz.
SCLOCK
MOSI
SCLK
SDATA
ADF4206/
ADF4207/
ADF4208
ADuC812
LE
I/O PORTS
MUXOUT
(LOCK DETECT)
Figure 9. ADuC812 to ADF420x Family Interface
–19–
REV. 0
ADF4206/ADF4207/ADF4208
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Thin Shrink Small Outline Package (TSSOP)
(RU-16)
Thin Shrink Small Outline Package (TSSOP)
(RU-20)
0.260 (6.60)
0.252 (6.40)
0.201 (5.10)
0.193 (4.90)
20
11
16
9
0.177 (4.50)
0.169 (4.30)
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.256 (6.50)
0.246 (6.25)
0.246 (6.25)
1
10
1
8
PIN 1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
8؇
0؇
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.028 (0.70)
0.020 (0.50)
0.0256 (0.65) 0.0118 (0.30)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
0.0075 (0.19)
–20–
REV. 0
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