ADF4208BRUZ_技术文档

Dual RF PLL Frequency Synthesizers

ADF4206/ADF4208

GENERAL DESCRIPTION

FEATURES

ADF4206: 550 MHz/550 MHz

ADF4208: 2.0 GHz/1.1 GHz

2.7 V to 5.5 V power supply

Selectable charge pump supply (V_P) allows extended

tuning voltage in 3 V systems

Selectable charge pump currents

On-chip oscillator circuit

Selectable dual modulus prescaler

RF2: 32/33 or 64/65

The ADF420x family of dual frequency synthesizers are used

to implement local oscillators in the upconversion and down-

conversion sections of wireless receivers and transmitters. Each

synthesizer consists of a low noise, digital, phase frequency detector

(PFD); a precision charge pump; a programmable reference

divider; programmable A and B counters; and a dual modulus

prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in

conjunction with the dual modulus prescaler (P/P + 1), implement

an N divider (N = BP + A). In addition, the 14-bit reference

counter (R counter) allows selectable REFIN frequencies at the

PFD input. The on-chip oscillator circuitry allows the reference

input to be derived from crystal oscillators.

RF1: 32/33 or 64/65

3-wire serial interface

Power-down mode

APPLICATIONS

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Base stations for wireless radio (GSM, PCS, DCS,

CDMA, WCDMA)

A complete phase-locked loop (PLL) can be implemented if the

synthesizers are used with an external loop filter and voltage

controlled oscillators (VCOs).

Wireless LANS

Communications test equipment

CATV equipment

Control of all the on-chip registers is via a simple 3-wire

interface. The devices operate with a power supply ranging

from 2.7 V to 5.5 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

V

1

V

2

V

1

V 2

P

DD

P

N = BP + A

ADF4206/ADF4208

11-BIT RF2

B-COUNTER

PHASE

COMPARATOR

RF2

A

B

IN

RF2

PRESCALER

RF2

CHARGE

PUMP

IN

CP

RF2

6-BIT RF2

A-COUNTER

RF2

LOCK

DETECT

OSC

IN

OSCILLATOR

OSC

OUT

14-BIT RF2

R-COUNTER

OUTPUT

MUX

MUXOUT

CLK

DATA

LE

22-BIT

DATA

REGISTER

SDOUT

RF1

14-BIT RF1

R-COUNTER

LOCK

DETECT

N = BP + A

CHARGE

PUMP

CP

RF1

11-BIT RF1

B-COUNTER

PHASE

COMPARATOR

RF1

A

B

IN

RF1

PRESCALER

RF1

IN

6-BIT RF1

A-COUNTER

AGND

RF1

DGND

AGND

RF2

DGND

RF1

RF2

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADF4206/ADF4208

TABLE OF CONTENTS

Features .............................................................................................. 1

Pulse Swallow Function............................................................. 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump............ 12

MUXOUT and Lock Detect...................................................... 12

Lock Detect ................................................................................. 12

Input Shift Register .................................................................... 12

Program Modes .............................................................................. 18

Power-Down ............................................................................... 18

IF Section (RF2) ......................................................................... 18

RF Section (RF1) ........................................................................ 19

Applications Section....................................................................... 20

Local Oscillator for GSM Handset Receiver........................... 20

Local Oscillator for WCDMA Receiver .................................. 21

Interfacing ....................................................................................... 22

ADuC812 Interface.................................................................... 22

ADSP-2181 Interface ................................................................. 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Timing Diagram ........................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 11

Reference Input Section............................................................. 11

RF Input Stage............................................................................. 11

Prescaler....................................................................................... 11

A and B Counters ....................................................................... 11

REVISION HISTORY

2/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Deleted ADF4207 ...............................................................Universal

Changes to Table 3............................................................................ 6

Changes to Function Description .................................................. 7

Changes to Table 4............................................................................ 7

Changes to Figure 22 Caption....................................................... 12

Changes to Pulse Swallow Function ............................................ 13

Changes to Figure 29...................................................................... 15

Changes to Figure 31...................................................................... 17

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide .......................................................... 25

3/01—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADF4206/ADF4208

SPECIFICATIONS

V_DD1 = V_DD2 = 3 V 10ꢀ, 5 V 10ꢀ; V_DD1, V_DD2 ≤ V_P1, V_P2 ≤ 6.0 V; AGND_RF1= DGND_RF1= AGND_RF2= DGND_RF2= 0 V;

T_A= T_MINto T_MAX, unless otherwise noted; dBm referred to 50 Ω.

Table 1.

Parameter

B Version¹

B Chips²

Unit

Test Conditions/Comments

RF/IF CHARACTERISTICS (3 V)

RF1 Input Frequency (RF1_IN)

ADF4206

See Figure 22 for input circuit

0.05/0.55

0.08/2.0

–15/+4

0.05/0.55

0.08/2.0

−15/+4

GHz min/max

dBm min/max

For f < 50 MHz ensure SR > 23 V/μs

For f < 50 MHz ensure SR > 37 V/μs

ADF4208

RF Input Sensitivity

IF Input Frequency (RF2_IN)

ADF4206

0.05/0.55

0.08/1.1

−15/+4

165

0.05/0.55

0.08/1.1

−15/+4

165

GHz min/max

dBm min/max

MHz max

For f < 50 MHz ensure SR > 23 V/μs

For f < 50 MHz ensure SR > 37 V/μs

ADF4208

IF Input Sensitivity

Maximum Allowable Prescaler

Output Frequency³

RF CHARACTERISTICS (5 V)

RF1 Input Frequency (RF1_IN)

ADF4206

0.05/0.55

0.08/2.0

−10/+4

0.05/0.55

0.08/2.0

−10/+4

GHz min/max

dBm min/max

MHz min/max

GHz min/max

dBm min/max

MHz max

For f < 50 MHz ensure SR > 32 V/μs

For f < 50 MHz ensure SR > 51 V/μs

ADF4208

RF Input Sensitivity

IF Input Frequency (RF2_IN)

ADF4206

0.05/0.55

0.08/1.1

−10/+4

200

0.05/0.55

0.08/1.1

–10/+4

200

For f < 50 MHz ensure SR > 32 V/μs

For f < 50 MHz ensure SR > 51 V/μs

ADF4208

IF Input Sensitivity

Maximum Allowable Prescaler

Output Frequency³

REFIN CHARACTERISTICS

REFIN Input Frequency

REFIN Input Sensitivity⁴

REFIN Input Capacitance

REFIN Input Current

PHASE DETECTOR

Phase Detector Frequency⁵

CHARGE PUMP

5/40

−2

10

5/40

−2

10

MHz min/max

dBm min

pF max

For f < 5 MHz ensure SR > 9 V/μs

100

ꢀA max

55

MHz max

I_CPSink/Source

High Value

Low Value

Absolute Accuracy

I_CPThree-State Leakage Current

LOGIC INPUTS

5

mA typ

% typ

1.25

2.5

1

1.25

2.5

1

nA typ

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

C_IN, Input Capacitance

LOGIC OUTPUTS

0.8 × V_DD

0.2 × V_DD

1

10

0.8 × V_DD

0.2 × V_DD

1

10

V min

V max

ꢀA max

pF max

V_OH, Output High Voltage

V_OL, Output Low Voltage

V_DD− 0.4

0.4

V_DD− 0.4

0.4

V min

V max

I_OH= 500 ꢀA

I_OL= 500 ꢀA

Rev. A | Page 3 of 24

ADF4206/ADF4208

Parameter

POWER SUPPLIES

V_DD1

V_DD2

V_P

I_DD(I_DD1 + I_DD2)⁶

B Version¹

B Chips²

Unit

Test Conditions/Comments

2.7/5.5

V_DD1

V_DD1/6.0

2.7/5.5

V_DD1

V_DD1/6.0

V min/V max

V_DD1, V_DD2 ≤ V_P1, V_P2 ≤ 6.0 V

ADF4206

ADF4208

14

21

14

21

mA max

9.5 mA typical at V_DD= 3 V, T_A= 25°C

14 mA typical at V_DD= 3 V, T_A= 25°C

I_DD1

ADF4206

ADF4208

8

14

8

14

mA max

5.5 mA typical at V_DD= 3 V, T_A= 25°C

9 mA typical at V_DD= 3 V, T_A= 25°C

I_DD2

ADF4206

ADF4208

I_P(I_P1 + I_P2)

Low Power Sleep Mode

NOISE CHARACTERISTICS

7.5

9

1

7.5

9

1

mA max

ꢀA typ

5 mA typical at V_DD= 3 V, T_A= 25°C

5.5 mA typical at V_DD= 3 V, T_A= 25°C

T_A= 25°C

0.5

Normalized Phase Noise Floor

(RF1)⁷

ADF4206

ADF4208

−213

−217

−213

−217

dBc/Hz typ

Phase Noise Performance⁸

ADF4206 (RF1, RF2)

ADF4208 (RF1)

@ VCO output

−92

−85

−91

−92

−85

−91

dBc/Hz typ

@ 540 MHz output, 200 kHz at PFD

@ 1750 MHz output, 200 kHz at PFD

@ 900 MHz output, 200 kHz at PFD

ADF4208 (RF1)

Spurious Signals

RF1, RF2 (20 kHz Loop B/W)

−80/−84

dB typ

@ 200 kHz/400 kHz offsets and

200 kHz PFD

¹Operating temperature range for B version: −40°C to +85°C.

²The B chip specifications are given as typical values.

³This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

⁴AC coupling ensures AV_DD/2 bias. V_DD1 = V_DD2 = 3 V; For V_DD1 = V_DD2 = 5 V, use CMOS-compatible levels.

⁵Guaranteed by design. Sample tested to ensure compliance.

⁶Typical values apply for V_DD= 3 V; P = 32; RF1_IN1/RF2_IN2 for ADF4206 = 540 MHz; RF1_IN1/RF2_IN2 for ADF4208 = 900 MHz.

⁷The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log F_PFD. PN_SYNTH= PN_TOT− 10 log F_PFD− 20 log N.

⁸The phase noise is measured at 1 kHz, unless otherwise noted. The phase noise is measured with the EVAL-ADF4206EB or the EVAL-ADF4208EB evaluation board and

the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f_REFOUT= 10 MHz @ 0 dBm).

Rev. A | Page 4 of 24

ADF4206/ADF4208

TIMING SPECIFICATIONS

V_DD1 = V_DD2 = 3 V 10ꢀ, 5 V 10ꢀ; V_DD1, V_DD2 ≤ V_P1, V_P2 ≤ 6.0 V; AGND_RF1= DGND_RF1= AGND_RF2= DGND_RF2= 0 V;

T_A= T_MINto T_MAX, unless otherwise noted; dBm referred to 50 Ω.

Table 2.

Parameter¹

Limit at T_MINto T_MAX(B Version)

Unit

Test Conditions/Comments

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

t₁

t₂

t₃

t₄

t₅

t₆

10

25

10

20

ns min

¹Guaranteed by design but not production tested.

TIMING DIAGRAM

t₄

t₃

CLK

t₁

t₂

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB21 (MSB)

DATA

DB20

DB2

(CONTROL BIT C2)

t₆

LE

t₅

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

ADF4206/ADF4208

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise noted.¹

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Ratings

V_DD1 to GND²

−0.3 V to +7 V

V_DD1 to V_DD2

−0.3 V to +0.3 V

−0.3 V to +7 V

V_P1, V_P2 to GND

V_P1, V_P2 to V_DD1

−0.3 V to +5.5 V

−0.3 V to DV_DD+ 0.3 V

−0.3 V to VP + 0.3 V

Digital I/O Voltage to GND

Analog I/O Voltage to GND

OSC_IN, OSC_OUT, RF1_IN(A, B),

RF2_IN(A, B) to GND

−0.3 V to V_DD+ 0.3 V

320 mV

TRANSISTOR COUNT

RF_INA to RF_INB (RF1, RF2)

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Maximum Junction Temperature

TSSOP θ_JAThermal Impedance

11,749 (CMOS) and 522 (Bipolar).

−40°C to +85°C

−65°C to +150°C

150°C

112°C/W

LFCSP θ_JAThermal Impedance

(Paddle Soldered)

30.4°C/W

Reflow Soldering

Peak Temperature (40 sec)

260°C

¹This device is a high performance RF integrated circuit with an ESD rating of

<2 kΩ and it is ESD sensitive. Proper precautions should be taken for

handling and assembly.

²GND = AGND = DGND = 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 6 of 24

ADF4206/ADF4208

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

2

V

2

DD

20

DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

1

V

2

19

V 1

V 2

P

DD

P

V 1

V 2

P

3

18

P

CP

RF2

RF1

ADF4208

TOP VIEW

(Not to Scale)

CP

4

17

DGND

RF1

RF2

DGND

RF1

RF2

RF1

A

ADF4206

TOP VIEW

(Not to Scale)

DGND

5

DGND

16

RF2

IN

A

RF2

IN

RF1

RF2

IN

6

15

RF2

IN

B

IN

RF1

B

IN

OSC

LE

7

14

AGND

RF2

RF1

OSC

DATA

CLK

8

13 LE

12

OUT

OSC

IN

MUXOUT

9

DATA

OSC

OUT

10

11

CLK

MUXOUT

Figure 3. 16-Lead TSSOP Pin Configuration

Figure 4. 20-Lead TSSOP Pin Configuration

Table 4. Pin Function Descriptions

ADF4206 ADF4208

Pin No.

Mnemonic

Description

1

V_DD1

Positive Power Supply for the RF1 Section. A 0.1 ꢀF capacitor is connected between this pin

and DGND_RF1(the RF1 ground pin). V_DD1 should have a value of between 2.7 V and 5.5 V. V_DD1

must have the same potential as V_DD2.

2

3

2

3

V_P1

CP_RF1

Power Supply for the RF1 Charge Pump. This is greater than or equal to V_DD.

Output from the RF1 Charge Pump. This is normally connected to a loop filter that drives the

input to an external VCO.

4

5

6

7

8

4

5

8

9

DGND_RF1

RF1_IN/RF1_INA

OSC_IN

OSC_OUT

MUXOUT

Ground Pin for the RF1 Digital Circuitry.

Input to the RF1 Prescaler. This low level input signal is taken from the RF1 VCO.

Oscillator Input. It has a V_DD/2 threshold and is driven from an external CMOS or TTL logic gate.

Oscillator Output.

This multiplexer output allows the IF/RF lock detect, the scaled RF, or the scaled reference

frequency external access. See Figure 30.

10

9

11

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance

CMOS input.

10

11

12

13

16

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This

input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded

into one of the four latches, the latch being selected using the control bits.

Input to the RF2 Prescaler. This low level input signal is normally ac-coupled to the external

VCO.

LE

RF2_IN/RF2_INA

13

14

17

18

DGND_RF2

CP_RF2

Ground Pin for the RF2, Digital, Interface, and Control Circuitry.

Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives the

input to an external VCO.

15

16

19

20

V_P2

V_DD2

Power Supply for the RF2 Charge Pump. This is greater than or equal to V_DD.

Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 ꢀF capacitor is

connected between this pin and DGND_RF2(the RF2 ground pin). V_DD2 has a value between 2.7 V

and 5.5 V. V_DD2 must have the same potential as V_DD1.

N/A

6

RF1_INB

Complementary Input to the RF1 Prescaler of the ADF4208. This point is decoupled to the

ground plane with a small bypass capacitor.

N/A

7

14

15

AGND_RF1

AGND_RF2

RF2_INB

Ground Pin for the RF1 Analog Circuitry.

Ground Pin for the RF2 Analog Circuitry.

Complementary Input to the RF2 Prescaler. This point is decoupled to the ground plane with a

small bypass capacitor.

Rev. A | Page 7 of 24

ADF4206/ADF4208

TYPICAL PERFORMANCE CHARACTERISTICS

0

FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE (Ω)

V

= 3V, V = 5V

DD P

= 5mA

GHz

S

MA

R

50

I

–10

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 30

REFERENCE LEVEL =

–4.2dBm

FREQ MAGS11

ANGS11

FREQ MAGS11

ANGS11

–20

–30

–40

–50

–60

0.0

0.957111193 –3.130429321 1.35

0.963546793 –6.686426265 1.45

0.953621785 –11.19913586 1.55

0.953757706 –15.35637483 1.65

0.816886959 –51.80711782

0.825983016 –56.20373378

0.791737125 –61.21554647

0.770543186 –61.88187496

0.793897072 –65.39516615

0.745765233 –69.24884474

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.95

1.05

1.15

1.25

0.929831379 –20.3793432

1.75

0.908459709 –22.69144845 1.85

0.897303634 –27.07001443 1.95

0.876862863 –31.32240763 2.05

0.849338092 –33.68058163 2.15

0.858403269 –38.57674885 2.25

0.841888714 –41.48606772 2.35

0.840354983 –45.97597958 2.45

0.822165839 –49.19163116 2.55

0.7517547

–71.21608147

0.745594889 –75.93169947

0.713387801 –78.8391674

0.711578577 –81.71934806

0.698487131 –85.49067481

0.669871818 –88.41958754

0.668353367 –91.70921678

–70

–90.2dBc/Hz

–80

–90

–100

–200k

900M

FREQUENCY (Hz)

200k

400k

–400k

Figure 8. ADF4208 RF1 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

Figure 5. S-Parameter Data for the ADF4208 RF1 Input (Up to 2.5 GHz)

0

–40

V

= 5V

10dB/DIVISION

DD

= 5V

–50

P

R

= –40dBc/Hz

L

–5

–10

–15

–20

–25

–30

–35

rms NOISE = 0.52°

–60

–70

–80

T

= +85°C

A

0.52° rms

–90

–100

–110

–120

T

= –40°C

A

–130

–140

T

= +25°C

1.5

A

0

0.5

1.0

2.0

2.5

3.0

3.5

100Hz

1kHz

10kHz

100kHz

1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

RF INPUT SENSITIVITY (GHz)

Figure 9. ADF4208 RF1 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)

Figure 6. ADF4208 RF1 Phase Noise (900 MHz, 200 kHz, 20 kHz)

–40

0

10dB/DIVISION

V

I

= 3V, V = 5V

P

DD

= 5mA

–50

–60

R = –40dBc/Hz

–10

L

CP

rms NOISE = 0.62°

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

REFERENCE LEVEL =

–4.2dBm

–20

–30

–40

–50

–60

–70

–80

0.62° rms

–90

–100

–110

–120

–70

–90.5dBc/Hz

–80

–90

–130

–140

–100

–2k

–1k

900M

FREQUENCY (Hz)

1k

2k

100Hz

1kHz

10kHz

100kHz

1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

Figure 10. ADF4208 RF1 Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz)

Figure 7. ADF4208 RF1 Phase Noise (900 MHz, 200 kHz, 20 kHz)

Rev. A | Page 8 of 24

ADF4206/ADF4208

0

V

I

= 3V, V = 5V

P

= 5mA

V

I

= 3V, V = 5V

P

= 5mA

DD

–10

CP

–10

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 3Hz

VIDEO BANDWIDTH = 3Hz

SWEEP = 255 SECONDS

POSITIVE PEAK

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 30

REFERENCE LEVEL =

–4.2dBm

REFERENCE LEVEL =

–5.7dBm

–20

–30

–40

–50

–60

–20

–30

–40

–50

–60

DETECT MODE

–70

–79.6dBc

–70

–89.3dBc

–80

–90

–80

–90

–100

–400k

–200k

200k

400k

900M

–200k

1750M

FREQUENCY (Hz)

40k

80k

–400k

FREQUENCY (Hz)

Figure 11. ADF4208 RF1 Reference Spurs (900 MHz, 200 kHz, 35 kHz)

Figure 14. ADF4208 RF1 Reference Spurs (1750 MHz, 30 kHz, 3 kHz)

0

–120

V

= 3V

V

I

= 3V, V = 5V

P

= 5mA

DD

P

DD

= 5V

–10

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

REFERENCE LEVEL =

–8.0dBm

–130

–140

–150

–160

–170

–180

–20

–30

–40

–50

–60

AVERAGES = 10

ADF4206

–70

ADF4208

–75.2dBc/Hz

–80

–90

–100

–200

1750M

200

400

–400

1

10

100

1000

10000

FREQUENCY (Hz)

PHASE DETECTOR FREQUENCY (kHz)

Figure 12. ADF4208 RF1 Phase Noise (1750 MHz, 30 kHz, 3 kHz)

Figure 15. ADF4208 RF1 Phase Noise vs. PFD Frequency

–40

–60

V

= 3V

10dB/DIVISION

DD

= 3V

P

R

= –40dBc/Hz

–50

–60

L

–70

–80

–90

1.6 rms

–80

–100

–110

–120

–90

–130

–140

–100

–40

–20

0

20

40

60

80

100

100Hz

1kHz

10kHz

100kHz

1MHz

TEMPERATURE (°C)

FREQUENCY OFFSET FROM 1750MHz CARRIER

Figure 16. ADF4208 RF1 Phase Noise vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

Figure 13. ADF4208 RF1 Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz)

Rev. A | Page 9 of 24

ADF4206/ADF4208

3.0

2.5

–60

V

= 3V

= 5V

V

= 3V

DD

= 3V

P

–70

–80

2.0

1.5

1.0

0.5

0

–90

–100

0

50

100

150

200

–40

–20

0

20

40

60

80

100

PRESCALER OUTPUT FREQUENCY (MHz)

TEMPERATURE (°C)

Figure 17. ADF4208 RF1 Reference Spurs vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

Figure 20. DI_DDvs. Prescaler Output Frequency RF1 and RF2 (All Models)

–5

10

V

= 3V

DD

= 5V

–15

P

9

ADF4208

–25

–35

8

7

6

5

4

–45

–55

–65

–75

–85

–95

–105

ADF4206

3

2

1

0

1

2

3

4

5

TUNING VOLTAGE (V)

32/33

64/65

PRESCALER VALUE

Figure 21. ADF4206/ADF4208 AI_DDvs. Prescaler Value (RFI)

Figure 18. ADF4208 RF1 Reference Spurs vs. V_TUNE

(900 MHz, 200 kHz, 20 kHz)

–120

V

= 3V

= 5V

DD

P

–130

–140

–150

–160

–170

–180

ADF4206

ADF4208

1

10

100

1000

10000

PHASE DETECTOR FREQUENCY (kHz)

Figure 19. ADF4208 RF2 Phase Noise vs. PFD Frequency

Rev. A | Page 10 of 24

ADF4206/ADF4208

A AND B COUNTERS

CIRCUIT DESCRIPTION

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The devices are guaranteed to work when the

prescaler output is 200 MHz or less.

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 22. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. Typical recommended external components are shown

in Figure 22.

PULSE SWALLOW FUNCTION

The A and B counters, in conjunction with the dual modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

equation for the VCO frequency is

POWER-DOWN

CONTROL

NC

100kΩ

SW2

f_VCO= [(P × B) + A] × f_REFIN/R

TO R

COUNTER

OSC

NC

IN

where:

BUFFER

30pF

SW1

f

_VCOis the output frequency of the external voltage controlled

oscillator (VCO).

SW3

NO

OUT

P is the preset modulus of the dual modulus prescaler

(32/33, 64/65).

18kΩ

B is the preset divide ratio of the binary 11-bit counter

(2 to 2047).

Figure 22. Reference Input Stage

A is the preset divide ratio of the binary 6-bit A counter

(0 to 63).

RF INPUT STAGE

The RF input stage is shown in Figure 23. It is followed by a

2-stage limiting amplifier to generate the CML clock levels

needed for the prescaler.

f

_REFINis the output frequency of the external reference frequency

oscillator.

R is the preset divide ratio of the binary 14-bit programmable

reference counter (1 to 16,383).

1.6V

BIAS

GENERATOR

AV

DD

R COUNTER

2kΩ

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

RF

A

B

IN

N = BP + A

11-BIT B

TO PFD

COUNTER

AGND

LOAD

FROM RF

INPUT STAGE

PRESCALER

P/P + 1

Figure 23. RF Input Stage

LOAD

MODULUS

CONTROL

6-BIT A

COUNTER

PRESCALER

The dual modulus prescaler (P/P + 1), along with the A and

B counters, enables the large division ratio, N, to be realized

(N = BP + A). This prescaler, operating at CML levels, takes

the clock from the RF input stage and divides it down to a

manageable frequency for the CMOS A and B counters. It is

based on a synchronous 4/5 core.

N DIVIDER

Figure 24. A and B Counters

The prescaler is selectable. Both RF1 and RF2 can be set to

either 32/33 or 64/65. DB20 of the AB counter latch selects the

value. See Figure 29 and Figure 31.

Rev. A | Page 11 of 24

ADF4206/ADF4208

DV

DD

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

RF2 ANALOG LOCK DETECT

RF2 R COUNTER OUTPUT

RF2 N COUNTER OUTPUT

RF2/RF1 ANALOG LOCK DETECT

RF1 R COUNTER OUTPUT

RF1 N COUNTER OUTPUT

The PFD takes inputs from the R counter and N counter (N =

BP + A) and produces an output proportional to the phase and

frequency difference between them. Figure 25 is a simplified

schematic.

MUXOUT

MUX

CONTROL

RF1 ANALOG LOCK DETECT

V

P

CHARGE

PUMP

DGND

UP

HI

D1

Q1

Figure 26. MUXOUT Circuit

U1

LOCK DETECT

R DIVIDER

CLR1

MUXOUT can be programmed for analog lock detect. The

N-channel open-drain analog lock detect is operated with an

external pull-up resistor of 10 kΩ nominal. When lock is

detected, it is high with narrow, low going pulses.

DELAY

ELEMENT

CP

U3

INPUT SHIFT REGISTER

CLR2

U2

DOWN

The functional block diagram for the ADF420x family is shown

in Figure 1. The main blocks include a 22-bit input shift register,

a 14-bit R counter, and a 17-bit N counter, comprising a 6-bit

A counter and an 11-bit B counter. Data is clocked into the

22-bit shift register on each rising edge of CLK. The data is

clocked in MSB first. Data is transferred from the shift register

to one of four latches on the rising edge of LE. The destination

latch is determined by the state of the two control bits (C2, C1)

in the shift register. These are the two LSBs (DB1, DB0) as

shown in the timing diagram of Figure 2.

HI

D2

Q2

N DIVIDER

CPGND

R DIVIDER

N DIVIDER

CP OUTPUT

Table 5 is the truth table for these bits.

Figure 25. PFD Simplified Schematic and Timing (In Lock)

Table 5. C2, C1 Truth Table

Control Bits

The PFD includes a delay element that sets the width of the

antibacklash phase. The typical value for this in the ADF420x

family is 3 ns. The pulse ensures that there is no dead zone in

the PFD transfer function and minimizes phase noise and

reference spurs.

C2

0

C1

0

Data Latch

RF2 R counter

0

1

0

RF2 AB counter (and prescaler select)

RF1 R counter

1

RF1 AB counter (and prescaler select)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4206 family allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by P3, P4, P11, and P12. See Figure 28

and Figure 30. Figure 26 shows the MUXOUT circuit in block

diagram form.

Rev. A | Page 12 of 24

ADF4206/ADF4208

RF2 REFERENCE COUNTER LATCH

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

P1 R14 R13 R12 R11 R10 R9 R8

DB8

R7

DB7

R6

DB6 DB5 DB4 DB3 DB2

DB1

DB0

R5

R4

R3

R2

R1

C2 (0) C1 (0)

P4

P3

P2

P5

RF2 AB COUNTER LATCH

CONTROL

BITS

6-BIT A COUNTER

11-BIT B COUNTER

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

DB8

DB7

A6

DB6

A5

DB5

A4

DB4 DB3 DB2

A3 A2 A1

DB1

DB0

C2 (0) C1 (0)

RF1 REFERENCE COUNTER LATCH

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

R14 R13 R12 R11 R10 R9 R8

DB8

R7

DB7

R6

DB6 DB5

R5 R4

DB4 DB3 DB2

R3 R2 R1

DB1

DB0

C1 (0)

P11 P10

P13

P9

P12

C2 (1)

RF1 AB COUNTER LATCH

CONTROL

BITS

11-BIT B COUNTER

6-BIT A COUNTER

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

P16 P14

DB8

DB7

A6

DB6 DB5 DB4 DB3 DB2

A5 A4 A3 A2 A1

DB1

DB0

B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

C2 (1) C1 (1)

Figure 27. ADF4206 Family Latch Summary

Rev. A | Page 13 of 24

ADF4206/ADF4208

RF2 REFERENCE COUNTER LATCH

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB21 DB20 DB19 DB18 DB17

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6 DB5 DB4 DB3 DB2

R5 R4 R3 R2 R1

DB1

DB0

DB16

P4

R13

R12

R11

R10

R9

R8

C2 (0) C1 (0)

P3

P2

R14

P5

P1

R14

R13

R12

..........

R3

R2

0

1

0

.

R1

DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

1

0

1

0

.

1

2

3

4

.

1

0

16380

1

..........

1

0

1

0

1

16381

16382

16383

P1

0

PD POLARITY

NEGATIVE

POSITIVE

1

P5

I

CP

0

1

1.25mA

4.375mA

P2

CHARGE PUMP

OUTPUT

0

1

NORMAL

THREE-STATE

P12

P11

FROM RF1 R LATCH

P4

0

P3

0

MUXOUT

0

1

0

X

1

X

0

LOGIC LOW STATE

RF2 ANALOG LOCK DETECT

0

1

0

RF2 REFERENCE DIVIDER OUTPUT

RF2 N DIVIDER OUTPUT

1

0

RF1 ANALOG LOCK DETECT

RF1/RF2 ANALOG LOCK DETECT

RF1 REFERENCE DIVIDER

RF1 N DIVIDER

0

1

0

1

0

FAST LOCK OUTPUT SWITCH ON

AND CONNECTED TO MUXOUT

RF2 COUNTER RESET

1

0

1

0

1

RF1 COUNTER RESET

RF2 AND RF1 COUNTER RESET

Figure 28. RF2 Reference Counter Latch Map

Rev. A | Page 14 of 24

ADF4206/ADF4208

RF2 AB COUNTER LATCH

CONTROL

BITS

6-BIT A COUNTER

11-BIT B COUNTER

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

A6

DB6 DB5 DB4 DB3 DB2

A5 A4 A3 A2 A1

DB1

DB0

C2 (0)

P7

P6

B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

C1 (1)

A COUNTER

A6

A5

X

.

A4

0

.

A3

A2

0

1

.

A1

DIVIDE RATIO

X

.

0

.

0

1

0

1

.

0

1

2

3

.

X

1

0

1

14

15

B11

B10

B9

0

.

B3

B2

0

1

.

B1

B COUNTER DIVIDE RATIO

0

.

0

.

..........

0

.

0

1

0

1

.

NOT ALLOWED

2

3

.

1

0

2044

1

..........

1

0

1

0

1

2045

2046

2047

P6

0

RF2 PRESCALER

64/65

1

32/33

P7

RF2 SECTION

0

1

NORMAL OPERATION

POWER-DOWN

N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER

THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES

2

OF N × F

REF

, N IS (P – P).

MIN

Figure 29. RF2 AB Counter Latch Map

Rev. A | Page 15 of 24

ADF4206/ADF4208

RF1 REFERENCE COUNTER LATCH

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6 DB5 DB4 DB3 DB2

R5 R4 R3 R2 R1

DB1

C2 (1)

DB0

P12

P9

R14

R13

R12

R11

R10

R9

R8

C1 (0)

P11 P10

P13

R14

R13

R12

..........

R3

R2

0

1

0

.

R1

DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

1

0

1

0

.

1

2

3

4

.

1

0

16380

1

..........

1

0

1

0

1

16381

16382

16383

P9

0

PD POLARITY

NEGATIVE

POSITIVE

1

P13

0

I

CP

1.25 mA

1

4.375 mA

P10

0

CHARGE PUMP OUTPUT

NORMAL

1

THREE-STATE

P4

P3

P12

P11

0

FROM RF2 R LATCH

MUXOUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

LOGIC LOW STATE

RF2 ANALOG LOCK DETECT

0

X

1

RF2 REFERENCE DIVIDER OUTPUT

RF2 N DIVIDER OUTPUT

RF1 ANALOG LOCK DETECT

RF1/RF2 ANALOG LOCK DETECT

RF1 REFERENCE DIVIDER

RF1 N DIVIDER

1

X

0

FAST LOCK OUTPUT SWITCH ON

AND CONNECTED TO MUXOUT

RF2 COUNTER RESET

1

0

1

0

1

RF1 COUNTER RESET

RF2 AND RF1 COUNTER RESET

Figure 30. RF1 Reference Counter Latch Map

Rev. A | Page 16 of 24

ADF4206/ADF4208

RF1 AB COUNTER LATCH

CONTROL

BITS

11-BIT B COUNTER

6-BIT A COUNTER

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

A6

DB6

A5

DB5 DB4 DB3 DB2

A4 A3 A2 A1

DB1

DB0

DB21

P16

P14 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

C2 (1) C1 (1)

A COUNTER

DIVIDE RATIO

0

1

2

3

A6

0

.

A5

A4

A3

A2

A1

0

.

0

.

0

.

0

1

.

0

1

0

1

.

1

0

1

62

63

B11

B10

B9

0

.

B3

B2

0

1

.

B1

0

1

0

1

.

B COUNTER DIVIDE RATIO

0

.

0

.

..........

0

.

NOT ALLOWED

..........

NOT ALLOWED

2

3

.

1

0

2044

1

..........

1

0

1

0

1

2045

2046

2047

P14

RF1 PRESCALER

0

1

64/65

32/33

P16

RF1 SECTION

0

1

NORMAL OPERATION

POWER-DOWN

N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER

THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF

2

N, N

IS (P – P).

MIN

Figure 31. RF1 AB Counter Latch Map

Rev. A | Page 17 of 24

ADF4206/ADF4208

PROGRAM MODES

Asynchronous RF1 Power-Down

Figure 28 and Figure 30 show how to set up the program modes

in the ADF420x family. Three points should be noted:

If P10 of the ADF420x family is set to 1 (three-state the RF1

charge pump), and P16 is subsequently set to 1, an asynchronous

power-down occurs. The device goes into power-down on the

rising edge of LE latching the 1 to P16 (the RF1 power-down bit).

1. RF2 and RF1 analog lock detect indicate when the PLL is

in lock. When the loop is locked and either RF2 or RF1

analog lock detect is selected, the MUXOUT pin shows a

logic high with narrow, low going pulses. When the

Activation of either synchronous or asynchronous power-down

forces the R and N dividers of the RF2/RF1 loop to their load

state conditions, and the RF2/RF1 input section is debiased to a

high impedance state.

RF2/RF1 analog lock detect is chosen, the locked condition

is indicated only when both RF2 and RF1 loops are locked.

2. The RF2 counter reset mode resets the R and AB counters

in the RF2 section and also puts the RF2 charge pump into

three-state. The RF1 counter reset mode resets the R and

AB counters in the RF1 section and also puts the RF1

charge pump into three-state. The RF2 and RF1 counter

reset mode resets the R and AB counters on both the RF1

and RF2 simultaneously.

The reference oscillator circuit is only disabled if both the RF2

and RF1 power-downs are set.

The input register and latches remain active and are capable of

loading and latching data during all power-down modes.

The RF2/RF1 section of the devices returns to normal powered

up operation immediately upon LE latching a 0 to the

appropriate power-down bit.

Upon removal of the reset bits, the AB counter resumes

counting in close alignment with the R counter (maximum

error is one prescaler output cycle).

IF SECTION (RF2)

3. The fast lock mode uses MUXOUT to switch a second loop

filter damping resistor to ground during fast lock operation.

Activation of fast lock occurs whenever the RF1 CP gain in

the RF1 reference counter is set to one.

Programmable RF2 Reference (R) Counter

If Control Bit C2 and Control Bit C1 are 0 and 0, the data is

transferred from the input shift register to the 14-bit RF2

R counter. Figure 28 shows the input shift register data format

for the RF2 R counter and the divide ratios that are possible.

POWER-DOWN

RF2 Phase Detector Polarity

It is possible to program the ADF420x family for either

synchronous or asynchronous power-down on either the RF2

or RF1 side.

P1 sets the RF2 phase detector polarity. When the RF2 VCO

characteristics are positive, this is set to 1. When they are

negative, it is set to 0. See Figure 28.

Synchronous RF2 Power-Down

RF2 Charge Pump Three-State

Programming a 1 to P7 of the ADF420x family initiates a

power-down. If P2 of the ADF420x family has been set to 0

(normal operation), a synchronous power-down is conducted.

The device automatically puts the charge pump into three-state

and completes the power-down.

P2 puts the RF2 charge pump into three-state mode when

programmed to a 1. It is set to 0 for normal operation.

See Figure 28.

RF2 Program Modes

Asynchronous RF2 Power-Down

Figure 28 and Figure 30 show how to set up the program modes

in the ADF420x family.

If P2 of the ADF420x family has been set to 1 (three-state the

RF2 charge pump), and P7 is subsequently set to 1, an

asynchronous power-down is conducted. The device enters

power-down on the rising edge of LE latching the 1 to P7 (the

RF2 power-down bit).

RF2 Charge Pump Currents

Bit P5 programs the current setting for the RF2 charge pump.

See Figure 28.

Synchronous RF1 Power-Down

Programmable RF2 AB Counter

Programming a 1 to P16 of the ADF420x family initiates a

power-down. If P10 of the ADF420x family is set to 0 (normal

operation), a synchronous power-down is conducted. The

device automatically puts the charge pump into three-state and

completes the power-down.

If Control Bit C2 and Control Bit C1 are 0 and 1, the data in the

input register is used to program the RF2 AB counter. The AB

counter is a 6-bit swallow counter (A counter) and an 11-bit

programmable counter (B counter). Figure 29 shows the input

register data format for programming the RF2 AB counter and

the divide ratios that are possible.

Rev. A | Page 18 of 24

ADF4206/ADF4208

RF2 Prescaler Value

RF1 Charge Pump Currents

P6 in the RF2 AB counter latch sets the RF2 prescaler value.

See Figure 29.

Bit P13 programs the current setting for the RF1 charge pump.

See Figure 30.

RF2 Power-Down

Programmable RF1 AB Counter

P7 in Figure 29 is the power-down bit for the RF2 side.

If Control Bit C2 and Control Bit C1 are 1 and 1, then the data

in the input register is used to program the RF1 AB counter.

The AB counter is a 6-bit swallow counter (A counter) and

11-bit programmable counter (B counter). Figure 31 shows the

input register data format for programming the RF1 AB counter

and the divide ratios that are possible.

RF SECTION (RF1)

Programmable RF1 Reference (R) Counter

If Control Bit C2 and Control Bit C1 are 1 and 0, the data is

transferred from the input shift register to the 14-bit RF1 R

counter. Figure 30 shows the input shift register data format for

the RF1 R counter and the divide ratios that are possible.

RF1 Prescaler Value

P14 in the RF1 A, B counter latch sets the RF1 prescaler value.

See Figure 31.

RF1 Phase Detector Polarity

P9 sets the RF1 phase detector polarity. When the RF1 VCO

characteristics are positive this is set to 1. When negative it is set

to 0. See Figure 30.

RF1 Power-Down

Setting P16 in the RF1 AB counter high powers down RF1 side.

RF Fast Lock

RF1 Charge Pump Three-State

The fast lock feature improves the lock time of the PLL. It

increases charge pump current to a maximum for a time.

Activate fast lock of the ADF420x family by setting P13 in the

reference counter high and setting the fast lock switch on using

MUXOUT. Switching in an external resistor using MUXOUT

compensates the loop dynamics for the effect of increasing

charge pump current. Setting P13 low removes the PLL from

fast lock mode.

P10 puts the RF1 charge pump into three-state mode when

programmed to a 1. It is set to 0 for normal operation.

See Figure 30.

RF1 Program Modes

Figure 28 and Figure 30 show how to set up the program modes

in the ADF420x family.

Rev. A | Page 19 of 24

ADF4206/ADF4208

APPLICATIONS SECTION

To have a channel spacing of 200 kHz (the GSM standard),

the reference input must be divided by 50 using the on-chip

reference counter.

LOCAL OSCILLATOR FOR GSM HANDSET

RECEIVER

Figure 33 shows the ADF4208 used in a classic superheterodyne

receiver to provide the required local oscillators (LOs).

The RF output frequency range is 1050 MHz to 1086 MHz. Loop

filter component values are chosen so that the loop bandwidth is

20 kHz. The synthesizer is set up for a charge pump current of

4.375 mA and the VCO sensitivity is 15.6 MHz/V.

In this circuit, the reference input signal is applied to the circuit

at OSC_INand is generated by a 10 MHz crystal oscillator. This is

a low cost solution. For better performance over temperature, a

TCXO (temperature controlled crystal oscillator) can be used

instead.

The IF output is fixed at 125 MHz. The IF loop bandwidth is

chosen to be 20 kHz with a channel spacing of 200 kHz. Loop

filter component values are chosen accordingly.

IF

OUT

V

RF

P

DD

OUT

100pF

VCO190-1068U

100pF

V

CC

18Ω

V

2

V

2

1

V 1

P

VCO190-125T

100pF

DD

3.3kΩ

P

DD

18Ω

CP

RF1

RF2

2.7kΩ

18Ω

1.3nF

620pF

13nF

ADF4208

MUXOUT

LOCK DETECT

100pF

RF2

RF1

IN

51Ω

OSC

51Ω

IN

CLK

DATA

LE

30pF

10MHz

18kΩ

OSC

OUT

DECOUPLING CAPACITORS (22µF/10pF) ON V , V OF

DD

P

THE ADF4208, AND ON V

OF THE VCOs HAVE BEEN

CC

OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 32. GSM Handset Receiver Local Oscillator Using the ADF4208

Rev. A | Page 20 of 24

ADF4206/ADF4208

200 kHz with a 20 kHz loop bandwidth. VCO sensitivity is

32 MHz/V. A charge pump current of 4.375 mA is used and the

desired phase margin for the loop is 45°.

LOCAL OSCILLATOR FOR WCDMA RECEIVER

Figure 33 shows the ADF4208 used to generate the local

oscillator frequencies for a wideband CDMA (WCDMA)

system.

When the IF output is fixed at 200 MHz, the VCO190-200T is

used. It has a sensitivity of 10 MHz/V. Channel spacing and

loop bandwidth are chosen to be the same as the RF side.

The required RF output range is 1720 MHz to 1780 MHz. The

VCO190-1750T meets this requirement. Channel spacing is

IF

OUT

V

RF

P

DD

OUT

100pF

V

CC

18Ω

V

2

V

V 2

P

1

V 1

P

VCO190-200T

VCO190-1750T

100pF

DD

18Ω

3.3kΩ

18Ω

CP

RF1

RF2

2.7k

18Ω

1.3nF

620pF

13nF

ADF4208

MUXOUT

LOCK DETECT

100pF

RF2

RF1

IN

51Ω

OSC

51Ω

IN

CLK

DATA

LE

30pF

10MHz

18kΩ

OSC

OUT

DECOUPLING CAPACITORS (22µF/10pF) ON V , V OF

DD

P

THE ADF4208, AND ON V

OF THE VCOs HAVE BEEN

CC

OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 33. Local Oscillator for WCDMA Receiver Using the ADF4208

Rev. A | Page 21 of 24

ADF4206/ADF4208

INTERFACING

The ADF420x family has a simple SPI®-compatible serial inter-

face for writing to the device. CLK, DATA, and LE control the

data transfer. When LE goes high, the 22 bits clocked into the

input register on each rising edge of CLK transfers to the

appropriate latch. See Figure 2 for the timing diagram and

Table 5 for the latch truth table.

ADSP-2181 INTERFACE

Figure 35 shows the interface between the ADF420x family and

the ADSP-21xx digital signal processor. The ADF420x family

needs a 22-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP21-xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for eight bits and use three memory locations for each

22-bit word. To program each 22-bit latch, store the three 8-bit

bytes, enable the autobuffered mode and then write to the

transmit register of the DSP. This last operation initiates the

autobuffer transfer.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz or one update every 1.1 ms. This is more than adequate

for systems that have typical lock times in hundreds of

microseconds.

ADuC812 INTERFACE

Figure 34 shows the interface between the ADF420x family and

the ADuC812 microconverter. Because the ADuC812 is based

on an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF420x family

needs a 22-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

SCLK

DT

CLK

DATA

ADF4206/

ADF4208

TFS

LE

ADSP-21xx

MUXOUT

(LOCK DETECT)

I/O FLAG

Figure 35. ADSP-21xx to ADF420x Family Interface

On first applying power to the ADF420x family, it requires four

writes (one each to the R counter latch and the AB counter latch

for both RF1 and RF2 sides) for the output to become active.

When operating in the mode described, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the

maximum rate at which the output frequency can be changed

will be about 180 kHz.

SCLOCK

MOSI

CLK

DATA

ADF4206/

ADF4208

ADuC812

LE

I/O PORTS

MUXOUT

(LOCK DETECT)

Figure 34. ADuC812 to ADF420x Family Interface

Rev. A | Page 22 of 24

ADF4206/ADF4208

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

6.60

6.50

6.40

20

11

10

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

COPLANARITY

0.10

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 37. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

Rev. A | Page 23 of 24

ADF4206/ADF4208

ORDERING GUIDE

Model

ADF4206BRU

ADF4206BRU-REEL

ADF4206BRU-REEL7

ADF4206BRUZ¹

ADF4206BRUZ-RL¹

ADF4206BRUZ-R7¹

ADF4208BRU

ADF4208BRU-REEL

ADF4208BRU-REEL7

ADF4208BRUZ¹

ADF4208BRUZ-RL¹

ADF4208BRUZ-R7¹

EVAL-ADF4206-7EB1

EVAL-ADF4208EB1

Temperature Range

−40°C to +85°C

Package Description

Package Option

RU-16

16-Lead Thin Shrink Small Outline Package [TSSOP]

20-Lead Thin Shrink Small Outline Package [TSSOP]

Evaluation Board

RU-16

RU-20

Evaluation Board

¹Z = Pb-free part.

registered trademarks are the property of their respective owners.

D01036-0-2/06(A)

Rev. A | Page 24 of 24


型号：	ADF4208BRUZ
厂家：	ADI
描述：	Dual, Integer-N 1.1 GHz / 2.0 GHz PLL 光电二极管
文件：	总24页 (文件大小：336K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF4208BRUZ [ADI]

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