ADF4196 [ADI]
Low Phase Noise, Fast Settling, 6 GHz; 低相位噪声，快速建立， 6 GHz的
| 型号： | ADF4196 |
| 厂家： | 
ADI |
| 描述： | Low Phase Noise, Fast Settling, 6 GHz |
| 文件： | 总28页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Phase Noise, Fast Settling, 6 GHz
PLL Frequency Synthesizer
Data Sheet
ADF4196
FEATURES
GENERAL DESCRIPTION
Fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
The ADF4196 frequency synthesizer can be used to implement
local oscillators (LO) in the upconversion and downconversion
Frequency hop across GSM band in 5 μs with phase settled
within 20 μs
1 degree rms phase error at 4 GHz RF output
Digitally programmable output phase
RF input range up to 6 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
sections of wireless receivers and transmitters. Its architecture is
specifically designed to meet the GSM/EDGE lock time require-
ments for base stations, and the fast settling feature makes the
ADF4196 suitable for pulse Doppler radar applications.
The ADF4196 consists of a low noise, digital phase frequency
detector (PFD) and a precision differential charge pump.
A differential amplifier converts the differential charge pump
output to a single-ended voltage for the external voltage controlled
oscillator (VCO). The sigma-delta (Σ-Δ) based fractional inter-
polator, working with the N divider, allows programmable modulus
fractional-N division. Additionally, the 4-bit reference (R) counter
and on-chip frequency doubler allow selectable reference signal
(REFIN) frequencies at the PFD input.
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Pulse Doppler radar
Instrumentation and test equipment
Beam-forming/phased array systems
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a VCO. The
switching architecture ensures that the PLL settles within the
GSM time slot guard period, removing the need for a second
PLL and associated isolation switches. This decreases the cost,
complexity, PCB area, shielding, and characterization found on
previous ping-pong GSM PLL architectures.
FUNCTIONAL BLOCK DIAGRAM
SDV
DV
1
DV
2
DV
3
AV
V 1
V 2
V 3
R
SET
DD
DD
×2
DD
DD
DD
P
P
P
REFERENCE
SW1
CP
4-BIT R
COUNTER
/2
DIVIDER
+
PHASE
+
REF
CHARGE
PUMP
OUT+
IN
FREQUENCY
DETECTOR
DOUBLER
CP
–
OUT–
–
SW2
CMR
V
DD
HIGH-Z
DGND
LOCK DETECT
DIFFERENTIAL
AMPLIFIER
AIN–
AIN+
–
+
OUTPUT
MUX
MUX
OUT
R
N
DIV
DIV
A
OUT
N COUNTER
SW3
FRACTIONAL
INTERPOLATOR
RF
RF
IN+
IN–
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION
REG
MODULUS
REG
INTEGER
REG
ADF4196
A
1
A
2
D
1
D
2
D
3
SD
SW
GND
GND
GND
GND
GND
GND
GND
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADF4196
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Shift Register .................................................................... 13
Register Map ................................................................................... 14
FRAC/INT Register (R0) Latch Map....................................... 15
MOD/R Register (R1) Latch Map............................................ 16
Phase Register (R2) Bit Latch Map .......................................... 17
Function Register (R3) Latch Map........................................... 18
Charge Pump Register (R4) Latch Map .................................. 19
Power-Down Register (R5) Bit Map........................................ 20
Mux Register (R6) Latch Map and Truth Table ..................... 21
Programming the ADF4196.......................................................... 22
Worked Example ........................................................................ 22
Spur Mechanisms ....................................................................... 22
Power-Up Initialization ............................................................. 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Transistor Count........................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
General Description................................................................... 11
Reference Input........................................................................... 11
RF Input Stage............................................................................. 11
PFD and Charge Pump.............................................................. 12
Differential Charge Pump ......................................................... 12
Fast Lock Timeout Counters..................................................... 12
Differential Amplifier ................................................................ 13
MUXOUT and Lock Detect ......................................................... 13
Changing the Frequency of the PLL and the Phase Lookup
Table ............................................................................................. 23
Applications Information.............................................................. 25
Local Oscillator for a GSM Base Station ................................. 25
Interfacing ................................................................................... 27
PCB Design Guidelines ............................................................. 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
12/11—Rev. A to Rev. B
Changes to Figure 10, Figure 11, Figure 13, and
Figure 14 ............................................................................................ 9
Change to Figure 31 ....................................................................... 17
10/11—Revision A: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADF4196
SPECIFICATIONS
AVDD = DVDD1, DVDD2, DVDD3 = SDVDD = 3 V 10%; VP1, VP2 = 5 V 10%; VP3 = 5.35 V 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V;
RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range = −40°C to +85°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN
RF Input Sensitivity
Maximum Allowable Prescaler Output
Frequency1
)
0.4
−10
6
0
750
GHz
dBm
MHz
See Figure 21 for input circuit
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Edge Slew Rate
REFIN Input Sensitivity
300
MHz
V/µs
V p-p
V
pF
µA
For f > 120 MHz, set REF/2 bit = 1 (Register R1)
300
0.7
VDD
0 to VDD
10
AC-coupled
CMOS compatible
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
100
26
MHz
ICP Up/Down
High Value
Low Value
6.6
104
5
mA
µA
%
kΩ
nA
%
RSET = 2.4 kΩ
RSET = 2.4 kΩ
Absolute Accuracy
RSET Range
ICP Three-State Leakage
ICP Up vs. Down Matching
ICP vs. VCP
ICP vs. Temperature
DIFFERENTIAL AMPLIFIER
Input Current
Output Voltage Range
VCO Tuning Range
Output Noise
1
4
Nominally RSET = 2.4 kΩ
1
0.1
1
0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
%
%
1
1
7
nA
V
V
1.4
1.8
VP3 − 0.3
VP3 − 0.8
nV/√Hz At 20 kHz offset
LOGIC INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IINH, IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
1.4
V
V
µA
pF
0.7
1
10
VDD − 0.4
2.7
V
V
IOH = 500 µA
IOL = 500 µA
0.4
3.3
V
DVDD1, DVDD2, DVDD3
VP1, VP2
VP3
IDD (AVDD + DVDD1, DVDD2, DVDD3 +
SDVDD)
AVDD
22
V
V
V
mA
4.5
5.0
5.5
5.65
27
AVDD ≤ VP1, VP2 ≤ 5.5 V
VP1, VP2 ≤ VP3 ≤ 5.65 V
IDD (VP1 + VP2)
IDD (VP3)
IDD Power-Down
22
24
10
27
30
mA
mA
µA
Rev. B | Page 3 of 28
ADF4196
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SW1, SW2, AND SW3
On Resistance
SW1 and SW2
SW3
65
75
Ω
Ω
NOISE CHARACTERISTICS
Output
900 MHz2
1800 MHz3
−108
−102
dBc/Hz
dBc/Hz
At 5 kHz offset and 26 MHz PFD frequency
At 5 kHz offset and 13 MHz PFD frequency
Phase Noise
Normalized Phase Noise Floor
−216
−110
dBc/Hz
dBc/Hz
At VCO output with dither off, PLL loop
bandwidth = 500 kHz
Measured at 10 kHz offset, normalized to 1 GHz
4
(PNSYNTH
)
Normalized 1/f Noise (PN1_f)5
1 Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz).
2 fREF = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz.
IN
3 fREF = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz.
IN
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N).
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency,
fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL™.
TIMING CHARACTERISTICS
AVDD = DVDD1, DVDD2, DVDD3 = 3 V 10%; VP1, VP2 = 5 V 10%; VP3 = 5.35 V 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V;
RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature = −40°C to +85°C.
Table 2.
Parameter
Limit
Description
t1
t2
t3
t4
t5
t6
t7
10 ns min
10 ns min
10 ns min
15 ns min
15 ns min
10 ns min
15 ns min
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Timing Diagram
t4
t5
CLK
t2
t3
DB23
(MSB)
DB2 (LSB)
(CONTROL BIT C3)
DB1 (LSB)
(CONTROL BIT C2)
DB0 (LSB)
DATA
LE
DB22
(CONTROL BIT C1)
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. B | Page 4 of 28
Data Sheet
ADF4196
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3.
Parameter
Rating
AVDD to Ground
AVDD to DVDD1, DVDD2, DVDD3, SDVDD −0.3 V to +0.3 V
VP1, VP2, VP3 to Ground
VP1, VP2, VP3 to AVDD
−0.3 V to +3.6 V
Table 4. Thermal Resistance
Package Type
θJA
Unit
−0.3 V to +5.8 V
−0.3 V to +5.8 V
32-Lead LFCSP (Paddle Soldered)
27.3
°C/W
Digital I/O Voltage to Ground
Analog I/O Voltage to Ground
REFIN, RFIN+, RFIN− to Ground
Operating Temperature Range
Industrial
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
−0.3 V to VDD + 0.3 V
−0.3 V to VP1, VP2, VP3 + 0.3 V
−0.3 V to VDD + 0.3 V
TRANSISTOR COUNT
This device includes 75,800 metal oxide semiconductors (MOS)
and 545 bipolar junction transistors (BJT).
−40°C to +85°C
−65°C to +125°C
150°C
ESD CAUTION
Peak Temperature
Time at Peak Temperature
260°C
40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with
an ESD rating of <2 kV, and it is ESD sensitive. Take proper
precautions for handling and assembly.
Rev. B | Page 5 of 28
ADF4196
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 V
2
CMR
1
2
P
PIN 1
A
23 R
22 A
21 D
20 V
OUT
SET
INDICATOR
SW3
3
4
2
3
GND
A
1
GND
GND
ADF4196
RF
RF
5
6
7
8
1
P
IN–
TOP VIEW
19 LE
18 DATA
17 CLK
IN+
(Not to Scale)
AV
DD
DV
1
DD
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
TO THE GROUND PLANE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
CMR
Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to
three-fifths of VP3. Requires a 0.1 µF capacitor to the ground plane.
2
3
4
5
AOUT
SW3
Differential Amplifier Output. This pin is the differential amplifier output to tune the external VCO.
Fast Lock Switch 3. This switch is closed when the SW3 timeout counter is active.
Analog Ground. This is the ground return pin for the differential amplifier and the RF section.
Complementary Input to the RF Prescaler. This pin must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
AGND1
RFIN−
6
7
RFIN+
AVDD
Input to the RF Prescaler. This small-signal input is ac-coupled to the external VCO.
Power Supply Pin for the RF Section. Nominally 3 V. Place a 100 pF decoupling capacitor to the ground plane as
close as possible to this pin.
8
DVDD1
Power Supply Pin for the N Divider. DVDD1 should be at the same voltage as AVDD. Place a 0.1 µF decoupling
capacitor to the ground plane as close as possible to this pin.
9
DGND1
Ground Return Pin for DVDD1.
10
DVDD2
Power Supply Pin for the REFIN Buffer and R Divider. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the
ground plane as close as possible to this pin.
11
REFIN
Reference Input. This CMOS input has a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
12
13
14
15
DGND
2
Ground Return Pin for DVDD2 and DVDD3.
Power Supply Pin for the Serial Interface Logic. Nominally 3 V.
Ground Return Pin for the Digital Σ-Δ Modulator.
Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground
plane as close as possible to this pin.
DVDD3
SDGND
SDVDD
16
17
18
19
20
MUXOUT
CLK
Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally (see Figure 35 for details).
Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is
selected by the three LSBs.
DATA
LE
VP1
Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, VP1 should be at the same voltage as VP2.
Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin.
21
22
DGND
3
Ground Return Pin for VP1.
Ground Return Pin for VP2.
AGND2
Rev. B | Page 6 of 28
Data Sheet
ADF4196
Pin No. Mnemonic Description
23
RSET
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at
the RSET pin is 0.55 V. The relationship between ICP and RSET is
0.25
RSET
ICP
=
Therefore, with RSET = 2.4 kΩ, ICP = 104 µA.
24
VP2
Power Supply Pin for the Charge Pump. Nominally 5 V, VP2 should be at the same voltage as VP1. Place a 0.1 µF
decoupling capacitor to the ground plane as close as possible to this pin.
25
26
27
28
29
30
31
32
AIN−
CPOUT−
SW2
SWGND
SW1
CPOUT+
AIN+
VP3
Negative Input Pin for the Differential Amplifier.
Differential Charge Pump Negative Output Pin. Connect this pin to AIN− and the loop filter.
Fast Lock Switch 2. This switch is closed to SWGND when the SW1/SW2 timeout counter is active.
Ground for SW1 and SW2 Switches. Connect this pin to the ground plane.
Fast Lock Switch 1. This switch is closed to SWGND when the SW1/SW2 timeout counter is active.
Differential Charge Pump Positive Output Pin. Connect this pin to AIN+ and the loop filter.
Positive Input Pin for the Differential Amplifier.
Power Supply Pin for the Differential Amplifier. Ranges from 5.0 V to 5.5 V. Place a 0.1 µF decoupling capacitor to
the ground plane as close as possible to this pin. VP3 also requires a 10 µF decoupling capacitor to the ground plane.
EP
Exposed Paddle. The exposed paddle must be connected to the ground plane.
Rev. B | Page 7 of 28
ADF4196
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
10
5
FREQ. UNIT GHz KEYWORD
R
PARAM TYPE S
DATA FORMAT
IMPEDANCE 50
MA
FREQ.
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
MAGS11 ANGS11
FREQ.
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
MAGS11 ANGS11
0.8897
–16.6691
–19.9279
–23.561
–26.9578
–30.8201
–34.9499
–39.0436
–42.3623
–46.322
–50.3484
–54.3545
–57.3785
–60.695
0.67107
0.66556
0.6564
0.6333
0.61406
0.5977
–75.8206
–77.6851
–80.3101
–82.5082
–85.5623
–87.3513
–89.7605
–93.0239
–95.9754
–99.1291
–102.208
–106.794
–111.659
–117.986
–125.62
0
0.87693
0.85834
0.85044
0.83494
0.81718
0.80229
0.78917
0.77598
0.75578
0.74437
0.73821
0.7253
–5
–10
–15
–20
–25
–30
0.5655
0.5428
0.51733
0.49909
0.47309
0.45694
0.44698
0.43589
0.42472
0.41175
0.41055
0.40983
0.71365
0.70699
0.7038
0.69284
0.67717
–63.9152
–66.4365
–68.4453
–70.7986
–73.7038
4/5 PRESCALER 8/9 PRESCALER
–133.291
–140.585
–147.97
0
1
2
3
4
5
6
7
FREQUENCY (GHz)
Figure 7. RF Input (RFIN) Sensitivity
Figure 4. S-Parameter Data for the RF Input
–30
–40
–30
–40
DCS1800 Tx SETUP, 60kHz LOOP BW, DITHER OFF
RF = 1842.6MHz, fREF = 13MHz, MOD = 65
DSB INTEGRATED PHASE ERROR = 0.46° RMS
SIRENZA 1843T VCO
GSM900 Rx SETUP, 40kHz LOOP BW, DITHER OFF
RF = 1092.8MHz, fREF = 26MHz, MOD = 130
N = 42 4/130
–50
–50
INTEGER BOUNDARY SPUR: –103dBc @ 800kHz
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. Single-Sideband (SSB) Phase Noise Plot at 1092.8 MHz
(GSM900 Rx Setup) vs. Free Running VCO Noise
Figure 8. Single-Sideband (SSB) Phase Noise Plot at 1842.6 MHz
(DCS1800 Tx Setup)
–60
–60
DCS1800 Tx SETUP WITH DITHER OFF,
60kHz LOOP BW, 13MHz PFD.
MEASURED ON EVAL-ADF4193EBZ1 BOARD
–70
DCS1800 Tx SETUP WITH DITHER OFF,
60kHz LOOP BW, 13MHz PFD.
MEASURED ON EVAL-ADF4193EBZ1 BOARD
–70
400kHz SPURS @ 25°C
–80
–80
–90
600kHz SPURS @ 25°C
–90
–100
–110
–100
–110
400kHz SPURS @ 85°C
600kHz SPURS @ 85°C
1872
–120
1846
–120
1846
1859
1859
1872
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. 400 kHz Fractional Spur Levels Across All DCS1800 Tx Channels
over Two Integer Multiples of the PFD Reference
Figure 9. 600 kHz Fractional Spur Levels Across All DCS1800 Tx Channels over
Two Integer Multiples of the PFD Reference
Rev. B | Page 8 of 28
Data Sheet
ADF4196
5
4
3
2
1
0
5
4
3
2
1
0
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD.
TIMERS: I = 28, SW1/SW2, SW3 = 35.
CP
FREQUENCY LOCK IN WIDE BW MODE @ 5µs.
V
TUNE
CP
V
OUT–
CP
CP
OUT+
OUT–
TUNE
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD.
TIMERS: I = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 4µs.
CP
OUT+
CP
–1
0
1
2
3
4
5
6
7
8
9
–1
0
1
2
3
4
5
6
7
8
9
TIME (µs)
TIME (µs)
Figure 10. VTUNE Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz with Sirenza 1843T VCO
Figure 13. VTUNE Settling Transient for a 75 MHz Jump Down from 1893 MHz
to 1818 MHz (Bottom of Allowed Tuning Range) with Sirenza 1843T VCO
50
50
DCS1800 Tx SETUP, 60kHz LOOP BW.
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD WITH AD8302
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD WITH AD8302
40
40
PHASE DETECTOR.
PHASE DETECTOR.
30
30
TIMERS: I = 28, SW1/SW2, SW3 = 35.
TIMERS: I = 28, SW1/SW2, SW3 = 35.
CP
CP
+25°C
+25°C
PEAK PHASE ERROR < 5° @ 17.8µs
PEAK PHASE ERROR < 5° @ 19.2µs
20
20
10
10
0
0
–10
–10
–20
–30
–40
–50
+85°C
–40°C
+85°C
–40°C
–20
–30
–40
–50
–5
0
5
10
15
20
25
30
35
40
45
–5
0
5
10
15
20
25
30
35
40
45
TIME (µs)
TIME (µs)
Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz (VTUNE = 1.8 V to 3.7 V with Sirenza 1843T VCO)
Figure 14. Phase Settling Transient for a 75 MHz Jump Down from 1893 MHz
to 1818 MHz (VTUNE = 3.7 V to 1.8 V with Sirenza 1843T VCO)
8
6
2.0
V 1 = V 2 = 5V
ICP
+ P, ICP – P
OUT
P
P
OUT
5
4
3
2
1
0
V 3 = 5.5V
P
1.5
A
(= V
)
V
= 3.3V
OUT
TUNE
CMR
I
I
= | ICP
OUT
+ P | + | ICP
OUT
– N |
+ N |
UP
4
1.0
= | ICP
– P | + | ICP
DOWN
OUT
OUT
2
0.5
CHARGE PUMP MISMATCH (%)
CP
(= AIN+)
0
0
OUT+
–2
–4
–6
–8
–0.5
–1.0
–1.5
–2.0
NORMAL OPERATING RANGE
CP
(= AIN–)
OUT–
ICP
+ N, ICP
2.5
– N
OUT
OUT
1780 1800 1820 1840 1860 1880 1900 1920 1940
0
0.5
1.0
1.5
CP
2.0
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
+ / CP
OUT
– VOLTAGE (V)
OUT
Figure 15. Tuning Range with a Sirenza 1843T VCO and a 5.5 V Differential
Amplifier Power Supply Voltage
Figure 12. Differential Charge Pump Output Compliance Range and
Charge Pump Mismatch with VP1 = VP2 = 5 V
Rev. B | Page 9 of 28
ADF4196
Data Sheet
1000
1.8
1.5
1.2
0.9
0.6
0.3
0
MEASURED USING AD8302 PHASE DETECTOR
Y-AXIS SCALE: 10mV/DEGREE
RF = 1880MHz, PFD = 26MHz, MOD = 130
X-AXIS SCALE: 2.77°/STEP
100
10
7nV/ Hz @ 20kHz
1
1k
10k
100k
1M
10M
0
13
26
39
52
65
78
91
104 117 130
FREQUENCY (Hz)
PHASE CODE
Figure 16. Voltage Noise Density Measured at the
Differential Amplifier Output
Figure 18. Detected RF Output Phase for Phase Code Sweep from 0 to MOD
100
90
ADF4193
104MHz
5dBm
SW3
EVAL BOARD
REF
IN
+85°C
SW1,
RF
OUT
80
SW2
1805MHz 1880MHz
+85°C
+25°C
+25°C
70
60
INPA
INPB
–40°C
SIGNAL
GENERATOR
OSCILLOSCOPE
VPHS
50
–40°C
TUNING VOLTAGE RANGE
40
30
20
AD8302
EVB
10MHz
EXT REF
1880MHz
SIGNAL
GENERATOR
10
0
0
1
2
3
4
5
INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD
REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS
DRAIN VOLTAGE (V)
Figure 17. On Resistance of the SW1, SW2, and SW3 Loop Filter Switches
Figure 19. Test Setup for Phase Lock Time Measurements
Rev. B | Page 10 of 28
Data Sheet
ADF4196
THEORY OF OPERATION
GENERAL DESCRIPTION
RF INPUT STAGE
The ADF4196 is targeted at GSM base station requirements,
specifically to eliminate the need for ping-pong solutions.
It can also be used in pulse Doppler radar applications. The
ADF4196 works on the basis of fast lock, using a wide loop
bandwidth during a frequency change and narrowing the loop
bandwidth when frequency lock is achieved.
The RF input stage is shown in Figure 21. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler. Two prescaler options are available:
4/5 and 8/9. Select the 8/9 prescaler for N divider values that
are greater than 80.
AV
DD
1.6V
BIAS
GENERATOR
Widening the loop bandwidth is achieved by increasing the
charge pump current. To maintain stability with the changing
charge pump current, the ADF4196 includes switches that
change the loop filter component values.
500Ω
500Ω
RF
RF
IN+
The narrow loop bandwidth ensures that phase noise and spur
specifications are met. A differential charge pump and loop filter
topology ensure that the fast lock time benefit obtained from
widening the loop bandwidth is maintained when the loop is
restored to narrow bandwidth mode for normal operation.
IN–
AGND
Figure 21. RF Input Stage
RF N Divider
REFERENCE INPUT
The RF N divider allows a fractional division ratio in the PLL
feedback path. The integer and fractional parts of the division
are programmed using separate registers, as shown in Figure 22
and described in the INT, FRAC, and MOD Relationship section.
Integer division ratios from 26 to 511 are allowed, and a third-
order Σ-Δ modulator interpolates the fractional value between
the integer steps.
The reference input stage is shown in Figure 20. Switch SW1
and Switch SW2 are normally closed, and Switch SW3 is
normally open. During power-down, SW3 is closed, and SW1
and SW2 are opened to ensure that there is no loading of the
REFIN pin. The falling edge of REFIN is the active edge at the
positive edge triggered PFD.
POWER-DOWN
CONTROL
RF N DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
100kΩ
TO PFD
NC
N COUNTER
SW2
TO R COUNTER
REF
IN
NC
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
BUFFER
SW1
NO
SW3
INT
VALUE
MOD
VALUE
FRAC
VALUE
Figure 20. Reference Input Stage
R Counter and Doubler
The 4-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the PFD.
A toggle flip-flop can be inserted after the R counter to provide
an additional divide-by-2. Using this option has the added
advantage of ensuring that the PFD reference clock has a 50/50
mark-to-space ratio. This ratio gives the maximum separation
between the fast lock timer clock, which is generated off the
falling edge of the PFD reference, and the rising edge, which is
the active edge in the PFD. It is recommended that this toggle
flip-flop be enabled for all even R divide values that are greater
than 2. The flip-flop must be enabled if dividing down a REFIN
frequency that is greater than 120 MHz.
Figure 22. Fractional-N RF Divider
INT, FRAC, and MOD Relationship
The INT, FRAC, and MOD values, programmed through the
serial interface, make it possible to generate RF output frequencies
that are spaced by fractions of the PFD reference frequency.
The N divider value, shown inside the brackets of the following
equation for the RF VCO frequency (RFOUT), is composed of an
integer part (INT) and a fractional part (FRAC/MOD).
RFOUT = fPFD × [INT + (FRAC/MOD)]
where:
RFOUT is the output frequency of the external VCO.
PFD is the PFD reference frequency.
(1)
An optional doubler before the 4-bit R counter can be used for
low REFIN frequencies, up to 20 MHz. With these programmable
options, reference division ratios from 0.5 to 30 between REFIN
and the PFD are possible.
f
The value of MOD is chosen to give the desired channel step
with the available reference frequency. Then, program the INT
and FRAC words for the desired RF output frequency. See the
Worked Example section for more information.
Rev. B | Page 11 of 28
ADF4196
Data Sheet
matching is improved by an order of magnitude over the
PFD AND CHARGE PUMP
conventional single-ended charge pump that depends on the
matching of two different device types. The up/down matching
in this structure depends on how a PMOS matches a PMOS,
and how an NMOS matches an NMOS.
The PFD takes inputs from the R divider and N divider and
produces up and down outputs with a pulse width difference
that is proportional to the phase difference between the inputs.
The charge pump outputs a net up or down current pulse of
a width that is equal to this difference, to pump up or pump down
the voltage that is integrated into the loop filter, which in turn
increases or decreases the VCO output frequency. If the N divider
phase lags the R divider phase, a net up-current pulse is produced
that increases the VCO frequency (and, thus, the phase). If the
N divider phase leads the R divider edge, a net down-current
pulse is produced to reduce the VCO frequency and phase.
Figure 23 is a simplified schematic of the PFD and charge pump.
The charge pump is made up of an array of 64 identical cells,
each of which is fully differential. All 64 cells are active during
fast lock, and only one cell is active during normal operation.
V
P
BIAS
P
P
UP
DOWN
CP
C
POUT–
OUT+
DOWN
UP
V
N
BIAS
N
N
Figure 24. Differential Charge Pump Cell
with External Loop Filter Components
Because a single-ended control voltage is required to tune the VCO,
an on-chip differential-to-single-ended amplifier is provided for
this purpose. In addition, because the phase-locked loop controls
only the differential voltage generated across the charge pump
outputs, an internal common-mode feedback (CMFB) loop
biases the charge pump outputs at a common-mode voltage of
approximately 2 V.
FAST LOCK TIMEOUT COUNTERS
Timeout counters, clocked at one-quarter of the PFD reference
frequency, are provided to precisely control the fast locking
operation (see Figure 25). When a new frequency is programmed,
the fast lock timers start and the PLL locks into wide bandwidth
mode with the 64 identical 100 µA charge pump cells active (for a
total of 6.4 mA).
CP
D
Q
OUT+
R DIVIDER
CLR
When the ICP counter times out, the charge pump current is
reduced to 1× by deselecting cells in binary steps over the next
six timer clock cycles, until only one 100 µA cell is active. The
switching of the charge pump current, from 6.4 mA to 100 µA,
equates to an 8-to-1 change in loop bandwidth; when this happens,
the loop filter must be changed to ensure stability. The SW1,
SW2, and SW3 switches change the loop filter.
CHARGE
PUMP
CMFB
ARRAY
[64:1]
CLR
CP
D
Q
OUT–
N DIVIDER
EN[64:1]
Figure 23. PFD and Differential Charge Pump Simplified Schematic
The applications circuit shown in Figure 37 shows how the
switches can be used to reconfigure the loop filter time constants.
They close to short out external loop filter resistors during fast lock
and open when their counters time out to restore the filter time
constants to their normal values for the 100 µA charge pump
current. Because it takes six timer clock cycles to reduce the
charge pump current to 1×, it is recommended that both switch
timers be pro-grammed to the value of the ICP timer plus 7.
DIFFERENTIAL CHARGE PUMP
The charge pump cell has a fully differential design for best up-
to-down current matching (see Figure 24). Good matching is
essential to minimize the phase offset created when switching
the charge pump current from its high value (in fast lock mode)
to its nominal value (in normal mode).
To pump up, the up switches are on, and the PMOS current sources
out through CPOUT+, which increases the voltage on the external
loop filter capacitors that are connected to CPOUT+. Similarly, the
NMOS current sink on CPOUT− decreases the voltage on the
START
WRITE
TO R0
I
SW1/SW2
TIMEOUT
COUNTER
SW3
TIMEOUT
COUNTER
CP
TIMEOUT
COUNTER
external loop filter capacitors that are connected to CPOUT−
Therefore, the differential voltage between CPOUT+ and CPOUT−
.
fPFD
÷4
SW3
increases.
CHARGE PUMP
ENABLE LOGIC
A
OUT
To pump down, PMOS current sources out through CPOUT− and
NMOS current sinks in through CPOUT+, which decreases the
(CPOUT+, CPOUT−) differential voltage. The charge pump up/down
SW1
SW2
EN[64:1]
SW
GND
Figure 25. Fast Lock Timeout Counters
Rev. B | Page 12 of 28
Data Sheet
ADF4196
DV
DD
DIFFERENTIAL AMPLIFIER
LOGIC LOW
SERIAL DATA OUTPUT
R DIVIDER OUTPUT
N DIVIDER OUTPUT
THREE-STATE OUTPUT
TIMER OUTPUTS
The internal, low noise, differential-to-single-ended amplifier
converts the differential charge pump output to a single-ended
control voltage for the tuning port of the VCO. Figure 26 shows
a simplified schematic of the differential amplifier. The output
voltage is equal to the differential voltage, offset by the voltage
on the CMR pin, according to the following equation:
MUX
MUX
CONTROL
OUT
DIGITAL LOCK DETECT
LOGIC HIGH
V
AOUT = (VAIN+ − VAIN−) + VCMR
(2)
D
GND
The CMR offset voltage is internally biased to three-fifths of
NOTE:
1. NOT ALL MUX
MUX REGISTER.
MODES THAT ARE SHOWN REFER TO THE
OUT
VP3, the differential amplifier power supply voltage, as shown in
Figure 26. Connect a 0.1 µF capacitor to the ground plane from
the CMR pin to roll off the thermal noise of the biasing resistors.
Figure 27. MUXOUT Circuit
Lock Detect
AIN–
MUXOUT can be programmed to provide a digital lock detect
signal. Digital lock detect is active high. Its output goes high if
there are 40 successive PFD cycles with an input error of <3 ns.
For reliable lock detect operation with RF frequencies of <2 GHz,
it is recommended that this threshold be increased to 10 ns by
programming Register R6. The digital lock detect goes low again
when a new channel is programmed or when the error at the
PFD input exceeds 30 ns for one or more cycles.
500Ω
500Ω
A
OUT
V
3
P
AIN+
20kΩ
CMR
500Ω
500Ω
C EXT =
0.1µF
30kΩ
Figure 26. Differential Amplifier Block Diagram
INPUT SHIFT REGISTER
As shown in Figure 15, the differential amplifier output voltage
behaves according to Equation 2 over a 4 V range from ~1.2 V
minimum up to VP3 − 0.3 V maximum. However, fast settling
is guaranteed over a tuning voltage range from 1.8 V up to
VP3 − 0.8 V only. This range allows sufficient room for overshoot
in the PLL frequency settling transient.
The ADF4196 serial interface includes a 24-bit input shift register.
Data is clocked in, MSB first, on each rising edge of CLK. Data
from the shift register is latched into one of eight control registers,
R0 to R7, on the rising edge of load enable (LE) The destination
register is determined by the state of the three control bits: C3
(DB2), C2 (DB1), and C1 (DB0) in the shift register. DB2, DB1,
and DB0 are the three LSBs, as shown in the timing diagram
in Figure 2. The truth table for these bits is shown in Table 6.
Figure 28 shows a summary of how the registers are programmed.
Noise from the differential amplifier is suppressed inside the
PLL loop bandwidth. For loop bandwidths of >20 kHz, the 1/f
noise has a negligible effect on the PLL output phase noise.
Outside the loop bandwidth, the FM noise of the differential
amplifier modulates the VCO. The passive filter network following
the differential amplifier (see Figure 37) suppresses this noise
contribution to below the VCO noise from offsets of 400 kHz
and greater. This network has a negligible effect on lock time
because it is bypassed when SW3 is closed while the loop is
locking.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3 (DB2) C2 (DB1) C1 (DB0) Register Name
Register
R0
R1
R2
R3
R4
R5
R6
R7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FRAC/INT
MOD/R
Phase
Function
Charge pump
Power-down
Mux
MUXOUT AND LOCK DETECT
MUXOUT Control
The output multiplexer on the ADF4196 allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by Bits[M4:M1] in the mux register. Figure 35
shows the full truth table; see Figure 27 for a block diagram
of the MUXOUT circuit.
Test mode
Rev. B | Page 13 of 28
ADF4196
Data Sheet
REGISTER MAP
FRAC/INT REGISTER (R0)
CONTROL
BITS
9-BIT RF INT VALUE
12-BIT RF FRAC VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F6
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
C3 (0) C2 (0) C1 (0)
MOD/R REGISTER (R1)
DBB DBB
DBB
DBB
DBB
4-BIT RF R
COUNTER
CONTROL
BITS
12-BIT MODULUS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F5 F4 F2 F1 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7
DB8
M6
DB7
M5
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
0
C3 (0) C2 (0) C1 (1)
PHASE REGISTER (R2)
DBB
CONTROL
BITS
12-BIT PHASE
DB15 DB14 DB13 DB12 DB11 DB10 DB9
P12 P11 P10 P9 P8 P7
DB8
P6
DB7
P5
DB6
P4
DB5
P3
DB4
P2
DB3
P1
DB2
DB1
DB0
0
C3 (0) C2 (1) C1 (0)
FUNCTION REGISTER (R3)
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
1
DB5
F3
DB4
1
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
C3 (0) C2 (1) C1 (1)
CHARGE PUMP REGISTER (R4)
TIMER
CONTROL
BITS
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
C9 C8 C7 C6 C5
9-BIT TIMEOUT COUNTER
SELECT
DB8
C4
DB7
C3
DB6
C2
DB5
C1
DB4
F2
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
C3 (1) C2 (0) C1 (0)
POWER-DOWN REGISTER (R5)
CONTROL
BITS
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
C3 (1) C2 (0) C1 (1)
MUX REGISTER (R6)
SIGMA-DELTA
AND
LOCK DETECT MODES
CONTROL
BITS
RESERVED
MUX
OUT
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
1
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
M13
M12
M11
M10
0
0
0
C3 (1) C2 (1) C1 (0)
TEST MODE REGISTER (R7)
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
DB1
DB0
0
0
0
0
0
0
0
C3 (1) C2 (1) C1 (1)
DBB = DOUBLE BUFFERED BIT(S)
Figure 28. Bit Maps for Register R0 to Register R7
Rev. B | Page 14 of 28
Data Sheet
ADF4196
FRAC/INT REGISTER (R0) LATCH MAP
CONTROL
BITS
9-BIT RF INT VALUE
12-BIT RF FRAC VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F6
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
C3 (0) C2 (0) C1 (0)
F12
F11
F10
F3
F2
F1
FRACTIONAL VALUE (FRAC)
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
4092
4093
4094
4095
0 ≤ FRAC < MOD
N9
N8
N7
N6
N5
N4
N3
N2
N1
INTEGER VALUE (INT)
0
.
0
.
0
.
0
.
1
.
1
.
0
.
1
.
0
.
26
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
511
Figure 29. Bit Map for Register R0
R0, the FRAC/INT register, is used to program the synthesizer
output frequency. On the PFD cycle following a write to R0,
the N divider section is updated with the new INT and FRAC
values, and the PLL automatically enters fast lock mode. The
charge pump current is increased to its maximum value and
remains at this value until the ICP timeout counter times out;
and the SW1, SW2, and SW3 switches close and remain closed
until the SW1/SW2 and SW3 timeout counters time out.
Control Bits
To select R0, the FRAC/INT register, the three LSBs (C3, C2,
and C1) should be set to 0, 0, 0.
9-Bit RF INT Value
Bits[DB23:DB15] set the INT value, which determines the
integer part of the feedback division factor. All integer values
from 26 to 511 are allowed (see the Worked Example section).
12-Bit RF FRAC Value
After all the registers are programmed during the initialization
sequence (see Table 9), a new channel can be programmed
by performing a write to R0. However, as described in the
Programming the ADF4196 section, it may also be desirable
to program the R1 and R2 register settings on a channel-by-
channel basis. These settings are double buffered by the write to
Register R0. This means that, although the data is loaded through
the serial interface on the respective R1 and R2 write cycles, the
synthesizer is not updated with their data until the next write to
Register R0.
Bits[DB14:DB3] set the numerator of the fraction that is input
to the Σ-Δ modulator. This fraction, along with INT, specifies
the new frequency channel that the synthesizer locks to, as shown
in the Worked Example section. FRAC values from 0 to MOD − 1
cover channels over a frequency range that is equal to the PFD
reference frequency.
Rev. B | Page 15 of 28
ADF4196
Data Sheet
MOD/R REGISTER (R1) LATCH MAP
4-BIT RF
R COUNTER
CONTROL
BITS
12-BIT MODULUS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
M6
DB7
M5
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
F5
F4
0
F2
F1
R4
R3
R2
R1
M12
M11
M10
M9
M8
M7
C3 (0) C2 (0) C1 (1)
F4 REF/2
0
1
DISABLED
ENABLED
F2 PRESCALER
F1 DOUBLER ENABLE
M12
M11
M10
M3
M2
M1
INTERPOLATOR MODULUS VALUE (MOD)
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
..........
1
1
1
.
.
.
1
1
1
1
0
1
1
.
.
.
0
0
1
1
1
0
1
.
.
.
0
1
0
1
13
14
15
.
.
.
4092
4093
4094
4095
0
1
4/5
8/9
0
1
DOUBLER DISABLED
DOUBLER ENABLED
..........
..........
..........
..........
..........
..........
..........
..........
..........
F5 CP ADJ
0
1
NOMINAL
ADJUSTED
R4
R3
R2
R1
RF R COUNTER DIVIDE RATIO
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
12
13
14
15
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Figure 30. Bit Map for Register R1
R1, the MOD/R register, sets the PFD reference frequency and
the channel step size, which is determined by the PFD frequency
divided by the fractional modulus. Note that the 12-bit modulus,
the 4-bit RF R counter, the doubler enable bits, REF/2, and
CP ADJ are double buffered. They do not take effect until the
next write to R0 (the FRAC/INT register) is complete.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with INT, FRAC,
and MOD, determine the overall division ratio from RFIN to the
PFD input. Operating at CML levels, it takes the clock from the
RF input stage and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating the
ADF4196 above 3 GHz, the prescaler must be set to 8/9. The
prescaler limits the INT value. If P = 4/5, then NMIN = 26.
If P = 8/9, NMIN = 80.
Control Bits
Register R1 is selected with C3, C2, and C1 set to 0, 0, 1.
CP ADJ
When the CP ADJ bit is set to 1, the charge pump current is
scaled up 25% from its nominal value on the next write to R0.
When this bit is set to 0, the charge pump current remains at its
nominal value on the next write to R0. See the Programming
the ADF4196 section for more information on how this feature
can be used.
Doubler Enable
Setting the doubler enabler bit to 1 inserts a frequency doubler
between REFIN and the 4-bit RF R counter. Setting this bit to 0
bypasses the doubler.
4-Bit RF R Counter
The 4-bit RF R counter allows the REFIN frequency to be divided
down to produce the reference clock to the PFD. All integer
values from 1 to 15 are allowed (see the Worked Example section).
REF/2
Setting the REF/2 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD, which extends the maximum
REFIN input rate.
12-Bit Modulus
For a given PFD reference frequency, the fractional denominator
or modulus sets the channel step resolution at the RF output. All
integer values from 13 to 4095 are allowed. See the Programming
the ADF4196 section for a Worked Example and guidelines for
selecting the value of MOD.
Reserved Bit
The reserved bit, DB21, must be set to 0.
Rev. B | Page 16 of 28
Data Sheet
ADF4196
PHASE REGISTER (R2) BIT LATCH MAP
CONTROL
BITS
12-BIT PHASE
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
P6
DB7
P5
DB6
P4
DB5
P3
DB4
P2
DB3
P1
DB2
DB1
DB0
0
P12
P11
P10
P9
P8
P7
C3 (0) C2 (1) C1 (0)
1
P12
P11
P10
P3
P2
P1
PHASE VALUE
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
.
.
.
1
1
1
1
0
0
1
.
.
.
0
0
1
1
0
1
0
.
.
.
0
1
0
1
0
1
2
.
.
.
4092
4093
4094
4095
1
0 ≤ PHASE VALUE < MOD
Figure 31. Bit Map for Register R2
R2, the phase register, is used to program the phase of the VCO
output signal.
The output of a fractional-N PLL can settle to any one of the
MOD possible phase offsets with respect to the reference, where
MOD is the fractional modulus.
Control Bits
To keep the output at the same phase offset with respect to the
reference, each time that particular output frequency is pro-
grammed, the interval between writes to Register R0 must be an
integer multiple of MOD reference cycles.
Register R2 is selected with C3, C2, and C1 set to 0, 1, 0.
12-Bit Phase
The 12-bit phase word sets the seed value of the Σ-Δ modulator.
It can be programmed to any integer value from 0 to MOD, where
MOD is the modulus value that is programmed in Register R1,
Bits[DB14:DB3]. As the phase word is swept from 0 to MOD,
the phase of the VCO output sweeps over a 360° range in steps
of 360°/MOD.
To keep the outputs of two ADF4196-based synthesizers phase
coherent with each other (but not necessarily with the reference
they have in common), the write to Register R0 on both chips
must be performed during the same reference cycle. In this
case, the interval between the R0 writes does not need to be
an integer multiple of MOD cycles.
Note that the phase bits are double buffered; they do not take
effect until the load enable of the next write to R0 (the FRAC/INT
register). Thus, to change the phase of the VCO output frequency,
it is necessary to rewrite the INT and FRAC values to Register R0
following the write to Register R2.
Reserved Bit
Set the reserved bit, DB15, to 0.
Rev. B | Page 17 of 28
ADF4196
Data Sheet
FUNCTION REGISTER (R3) LATCH MAP
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
0
DB6
1
DB5
F3
DB4
1
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
C3 (0) C2 (1) C1 (1)
F1 PFD POLARITY
0
1
NEGATIVE
POSITIVE
F3 CPO GND
0
1
CPO/CPO GND
NORMAL
Figure 32. Bit Map for Register R3
R3, the function register, needs to be programmed only during
the initialization sequence (see Table 9).
PFD Polarity
Set the PFD polarity bit to 1 for positive polarity, and set it to 0
for negative polarity.
Control Bits
Register R3 is selected with C3, C2, and C1 set to 0, 1, 1.
Reserved Bits
Program the DB15 to DB6 reserved bits to a hexadecimal code of
0x001, and set the DB4 reserved bit to 1.
CPO GND
When the CPO GND bit is low, the charge pump outputs are
internally pulled to ground. This is invoked during the initiali-
zation sequence to discharge the loop filter capacitors. For
normal operation, this bit should be set to 1.
Rev. B | Page 18 of 28
Data Sheet
ADF4196
CHARGE PUMP REGISTER (R4) LATCH MAP
TIMER
SELECT
CONTROL
BITS
RESERVED
9-BIT TIMEOUT COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
C4
DB7
C3
DB6
C2
DB5
C1
DB4
F2
DB3
F1
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
C9
C8
C7
C6
C5
C3 (1) C2 (0) C1 (0)
F2 F1 TIMER SELECT
0
0
1
1
0
1
0
1
SW1/SW2
SW3
I
CP
NOT USED
1
C9
C8
C7
C3
C2
C1
TIMEOUT COUNTER xPFD CYCLES
DELAY µs
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
508
509
510
511
0
4
8
12
.
.
.
2032
2036
2040
2044
0
0.15
0.30
0.46
.
.
.
78.15
78.30
78.46
78.61
1
DELAY WITH 26MHz PFD
Figure 33. Bit Map for Register R4
Timer Select
R4, the charge pump register, is used for programming the timers
for loop filter switches. These switches help maintain the stability
of the loop filter after boosting the charge pump current.
The two timer select bits select the timeout counter that is to
be programmed. Note that setting up the ADF4196 for correct
operation requires setup of these three timeout counters: ICP,
SW1/SW2, and SW3. Therefore, three writes to this register
are required in the initialization sequence. Table 7 shows
example values for a GSM Tx synthesizer with a 60 kHz final
loop bandwidth. See the Applications Information section for
more information.
Control Bits
Register R4 is selected with C3, C2, and C1 (Bits[DB2:DB0]) set
to 1, 0, 0.
Reserved Bits
For normal operation, set the DB23 to DB14 reserved bits to
a hexadecimal code of 0x001.
Table 7. Recommended Values for a GSM Tx LO
Timer
Select
9-Bit Timeout Counter
Timeout
Counter
Time (µs) with
PFD = 13 MHz
Value
28
35
These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency; therefore, their time delay scales with the PFD
frequency according to the following equation:
10
01
00
ICP
SW3
SW1/SW2
8.6
10.8
10.8
35
On each write to R0, the timeout counters start. Switch SW3 closes
until the SW3 counter times out. Similarly, the SW1 and SW2
switches close until the SW1/SW2 counter times out. When the
Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)
For example, if 35 is loaded with timer select = 00, with
a 13 MHz PFD, SW1 and SW2 switch after the following:
I
CP counter times out, the charge pump current is ramped down
(35 × 4)/13 MHz = 10.8 µs
from 64× to 1× in six binary steps. It is recommended that the
SW1/SW2 and SW3 timeout counter values be set equal to the
ICP timeout counter value plus 7, as in the example shown in
Table 7.
Rev. B | Page 19 of 28
ADF4196
Data Sheet
POWER-DOWN REGISTER (R5) BIT MAP
PD
DIFF AMP
CONTROL
BITS
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
DB1
DB0
C3 (1) C2 (0) C1 (1)
F1
COUNTER RESET
0
1
NORMAL OPERATION
COUNTER RESET
CHARGE PUMP
F2 3-STATE
0
1
NORMAL OPERATION
3-STATE ENABLED
CHARGE PUMP
F3 POWER-DOWN
0
1
DISABLED
ENABLED
DIFF AMP
F5 F4 POWER-DOWN
0
1
0
1
DISABLED
ENABLED
Figure 34. Bit Map for Register R5
R5, the power-down register, can be used to power down the PLL
and differential amplifier sections. After power is initially applied,
Register R5 must be programmed to clear the power-down bits.
Then, before the ADF4196 comes out of power-down, the R2,
R1, and R0 registers must be programmed.
•
The charge pump is powered down with its outputs in
three-state mode.
•
•
•
•
The digital lock detect circuitry is reset.
The RFIN input is debiased.
The reference input buffer circuitry is disabled.
The serial interface remains active and capable of loading
and latching data.
Control Bits
Register R5 is selected with C3, C2, and C1 set to 1, 0, 1.
Power-Down Differential Amplifier
For normal operation, set Bit DB5 to 0, followed by a write to R0.
CP Three-State
When the DB7 and DB6 bits are set to 1, the differential
amplifier is put into power-down. When DB7 and DB6 are set
to 0, normal operation resumes.
When the CP three-state bit is set to 1, the charge pump outputs
enter three-state. Setting the CP three-state bit to 0 enables the
charge pump outputs.
Power-Down Charge Pump
Counter Reset
Setting Bit DB5 to 1 activates a charge pump power-down, and
the following events occur:
When the counter reset bit is set to 1, the counters are held in reset.
For normal operation, set this bit to 0, followed by a write to R0.
•
All active dc current paths are removed, except for the
differential amplifier.
•
The R and N divider counters are forced to their load state
conditions.
Rev. B | Page 20 of 28
Data Sheet
ADF4196
MUX REGISTER (R6) LATCH MAP AND TRUTH TABLE
SIGMA-DELTA
CONTROL
BITS
AND
RESERVED
MUX
OUT
LOCK DETECT MODES
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
0
DB7
1
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
DB1
DB0
M13
M12
M11
M10
0
0
0
C3 (1) C2 (1) C1 (0)
SIGMA-DELTA MODES
M13
0
M12
M11
M10
0
M4 M3 M2 M1 MUX
OUT
0
0
INIT STATE, DITHER OFF,
3ns LOCK DETECT THRESHOLD
DITHER ON
10ns LOCK DETECT THRESHOLD
RESERVED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3-STATE
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
LOGIC HIGH
R DIVIDER OUTPUT
RESERVED
SERIAL DATA OUTPUT
LOGIC LOW
R DIVIDER/2 OUTPUT
N DIVIDER/2 OUTPUT
RESERVED
0
1
0
0
1
0
1
1
ALL OTHER STATES
RESERVED
I
TIMEOUT SIGNAL
CP
SW1/SW2 TIMEOUT SIGNAL
SW3 TIMEOUT SIGNAL
RESERVED
Figure 35. Bit Map and MUXOUT Truth Table for Register R6
R6, the mux register, is used to program MUXOUT, as well as
Σ-Δ and lock detect modes.
Reserved Bits
For normal operation, the reserved bits (Bits[DB11:DB7]) must
be set to 00001.
Control Bits
Register R6 is selected with C3, C2, and C1 set to 1, 1, 0.
Σ-Δ and Lock Detect Modes
MUXOUT Modes
These bits control the on-chip multiplexer, Pin 16 (see Figure 35
for the truth table). This pin is useful for diagnosis because it
allows the user to look at various internal points of the chip,
such as the R divider and the INT divider outputs.
Bit DB15 to Bit DB12 are used to reconfigure certain PLL
operating modes. In the initialization sequence after power is
applied to the chip, the four bits must first be programmed to
all zeros. This initializes the PLL to a known state with dither
off in the Σ-Δ modulator and a 3 ns PFD error threshold in the
lock detect circuit.
In addition, it is possible to monitor the programmed timeout
counter intervals on MUXOUT. For example, if the ICP timeout
counter is programmed to 65 (with a 26 MHz PFD), then
following the next write to R0, a pulse width of 10 µs is
observed on the MUXOUT pin.
To turn on dither in the Σ-Δ modulator, an additional write should
be made to Register R6 to program Bits[DB15:DB12] = 0011.
However, for lowest noise operation, it is best to leave dither off.
Digital lock detect is available via the MUXOUT pin.
To change the lock detect threshold from 3 ns to 10 ns, perform
a separate write to R6 to program Bits[DB15:DB12] = 1001.
This separate write is needed for reliable lock detect operation
when the RF frequency is <2 GHz.
A write to R6 that programs Bits[DB15:DB12] = 0000 returns
operation to the default state with both dither off and a 3 ns
lock detect threshold.
Rev. B | Page 21 of 28
ADF4196
Data Sheet
PROGRAMMING THE ADF4196
The ADF4196 can synthesize output frequencies with a channel
step or resolution that is a fraction of the input reference fre-
quency. For a given input reference frequency and a desired
output frequency step, the first choice to make is the PFD
reference frequency and the MOD value. After these are chosen,
the desired output frequency channels are set by programming
the INT and FRAC values.
minimum allowed value of MOD is 50. The SDM is clocked at
the PFD reference rate (fPFD), which allows PLL output frequencies
to be synthesized at a channel step resolution of fPFD/MOD.
With dither turned off, the quantization noise from the Σ-Δ
modulator appears as fractional spurs. The interval between spurs
is fPFD/L, where L is the repeat length of the code sequence in
the digital Σ-Δ modulator. For the third-order modulator used
in the ADF4196, the repeat length depends on the value of
MOD, as shown in Table 8.
WORKED EXAMPLE
In this example of a GSM900 Rx system, the RF output frequencies
must be generated with channel steps of 200 kHz. A reference
frequency input (REFIN) of 104 MHz is available. The R divider
setting that determines the PFD reference is shown in Equation 3.
Table 8. Fractional Spurs with Dither Off
Repeat
Length
Condition (Dither Off)
Spur Interval
MOD Is Divisible by 2 but Not by 3 2 × MOD Channel step/2
MOD Is Divisible by 3 but Not by 2 3 × MOD Channel step/3
f
PFD = REFIN × [(1 + D)/(R × (1 + T))]
(3)
where:
MOD Is Divisible by 6
All Other Divisors
6 × MOD Channel step/6
MOD Channel step
REFIN is the input reference frequency.
D is the doubler enable bit (0 or 1).
R is the 4-bit R counter code (1 to 15).
T is the REF/2 bit (0 or 1).
With dither enabled, the repeat length is extended to 221 cycles,
regardless of the value of MOD, which makes the quantization
error spectrum look like broadband noise. This can degrade the
in-band phase noise at the PLL output by as much as 10 dB.
Therefore, for lowest noise, dither off is a better choice, particularly
when the final loop bandwidth is low enough to attenuate even
the lowest frequency fractional spur. The wide loop bandwidth
range that is available with the ADF4196 allows the use of dither
in most applications.
The maximum PFD reference frequency of 26 MHz is chosen,
and the following settings are programmed to give an R divider
value of 4:
•
•
•
Doubler enable = 0
R = 2
REF/2 = 1
Integer Boundary Spurs
Next, the modulus is chosen to allow fractional steps of 200 kHz:
Another mechanism for fractional spur creation involves
interactions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related
(which is the purpose of a fractional-N synthesizer), spur
sidebands appear on the VCO output spectrum at an offset
frequency that corresponds to the beat note or difference
frequency between an integer multiple of the reference and
the VCO frequency.
MOD = 26 MHz/200 kHz = 130
(4)
When the channel step is defined, Equation 5 shows how output
frequency channels are programmed.
RFOUT = [INT + (FRAC/MOD)] × fPFD
where:
RFOUT is the desired RF output frequency.
INT is the integer part of the division.
FRAC is the numerator part of the fractional division.
MOD is the modulus or denominator part of the fractional
division.
(5)
These spurs are attenuated by the loop filter and are more
noticeable on channels that are close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth (thus, the name integer boundary spurs).
Thus, the frequency channel at 962.4 MHz is synthesized by
programming the following values: INT = 37 and FRAC = 2.
The 8:1 loop bandwidth switching ratio of the ADF4196 makes
it possible to attenuate all spurs to sufficiently low levels for most
applications. The final loop bandwidth can be chosen to ensure
that all spurs are far enough out of band and meet the lock time
requirements with the 8× bandwidth boost.
SPUR MECHANISMS
The following sections describe the three different spur
mechanisms that arise with a fractional-N synthesizer and how
the ADF4196 can best be programmed to minimize them.
The programmable modulus and R divider of the ADF4196 can
also be used to avoid integer boundary channels. This option is
described in the Avoiding Integer Boundary Channels section.
Fractional Spurs
The fractional interpolator in the ADF4196 is a third-order, Σ-Δ
modulator (SDM) with a modulus MOD that is programmable
to any integer value from 13 to 4095. If dither is enabled, the
Rev. B | Page 22 of 28
Data Sheet
ADF4196
Reference Spurs
Two initialization sequences are available for the ADF4196:
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mechanism
is feedthrough of low levels of on-chip reference switching noise
out of the RFIN pins back to the VCO, resulting in reference
spur levels as high as −90 dBc. These spurs can be suppressed
below −110 dBc by inserting sufficient reverse isolation, for
example, through an RF buffer between the VCO and RFIN pins.
Also, take care in the printed circuit board (PCB) layout to ensure
that the VCO is well separated from the input reference to avoid
a possible feedthrough path on the board.
Initialization Sequence A and Initialization Sequence B. One or
the other must be selected. Initialization Sequence A consists of
Step 1 through Step 14 in Table 9, including Step 5A (but not
Step 5B). (For Initialization Sequence B, Step 5A is replaced by
Step 5B.) In Initialization Sequence A, the frequency hop starts
immediately after the rising edge of LE, whereas in Initialization
Sequence B, the ADF4196 waits 16 PFD cycles and then starts the
hop. Initialization Sequence B reduces the overshoot of a
frequency jump, but the start of a jump is delayed by 16 PFD
cycles. Figure 36 shows this phenomenon.
LE
POWER-UP INITIALIZATION
5.5
INITIALIZATION SEQUENCE A
After applying power to the ADF4196 for the first time, a 14-2530
sequence is recommended, as described in Table 9.
5.0
INITIALIZATION SEQUENCE B
The divider and timer settings used in the example in Table 9 are
for a DCS1800 Tx synthesizer with a 104 MHz REFIN frequency.
4.5
4.0
3.5
3.0
2.5
The ADF4196 powers up after Step 13 and locks to the pro-
grammed channel frequency after Step 14.
Table 9. Power-Up Initialization Sequence A and
Initialization Sequence B
Register/
Step1 Bits
Hex Code Description
1
2
R5 [7:0]
R3 [15:0]
0xFD
0x005B
Set all power-down bits.
PFD polarity = 1, ground
CPOUT+/CPOUT−
2.0
.
TIME (µs/DIV)
Wait
10 ms
Allow time for loop filter
capacitors to discharge.
Figure 36. Frequency Jumps for Initialization Sequence A and
Initialization Sequence B
3
4
R7 [15:0]
R6 [15:0]
0x0007
0x000E
Clear test modes.
Initialize PLL modes, digital
lock detect on MUXOUT
CHANGING THE FREQUENCY OF THE PLL AND THE
PHASE LOOKUP TABLE
.
5A
5B
R6 [15:0]
R6 [15:0]
0x900E
0x000E
10 ns lock detect threshold,
digital lock detect on MUXOUT
Add 16 PFD cycle delay after
LE before starting hop to next
frequency.
After the ADF4196 is initialized, only a write to Register R0 is
required to program a new output frequency. The N divider is
updated with the values of INT and FRAC on the next PFD cycle
following the LE edge that latches in the R0 word. However, the
settling time and spurious performance of the synthesizer can
be further optimized by modifying the R1 and R2 register settings
on a channel-by-channel basis. These settings are double buffered
by the write to R0. This means that, although the data is loaded
through the serial interface on the respective R1 and R2 write
cycles, the synthesizer is not updated with the new data until
the next write to Register R0.
.
6
7
8
9
R4 [23:0]
R4 [23:0]
R4 [23:0]
R2 [15:0]
R1 [23:0]
0x004464
0x00446C SW3 timer = 10.8 μs.
0x004394
0x00D2
0x520209 8/9 prescaler, doubler disabled,
R = 4, toggle FF on, MOD = 65.
0x480140 INT = 144, FRAC = 40 for
1880 MHz output frequency.
SW1/SW2 timer = 10.8 μs.
ICP timer = 8.6 μs.
Phase = 26.
10
11
12
R0 [23:0]
R3 [15:0]
Register R2 can be used to digitally adjust the phase of the VCO
output relative to the reference edge. The phase can be adjusted
over the full 360° range at RF with a resolution of 360°/MOD.
In most frequency synthesizer applications, the actual phase offset
of the VCO output with respect to the reference is unknown
and is irrelevant. In such applications, the phase adjustment
capability of R2 can, instead, be used to optimize the settling time
performance as described in the Phase Lookup Table section.
0x007B
PFD polarity = 1, release
CPOUT+/CPOUT−
Clear all power-down bits.
.
13
14
R5 [7:0]
R0 [23:0]
0x05
0x480140 INT = 144, FRAC = 40 for
1880 MHz output frequency.
1 Initialization Sequence A includes Step 5A and omits Step 5B; Initialization
Sequence B includes Step 5B and omits Step 5A.
Rev. B | Page 23 of 28
ADF4196
Data Sheet
Phase Lookup Table
Avoiding Integer Boundary Channels
The fast lock sequence of the ADF4196 is initiated after the
write to Register R0. The fast lock timers are programmed so
that after the PLL has settled into wide bandwidth mode, the
charge pump current is reduced and the loop filter resistor
switches are opened, which reduces the loop bandwidth. The
reference cycle on which these events occur is determined by
the values that are preprogrammed into the timeout counters.
When programming a new frequency, another option involves
a write to Register R1 to avoid integer boundary spurs. If the
integer boundary spur level is too high, the integer boundary
can be moved away from the desired channel by reprogramming
the R divider to select a different PFD frequency. For example,
if REFIN = 104 MHz and R = 4 for a 26 MHz PFD reference,
and MOD = 130 for 200 kHz steps, the frequency channel at
910.2 MHz has a 200 kHz integer boundary spur because it is
offset by 200 kHz from 35 × 26 MHz.
The phase locking plots of Figure 11 and Figure 14 show that
the lock time to final phase is dominated by the phase swing
that occurs when the bandwidth is reduced. When the PLL
settles to its final frequency and phase, in wide bandwidth
mode, this phase swing is the same regardless of the size of the
frequency jump of the synthesizer. The amplitude of the phase
swing is related to the current flowing through the loop filter
resistors on the PFD reference cycle that open the SW1 and
SW2 switches.
An alternative way to synthesize this channel is to set R = 5 for
a 20.8 MHz PFD reference and MOD = 104 for 200 kHz steps.
The 910.2 MHz channel becomes a 5 MHz offset from the nearest
integer multiple of 20.8 MHz, and the 5 MHz beat note spurs
are well attenuated by the loop. Setting the double buffered DB23
bit (Bit CP ADJ in Register R1) to 1 increases the charge pump
current by 25%, which compensates for the 25% increase in N
with the change to the 20.8 MHz PFD frequency. This maintains
constant loop dynamics and settling time performance for jumps
between the two PFD frequencies. Clear the CP ADJ bit when
returning to 26 MHz-based channels.
In an integer-N PLL, this current is zero when the PLL has
settled. In a fractional-N PLL, the current is zero, on average,
but it varies from one reference cycle to the next, depending
on the quantization error sequence output from the digital Σ-Δ
modulator. Because the Σ-Δ modulator is all digital logic, clocked
at the PFD reference rate for a given value of MOD, the actual
quantization error on any given reference cycle is determined
by the value of FRAC and the phase word with which the
modulator is seeded, following the write to R0.
The Register R1 settings that are required for integer boundary
spur avoidance are all double buffered and do not become active
on the chip until the next write to Register R0. Always ensure that
Register R0 is the last register written to when programming
a new frequency.
By choosing an appropriate value of phase corresponding to the
value of FRAC that is programmed on the next write to R0, the
size of the error current when the SW1 and SW2 switches are
opened can be minimized. Thus, the phase swing that occurs
when the bandwidth is reduced can be minimized.
Serial Interface Activity
The serial interface activity when programming the R2 or R1
register causes no noticeable disturbance to the synthesizer’s
settled phase or degradation in its frequency spectrum. Thus,
in a GSM application, serial interface activity can be performed
during the active part of the data burst. Because it takes only
10.2 µs to program the three registers (R2, R1, and R0) with the
6.5 MHz serial interface clock rate typically used, this program-
ming can also be performed during the previous guard period
with the LE edge to latch in the R0 data, delayed until it is time
to switch the frequency.
With dither off, the fractional spur pattern that is due to the
quantization noise of the SDM also depends on the phase word
with which the modulator is seeded. Tables of optimized FRAC
and phase values for popular SW1/SW2 and ICP timer settings can
be downloaded from the ADF4196 product page. If using a phase
table, first write the phase to double buffered Register R2, and
then write the INT and FRAC values to Register R0.
Rev. B | Page 24 of 28
Data Sheet
ADF4196
APPLICATIONS INFORMATION
LOCAL OSCILLATOR FOR A GSM BASE STATION
Timer Values for Tx
To comply with the GSM spectrum due to switching requirements,
the Tx synthesizer should not switch frequency until the PA output
power has ramped down by at least 50 dB. If it takes 10 µs to ramp
down to this level, only the last 20 µs of the 30 µs guard period is
available for the Tx synthesizer to lock to final frequency and phase.
Figure 37 shows the ADF4196 being used with a VCO to
produce the LO for a GSM1800 base station. For GSM, the
REFIN signal can be any integer multiple of 13 MHz, but the
main requirement is that the slew rate be at least 300 V/µs.
The 104 MHz, 5 dBm input sine wave shown in Figure 37
satisfies this requirement.
In fast lock mode, the Tx loop bandwidth is widened by a factor
of 8 to 480 kHz and, therefore, the PLL achieves frequency lock
for a jump across the entire band in <6 µs. After this, the PA
power can start to ramp up again, and the loop bandwidth can
be restored to the final value. With the ICP timer = 28, the charge
pump current reduction begins at ~8.6 µs. When the SW1, SW2,
and SW3 timers = 35, the current reaches its final value before
the loop filter switches open at ~10.8 µs.
Recommended parameters for the various GSM/DCS/PCS
synthesizers are listed in Table 10.
Table 10. Recommended Setup Parameters
GSM900
DCS1800/PCS1900
Parameter
Loop BW
PFD
Tx
Rx
Tx
Rx
60 kHz
13 MHz
65
40 kHz
26 MHz
130
60 kHz
13 MHz
65
40 kHz
13 MHz
65
With these timer values, the phase disturbance created when
the bandwidth is reduced settles back to its final value by 20 µs,
in time for the start of the active part of the GSM burst. If faster
phase settling is desired with the 60 kHz bandwidth setting, the
timer values can be reduced further but should not be brought
less than the 6 µs that is required to achieve frequency lock in
wide bandwidth mode.
MOD
Dither
Off
Off
Off
Off
Prescaler
ICP Timer
4/5
28
4/5
78
8/9
28
8/9
38
SW1, SW2,
35
85
35
45
SW3 Timers
VCO KV
18 MHz/V 18 MHz/V 38 MHz/V 38 MHz/V
Timer Values for Rx
Loop Bandwidth and PFD Frequency
The 40 kHz Rx loop bandwidth is increased by a factor of 8 to
approximately 320 kHz during fast lock. With the Rx timer values
shown in Table 10, the bandwidth is reduced after ~12 µs, which
allows sufficient time for the phase disturbance to settle back
before the start of the active part of the Rx time slot at 30 µs.
As in the Tx synthesizer case, faster Rx settling can be achieved by
reducing these timer values, their lower limit being determined
by the time it takes to achieve frequency lock in wide bandwidth
mode. In addition, the DCS and PCS Rx synthesizers have relaxed
800 kHz blocker specifications and, thus, can tolerate a wider
loop bandwidth, which allows correspondingly faster settling.
A 60 kHz loop bandwidth is narrow enough to attenuate the
PLL phase noise and spurs to the required level for a Tx low.
A 40 kHz bandwidth is necessary to meet the GSM900 Rx
synthesizer’s particularly tough phase noise and spur requirements
at 800 kHz offsets. To get the lowest spur levels at 800 kHz
offsets for Rx, the Σ-Δ modulator should be run at the highest over-
sampling rate possible. Therefore, for GSM900 Rx, a 26 MHz PFD
frequency is chosen, and MOD = 130 is required for 200 kHz steps.
Because this value of MOD is divisible by two, certain FRAC
channels have a 100 kHz fractional spur. This is attenuated by the
40 kHz loop filter and, therefore, is not a concern. However, the
60 kHz loop filter that is recommended for Tx has a closed-loop
response that peaks close to 100 kHz. Therefore, a 13 MHz PFD
with MOD = 65, which avoids the 100 kHz spur, is the best choice
for a Tx synthesizer.
VCO KV
In general, the VCO gain, KV, should be set as low as possible to
minimize the reference and integer boundary spur levels that arise
due to feedthrough mechanisms. When deciding on the optimum
VCO KV, a good choice is to allow 2 V to tune across the desired
band, centered on the available tuning range. With VP3 regulated
to 5.5 V 100 mV, the tuning range available is 2.8 V.
Dither
Dither off should be selected for the lowest rms phase error.
Prescaler
Loop Filter Components
The 8/9 prescaler should be selected for the DCS and PCS bands.
The 4/5 prescaler allows an N divider range low enough to cover
the GSM900 Tx and Rx bands with either a 13 MHz or 26 MHz
PFD frequency.
For good settling performance, it is important that capacitors
with low dielectric absorption be used in the loop filter. Ceramic
NPO C0G capacitors are a good choice for this application.
A 2% tolerance is recommended for loop filter capacitors and
1% for resistors. A 10% tolerance is adequate for the inductor, L1.
Rev. B | Page 25 of 28
ADF4196
Data Sheet
ADIsimPLL Support
Also available is a technical note (ADF4193-TN-001, ADF4193
Loop Filter Design Using ADIsimPLL) that outlines a loop filter
design procedure that takes full advantage of the new degree of
freedom in the filter design that the differential amplifier and
loop filter switches provide.
The ADF4193 loop filter design is supported on ADIsimPLL v2.7
or later. Example files for popular applications are available for
download from the ADF4193 and ADF4196 product pages.
10pF
100pF
18Ω 18Ω
RF OUT
5V
18Ω
+
10µF
3V
5.5V
100nF
+
10µF
100nF
100nF
100nF
100nF
20
100pF
24
15
8, 10, 13
7
32
SDV
DV
x
V 1
V 2
AV
V 3
P
DD
DD
P
P
DD
+
10µF
30
29
CP
OUT+
SW1
C1A
100pF
C2A
6
5
120pF
1.20nF
RF
RF
IN+
IN–
INTEGRATED
R1A1
820Ω
DIFFERENTIAL
AMPLIFIER
100nF
51Ω
R3
62Ω
3
2
R1A2
6.20kΩ
SW3
AIN+
100pF
R2
1.80kΩ
ADF4196
31
25
28
27
SW
AIN–
A
GND
L1
2.2mH
C3
470pF
Ct
30pF
OUT
R1B2
6.20kΩ
1nF
1nF
11
REF
LE
IN
CMR
1
SW2
51Ω
REFERENCE
104MHz, 5dBm
R1B1
820Ω
C2B
1.20nF
SIRENZA VCO190-1843T
38MHz/V
19
18
17
100nF
DATA
CLK
26
16
CP
OUT–
C1B
120pF
23
R
MUX
D
SET
OUT
1
R
SET
9
GND
2.40kΩ
D
D
2
LOCK DETECT OUT
12
21
GND
3
GND
SD
14
A
1
A
2
GND
GND
GND
4
22
Figure 37. LO for DCS1800 Tx Using the ADF4196
Rev. B | Page 26 of 28
Data Sheet
ADF4196
Blackfin ADSP-BF527 Interface
INTERFACING
Figure 39 shows the interface between the ADF4196 and the
Blackfin® ADSP-BF527 digital signal processor (DSP). The
ADF4196 needs a 24-bit serial word for each latch write. The
easiest way to accomplish this, when using the Blackfin family,
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
The ADF4196 has a simple SPI-compatible serial interface for
writing to the device. The CLK, DATA, and LE pins control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the input register on each rising edge of CLK are
latched into the appropriate register. See Figure 2 for the timing
diagram and Table 6 for the register address table.
The maximum allowable serial clock rate is 33 MHz.
Set up the word length for eight bits, and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer. Ensure that the clock speeds are
within the maximum limits that are outlined in Table 2.
ADuC70xx Interface
Figure 38 shows the interface between the ADF4196 and the
ADuC70xx family of analog microcontrollers. The ADuC70xx
family is based on an ARM7™ core, although the same interface
can be used with any 8051-based microcontroller. The micro-
controller is set up for SPI master mode with CPHA = 0. To
initiate the operation, the I/O port driving LE is brought low.
Each latch of the ADF4196 needs a 24-bit word. This is achieved
by writing three 8-bit bytes from the microcontroller to the device.
When the third byte is written, bring the LE input high to
complete the transfer.
ADSP-BF527
SCLK
ADF4196
CLK
MOSI
GPIO
DATA
LE
When power is first applied to the ADF4196, an initialization
sequence is required for the output to become active (see Table 9).
MUX
(LOCK DETECT)
I/O FLAGS
OUT
I/O port lines on the microcontroller are also used to detect lock
(MUXOUT configured as lock detect and polled by the port input).
Figure 39. ADSP-BF527-to-ADF4196 Interface
PCB DESIGN GUIDELINES
When operating in the SPI master mode, the maximum SPI transfer
rate of the ADuC7023, for example, is 20 Mbps. This means that
the maximum rate at which the output frequency can be changed
is 833 kHz. If using a faster SPI clock, ensure adherence to the
SPI timing requirements that are listed in Table 2.
The lands on the chip scale package (CP-32-2) are rectangular.
The printed circuit board (PCB) pad for these lands should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. To ensure that the solder joint size
is maximized, center the land on the pad.
ADuC70xx
ADF4196
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as the
exposed pad. To avoid shorting, provide a clearance on the PCB
of at least 0.25 mm between the thermal pad and the inner edges
of the pad pattern.
SPICLK
CLK
MOSI
DATA
LE
I/O PORTS
MUX
(LOCK DETECT)
OUT
Thermal vias can be used on the PCB thermal pad to improve the
thermal performance of the package. If vias are used, incorporate
them into the thermal pad at a 1.2 mm pitch grid. Provide a via
diameter between 0.3 mm and 0.33 mm, and plate the via barrel
with 1 oz copper to plug the via. Connect the PCB thermal pad
to AGND1 or AGND2.
Figure 38. ADuC70xx-to-ADF4196 Interface
Rev. B | Page 27 of 28
ADF4196
Data Sheet
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
32
1
24
0.50
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
0.30
0.25
0.18
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
Package Description
Package Option
ADF4196BCPZ
−40°C to +85°C
−40°C to +85°C
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
Evaluation Board (GSM1800)
Evaluation Board (No VCO or Loop Filter)
CP-32-2
CP-32-2
ADF4196BCPZ-RL7
EVAL-ADF4193EBZ1
EVAL-ADF4193EBZ2
1 Z = RoHS Compliant Part.
2 The EVAL-ADF4193EBZ1 and EVAL-ADF4193EBZ2 evaluation boards are designed to accommodate either the ADF4193 or the ADF4196.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09450-0-12/11(B)
Rev. B | Page 28 of 28
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