ADF4169CCPZ [ADI]
Direct Modulation/Fast Waveform Generating, Fractional-N Frequency Synthesizer;
| 型号： | ADF4169CCPZ |
| 厂家： | 
ADI |
| 描述： | Direct Modulation/Fast Waveform Generating, Fractional-N Frequency Synthesizer |
| 文件： | 总36页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Direct Modulation/Fast Waveform Generating,
13.5 GHz, Fractional-N Frequency Synthesizer
Data Sheet
ADF4169
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 13.5 GHz
High and low speed FMCW ramp generation
The ADF4169 is a 13.5 GHz, fractional-N frequency synthesizer
with modulation and both fast and slow waveform generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 130 MHz
capability. The device uses a 25-bit fixed modulus, allowing
subhertz frequency resolution.
Normalized phase noise floor of −224 dBc/Hz
FSK and PSK functions
Sawtooth and triangular waveform generation
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay, frequency readback, and interrupt functions
Programmable phase control
2.7 V to 3.45 V analog power supply
1.8 V to 2 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
ESD performance: 3000 V HBM, 1000 V CDM
Qualified for automotive applications
The ADF4169 consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. The Σ-Δ-based fractional interpolator allows
programmable fractional-N division. The INT and FRAC registers
define an overall N divider as N = INT + (FRAC/225).
The ADF4169 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. Frequency sweep
modes are also available to generate various waveforms in the
frequency domain, for example, sawtooth waveforms and
triangular waveforms. Sweeps can be set to run automatically
or with each step manually triggered by an external pulse. The
ADF4169 features cycle slip reduction (CSR) circuitry, which
enables faster lock times without the need for modifications to
the loop filter.
APPLICATIONS
Control of all on-chip registers is via a simple 3-wire interface. The
ADF4169 operates with an analog power supply in the range of
2.7 V to 3.45 V and a digital power supply in the range of 1.8 V
to 2 V. The device can be powered down when not in use.
FMCW radars
Communications test equipment
Communications infrastructure
FUNCTIONAL BLOCK DIAGRAM
AV
DV
SDV
V
R
SET
DD
DD
DD
P
ADF4169
SW2
CP
REFERENCE
×2
5-BIT
R COUNTER
REF
IN
DOUBLER
÷2
DIVIDER
+
PHASE
CHARGE
PUMP
FREQUENCY
DETECTOR
–
CSR
HIGH-Z
DGND
LOCK
DETECT
FAST LOCK
SWITCH
SW1
SERIAL DATA
OUTPUT
OUTPUT
MUX
MUXOUT
DV
DD
R DIVIDER/2
N DIVIDER/2
+
–
RF
RF
A
B
IN
N COUNTER
IN
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
CE
TX
DATA
CLK
DATA
LE
FRACTION MODULUS
25
INTEGER
VALUE
32-BIT
DATA
REGISTER
VALUE
2
VALUE
AGND
DGND
SDGND
CPGND
Figure 1.
Rev. 0
Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Technical Support
©2015 Analog Devices, Inc. All rights reserved.
www.analog.com
ADF4169
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Step Register (R6) Map.............................................................. 23
Delay Register (R7) Map ........................................................... 24
Applications Information .............................................................. 25
Initialization Sequence .............................................................. 25
RF Synthesizer Worked Example ............................................. 25
Reference Doubler...................................................................... 25
Cycle Slip Reduction for Faster Lock Times........................... 25
Modulation.................................................................................. 26
Waveform Generation ............................................................... 26
Waveform Deviations and Timing........................................... 27
Single Ramp Burst...................................................................... 27
Single Triangular Burst.............................................................. 27
Single Sawtooth Burst................................................................ 27
Continuous Sawtooth Ramp..................................................... 27
Continuous Triangular Ramp................................................... 27
FMCW Radar Ramp Settings Worked Example...................... 27
Activating the Ramp .................................................................. 28
Other Waveforms ....................................................................... 28
Ramp Complete Signal to MUXOUT ..................................... 31
External Control of Ramp Steps............................................... 31
Interrupt Modes and Frequency Readback ............................ 31
Fast Lock Mode .......................................................................... 33
Spur Mechanisms ....................................................................... 33
Filter Design Using ADIsimPLL............................................... 34
PCB Design Guidelines for the Chip Scale Package.............. 34
Application of the ADF4169 in FMCW Radar ...................... 35
Outline Dimensions....................................................................... 36
Ordering Guide .......................................................................... 36
Automotive Products................................................................. 36
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 10
Reference Input Section............................................................. 10
RF Input Stage............................................................................. 10
RF INT Divider........................................................................... 10
25-Bit Fixed Modulus ................................................................ 10
INT, FRAC, and R Counter Relationship................................ 10
R Counter .................................................................................... 10
Phase Frequency Detector and Charge Pump ........................... 11
MUXOUT and Lock Detect...................................................... 11
Input Shift Register..................................................................... 11
Program Modes .......................................................................... 11
Register Maps.................................................................................. 12
FRAC/INT Register (R0) Map.................................................. 14
LSB FRAC Register (R1) Map................................................... 15
R Divider Register (R2) Map .................................................... 16
Function Register (R3) Map...................................................... 18
Clock Register (R4) Map ........................................................... 20
Deviation Register (R5) Map .................................................... 22
REVISION HISTORY
7/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
Data Sheet
ADF4169
SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.9 V, AGND = DGND = SDGND = CPGND = 0 V, fPFD = 130 MHz, TA = TMIN to TMAX
,
dBm referred to 50 Ω, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency, RFIN
0.5
13.5
GHz
−10 dBm minimum to 0 dBm maximum; for
lower frequencies, ensure a slew rate ≥
400 V/μs
Prescaler Output Frequency
REFERENCE CHARACTERISTICS
REFIN Input Frequency
2
GHz
MHz
For higher frequencies, use 8/9 prescaler
10
10
260
−5 dBm minimum to +9 dBm maximum
biased at 1.9/2 (ac coupling ensures 1.9/2
bias); for frequencies < 10 MHz, use a dc-
coupled, CMOS-compatible square wave
with a slew rate > 25 V/μs
Reference Doubler Enabled
REFIN Input Capacitance
REFIN Input Current
50
1.2
100
MHz
pF
μA
Bit DB20 in Register R2 set to 1
PHASE FREQUENCY DETECTOR, PFD
2
Phase Detector Frequency, fPFD
130
MHz
CHARGE PUMP (CP)
ICP Sink/Source Current
High Value
Programmable
RSET = 5.1 kΩ
4.8
300
2.5
5.1
1
2
2
2
mA
μA
%
kΩ
nA
%
Low Value
Absolute Accuracy
RSET Range
RSET = 5.1 kΩ
4.59
5.61
ICP Three-State Leakage Current
Sink and Source Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Sink and source current
0.5 V < VCP < VP − 0.5 V
0.5 V < VCP < VP − 0.5 V
VCP = VP/2
%
%
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output Voltage High, VOH
Output Voltage Low, VOL
Output High Current, IOH
POWER SUPPLIES
AVDD
1.17
V
V
μA
pF
0.4
1
10
DVDD − 0.4
V
V
μA
CMOS output selected
IOL = 500 μA
0.3
100
2.7
1.8
2.7
3.45
2
3.45
40
12
7
V
V
V
mA
mA
mA
μA
DVDD, SDVDD
VP
AIDD
DIDD
26
7.5
5.5
2
Supply current drawn by AVDD; fPFD = 130 MHz
Supply current drawn by DVDD; fPFD = 130 MHz
Supply current drawn by VP; fPFD = 130 MHz
IP
Power-Down Mode
Rev. 0 | Page 3 of 36
ADF4169
Data Sheet
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor3
Phase-locked loop (PLL) bandwidth (BW) =
1 MHz
Integer-N Mode
Fractional-N Mode
Normalized 1/f Noise (PN1_f)4
−224
−217
−120
dBc/Hz
dBc/Hz
dBc/Hz
FRAC = 0; see Σ-Δ Modulator Mode section
Measured at 10 kHz offset, normalized
to 1 GHz
At the voltage controlled oscillator (VCO)
output
Phase Noise Performance5
12,002 MHz Output6
−96
dBc/Hz
At 50 kHz offset, 100 MHz PFD frequency
1 Operating temperature: −40°C to +125°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL™.
)
5 The phase noise performance is measured with a modified EV-ADF4159EB3Z evaluation board and the Rohde & Schwarz® FSUP signal source analyzer.
6 fREFIN = 100 MHz, fPFD = 100 MHz, offset frequency = 50 kHz, RFOUT = 12,002 MHz, N = 120.02, and loop bandwidth = 250 kHz.
TIMING SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.9 V, AGND = DGND = SDGND = CPGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
Limit at TMIN to TMAX
Unit
Description
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTRO BIT C1)
DB30
DATA
DB31 (MSB)
(CONTROL BIT C2)
L
t7
t1
LE
t6
Figure 2. Write Timing Diagram
Rev. 0 | Page 4 of 36
Data Sheet
ADF4169
Table 3. Read Timing
Parameter
Limit at TMIN to TMAX
Unit
Description
1
t1
tPFD + 20
20
25
25
10
ns min
ns min
ns min
ns min
ns min
TXDATA setup time
CLK setup time to data (on MUXOUT)
CLK high duration
CLK low duration
CLK to LE setup time
t2
t3
t4
t5
1 tPFD is the period of the PFD frequency; for example, if the PFD frequency is 50 MHz, tPFD = 20 ns.
Read Timing Diagram
TXDATA
t1
t3
t4
CLK
t2
DB2
DB1
DB36
DB35
MUXOUT
DB0
t5
LE
NOTES
1. DURING READBACK, KEEP LE HIGH.
Figure 3. Read Timing Diagram
I
500µA
OL
TO MUXOUT
PIN
0.9V
C
L
10pF
I
100µA
OH
Figure 4. Load Circuit for MUXOUT Timing, CL = 10 pF
Rev. 0 | Page 5 of 36
ADF4169
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = SDGND = CPGND =
0 V, unless otherwise noted.
THERMAL RESISTANCE
Thermal impedance (θJA) is specified for a device with the
exposed pad soldered to AGND.
Table 4.
Parameter
Rating
Table 5. Thermal Resistance
AVDD to GND
DVDD to GND
VP to GND
VP to AVDD
Digital Input/Output Voltage to GND
Analog Input/Output Voltage to GND
REFIN to GND
RFIN to GND
Operating Temperature Range,
Industrial
−0.3 V to +3.9 V
−0.3 V to +2.4 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +125°C
Package Type
θJA
Unit
24-Lead LFCSP_WQ
30.4
°C/W
ESD CAUTION
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
−65°C to +125°C
150°C
Peak Temperature
Time at Peak Temperature
ESD
260°C
40 sec
Charged Device Model (CDM)
Human Body Model (HBM)
1000 V
3000 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 6 of 36
Data Sheet
ADF4169
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 SDV
CPGND 1
DD
2
MUXOUT
LE
AGND
AGND 3
RF
17
16
15
14
ADF4169
TOP VIEW
(Not to Scale)
B
4
DATA
CLK
IN
RF A 5
IN
AV
6
13 CE
DD
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO AGND.
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This pin is the ground return path for the charge pump.
Analog Ground.
Complementary Input to the RF Prescaler. Decouple this pin to the ground plane with a small bypass capacitor,
typically 100 pF.
5
RFINA
AVDD
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Positive Power Supplies for the RF Section. Place decoupling capacitors to the ground plane as close as possible
to these pins.
6, 7, 8
9
REFIN
Reference Input. This CMOS input has a nominal threshold of DVDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10
11
12
DGND
SDGND
TXDATA
Digital Ground.
Digital Σ-Δ Modulator Ground. This pin is the ground return path for the Σ-Δ modulator.
Transmit Data Pin. This pin provides the transmitted data in FSK or PSK mode and also controls some ramping
functionality.
13
14
15
16
CE
Chip Enable (1.9 V Logic). A logic low on this pin powers down the device and places the charge pump output
into three-state mode.
Serial Clock Input. This input is used to clock in the serial data to the registers. The data is latched into the input
shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first; the three least significant bits (LSBs)
are the control bits. This input is a high impedance CMOS input.
Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight
latches; the latch is selected using the control bits. This input is a high impedance CMOS input.
CLK
DATA
LE
17
18
MUXOUT
SDVDD
Multiplexer Output. This pin allows various internal signals to be accessed externally.
Power Supply for the Digital Σ-Δ Modulator. Place decoupling capacitors to the ground plane as close as
possible to this pin.
19
DVDD
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close
as possible to this pin.
20, 21
22
SW1, SW2
VP
Fast Lock Switches.
Charge Pump Power Supply. The voltage on this pin must be greater than or equal to AVDD.
23
RSET
Reset. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The
relationship between ICP and RSET is as follows:
ICP_MAX = 24.48/RSET
where:
ICP_MAX = 4.8 mA.
RSET = 5.1 kΩ.
24
25
CP
Charge Pump Output. When the charge pump is enabled, this output provides ICP to the external loop filter,
which, in turn, drives the external VCO.
Exposed Pad. The LFCSP has an exposed pad that must be connected to AGND.
EPAD
Rev. 0 | Page 7 of 36
ADF4169
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–40
12.06
12.05
12.04
12.03
12.02
12.01
12.00
11.99
11.98
–60
–80
–100
–120
–140
–160
–180
100
1k
10k
100k
1M
10M
100M
0
20
40
60
80
100
FREQUENCY OFFSET (Hz)
TIME (µs)
Figure 6. Phase Noise at 12.002 GHz, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, Bleed Current = 11.03 µA
Figure 9. Sawtooth Burst, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
12.06
12.06
12.05
12.04
12.03
12.02
12.01
12.00
11.99
11.98
12.05
12.04
12.03
12.02
12.01
12.00
11.99
11.98
0
50
100
150
200
0
100
200
300
TIME (µs)
400
500
TIME (µs)
Figure 7. Sawtooth Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
Figure 10. Dual Sawtooth Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3; First Ramp: CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64; Second Ramp: CLK2 = 52,
DEV = 1024, DEV_OFFSET = 7, Number of Steps = 64
12.06
12.06
12.05
12.04
12.03
12.02
12.01
12.00
11.99
12.05
12.04
12.03
12.02
12.01
12.00
11.99
11.98
0
50
100
150
200
0
100
200
300
TIME (µs)
400
500
TIME (µs)
Figure 11. Triangle Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
Figure 8. Sawtooth Ramp with Delay, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64, Delay Word = 1000
Rev. 0 | Page 8 of 36
Data Sheet
ADF4169
12.06
12.05
12.04
12.03
12.02
12.01
12.00
12.014
12.012
12.010
12.008
12.006
12.004
12.002
12.000
11.998
11.996
11.994
11.99
0
50
100
150
200
0
100
200
300
TIME (µs)
400
500
TIME (µs)
Figure 12. Fast Ramp (Triangle Ramp with Different Slopes), fPFD = 100 MHz,
CP = 2.5 mA, Loop Bandwidth = 250 kHz, CLK1 = 3; Up Ramp: CLK2 = 26,
DEV = 1024, DEV_OFFSET = 8, Number of Steps = 64; Down Ramp: CLK2 = 70,
Figure 15. FSK Ramp, fPFD = 100 MHz, ICP = 2.5 mA, Loop Bandwidth = 250 kHz,
CLK1 = 3, CLK2 = 26, DEV = 1024, DEV_OFFSET = 8, Number of Steps = 64;
FSK: DEV = −512, DEV_OFFSET = 8
I
DEV = 16,384, DEV_OFFSET = 8, Number of Steps = 4
200
150
100
50
0
PRESCALER 8/9
PRESCALER 4/5
–5
–10
–15
–20
–25
–30
–35
–40
0
–50
–100
–150
–200
5
0
10
15
20
0
50
100
150
200
TIME (µs)
FREQUENCY (GHz)
Figure 13. Phase Shift Keying (PSK), Loop Bandwidth = 250 kHz,
Phase Value = 1024, Data Rate = 20 kHz
Figure 16. RFIN Sensitivity at Nominal Temperature
12.004
12.003
12.002
12.001
12.000
11.999
11.998
11.997
11.996
6
4
2
0
–2
–4
–6
0
50
100
150
200
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
TIME (µs)
V
CP
Figure 14. Frequency Shift Keying (FSK), Loop Bandwidth = 250 kHz,
DEV = 1049, DEV_OFFSET = 9, Data Rate = 20 kHz
Figure 17. Charge Pump Output Characteristics
Rev. 0 | Page 9 of 36
ADF4169
Data Sheet
THEORY OF OPERATION
REFERENCE INPUT SECTION
25-BIT FIXED MODULUS
Figure 18 shows the reference input stage. The SW1 and SW2
switches are normally closed (NC in Figure 18). The SW3
internal switch is normally open (NO in Figure 18). When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. In this way, no loading of the REFIN pin occurs during
power-down.
The ADF4169 has a 25-bit fixed modulus. This modulus allows
output frequencies to be spaced with a resolution of
f
RES = fPFD/225
(1)
where fPFD is the frequency of the phase frequency detector (PFD).
For example, with a PFD frequency of 100 MHz, frequency
steps of 2.98 Hz are possible. Due to the architecture of the Σ-Δ
modulator, there is a fixed +(fPFD/226) offset on the VCO output.
To remove this offset, see the Σ-Δ Modulator Mode section.
POWER-DOWN
CONTROL
100kΩ
NC
SW2
INT, FRAC, AND R COUNTER RELATIONSHIP
TO R COUNTER
REF
IN
NC
SW1
BUFFER
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the PFD frequency.
SW3
NO
Figure 18. Reference Input Stage
The RF VCO frequency (RFOUT) equation is
RF INPUT STAGE
RFOUT = (INT + (FRAC/225)) × fPFD
(2)
Figure 19 shows the RF input stage. The input stage is followed
by a two-stage limiting amplifier to generate the current-mode
logic (CML) clock levels required for the prescaler.
where:
RFOUT is the output frequency of the external VCO.
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
1.6V
BIAS
GENERATOR
FRAC is the numerator of the fractional division (0 to (225 − 1)).
AV
DD
The PFD frequency (fPFD) equation is
2kΩ
2kΩ
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
(3)
where:
RF
RF
A
B
IN
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference (R) counter (1 to 32).
IN
T is the REFIN divide by 2 bit (0 or 1).
R COUNTER
AGND
The 5-bit R counter allows the reference input (REFIN) frequency
to be divided down to supply the reference clock to the PFD.
Division ratios from 1 to 32 are allowed.
Figure 19. RF Input Stage
RF INT DIVIDER
The RF INT CMOS divider allows a division ratio in the PLL
feedback counter (see Figure 20). Division ratios from 23 to
4095 are allowed.
RF INT DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
VALUE
MOD
VALUE
FRAC
VALUE
Figure 20. RF INT Divider
Rev. 0 | Page 10 of 36
Data Sheet
ADF4169
PHASE FREQUENCY DETECTOR AND CHARGE PUMP
INPUT SHIFT REGISTER
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 21 shows a simplified sche-
matic of the PFD.
The ADF4169 digital section includes a 5-bit R counter, a 12-bit
INT counter, and a 25-bit FRAC counter. Data is clocked into the
32-bit input shift register on each rising edge of CLK. The data
is clocked in MSB first. Data is transferred from the input shift
register to one of eight latches on the rising edge of LE.
UP
HIGH
D1
Q1
The destination latch is determined by the state of the three
control bits (C3, C2, and C1) in the input shift register. As shown
in Figure 2, the control bits are the three LSBs (DB2, DB1, and
DB0, respectively). Table 7 shows the truth table for these bits.
Figure 23 and Figure 24 provide a summary of how the latches
are programmed.
U1
CLR1
+IN
CHARGE
PUMP
CP
DELAY
DOWN
U3
Table 7. Truth Table for the C3, C2, and C1 Control Bits
CLR2
D2 Q2
HIGH
–IN
Control Bits
U2
C3
0
C2
0
C1
0
Register
R0
Figure 21. PFD Simplified Schematic
0
0
1
R1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
R2
R3
R4
R5
R6
R7
The PFD includes a fixed delay element that sets the width of the
antibacklash pulse, which is typically 1 ns. This pulse ensures that
there is no dead zone in the PFD transfer function and gives a
consistent reference spur level.
MUXOUT AND LOCK DETECT
The multiplexer output on the ADF4169 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M4, M3, M2, and M1 bits in
Register R0 (see Figure 25). Figure 22 shows the MUXOUT
section in block diagram form.
PROGRAM MODES
Table 7 and Figure 25 through Figure 32 show how the program
modes are set up in the ADF4169.
The following settings in the ADF4169 are double buffered:
LSB fractional value, phase value, charge pump current setting,
reference divide by 2, reference doubler, R counter value, and
CLK1 divider value. Before the device uses a new value for any
double-buffered setting, the following two events must occur:
DV
DD
THREE-STATE OUTPUT
DV
DD
DGND
R DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
R DIVIDER/2
1. The new value is latched into the device by writing to the
appropriate register.
2. A new write is performed to Register 0 (R0).
CONTROL
MUXOUT
MUX
For example, updating the fractional value involves a write to
the 13 LSB bits in Register R1 and the 12 MSB bits in Register R0.
Register R1 must be written to first, followed by the write to R0.
The frequency change begins after the write to Register R0.
Double buffering ensures that the bits written to Register R1 do
not take effect until after the write to Register R0.
N DIVIDER/2
DGND
READBACK TO MUXOUT
Figure 22. MUXOUT Schematic
Rev. 0 | Page 11 of 36
ADF4169
Data Sheet
REGISTER MAPS
FRAC/INT REGISTER (R0)
MUXOUT
CONTROL
12-BIT MSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
12-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R1
M4 M3 M2 M1 N12 N11 N10 N9
N8
N7
N6
N5
N4
N3
N2
N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
LSB FRAC REGISTER (R1)
DBB
DBB
13-BIT LSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
12-BIT PHASE VALUE
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P1 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(0) C1(1)
0
0
0
R DIVIDER REGISTER (R2)
DBB
DBB
DBB
CP
CURRENT
SETTING
RESERVED
5-BIT R COUNTER
CONTROL
BITS
12-BIT CLK DIVIDER VALUE
1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
CR1 CPI4 CPI3 CPI2 CPI1
0
P1
U2
U1
R5
R4
R3
R2
R1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 C3(0) C2(1) C1(0)
FUNCTION REGISTER (R3)
NEG BLEED
CURRENT
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
NB3 NB2 NB1 L1 NS1 U12 RM2 RM1 U11 U10 U9 U8 U7 C3(0) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 23. Register Summary 1
Rev. 0 | Page 12 of 36
Data Sheet
ADF4169
CLOCK REGISTER (R4)
CLK
DIV
MODE
Σ-Δ
MODULATOR MODE
RAMP
STATUS
CONTROL
BITS
12-BIT CLK DIVIDER VALUE
2
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LS1 S5
S4
S3
S2
S1
R5
R4
R3
R2
R1
C2
C1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 CS1
0
0
C3(1) C2(0) C1(0)
0
DEVIATION REGISTER (R5)
4-BIT DEVIATION
OFFSET WORD
CONTROL
BITS
16-BIT DEVIATION WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
TR1
0
I2
I1
0
0
DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 C3(1) C2(0) C1(1)
STEP REGISTER (R6)
CONTROL
BITS
20-BIT STEP WORD
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
SSE1 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9
S8
S7
S6
S5
S4
S3
S2
S1 C3(1) C2(1) C1(0)
DELAY REGISTER (R7)
CONTROL
BITS
RESERVED
12-BIT DELAY START WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
TD1 ST1 TR1 FR1
0
RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 C3(1) C2(1) C1(1)
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 24. Register Summary 2
Rev. 0 | Page 13 of 36
ADF4169
Data Sheet
12-Bit Integer Value (INT)
FRAC/INT REGISTER (R0) MAP
Bits DB[26:15] set the INT value, which forms part of the overall
feedback division factor. For more information, see the INT,
FRAC, and R Counter Relationship section.
When Bits DB[2:0] are set to 000, the on-chip FRAC/INT
register (Register R0) is programmed (see Figure 25).
Ramp On
12-Bit MSB Fractional Value (FRAC)
When Bit DB31 is set to 1, the ramp function is enabled. When
Bit DB31 is set to 0, the ramp function is disabled.
Bits DB[14:3], along with Bits DB[27:15] in the LSB FRAC register
(Register R1), set the FRAC value that is loaded into the fractional
interpolator. The FRAC value forms part of the overall feedback
division factor. These 12 bits are the MSBs of the 25-bit FRAC
value; Bits DB[27:15] in the LSB FRAC register (Register R1) are
the LSBs. For more information, see the RF Synthesizer Worked
Example section.
MUXOUT Control
The on-chip multiplexer of the ADF4169 is controlled by
Bits DB[30:27]. See Figure 25 for the truth table.
MUXOUT
12-BIT MSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
12-BIT INTEGER VALUE (INT)
CONTROL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
MSB FRACTIONAL VALUE
R1 RAMP ON
M4 M3 M2 M1
OUTPUT
THREE-STATE OUTPUT
DV
F25 F24
... F15 F14
(FRAC)*
0
1
RAMP DISABLED
RAMP ENABLED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
DD
1
DGND
2
R DIVIDER OUTPUT
RESERVED
3
.
RESERVED
.
.
.
.
.
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
RESERVED
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
RESERVED
CLK DIVIDER OUTPUT
RESERVED
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R0 AND THE 13-BIT LSB STORED IN REGISTER R1.
RESERVED
R DIVIDER/2
13
FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2
.
N DIVIDER/2
READBACK TO MUXOUT
N12
N11
N10
N9
0
0
0
0
.
N8
0
0
0
0
.
N7
0
0
0
0
.
N6
N5
1
1
1
1
.
N4
0
1
1
1
.
N3
1
0
0
0
.
N2
1
0
0
1
.
N1
1
0
1
0
.
INTEGER VALUE (INT)
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
23
24
25
26
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
4093
4094
4095
Figure 25. FRAC/INT Register (R0) Map
Rev. 0 | Page 14 of 36
Data Sheet
ADF4169
These 13 bits are the LSBs of the 25-bit FRAC value; Bits DB[14:3]
in the FRAC/INT register (Register R0) are the MSBs. For more
information, see the RF Synthesizer Worked Example section.
LSB FRAC REGISTER (R1) MAP
When Bits DB[2:0] are set to 001, the on-chip LSB FRAC
register (Register R1) is programmed (see Figure 26).
12-Bit Phase Value
Reserved Bits
Bits DB[14:3] control the phase word. The phase word is used
to increase the RF output phase relative to the current phase.
The phase change occurs after a write to Register R0.
All reserved bits must be set to 0 for normal operation.
Phase Adjustment
Bit DB28 enables and disables phase adjustment. The phase
shift is generated by the value programmed in Bits DB[14:3].
Phase Shift = (Phase Value × 360°)/212
For example, Phase Value = 512 increases the phase by 45°.
13-Bit LSB Fractional Value (FRAC)
To use phase adjustment, Bit DB28 must be set to 1. When
phase adjustment is not used, set the phase value to 0.
Bits DB[27:15], along with Bits DB[14:3] in the FRAC/INT
register (Register R0), set the FRAC value that is loaded into
the fractional interpolator. The FRAC value forms part of the
overall feedback division factor.
DBB
DBB
13-BIT LSB FRACTIONAL VALUE
CONTROL
RESERVED
(FRAC)
12-BIT PHASE VALUE
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
P1 F13 F12 F11 F10 F9
F8
F7
F6
F5
F4
F3
F2
F1 P12 P11 P10 P9
P8
P7
P6
P5
P4
P3
P2
P1 C3(0) C2(0) C1(1)
LSB FRACTIONAL VALUE
(FRAC)*
F13 F12
...
F2
F1
P12
0
.
P11
1
.
...
P2
1
.
P1
1
.
PHASE VALUE
P1 PHASE ADJUST
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
...
...
...
...
...
...
...
...
...
...
...
2047
0
1
DISABLED
ENABLED
1
.
2
0
0
0
0
1
1
1
.
0
0
0
0
1
1
1
.
1
1
0
0
1
1
0
.
1
0
1
0
1
0
1
.
3
2
1
3
.
.
.
.
.
.
0 (RECOMMENDED)
.
.
.
.
.
–1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
–2
–3
.
1
0
0
0
–2048
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R0 AND THE 13-BIT LSB STORED IN REGISTER R1.
13
FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2
.
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 26. LSB FRAC Register (R1) Map
Rev. 0 | Page 15 of 36
ADF4169
Data Sheet
RDIV2
R DIVIDER REGISTER (R2) MAP
When Bit DB21 is set to 1, the R divider is enabled and a divide
by 2 toggle flip-flop is inserted between the R counter and the
PFD. This feature provide a 50% duty cycle signal at the PFD.
When Bits DB[2:0] are set to 010, the on-chip R divider register
(Register R2) is programmed (see Figure 27).
Reserved Bits
Reference Doubler
All reserved bits must be set to 0 for normal operation.
When Bit DB20 is set to 0, the reference doubler is disabled,
and the REFIN signal is fed directly to the 5-bit R counter. When
Bit DB20 is set to 1, the reference doubler is enabled, and the REFIN
frequency is multiplied by a factor of 2 before the signal is fed into
the 5-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
CSR Enable
When Bit DB28 is set to 1, cycle slip reduction (CSR) is enabled.
CSR is a method for improving lock times. Note that the signal
at the PFD must have a 50% duty cycle for CSR to work. In
addition, the charge pump current setting must be set to its
minimum value. For more information, see the Cycle Slip
Reduction for Faster Lock Times section.
The CSR feature can be used only when the phase detector
polarity setting is positive (Bit DB6 = 1 in Register R3). CSR
cannot be used if the phase detector polarity setting is negative
(Bit DB6 = 0 in Register R3).
When the reference doubler is enabled, for optimum phase noise
performance, it is recommended to only use charge pump
current settings 0b0000 to 0b0111, that is, 0.31 mA to 2.5 mA.
In this case, best practice is to design the loop filter for a charge
pump current of 1.25 mA or 1.57 mA and then use the
programmable charge pump current to tweak the frequency
response.
Charge Pump (CP) Current Setting
Bits DB[27:24] set the charge pump current (see Figure 27).
Set these bits to the charge pump current that the loop filter
is designed with. Best practice is to design the loop filter for a
charge pump current of 2.5 mA or 2.81 mA and then use the
programmable charge pump current to tweak the frequency
response. See the Reference Doubler section for information on
setting the charge pump current when the doubler is enabled.
For more information on using the reference doubler, see the
Clock Register (R4) Map section.
5-Bit R Counter
The 5-bit R counter (Bits DB[19:15]) allows the input reference
frequency (REFIN) to be divided down to supply the reference
clock to the PFD. Division ratios from 1 to 32 are allowed.
Prescaler
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and fixed modulus values, determines the overall
division ratio from RFIN to the PFD input. Bit DB22 sets the
prescaler value.
12-Bit CLK1 Divider Value
Bits DB[14:3] program the CLK1 divider value, which determines
the duration of the time step in ramp mode.
Operating at CML levels, the prescaler takes the clock from the
RF input stage and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 8 GHz. Therefore,
when operating the ADF4169 at frequencies greater than 8 GHz,
the prescaler must be set to 8/9. The prescaler limits the INT
value as follows:
•
•
Prescaler = 4/5: NMIN = 23
Prescaler = 8/9: NMIN = 75
Rev. 0 | Page 16 of 36
Data Sheet
ADF4169
DBB
DBB
5-BIT R COUNTER
DBB
CP
CONTROL
BITS
RESERVED
CURRENT (I
SETTING
)
12-BIT CLK DIVIDER VALUE
1
CP
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
CR1 CPI4 CPI3 CPI2 CPI1
0
P1
U2
U1
R5
R4
R3
R2
R1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 C3(0) C2(1) C1(0)
REFERENCE
DOUBLER
U1
CYCLE SLIP
REDUCTION
CR1
D12 D11 ...
D2 D1
CLK DIVIDER VALUE
1
0
1
DISABLED
ENABLED
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
0
1
DISABLED
ENABLED
1
2
3
U2
0
R DIVIDER
DISABLED
ENABLED
.
.
.
.
.
.
.
.
.
.
.
1
I
(mA)
CP
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
CPI4
CPI3
CPI2
CPI1
5.1kΩ
P1
0
PRESCALER
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31
0.63
0.94
1.25
1.57
1.88
2.19
2.5
4/5
8/9
1
R5
0
0
0
0
.
R4
0
0
0
0
.
R3
0
0
0
1
.
R2
0
1
1
0
.
R1
1
0
1
0
.
R COUNTER DIVIDE RATIO
1
2
3
4
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.0
.
.
.
.
.
.
.
.
.
.
1
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
29
30
31
32
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 27. R Divider Register (R2) Map
Rev. 0 | Page 17 of 36
ADF4169
Data Sheet
Σ-Δ Reset
FUNCTION REGISTER (R3) MAP
For most applications, Bit DB14 is set to 0. When this bit is set to 0,
the Σ-Δ modulator is reset on each write to Register R0. If it is
not required that the Σ-Δ modulator be reset on each write to
Register R0, set this bit to 1.
When Bits DB[2:0] are set to 011, the on-chip function register
(Register R3) is programmed (see Figure 28).
Reserved Bits
All reserved bits except Bit DB17 must be set to 0 for normal
operation. Bit DB17 must be set to 1 for normal operation.
Ramp Mode
Bits DB[11:10] determine the type of generated waveform (see
Figure 28 and the Waveform Generation section).
Negative Bleed Current
Bits DB[24:22] set the negative bleed current value (IBLEED).
Calculate IBLEED using the following formula, and then select the
value of Bits DB[24:22] that is closest to the calculated value.
PSK Enable
When Bit DB9 is set to 1, PSK modulation is enabled. When this bit
is set to 0, PSK modulation is disabled. For more information, see
the Phase Shift Keying section.
I
BLEED = (4 × ICP)/N
where:
CP is the charge pump current.
FSK Enable
I
When Bit DB8 is set to 1, FSK modulation is enabled. When this bit
is set to 0, FSK modulation is disabled. For more information, see
the Frequency Shift Keying section.
N is the N counter value.
Negative Bleed Current Enable
DB21 enables a negative bleed current in the charge pump. When
the charge pump is operating in a nonlinear region, phase noise
and spurious performance can degrade. Negative bleed current
operates by pushing the charge pump operation region away from
this nonlinear region. The programmability feature controls how
far the region of operation is moved. If the current is too little,
the charge pump remains in the nonlinear region; if the current
is too high, the charge pump becomes unstable or degrades the
maximum PFD frequency. It is necessary to experiment with
various charge pump currents to find the optimum performance.
Lock Detect Precision (LDP)
The digital lock detect circuit monitors the PFD up and down
pulses (logical OR of the up and down pulses; see Figure 21).
Every 32nd pulse is measured. The LDP bit (Bit DB7) specifies
the length of each lock detect reference cycle.
•
LDP = 0: if five consecutive pulses of less than 14 ns are
measured, digital lock detect is asserted.
•
LDP = 1: if five consecutive pulses of less than 6 ns are
measured, digital lock detect is asserted.
The formula for calculating the optimum negative bleed current
is shown in the Negative Bleed Current section; however, exper-
imentation may show a different current gives the optimum result.
Digital lock detect remains asserted until the pulse width exceeds
22 ns, a write to Register R0 occurs, or the device is powered down.
For more robust operation, set LDP = 1.
Loss of Lock (LOL)
Phase Detector (PD) Polarity
Bit DB16 enables or disables the loss of lock indication. When
this bit is set to 0, the device indicates loss of lock even when
the reference is removed. This feature provides an advantage
over the standard implementation of lock detect. For more
robust operation, set this bit to 1. The loss of lock does not
operate as expected when negative bleed current is enabled.
Bit DB6 sets the phase detector polarity. When the VCO
characteristics are positive, set this bit to 1. When the VCO
characteristics are negative, set this bit to 0.
Power-Down
Bit DB5 provides the programmable power-down mode. Setting
this bit to 1 performs a power-down. Setting this bit to 0 returns
the synthesizer to normal operation. When the device is in software
power-down mode, it retains all information in its registers. The
register contents are lost only when the supplies are removed.
N SEL
Bit DB15 can be used to circumvent the issue of pipeline delay
between updates of the integer and fractional values in the
N counter. Typically, the INT value is loaded first, followed by
the FRAC value. This order can cause the N counter value to be
incorrect for a brief period of time equal to the pipeline delay
(about four PFD cycles). This delay has no effect if the INT value
was not updated. However, if the INT value has changed, this
incorrect N counter value can cause the PLL to overshoot in
frequency while it tries to lock to the temporarily incorrect
N counter value. After the correct fractional value is loaded,
the PLL quickly locks to the correct frequency. Introducing an
additional delay to the loading of the INT value using the N SEL bit
causes the INT and FRAC values to be loaded at the same time,
preventing frequency overshoot. The delay is turned on by setting
Bit DB15 to 1.
When power-down is activated, the following events occur:
•
•
All active dc current paths are removed.
The RF synthesizer counters are forced to their load state
conditions.
•
•
•
•
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RFIN input is debiased.
The input shift register remains active and capable of
loading and latching data.
Rev. 0 | Page 18 of 36
Data Sheet
ADF4169
Charge Pump Three-State
RF Counter Reset
When Bit DB4 is set to 1, the charge pump is placed into three-
state mode. For normal charge pump operation, set this bit to 0.
Bit DB3 is the RF counter reset bit. When this bit is set to 1, the
RF synthesizer counters are held in reset. For normal operation,
set this bit to 0.
NEG BLEED
CURRENT
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
NB3 NB2 NB1
0
0
0
0
1
L1 NS1 U12
0
0
RM2 RM1
0
0
U11 U10 U9
U8
U7 C3(0) C2(1) C1(1)
RF COUNTER
U7 RESET
0
1
DISABLED
ENABLED
0
NEG BLEED
U12 Σ-Δ RESET
CURRENT ENABLE
0
1
ENABLED
DISABLED
0
1
DISABLED
L1 LOL
ENABLED
CP
0
1
ENABLED
DISABLED
U8
THREE-STATE
0
1
DISABLED
ENABLED
NS1
0
N SEL
N WORD LOAD ON Σ-Δ CLOCK
N WORD LOAD DELAYED 4 CYCLES
U9
0
POWER-DOWN
DISABLED
1
1
ENABLED
NB3 NB2 NB1 NEGATIVE BLEED CURRENT (µA)
0
0
0
0
0
0
1
1
0
1
0
1
3.73
RM2 RM1 RAMP MODE
U10
0
PD POLARITY
NEGATIVE
POSITIVE
11.03
25.25
53.1
0
0
1
1
0
1
0
1
CONTINUOUS SAWTOOTH
CONTINUOUS TRIANGULAR
SINGLE SAWTOOTH BURST
SINGLE RAMP BURST
1
109.7
224.7
454.7
916.4
1
1
0
0
0
1
U11 LDP (ns)
0
1
14
6
1
1
1
1
0
1
0
0
1
FSK
DISABLED
ENABLED
0
0
1
PSK
DISABLED
ENABLED
Figure 28. Function Register (R3) Map
Rev. 0 | Page 19 of 36
ADF4169
Data Sheet
Ramp Status
CLOCK REGISTER (R4) MAP
Bits DB[25:21] provide access to the following advanced
features (see Figure 29):
When Bits DB[2:0] are set to 100, the on-chip clock register
(Register R4) is programmed (see Figure 29).
•
Readback to MUXOUT option: the synthesizer frequency
at the moment of interruption can be read back (see the
Interrupt Modes and Frequency Readback section).
Ramp complete to MUXOUT option: a logic high pulse is
output on the MUXOUT pin at the end of each ramp.
Charge pump up and charge pump down options: the
charge pump is forced to constantly output up or down
pulses, respectively.
If the reference doubler (R2, DB20) is enabled, the last write to
R4 must have the ramp status (DB[25:21]) set to 0b11000.
To use the ramp complete to MUXOUT ramp status with the
reference doubler enabled, two writes to R4 are required:
•
•
1. Program Register R4 with the ramp status = 0b00011,
followed by Step 2
2. Program Register R4 with the ramp status = 0b11000.
LE SEL
When using the readback to MUXOUT or ramp complete
to MUXOUT option, the MUXOUT control bits in Register R0
(Bits DB[30:27]) must be set to 1111.
In some applications, it is necessary to synchronize the LE pin
with the reference signal. To do this, Bit DB31 must be set to 1.
Synchronization is performed internally on the device.
Clock Divider Mode
Σ-Δ Modulator Mode
Bits DB[20:19] enable ramp divider mode or fast lock divider
mode. If neither is being used, set these bits to 0b00.
To completely disable the Σ-Δ modulator, set Bits DB[30:26]
to 0b01110, which disables the Σ-Δ modulator and puts the
ADF4169 into integer-N mode, and the channel spacing
becomes equal to the PFD frequency. Both the 12-bit MSB
fractional value (Register R0, DB[14:3]) and the 13-bit LSB
fractional value (Register R1, DB[27:15]) must be set to 0. After
writing to Register R4, Register R3 must be written to twice, to
trigger an RF counter reset. (That is, write Register R3 with
Bit DB3 = 1, then write Register R3 with Bit DB3 = 0.)
12-Bit CLK2 Divider Value
Bits DB[18:7] program the clock divider (the CLK2 timer) when
the device operates in ramp mode (see the Timeout Interval
section). The CLK2 timer also determines how long the loop
remains in wideband mode when fast lock mode is used (see
the Fast Lock Mode section).
Clock Divider Select
All features driven by the Σ-Δ modulator are disabled, such as
ramping, PSK, FSK, and phase adjust.
Disabling the Σ-Δ modulator also removes the fixed +(fPFD/226)
offset on the VCO output.
When Bit DB6 is set to 0, CLK2 is used as the CLK2 value for a
standard ramp, such as sawtooth or triangular. When Bit DB6 is
set to 1, CLK2 is used as the CLK2 value for the second ramp of
the fast ramp or dual ramp functions. For more information,
see the Waveform Deviations and Timing section.
For normal operation, set these bits to 0b00000.
Reserved Bits
All reserved bits (DB[5:3]) must be set to 0 for normal operation.
Rev. 0 | Page 20 of 36
Data Sheet
ADF4169
CLK
DIV
MODE
Σ-Δ
MODULATOR MODE
CONTROL
BITS
RAMP STATUS
12-BIT CLK DIVIDER VALUE
RESERVED
2
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(1) C2(0) C1(0)
0
0
0
CS1
LS1 S5
S4
S3
S2
S1
R5
R4
R3
R2
R1
C2
C1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
CS1 CLK DIV SEL
S5 S4 S3 S2 S1 Σ-Δ MODULATOR MODE
0
1
LOAD CLK DIV 1
2
0
0
0
1
0
1
0
1
0
0
NORMAL OPERATION
DISABLED WHEN FRAC = 0
LOAD CLK DIV 2
2
R5 R4 R3 R2 R1
RAMP STATUS
D12 D11
...
D2
D1
CLK DIVIDER VALUE
2
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
NORMAL OPERATION
READBACK TO MUXOUT
RAMP COMPLETE TO MUXOUT
CHARGE PUMP UP
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
1
2
3
CHARGE PUMP DOWN
.
.
.
.
.
.
.
.
.
.
.
C2
C1
CLOCK DIVIDER MODE
LS1
0
LE SEL
LE FROM PIN
LE SYNCH WITH REF
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
0
0
1
1
0
1
0
1
CLOCK DIVIDER OFF
FAST LOCK DIVIDER
RESERVED
1
IN
RAMP DIVIDER
Figure 29. Clock Register (R4) Map
Rev. 0 | Page 21 of 36
ADF4169
Data Sheet
FSK Ramp Enable
DEVIATION REGISTER (R5) MAP
When Bit DB25 is set to 1, the FSK ramp is enabled. When
Bit DB25 is set to 0, the FSK ramp is disabled.
When Bits DB[2:0] are set to 101, the on-chip deviation register
(Register R5) is programmed (see Figure 30).
Dual Ramp Enable
Reserved Bit
When Bit DB24 is set to 1, the second ramp is enabled. When
Bit DB24 is set to 0, the second ramp is disabled.
The reserved bit must be set to 0 for normal operation.
TXDATA Invert
Deviation Select (DEV SEL)
When Bit DB30 is set to 0, events triggered by TXDATA occur on
the rising edge of the TXDATA pulse. When Bit DB30 is set to 1,
events triggered by TXDATA occur on the falling edge of the
TXDATA pulse.
When Bit DB23 is set to 0, the first deviation word is selected.
When Bit DB23 is set to 1, the second deviation word is selected.
4-Bit Deviation Offset Word
TXDATA Ramp Clock (CLK)
Bits DB[22:19] determine the deviation offset word (DEV_OFFSET).
The deviation offset word affects the deviation resolution.
When Bit DB29 is set to 0, the clock divider clock is used to
clock the ramp. When Bit DB29 is set to 1, the TXDATA clock
is used to clock the ramp.
16-Bit Deviation Word
Bits DB[18:3] determine the signed deviation word. The deviation
word defines the deviation step.
Interrupt
Bits DB[27:26] determine which type of interrupt is used. This
feature is used for reading back the INT and FRAC value of a
ramp at a given moment in time (a rising edge on the TXDATA pin
triggers the interrupt). From the INT and FRAC bits, the frequency
can be obtained. After readback, the sweep can continue or stop at
the readback frequency. For more information, see the Interrupt
Modes and Frequency Readback section.
4-BIT DEVIATION
OFFSET WORD
CONTROL
BITS
16-BIT DEVIATION WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D4
D3
0
0
TR1
0
I2
I1
0
0
DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D1 C3(1) C2(0) C1(1)
D2
0
DUAL RAMP
DS1 DEV SEL
ENABLE
0
TXDATA INVERT
0
DEV WORD 1
0
1
DISABLED
ENABLED
0
1
DISABLED
ENABLED
1
DEV WORD 2
D16
D15
...
D2
D1
DEVIATION WORD
0
.
1
.
...
...
1
.
1
.
32,767
TR1 TXDATA RAMP CLK
0
FSK RAMP
ENABLE
.
0
1
CLK DIV
DO4 DO3 DO2 DO1 DEV_OFFSET WORD
0
0
0
0
1
1
1
0
3
2
...
...
0
1
DISABLED
ENABLED
TX
DATA
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
0
1
2
.
...
...
0
0
0
0
0
0
1
0
1
0
1
1
1
.
1
1
1
.
...
...
...
...
...
1
1
0
.
1
0
1
.
–1
–2
.
.
.
.
.
–3
0
1
1
1
1
0
0
1
0
1
7
8
9
.
I2
0
I1 INTERRUPT
0
1
0
0
0
–32,768
0
1
0
1
INTERRUPT OFF
0
0
INTERRUPT ON TX
NOT USED
, LOAD CHANNEL SWEEP CONTINUES
, LOAD CHANNEL SWEEP STOPS
DATA
DATA
1
1
INTERRUPT ON TX
Figure 30. Deviation Register (R5) Map
Rev. 0 | Page 22 of 36
Data Sheet
ADF4169
Step Select
STEP REGISTER (R6) MAP
When Bit DB23 is set to 0, Step Word 1 is selected. When
Bit DB23 is set to 1, Step Word 2 is selected.
When Bits DB[2:0] are set to 110, the on-chip step register
(Register R6) is programmed (see Figure 31).
20-Bit Step Word
Reserved Bits
Bits DB[22:3] determine the step word. The step word is the
number of steps in the ramp.
All reserved bits must be set to 0 for normal operation.
CONTROL
BITS
RESERVED
20-BIT STEP WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
SSE1 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9
S8
S7
S6
S5 S4
S3
C3(1) C2(1) C1(0)
S2
S1
...
S20 S19
S2
S1
STEP WORD
SSE1 STEP SELECT
0
1
STEP WORD 1
STEP WORD 2
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1,048,572
1,048,573
1,048,574
1,048,575
Figure 31. Step Register (R6) Map
Rev. 0 | Page 23 of 36
ADF4169
Data Sheet
Fast Ramp
DELAY REGISTER (R7) MAP
When Bit DB19 is set to 1, the triangular waveform is activated
with two different slopes. This waveform can be used as an
alternative to the sawtooth ramp because it mitigates the overshoot
at the end of the ramp in a waveform. Fast ramp is achieved by
changing the top frequency to the bottom frequency in a series of
small steps instead of one big step. When Bit DB19 is set to 0, the
fast ramp function is disabled (see the Fast Ramp Mode section).
When Bits DB[2:0] are set to 111, the on-chip delay register
(Register R7) is programmed (see Figure 32).
Reserved Bits
All reserved bits must be set to 0 for normal operation.
TXDATA Trigger Delay
When Bit DB23 is set to 0, there is no delay before the start of
the ramp when using TXDATA to trigger a ramp. When Bit DB23
is set to 1, a delay is enabled before the start of the ramp if the
delayed start is enabled via Bit DB15.
Ramp Delay
When Bit DB17 is set to 1, the delay between ramps function is
enabled. When Bit DB17 is set to 0, this function is disabled.
Triangular (TRI) Delay
Delay Clock Select (DEL CLK SEL)
When Bit DB22 is set to 1, a delay is enabled between each
section of a triangular ramp, resulting in a clipped ramp. This
setting works only for triangular ramps and when the ramp
delay is activated. When Bit DB22 is set to 0, the delay between
triangular ramps is disabled.
When Bit DB16 is set to 0, the PFD CLK is selected as the delay
clock. When Bit DB16 is set to 1, PFD CLK × CLK1 is selected
as the delay clock. (CLK1 is set by Bits DB[14:3] in Register R2.)
Delayed Start Enable (DEL START EN)
When Bit DB15 is set to 1, the delayed start is enabled. When
Bit DB15 is set to 0, the delayed start is disabled.
Single Full Triangle
When Bit DB21 is set to 1, the single full triangle function is
enabled. When Bit DB21 is set to 0, the single full triangle
function is disabled. For more information, see the Waveform
Generation section.
12-Bit Delay Start Word
Bits DB[14:3] determine the delay start word. The delay start
word affects the duration of the ramp start delay.
TXDATA Trigger
When Bit DB20 is set to 1, a logic high on TXDATA activates the
ramp. When Bit DB20 is set to 0, this function is disabled.
RESERVED
CONTROL
12-BIT DELAY START WORD
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DS4 DS3 DS2 DS1 C3(1) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
TD1 ST1 TR1 FR1
0
RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5
TD1 TRI DELAY
0
1
DISABLED
ENABLED
0
0
1
TX
TRIGGER DELAY
DATA
DISABLED
ENABLED
DS12 DS11
...
DS2 DS1
DELAY START WORD
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
FR1 FAST RAMP
DSE1 DEL START EN
1
0
1
DISABLED
ENABLED
0
1
DISABLED
ENABLED
2
SINGLE FULL
ST1 TRIANGLE
3
.
0
1
DISABLED
ENABLED
DC1 DEL CLK SEL
.
.
.
.
.
0
1
PFD CLK
.
.
.
.
.
PFD CLK × CLK
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
TR1 TX
TRIGGER
RD1 RAMP DELAY
DATA
0
1
DISABLED
ENABLED
0
1
DISABLED
ENABLED
Figure 32. Delay Register (R7) Map
Rev. 0 | Page 24 of 36
Data Sheet
ADF4169
APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
REFERENCE DOUBLER
After powering up the ADF4169, initialize the device by
programming the registers in the following sequence:
The on-chip reference doubler allows the input reference signal
to be doubled. This doubling is useful for increasing the PFD
comparison frequency. Doubling the PFD frequency usually
improves the noise performance of the system by 3 dB. It is
important to note that the PFD cannot be operated above
130 MHz due to a limitation in the speed of the Σ-Δ circuit of
the N divider.
1. Delay register (R7).
2. Step register (R6). Load the step register twice, first with
STEP SEL = 0 and then with STEP SEL = 1.
3. Deviation register (R5). Load the deviation register twice,
first with DEV SEL = 0 and then with DEV SEL = 1.
4. Clock register (R4). Load the clock register twice, first with
CLK DIV SEL = 0 and then with CLK DIV SEL = 1.
5. Function register (R3).
6. R divider register (R2).
7. LSB FRAC register (R1).
8. FRAC/INT register (R0).
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
In fast locking applications, a wide loop filter bandwidth is
required for fast frequency acquisition, resulting in increased
integrated phase noise and reduced spur attenuation. Using CSR,
the loop bandwidth can be kept narrow to reduce integrated phase
noise and to attenuate spurs, while still realizing fast lock times.
RF SYNTHESIZER WORKED EXAMPLE
Cycle Slips
The following equation governs how the synthesizer must be
programmed.
Cycle slips occur in integer-N/fractional-N synthesizers when the
loop bandwidth is narrow compared with the PFD frequency. The
phase error at the PFD inputs accumulates too fast for the PLL to
correct, and the charge pump temporarily pumps in the wrong
direction, slowing down the lock time dramatically. The ADF4169
contains a CSR circuit to extend the linear range of the PFD,
allowing faster lock times without loop filter changes.
RFOUT = (INT + (FRAC/225)) × fPFD
(4)
(5)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
When the ADF4169 detects that a cycle slip is about to occur, it
turns on an extra charge pump current cell. The extra charge pump
current cell outputs a constant current to the loop filter or removes
a constant current from the loop filter, depending on whether
the VCO tuning voltage must increase or decrease to acquire the
new frequency. The effect is that the linear range of the PFD is
increased. Stability is maintained because the current is constant
and is not a pulsed current.
The PFD frequency (fPFD) equation is
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit, Bit DB20 in Register R2 (0 or 1).
R is the RF reference division factor (1 to 32).
T is the reference divide by 2 bit, Bit DB21 in Register R2 (0 or 1).
If the phase error increases again to a point where another cycle
slip is likely, the ADF4169 turns on another charge pump cell. This
continues until the ADF4169 detects that the VCO frequency has
exceeded the desired frequency. It then begins to turn off the
extra charge pump cells one by one until they are all turned off
and the frequency is settled.
For example, in a system where a 12.102 GHz RF frequency
output (RFOUT) is required and a 100 MHz reference frequency
input (REFIN) is available, the frequency resolution is
f
f
RES = REFIN/225
RES = 100 MHz/225 = 2.98 Hz
(6)
From Equation 5,
Up to seven extra charge pump cells can be turned on. In
most applications, seven cells is enough to eliminate cycle
slips altogether, giving much faster lock times.
f
PFD = (100 MHz × (1 + 0)/1) = 100 MHz
12.102 GHz = 100 MHz × (N + FRAC/225)
When Bit DB28 in the R divider register (Register R2) is set to 1,
CSR is enabled. Note that a 45% to 55% duty cycle is needed on
the signal at the PFD in order for CSR to operate correctly. The
reference divide by 2 flip-flop can help provide a 50% duty cycle
at the PFD. For example, if a 100 MHz reference frequency is
available and the user wants to run the PFD at 10 MHz, setting
the R divide factor to 10 results in a 10 MHz PFD signal that is not
50% duty cycle. By setting the R divide factor to 5 and enabling
the reference divide by 2 bit, a 50% duty cycle 10 MHz signal
can be achieved.
Calculating the N and FRAC values,
N = int(RFOUT/fPFD) = 121
FRAC = FMSB × 213 + FLSB
F
F
MSB = int(((RFOUT/fPFD) − N) × 212) = 81
LSB = int(((((RFOUT/fPFD) − N) × 212) − FMSB) × 213) = 7536
where:
F
F
MSB is the 12-bit MSB FRAC value in Register R0.
LSB is the 13-bit LSB FRAC value in Register R1.
int() makes an integer of the argument in parentheses.
Rev. 0 | Page 25 of 36
ADF4169
Data Sheet
Note that the CSR feature can be operated only when the phase
detector polarity setting is positive (Bit DB6 in Register R3 is set
to 1). It cannot be used if the phase detector polarity is negative.
WAVEFORM GENERATION
The ADF4169 is capable of generating five types of waveforms
in the frequency domain: single ramp burst, single triangular
burst, single sawtooth burst, continuous sawtooth ramp, and
continuous triangular ramp. Figure 33 through Figure 37 show
the types of waveforms available.
MODULATION
The ADF4169 can operate in frequency shift keying (FSK) or
phase shift keying (PSK) mode.
Frequency Shift Keying
FSK is implemented by configuring the ADF4169 N divider
for the center frequency and then toggling the TXDATA pin.
The deviation from the center frequency is set by
f
DEV = (fPFD/225) × (DEV × 2DEV_OFFSET
where:
PFD is the PFD frequency.
DEV is a 16-bit word (Bits DB[18:3] in Register R5).
)
(7)
TIME
f
Figure 33. Single Ramp Burst
DEV_OFFSET is a 4-bit word (Bits DB[22:19] in Register R5).
The ADF4169 implements fDEV by incrementing or decrementing
the configured N divider value by DEV × 2DEV_OFFSET
.
FSK Settings Worked Example
In this example, an FSK system operates at 5.8 GHz with a
25 MHz fPFD, requiring 250 kHz deviation (fDEV).
TIME
Figure 34. Single Triangular Burst
Rearrange Equation 7 as follows:
(DEV × 2DEV_OFFSET) = fDEV/(fPFD/225)
(DEV × 2DEV_OFFSET) = 250 kHz/(25 MHz/225)
(DEV × 2DEV_OFFSET) = 335,544.32
If DEV_OFFSET is set to 6,
DEV = 335,544.32/(26) = 5242.88 ≈ 5243
TIME
Due to the rounding of DEV, fDEV = 250.005722 kHz.
Figure 35. Single Sawtooth Burst
Toggling the TXDATA pin causes the frequency to hop between
250 kHz from the programmed center frequency.
Phase Shift Keying
When the ADF4169 is configured for PSK mode, the output
phase of the ADF4169 is equal to
(Phase Value × 360°)/212
TIME
The phase value is set in Register 1, Bits DB[14:3]. The PSK
modulation is controlled by the TXDATA pin.
Figure 36. Continuous Sawtooth Ramp
For example, if the phase value is 1024, a logic high on the TXDATA
pin results in a 90° increase of the output phase. A logic low on
the TXDATA pin results in a 90° decrease of the output phase. The
polarity can be inverted by negating the phase value.
TIME
Figure 37. Continuous Triangular Ramp
Rev. 0 | Page 26 of 36
Data Sheet
ADF4169
WAVEFORM DEVIATIONS AND TIMING
SINGLE TRIANGULAR BURST
Figure 38 shows a version of a ramp.
The single triangular burst is similar to the single ramp burst
(see Figure 34). However, when the steps are complete, the
ADF4169 begins to decrement the N divider value by DEV ×
2DEV_OFFSET on each timeout interval.
TIMER
fDEV
SINGLE SAWTOOTH BURST
In the single sawtooth burst, the N divider value is reset to its
initial value on the next timeout interval after the number of
steps occured (see Figure 35). The ADF4169 retains this
N divider value.
TIME
Figure 38. Waveform Timing
CONTINUOUS SAWTOOTH RAMP
The key parameters that define a ramp are
The sawtooth ramp is a repeated version of the single sawtooth
burst (see Figure 36). The waveform is repeated until the ramp
is disabled.
•
•
•
Frequency deviation
Timeout interval
Number of steps
CONTINUOUS TRIANGULAR RAMP
Frequency Deviation
The frequency deviation for each frequency hop is set by
DEV = (fPFD/225) × (DEV × 2DEV_OFFSET
where:
PFD is the PFD frequency.
DEV is a 16-bit word (Bits DB[18:3] in Register R5).
The triangular ramp is a repeated version of the single triangular
burst (see Figure 37). However, when the steps are complete, the
ADF4169 begins to decrement the N divider value by DEV ×
2DEV_OFFSET on each timeout interval. When the number of steps
has again been completed, the device reverts to incrementing
the N divider value. Repeating this pattern creates a triangular
waveform. The waveform is repeated until the ramp is disabled.
f
)
(8)
f
DEV_OFFSET is a 4-bit word (Bits DB[22:19] in Register R5).
FMCW RADAR RAMP SETTINGS WORKED EXAMPLE
Timeout Interval
This example describes a frequency modulated continuous wave
(FMCW) radar system that requires the RF local oscillator (LO)
to use a sawtooth ramp over a 50 MHz range every 2 ms. The
PFD frequency is 25 MHz, and the RF output range is 5800 MHz
to 5850 MHz.
The time between each frequency hop is set by
Time = CLK1 × CLK2 × (1/fPFD
where:
)
(9)
CLK1 and CLK2 are the 12-bit clock values (12-bit CLK1 divider in
Register R2 and 12-bit CLK2 divider in Register R4). Bits DB[20:19]
in Register R4 must be set to 11 for ramp divider mode.
The frequency deviation for each hop in the ramp is set to
~250 kHz.
f
PFD is the PFD frequency.
The frequency resolution of the ADF4169 is calculated
as follows:
Number of Steps
f
RES = fPFD/225
Using Equation 10, fRES is calculated as follows:
RES = 25 MHz/225 = 0.745 Hz
(10)
A 20-bit step word value (Bits DB[22:3] in Register R6) defines
the number of frequency hops that occur. The INT value cannot
be incremented by more than 28 = 256 from its starting value.
f
SINGLE RAMP BURST
DEV_OFFSET is calculated after rearranging Equation 7.
The most basic waveform is the single ramp burst (see Figure 33).
All other waveforms are variations of this waveform. In the
single ramp burst, the ADF4169 is locked to the frequency
defined in the FRAC/INT register (R0). When the ramp mode
is enabled, the ADF4169 increments the N divider value by
DEV × 2DEV_OFFSET, causing a frequency shift, fDEV, on each timer
interval. This shift is repeated until the set number of steps has
occured. The ADF4169 then retains the final N divider value.
DEV_OFFSET = log2(fDEV/(fRES × DEVMAX))
(11)
(12)
Expressed in log10(x), Equation 11 can be rearranged into
the following equation:
DEV_OFFSET = log10(fDEV/(fRES × DEVMAX))/log10(2)
where:
DEV_OFFSET is a 4-bit word.
f
DEV is the frequency deviation.
DEVMAX = 215 (maximum value of the deviation word).
Using Equation 12, DEV_OFFSET is calculated as follows:
DEV_OFFSET = log10(250 kHz/(0.745 Hz × 215))/log10(2) = 3.356
After rounding, DEV_OFFSET = 4.
Rev. 0 | Page 27 of 36
ADF4169
Data Sheet
From DEV_OFFSET, the resolution of the frequency deviation
can be calculated as follows:
OTHER WAVEFORMS
Dual Ramps with Different Ramp Rates
f
f
DEV_RES = fRES × 2DEV_OFFSET
DEV_RES = 0.745 Hz × 24 = 11.92 Hz
(13)
The ADF4169 can be configured for two ramps with different
step and deviation settings. It also allows the ramp rate to be
reprogrammed while another ramp is running.
To calculate the DEV word, use Equation 14.
Example
DEV = fDEV/(fRES × 2DEV_OFFSET
)
(14)
In this example, the PLL is locked to 5790 MHz and
fPFD = 25 MHz. Two ramps are configured, as follows:
250 kHz
DEV =
= 20,971.52
25 MHz
225
×24
•
Ramp 1 jumps 100 steps; each step lasts 10 µs and has a
frequency deviation of 100 kHz.
Rounding this value to 20,972 and recalculating using Equation 7
to obtain the actual deviation frequency, fDEV, thus produces the
following:
•
Ramp 2 jumps 80 steps; each step lasts 10 µs and has a
frequency deviation of 125 kHz.
To enable the two ramp rates, follow these steps:
f
DEV = (25 MHz/225) × (20,972 × 24) = 250.006 kHz
1. Activate the dual ramp rates mode by setting Bit DB24
The number of fDEV steps required to cover the 50 MHz range
is 50 MHz/250.006 kHz = 200. To cover the 50 MHz range in
2 ms, the ADF4169 must hop every 2 ms/200 = 10 µs.
in Register R5 to 1.
2. Program the ramp rate for Ramp 1 by setting the following
values:
Rearrange Equation 9 to set the timer value (and set CLK2 to 1):
CLK1 = Timer × fPFD/CLK2 = 10 µs × 25 MHz/1 = 250
To summarize the settings,
•
Register R5: set Bit DB23 = 0, Bits DB[18:3] = 16,777,
and Bits DB[22:19] = 3
•
Register R6: set Bit DB23 = 0 and Bits DB[22:3] = 100
•
•
•
•
DEV = 20,972
Number of steps = 200
CLK1 = 250
3. Program the ramp rate for Ramp 2 by setting the following
values:
•
Register R5: set Bit DB23 = 1, Bits DB[18:3] = 20,972,
and Bits DB[22:19] = 3
CLK2 = 1 (Bits DB[20:19] = 11, ramp divider, in Register R4)
Using these settings, program the ADF4169 to a center frequency
of 5800 MHz and enable the sawtooth ramp to produce the
required waveform. If a triangular ramp is used with the same
settings, the ADF4169 sweeps from 5800 MHz to 5850 MHz and
back down again, taking 4 ms for the entire sweep.
•
Register R6: set Bit DB23 = 1 and Bits DB[22:3] = 80
Figure 39 shows the resulting ramp with two ramp rates. To
activate the ramp, see the Activating the Ramp section.
SWEEP RATE SET BY OTHER REGISTER
ACTIVATING THE RAMP
After setting all required parameters, the ramp must be activated by
choosing the desired type of ramp (Bits DB[11:10] in Register R3)
and starting the ramp (Bit DB31 = 1 in Register R0).
SWEEP RATE SET BY ONE REGISTER
Ramp Programming Sequence
TIME
The setting of parameters described in the FMCW Radar Ramp
Settings Worked Example section and the activation of the ramp
described in the Activating the Ramp section must be completed
in the following register write order:
Figure 39. Dual Ramp with Two Ramp Rates
1. Delay register (R7)
2. Step register (R6)
3. Deviation register (R5)
4. Clock register (R4)
5. Function register (R3)
6. R divider register (R2)
7. LSB FRAC register (R1)
8. FRAC/INT register (R0)
Rev. 0 | Page 28 of 36
Data Sheet
ADF4169
Ramp Mode with Superimposed FSK Signal
Delayed Start
In traditional approaches, FMCW radars use either linear
frequency modulation (LFM) or FSK modulation. Used separately,
these modulations introduce ambiguity between measured distance
and velocity, especially in multitarget situations. To overcome this
issue and enable unambiguous (distance and velocity) multitarget
detection, use a ramp with FSK superimposed on it.
A delayed start can be used with two different devices to control
the start time. Figure 41 shows the theory of delayed start.
RAMP WITHOUT
DELAYED START
Example
In this example, the PLL is locked to 5790 MHz and fPFD
25 MHz. The ramp with superimposed FSK is configured as
=
RAMP WITH
DELAYED START
TIME
follows:
Figure 41. Delayed Start of Sawtooth Ramp
The number of steps is set to 100; each step lasts 10 μs and
has a deviation of 100 kHz.
The FSK signal is 25 kHz.
Example
For example, to program a delayed start with two different
devices to control the start time, follow these steps:
To enable ramp mode with FSK superimposed on it, follow
these steps:
1. Enable the delayed start of ramp option by setting Bit DB15
in Register R7 to 1.
2. Delay the ramp on the first part by 5 μs by setting Bit DB16
in Register R7 to 0 and setting the 12-bit delay start word
(Bits DB[14:3] in Register R7) to 125 (fPFD = 25 MHz). The
delay is calculated as follows:
1. Set Bit DB23 in Register R5 and Bit DB23 in Register R6 to 0.
2. Program the ramp as described in the FMCW Radar Ramp
Settings Worked Example section.
3. Program FSK on the ramp to 25 kHz by setting the bits in
Register R5 as follows:
Delay = tPFD × Delay Start Word
Delay = 40 ns × 125 = 5 μs
Bits DB[18:3] = 4194 (deviation word)
Bits DB[22:19] = 3 (deviation offset word)
Bits DB23 = 1 (deviation word for FSK on the ramp)
Bit DB25 = 1 (ramp with FSK enabled)
3. Delay the ramp on the second part by 125 μs by setting
Bit DB16 in Register R7 to 1 and setting the 12-bit delay
start word (Bits DB[14:3] in Register R7) to 125. The delay
is calculated as follows:
Figure 40 shows an example of a ramp with FSK superimposed
on it. To activate the ramp, see the Activating the Ramp section.
Delay = tPFD × CLK1 × Delay Start Word
Delay = 40 ns × 25 × 125 = 125 μs
To activate the ramp, see the Activating the Ramp section.
FSK SHIFT
LFMSTEP =
FREQUENCY
SWEEP/NUMBER
OF STEPS
0
RAMP END
TIME
Figure 40. Combined FSK and LFM Waveform
Rev. 0 | Page 29 of 36
ADF4169
Data Sheet
Delay Between Ramps
It is also possible to activate fast lock operation for the first
period of delay by setting Bit DB18 in Register R7 to 1. This
feature is useful for sawtooth ramps to mitigate the frequency
overshoot on the transition from one sawtooth to the next.
The ADF4169 can be configured to add a delay between bursts in
ramps. Figure 42, Figure 43, and Figure 44 show a delay between
ramps in sawtooth, triangular, and clipped triangular mode,
respectively.
To activate the ramp, see the Activating the Ramp section.
Dual Ramp Rates Mode with Delay
DELAY
This mode combines the modes described in the Dual Ramps
with Different Ramp Rates section and the Delay Between
Ramps section (see Figure 45).
TIME
Figure 42. Delay Between Ramps for Sawtooth Mode
DELAY
TIME
Figure 45. Dual Ramp Rates Mode with Delay
To enable this configuration,
TIME
1. Program the two ramp rates mode as described in the
Dual Ramps with Different Ramp Rates section.
2. Program the delay as described in the Delay Between
Ramps section.
Figure 43. Delay Between Ramps for Triangular Mode
DELAY
Fast Ramp Mode
The ADF4169 is capable of generating a fast ramp. The fast ramp
is a triangular ramp with two different slopes (see Figure 46).
The number of steps, time per step, and deviation per step are
programmable for both the up and down ramps.
TIME
Figure 44. Delay Between Ramps for Clipped Triangular Mode
Example
For example, to add a delay between bursts in a ramp, follow
these steps:
1. Enable the delay between ramps option by setting Bit DB17
in Register R7 to 1.
2. Delay the ramp by 5 µs by setting Bit DB16 in Register R7
to 0 and setting the 12-bit delay start word (Bits DB[14:3] in
Register R7) to 125 (fPFD = 25 MHz). The delay is calculated
as follows:
TIME
Figure 46. Fast Ramp Mode
To activate the fast ramp waveform, follow these steps:
Delay = tPFD × Delay Start Word
Delay = 40 ns × 125 = 5 µs
1. Select the continuous triangular waveform by setting
Bits DB[11:10] in Register R3 to 01.
2. Enable the fast ramp by setting Bit DB19 in Register R7 to 1.
3. Program the up ramp as follows:
If a longer delay is needed, for example, 125 µs, set Bit DB16 in
Register R7 to 1, and set the 12-bit delay start word (Bits DB[14:3]
in Register R7) to 125. The delay is calculated as follows:
•
Set Bit DB6 in Register R4 (CLK DIV SEL), Bit DB23
in Register R5 (DEV SEL), and Bit DB23 in Register R6
(STEP SEL) to 0 for Ramp 1.
Delay = tPFD × CLK1 × Delay Start Word
Delay = 40 ns × 25 × 125 = 125 µs
•
Calculate and program the timer, DEV, DEV_OFFSET,
and the step word as described in the FMCW Radar
Ramp Settings Worked Example section.
Rev. 0 | Page 30 of 36
Data Sheet
ADF4169
4. Program the down ramp as follows.
INTERRUPT MODES AND FREQUENCY READBACK
Interrupt modes are triggered from the rising edge of TXDATA
.
•
Set Bit DB6 in Register R4 (CLK DIV SEL), Bit DB23
in Register R5 (DEV SEL), and Bit DB23 in Register R6
(STEP SEL) to 1 for Ramp 2.
Calculate and program the timer, DEV, DEV_OFFSET,
and the step word as described in the FMCW Radar
Ramp Settings Worked Example section.
To activate this function, set Bits DB[30:27] in Register R0 to
1111, and set Bits DB[25:21] in Register R4 to 00010 to enable
readback to MUXOUT. To select and enable the interrupt mode,
set Bits DB[27:26] in Register R5 as shown in Table 8. A ramp
must be active for readback to work.
•
5. Start the ramp by setting Bit DB31 = 1 in Register R0.
Table 8. Interrupt Modes (Register R5)
Bits DB[27:26] Interrupt Mode
Note that the total frequency change of the up and down ramps
must be equal for stability.
00
01
Interrupt is off
Interrupt on TXDATA, load channel sweep
continues
RAMP COMPLETE SIGNAL TO MUXOUT
11
Interrupt on TXDATA, load channel sweep stops
Figure 47 shows the ramp complete signal on MUXOUT.
Figure 49 shows the theory of interrupt and frequency readback.
FREQUENCY AT WHICH INTERRUPT TOOK PLACE
1
2
TIME
TIME
TIME OF INTERRUPT
1. SWEEP CONTINUES MODE
2. SWEEP STOPS MODE
INTERRUPT SIGNAL
TIME
Figure 47. Ramp Complete Signal on MUXOUT
LOGIC HIGH
LOGIC LOW
To activate the ramp complete signal on MUXOUT, set
Bits DB[30:27] in Register R0 to 1111, and set Bits DB[25:21]
in Register R4 to 00011.
TIME
EXTERNAL CONTROL OF RAMP STEPS
Figure 49. Interrupt and Frequency Readback
The internal ramp clock can be bypassed and a pulse on the
TXDATA pin can trigger each step, which allows more transparent
control of each step. Enable this feature by setting Bit DB29 in
Register R5 to 1 (see Figure 48).
When an interrupt occurs, the data, consisting of the INT and
FRAC values, can be read back via MUXOUT. The data comprises
37 bits: 12 bits represent the INT value and 25 bits represent the
FRAC value. Figure 50 shows how single bits are read back.
DATA CLOCKED OUT ON POSITIVE EDGE OF CLK AND READ
ON NEGATIVE EDGE OF CLK READBACK WORD (37 BITS)
0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (0x1CF623A78)
RF
OUT
TX
LE
DATA
CLK
TIME
MUXOUT
LSB
MSB
12-BIT INTEGER WORD
25-BIT FRAC WORD
1 0110 0010 0011 1010 0111 1000
0x1623A78
0000 1110 0111
0x0E7
TX
DATA
231
23,214,712
25
RF = fPFD × (231 + 23,214,712/2 ) = 1.7922963GHz
Figure 50. Reading Back Single Bits to Determine the Output Frequency
at the Moment of Interrupt
TIME
Figure 48. External Control of Ramp Steps
Rev. 0 | Page 31 of 36
ADF4169
Data Sheet
For continuous frequency readback, the following sequence
must be used (see Figure 51).
6. Register R4 write
7. Frequency readback
8. Pulse on TXDATA
1. Register R0 write
2. LE high
3. Pulse on TXDATA
4. Frequency readback
5. Pulse on TXDATA
Figure 51 shows the continuous frequency readback sequence.
TX
DATA
32 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
37 CLK
PULSES
CLK
FREQUENCY
READBACK
FREQUENCY
READBACK
FREQUENCY
READBACK
MUXOUT
R0 WRITE
R4 WRITE
R4 WRITE
DATA
LE
Figure 51. Continuous Frequency Readback
Rev. 0 | Page 32 of 36
Data Sheet
ADF4169
R3
R2
FAST LOCK MODE
SW2
CP
VCO
The ADF4169 can operate in fast lock mode. In this mode, the
charge pump current is boosted and additional resistors are
connected to maintain the stability of the loop.
C1
C2
R1
C3
ADF4169
SW1
Fast Lock Timer and Register Sequences
R1A
When fast lock mode is enabled (Register R4, Bits DB[20:19]),
after a write to Register R0, the PLL operates in a wide bandwidth
mode for a selected amount of time. Before fast lock is enabled,
the initialization sequence must be performed after the device is
first powered up (see the Initialization Sequence section). The
time in bandwidth mode is set by:
Figure 52. Fast Lock Loop Filter Topology 1
R3
SW2
R2
CP
VCO
C1
C2
R1
C3
CLK1 × CLK2/fPFD = Time in Wide Bandwidth
ADF4169
where:
R1A
CLK1 = Register R2, Bits DB[14:3].
CLK2 = Register R4, Bits DB[18:7].
SW1
fPFD = the PFD frequency.
Figure 53. Fast Lock Loop Filter Topology 2
For more fast lock topologies, see the ADIsimPLL.
SPUR MECHANISMS
Note that the fast lock feature does not work in ramp mode.
Fast Lock Example
In this example, the PLL has fPFD of 100 MHz and requires being
in wide bandwidth mode for 12 µs.
The fractional interpolator in the ADF4169 is a third-order Σ-Δ
modulator with a 25-bit fixed modulus (MOD). The Σ-Δ modulator
is clocked at the PFD frequency (fPFD), which allows PLL output
frequencies to be synthesized at a channel step resolution of
CLK1 × CLK2/fPFD = 12 µs
CLK1 × CLK2 = (12 × 10−6) × (100 × 106) = 1200
Therefore, CLK1 = 12 and CLK2 = 100, which results in 12 µs.
Fast Lock Loop Filter Topology
fPFD/CLK1. This section describes the various spur mechanisms
that are possible with fractional-N synthesizers and how they
affect the ADF4169.
To use fast lock mode, an extra connection from the PLL to the
loop filter is needed. The damping resistor in the loop filter must
be reduced to ¼ of its value in wide bandwidth mode. This reduction
is required because the charge pump current is increased by 16
in wide bandwidth mode, and stability must be ensured.
Fractional Spurs
In most fractional synthesizers, fractional spurs can appear at
the set channel spacing of the synthesizer. In the ADF4169,
these spurs do not appear. The high value of the fixed modulus
in the ADF4169 makes the Σ-Δ modulator quantization error
spectrum look like broadband noise, effectively spreading the
fractional spurs into noise.
To further enhance stability and mitigate frequency overshoot
during a frequency change in wide bandwidth mode, Resistor R3
is connected (see Figure 52). During fast lock, the SW1 pin is
shorted to ground, and the SW2 pin is connected to CP (set
Bits DB[20:19] in Register R4 to 01 for fast lock divider mode).
Integer Boundary Spurs
Interactions between the RF VCO frequency and the PFD
frequency can lead to spurs known as integer boundary spurs.
When these frequencies are not integer related (which is the
purpose of a fractional-N synthesizer), spur sidebands appear on
the VCO output spectrum at an offset frequency that corresponds
to the beat note, or difference frequency, between an integer
multiple of the PFD and the VCO frequency.
The following two topologies can be used:
•
Divide the damping resistor (R1) into two values (R1 and
R1A) that have a ratio of 1:3 (see Figure 52).
•
Connect an extra resistor (R1A) directly from SW1 (see
Figure 53). The extra resistor must be selected such that the
parallel combination of an extra resistor and the damping
resistor (R1) is reduced to ¼ of the original value of R1.
These spurs are called integer boundary spurs because they are
more noticeable on channels close to integer multiples of the PFD,
where the difference frequency can be inside the loop bandwidth.
These spurs are attenuated by the loop filter on channels far from
integer multiples of the PFD.
For both topologies, the ratio R3:R2 must equal 1:4.
Rev. 0 | Page 33 of 36
ADF4169
Data Sheet
Reference Spurs
PCB DESIGN GUIDELINES FOR THE CHIP SCALE
PACKAGE
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mecha-
nism is the feedthrough of low levels of on-chip reference switching
noise out through the RFINx pins back to the VCO, resulting in
reference spur levels as high as −90 dBc. Take care in the printed
circuit board (PCB) layout to ensure that the VCO is well separated
from the input reference to avoid a possible feedthrough path
on the board.
The lands on the chip scale package (CP-24-10) are rectangular.
The PCB pad for these lands must be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. Center the land on the pad to ensure that the solder joint
size is maximized.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as this exposed pad. On the PCB, there must be a clearance
of at least 0.25 mm between the thermal pad and the inner edges
of the pad pattern to ensure that shorting is avoided.
Low Frequency Applications
The specification of the RF input is 0.5 GHz minimum; however,
RF frequencies lower than 0.5 GHz can be used if the minimum
slew rate specification of 400 V/µs is met. An appropriate driver,
for example, the ADCMP553, can accelerate the edge transitions
of the RF signal before it is fed back to the ADF4169 RF input.
Thermal vias can be used on the PCB thermal pad to improve the
thermal performance of the package. If vias are used, incorporate
them into the thermal pad at the 1.2 mm pitch grid. The via
diameter must be between 0.3 mm and 0.33 mm, and the via
barrel must be plated with 1 ounce of copper to plug the via.
Connect the PCB thermal pad to AGND.
FILTER DESIGN USING ADIsimPLL
A filter design and analysis program is available to help the user
implement PLL design. Visit www.analog.com/ADIsimPLL to
download the free ADIsimPLL software. This software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter
architectures are allowed.
Rev. 0 | Page 34 of 36
Data Sheet
ADF4169
The PLL solution also has advantages over another method for
generating FMCW ramps: a digital-to-analog converter (DAC)
driving the VCO directly, this method suffers from nonlinearities
of the VCO tuning characteristics, requiring compensation. The
PLL method produces highly linear ramps without the need for
calibration.
APPLICATION OF THE ADF4169 IN FMCW RADAR
Figure 54 shows the application of the ADF4169 in a frequency
modulated continuous wave (FMCW) radar system. In the FMCW
radar system, the ADF4169 generates the sawtooth or triangle
ramps that are necessary for this type of radar to operate.
Traditionally, the PLL is driven directly by a direct digital
synthesizer (DDS) to generate the required type of waveform. Due
to the waveform generating mechanism that is implemented on
the ADF4169, a DDS is no longer needed, which reduces cost.
NO DDS REQUIRED
WITH ADF4169
LINEAR
FREQUENCY
SWEEP
REFERENCE
OSCILLATOR
VCO
Tx
ADF4169
PA
×2
ANTENNA
MULT ×2
Rx
ANTENNAS
AD8283
BASEBAND
MICRO-
CONTROLLER
ADC
HPF
DSP
MUX
:
.
MIXER
10 BITS TO
12 BITS
RANGE
.
16 BITS
BUS
COMPENSATION
ADSP-BF531
FREQUENCY MODULATED CONTINUOUS WAVE
LONG RANGE RADAR
CAN/FLEXRAY
Figure 54. FMCW Radar with the ADF4169
Rev. 0 | Page 35 of 36
ADF4169
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
24
19
18
0.50
BSC
1
6
EXPOSED
PAD
2.20
2.10 SQ
2.00
13
12
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-24-10
CP-24-10
CP-24-10
CP-24-10
ADF4169CCPZ
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board (Set up for External, SMA Connected VCO Board;
Filter Unpopulated)
ADF4169CCPZ-RL7
ADF4169WCCPZ
ADF4169WCCPZ-RL7
EV-ADF4159EB3Z
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 The EV-ADF4159EB3Z evaluation board works with the ADF4169 if modifications are made. See the UG-383 for additional information.
AUTOMOTIVE PRODUCTS
The ADF4169W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12957-0-7/15(0)
Rev. 0 | Page 36 of 36
相关型号：
ADF4206BCHIPS
IC PLL FREQUENCY SYNTHESIZER, 500 MHz, UUC, DIE, PLL or Frequency Synthesis Circuit
ADI
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