ADE7754ARZRL_技术文档

PRELIMINARY TECHNICAL DATA

Poly-phaseMulti-Function

a

Energy Metering IC with Serial Port

ADE7754*

Preliminary Technical Data

The ADE7754 provides different solutions to measure Active

and Apparent Energy from the six analog inputs thus en-

abling the use of the ADE7754 in various Power meter

services as 3-phase 4-wire, 3-phase 3-wire but also 4-wire

delta.

In addition to RMS calculation, Real and Apparent power

informations, the ADE7754 provides system calibration

features for each phase, i.e., channel offset correction, phase

calibration and gain calibration. The CF logic output gives

instantaneous real power information.

The ADE7754 has a waveform sample register which enables

access to ADC outputs. The part also incorporates a detec-

tion circuit for short duration low or high voltage variations.

The voltage threshold levels and the duration (no. of half line

cycles) of the variation are user programmable.

A zero crossing detection is synchronized which the zero

crossing point of the line voltage of each of the three phases.

This information is used to measure each line’s Period. It is

also used internally to the chip in the Line Active Energy and

Line Apparent Energy accumulation modes. This permits

faster and more accurate calibration of the power calcula-

FEATURES

High Accuracy, supports IEC 687/61036

Compatible with 3-phase/3-wire, 3-phase/4-wire

and any type of 3-phase services

Less than 0.1% error in Active Power Measurement

over a dynamic range of 1000 to 1

The ADE7754 supplies Active Energy, Apparent Energy,

Voltage rms, Current rms and Sampled Waveform Data.

Digital Power, Phase & Input Offset Calibration.

An On-Chip temperature sensor ( 3ꢀC typ. after calibrationꢁ

On-Chip user Programmable thresholds for line voltage

SAG and overdrive detections.

A SPI compatible Serial Interface with Interrupt Request line

(IRQꢁ.

A pulse output with programmable frequency

Proprietary ADCs and DSP provide high accuracy over large

variations in environmental conditions and time.

Reference 2.4V 8% (Drift 30 ppm/ꢀC typicalꢁ

with external overdrive capability

Single 5V Supply, Low power (80mW typicalꢁ

GENERAL DESCRIPTION

The ADE7754 is a high accuracy Poly-phase electrical tions. This signal is also useful for synchronization of relay

switching.

energy measurement IC with a serial interface and a pulse

output. The ADE7754 incorporates second order sigma-

delta ADCs, reference circuitry, temperature sensor, and all

the signal processing required to perform Active, Apparent

Energy measurements and rms calculation.

Data is read from the ADE7754 via the SPI serial interface.

The interrupt request output (IRQ) is an open drain, active

low logic output. The IRQ output will go active low when one

or more interrupt events have occurred in the ADE7754. A

status register will indicate the nature of the interrupt.

The ADE7754 is available in a 24-lead SOIC package.

FUNCTIONAL BLOCK DIAGRAM

AVDD

RESET

17

4

AVGAIN

AVRMSOS

ADE7754

2

Σ

X

Power

Supply

Monitor

AVAG

AIRMSOS

2

X

Σ

AAPGAIN

PGA1

5

6

IAP

IAN

VAP

|X|

ABS

ADC

Σ

HPF

LPF2

PGA2

16

AAPOS

AWG

Φ

APHCAL

BVGAIN

BVRMSOS

2

Σ

X

BVAG

BIRMSOS

CFNUM

2

X

Σ

BAPGAIN

PGA1

Σ

7

IBP

IBN

|X|

1

CF

ADC

Σ

DFC

8

HPF

BPHCAL

LPF2

PGA2

15

VBP

ABS

BAPOS

CVRMSOS

BWG

Φ

CFDEN

3

2

DVDD

DGND

CLKIN

CLKOUT

2

X

Σ

CVAG

CIRMSOS

CVGAIN

19

20

2

X

PGA1

Σ

CAPGAIN

ICP

ICN

VCP

VN

VADIV

WDIV

|X|

ADC

Σ

10

14

HPF

CPHCAL

PGA2

LPF2

ABS

ADC

CAPOS

CWG

Φ

13

ADE7754 REGISTERS &

SERIAL INTERFACE

TEMP

SENSOR

4kΩ

2.5V

REF

11

12

22

24

23

18

21

* Patents pending.

REF_IN/OUT

DIN DOUT SCLK

CS IRQ

AGND

REV. PrG 01/03

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

PRELIMINARY TECHNICAL DATA

(AVDD = DVDD = 5V 5ꢀ% AꢁND = DꢁND = ꢂV% On-Chip ꢃeꢄerence%

CLKIN=1ꢂMHz% TMIN to TMAX = -4ꢂºC to +85ºC)

ADE7754–SPECIFICATIONS

Parameters

Units

TestConditions/Comments

ACCURACY

Active Power Measurement Error

Phase Error Between Channels

(PF=0.8 capacitive)

0.1

% typ

Over a dynamic range of 1000 to 1

0.05

º max

Phase Lead 37º

Phase Lag 60º

(PF=0.5 inductive)

AC Power Supply Rejection¹

Output Frequency Variation

DC Power Supply Rejection¹

Output Frequency Variation

0.01

% typ

IAP/N=IBP/N=ICP/N= 100mV rms

0.01

500

ANALOG INPUTS

Maximum Signal Levels

mV peak max

Differential input: V_AP-V_N,V_BP-V_N,V_CP-V_N

I_AP-I_AN, I_BP-I_BN,I_CP-I_CN

Input Impedance (DC)

Bandwidth (-3dB)

ADC Offset Error¹

Gain Error¹

400

14

25

8

kΩ min

kHz typ

mV max

% typ

Uncalibrated error, see Terminology for detail

External 2.5V reference

Gain Error Match¹

3

% typ

REFERENCE INPUT

REF_IN/OUTInput Voltage Range

2.6

2.2

4

V max

V min

kW min

pF max

2.4V +8%

2.4V -8%

Input Impedance

Input Capacitance

10

TEMPERATURE SENSOR

2

ºC

Calibrated DC offset

ON-CHIP REFERENCE

Reference Error

Temperature Coefficient

200

30

mV max

ppm/ºC typ

CLKIN

Input Clock Frequency

10

MHz typ

LOGIC INPUTS

RESET, DIN, SCLK CLKIN

and CS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

3

V min

DV_DD=5V

Typical 10nA, Vin=0V to DV_DD

5%

V max

mA max

pF max

Input Capacitance, C_IN

10

LOGIC OUTPUTS

CF, IRQ, DOUT and CLKOUT

Output High Voltage, V_OH

4

1

V min

V max

DVDD=5V

5%

Output Low Voltage, V_OL

POWER SUPPLY

AV_DD

For specified performance

5V - 5%

5V +5%

5V - 5%

5V +5%

4.75

5.25

4.75

5.25

7

V min

V max

V min

V max

mA max

DV_DD

AI_DD

DI_DD

10

NOTES:

1. See Terminology section for explanation of specifications.

2. See plots in Typical Performance Graph.

ORDERING GUIDE

MODEL

PACKAGE OPTION^*

3. Specification subject to change without notice.

ADE7754AR

RW-24

ADE7754ARRL

EVAL-ADE7754EB

RW-24 in Reel

ADE7754 Evaluation Board

REV. PrG 01/03

–2–

PRELIMINARY TECHNICAL DATA

ADE7754

ADE7754TIMINꢁCHAꢃACTEꢃISTICS^1%2

(AV = DV = 5V 5ꢀ% AꢁND = DꢁND = ꢂV% On-Chip ꢃeꢄerence%

DD

CLKIN = 1ꢂMHz XTAL% TMIN to TMAX = -4ꢂ°C to +85°C)

Parameter

Units

Test Conditions/Comments

Write timing

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

50

10

5

400

50

100

ns (min) CS falling edge to first SCLK falling edge

ns (min) SCLK logic high pulse width

ns (min) SCLK logic low pulse width

ns (min) Valid Data Set up time before falling edge of SCLK

ns (min) Data Hold time after SCLK falling edge

ns (min) Minimum time between the end of data byte transfers.

ns (min) Minimum time between byte transfers during a serial write.

ns (min) CS Hold time after SCLK falling edge.

Read timing

5

t₉

4

µs (min) Minimum time between read command (i.e. a write to Communication

Register) and data read.

t₁₀

t₁₁

50

30

ns (min) Minimum time between data byte transfers during a multibyte read.

ns (min) Data access time after SCLK rising edge following a write to the

Communications Register

ns (max) Bus relinquish time after falling edge of SCLK.

ns (min)

3

4

t₁₂

100

10

100

4

t₁₃

ns (max) Bus relinquish time after rising edge of CS.

10

ns (min)

N O T E S

¹Sample tested during initial release and after any redesign or process change that may

affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)

and timed from a voltage level of 1.6V.

I

OL

200 µA

1.6 mA

²See timing diagram below and Serial Interface section of this data sheet.

³Measured with the load circuit in Figure 1 and defined as the time required for the

output to cross 0.8V or 2.4V.

TO

OUTPUT

+2.1V

⁴Derived from the measured time taken by the data outputs to change 0.5V when

loaded with the circuit in Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50pF capacitor. This means that

the time quoted in the timing characteristics is the true bus relinquish time of the

part and is independent of the bus loading.

C

50pF

L

I

OH

Figure 1 - Load Circuit for Timing Specifications

⁵Minimum time between read command and data read for all registers

except WAVFORM register. For WAVFORM register t₉=500ns min

Serial Write Timing

t

8

CS

t

1

6

2

3

t

7

SCLK

DIN

t

4

t

5

DB0

Most Significant Byte

SerialReadTiming

DB7

Least Significant Byte

0

DB7

DB0

A1

1

A5 A4 A3 A2

Command Byte

A0

CS

t

1

t

14

t

10

9

SCLK

DIN

0

A1

A5 A4 A3 A2

A0

t

13

t

12

11

DB0

DB7

DB0

DB7

DOUT

Least Significant

Byte

Most Significant

Byte

Command

Byte

REV. PrG 01/03

–3–

PRELIMINARY TECHNICAL DATA

ADE7754

ABSOLUTE MAXIMUM RATINGS*

(T_A= +25°C unless otherwise noted)

24-Lead SOIC, Power Dissipation . . . . . . . . . TBD mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . 53°C/W

Lead Temperature, Soldering

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . –0.3V to +7V

DV_DDto AV_DD. . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V

Analog Input Voltage to AGND

I_AP,I_AN,I_BP,I_BN,I_CP,I_CN,V_AP,V_BP,V_CP,V_N. –6V to +6V

Reference Input Voltage to AGND –0.3V to AV_DD+0.3V

Digital Input Voltage to DGND . –0.3V to DV_DD+0.3V

Digital Output Voltage to DGND –0.3V to DV_DD+0.3V

Operating Temperature Range

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C

*StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extendedperiodsmayaffectdevicereliability.

Industrial . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADE7754 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjectedtohigh-energyelectrostaticdischarges. Therefore, properESDprecautionsarerecommended

to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

Terminology

MEASUREMENT ERROR

ADC OFFSET ERROR

The error associated with the energy measurement made by

the ADE7754 is defined by the following formula:

This refers to the DC offset associated with the analog inputs

to the ADCs. It means that with the analog inputs connected

to AGND the ADCs still see a dc analog input signal. The

magnitude of the offset depends on the gain and input range

selection - see characteristic curves. However, when HPFs

are switched on the offset is removed from the current

channels and the power calculation is not affected by this

offset.

Percentage Error =









Energy registered by ADE7754 − True Energy

×100%





True Energy

PHASE ERROR BETWEEN CHANNELS

GAIN ERROR

The HPF (High Pass Filter) in the current channel has a

phase lead response. To offset this phase response and

equalize the phase response between channels a phase correc-

tion network is also placed in the current channel. The phase

correction network ensures a phase match between the

current channels and voltage channels to within 0.1° over a

range of 45Hz to 65Hz and 0.2° over a range 40Hz to 1kHz.

This phase mismatch between the voltage and the current

channels can be further reduced with the phase calibration

register in each phase.

The gain error in the ADE7754 ADCs, is defined as the

difference between the measured ADC output code (minus

the offset) and the ideal output code - see Current Channel ADC

& Voltage Channel ADC. The difference is expressed as a

percentage of the ideal code.

GAIN ERROR MATCH

The Gain Error Match is defined as the gain error (minus the

offset) obtained when switching between a gain of 1, 2 or 4.

It is expressed as a percentage of the output ADC code

obtained under a gain of 1.

POWER SUPPLY REJECTION

This quantifies the ADE7754 measurement error as a per-

centage of reading when the power supplies are varied.

For the AC PSR measurement a reading at nominal supplies

(5V) is taken. A second reading is obtained with the same

input signal levels when an ac (175mVrms/100Hz) signal is

introduced onto the supplies. Any error introduced by this ac

signal is expressed as a percentage of reading—see Measure-

ment Error definition above.

For the DC PSR measurement a reading at nominal supplies

(5V) is taken. A second reading is obtained with the same

input signal levels when the power supplies are varied 5%.

Any error introduced is again expressed as a percentage of

reading.

–4–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

Characteristic Curves– ADE7754

TBD TBD

TPC 1. Real Power Error as a percent of reading with Gain

= 1 and Internal reference (WYE connection)

TPC 2. Real Power Error as a percent of reading over

Power Factor with Internal reference (DELTA connection)

TBD TBD

TPC 3. Real Power Error as a percent of reading over

Power Factor with Internal reference (Gain = 1)

TPC 4. Real Power Error as a percent of reading over

Power Factor with Internal reference (Gain = 4)

TBD TBD

TPC 5. Current rms Error as a percent of reading with

Internal reference (Gain = 1)

TPC 6. Voltage rms Error as a percent of reading with

Internal reference (Gain = 1)

–5–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

TBD TBD

TPC 7. Real Power Error as a percent of reading over

Power Factor with External reference (Gain = 1)

TPC 8. Voltage rms Error as a percent of reading with

External reference (Gain = 1)

TBD TBD

TPC 9. Real Power Error as a percent of reading over input

frequency with Internal reference

TPC 10. Real Power Error as a percent of reading over

power supply with External reference (Gain = 1)

TBD

TPC 11. Real Power Error as a percent of reading over

power supply with Internal reference (Gain = 1)

TPC 12. Test circuit for performances curves

REV. PrG 01/03

–6–

PRELIMINARY TECHNICAL DATA

ADE7754

TBD TBD

TPC 13. Current Channel offset distribution (Gain = 1)

TPC 14. Current Channel offset distribution (Gain = 4)

REV. PrG 01/03

–7–

PRELIMINARY TECHNICAL DATA

ADE7754

PIN FUNCTION DESCRIPTION

DESCRIPTION

Pin No.

MNEMONIC

1

C F

Calibration Frequency logic output. The CF logic output gives Active Power informa-

tion. This output is intended to be used for operational and calibration purposes. The

full-scale output frequency can be scaled by writing to the CFNUM and CFDEN reg-

isters—see Energy To Frequency Conversion.

2

DGND

This provides the ground reference for the digital circuitry in the ADE7754, i.e. multi-

plier, filters and digital-to-frequency converter. Because the digital return currents in

the ADE7754 are small, it is acceptable to connect this pin to the analog ground plane

of the whole system. However high bus capacitance on the DOUT pin may result in

noisy digital current which could affect performance.

3

DV_DD

Digital power supply. This pin provides the supply voltage for the digital circuitry in

the ADE7754. The supply voltage should be maintained at 5V

5% for specified op-

eration. This pin should be decoupled to DGND with a 10µF capacitor in parallel with

a ceramic 100nF capacitor.

4

AV_DD

Analog power supply. This pin provides the supply voltage for the analog circuitry in

the ADE7754. The supply should be maintained at 5V

5% for specified operation.

Every effort should be made to minimize power supply ripple and noise at this pin by

the use of proper decoupling. The typical performance graphs in this data sheet show

the power supply rejection performance. This pin should be decoupled to AGND with a

10µF capacitor in parallel with a ceramic 100nF capacitor.

5,6;

7,8;

9,10

I

_AP, I_AN

_BP, I_BN

;

Analog inputs for current channel. This channel is intended for use with the current

transducer and is referenced in this document as the current channel. These inputs are

fully differential voltage inputs with maximum differential input signal levels of 0.5V,

0.25V and 0.125V, depending on the gain selections of the internal PGA -See Analog

Inputs.

I_CP, I_CN

All inputs have internal ESD protection circuitry, and in addition an overvoltage of

6V can be sustained on these inputs without risk of permanent damage.

11

12

AGND

This pin provides the ground reference for the analog circuitry in the ADE7754, i.e.

ADCs, temperature sensor, and reference. This pin should be tied to the analog ground

plane or the quietest ground reference in the system. This quiet ground reference

should be used for all analog circuitry, e.g. anti aliasing filters, current and voltage

transducers etc. In order to keep ground noise around the ADE7754 to a minimum, the

quiet ground plane should only connected to the digital ground plane at one point. It is

acceptable to place the entire device on the analog ground plane.

REF_IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a

nominal value of 2.4V

8% and a typical temperature coefficient of 30ppm/°C. An

external reference source may also be connected at this pin. In either case this pin

should be decoupled to AGND with a 1µF ceramic capacitor.

13, 14

15, 16

V_N, V_CP

_BP, V_AP

,

Analog inputs for the voltage channel. This channel is intended for use with the voltage

transducer and is referenced as the voltage channel in this document. These inputs are

single-ended voltage inputs with maximum signal level of 0.5V with respect to V_Nfor

specified operation. These inputs are voltage inputs with maximum differential input

signal levels of 0.5V, 0.25V and 0.125V, depending on the gain selections of the

internal PGA - see Analog Inputs.

V

All inputs have internal ESD protection circuitry, and in addition an over voltage of

6V can be sustained on these inputs without risk of permanent damage.

17

18

RESET

IRQ

Reset pin for the ADE7754. A logic low on this pin will hold the ADCs and digital

circuitry (including the Serial Interface) in a reset condition.

Interrupt Request Output. This is an active low open drain logic output. Maskable

interrupts include: Active Energy Register at half level, Apparent Energy Register at

half level, and waveform sampling up to 26kSPS. See ADE7754 Interrupts.

–8–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Pin No.

MNEMONIC

DESCRIPTION

19

CLKIN

Master clock for ADCs and digital signal processing. An external clock can be pro-

vided at this logic input. Alternatively, a parallel resonant AT crystal can be connected

across CLKIN and CLKOUT to provide a clock source for the ADE7754. The clock

frequency for specified operation is 10MHz. Ceramic load capacitors of between 22pF

and 33pF should be used with the gate oscillator circuit. Refer to crystal manufacturers

data sheet for load capacitance requirements

20

21

CLKOUT

A crystal can be connected across this pin and CLKIN as described above to provide a

clock source for the ADE7754. The CLKOUT pin can drive one CMOS load when

either an external clock is supplied at CLKIN or a crystal is being used.

CS

Chip Select. Part of the four wire Serial Interface. This active low logic input allows

the ADE7754 to share the serial bus with several other devices. See ADE7754 Serial Inter-

face.

.

22

23

DIN

Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of

SCLK—see ADE7754 Serial Interface.

SCLK

Serial Clock Input for the synchronous serial interface. All Serial data transfers are

synchronized to this clock—see ADE7754 Serial Interface. The SCLK has a Schmidt-trig-

ger Input for use with a clock source which has a slow edge transition time, e.g.,

opto-isolator outputs etc.

24

DOUT

Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of

SCLK. This logic output is normally in a high impedance state unless it is driving data

onto the serial data bus—see ADE7754 Serial Interface.

PIN CONFIGURATION

SOIC Package

1

2

DOUT

SCLK

24

23

22

21

20

19

18

17

16

15

14

CF

DGND

DVDD

AVDD

IAP

3

DIN

CS

4

5

CLKOUT

CLKIN

IRQ

ADE7754

TOP VIEW

(Not to Scale)

6

IAN

7

IBP

8

IBN

RESET

VAP

9

ICP

10

11

ICN

VBP

AGND

VCP

12

13

REF

In/Out

VN

REV. PrG 01/03

–9–

PRELIMINARY TECHNICAL DATA

ADE7754

ANALOG INPUTS

POWER SUPPLY MONITOR

The ADE7754 has a total of six analog inputs, dividable into

two channels: current channel and voltage channel. The

current channel consists of three pairs of fully-differential

voltage inputs, namely (I_AP, I_AN; I_BP, I_BN; I_CP, I_CN). The fully

differential voltage input pairs have a maximum differential

voltage of 0.5V. The voltage channel has three single-ended

voltage inputs V_AP, V_BP, and V_CP. These single-ended volt-

age inputs have a maximum input voltage of 0.5V with

respect to V_N. Both the current channel and the voltage

channel have a PGA (Programmable Gain Amplifier) with

possible gain selections of 1, 2, or 4. The same gain is applied

to all the inputs of each channel.

The gain selections are made by writing to the Gain register.

Bits 0 to 1 select the gain for the PGA in the fully-differential

current channel. The gain selection for the PGA in the single-

ended voltage channel is made via bits 5 to 6. Figure 3 shows

how a gain selection for the current channel is made using the

Gain register.

The ADE7754 also contains an on-chip power supply moni-

tor. The Analog Supply (AV ) is continuously monitored

DD

by the ADE7754. If the supply is less than 4V

5% then the

ADE7754 will go in an inactive state, i.e. no energy will be

accumulated when the supply voltage is below 4V. This is

useful to ensure correct device operation at power up and

during power down. The power supply monitor has built-in

hysteresis and filtering. This gives a high degree of immunity

to false triggering due to noisy supplies.

AV

DD

5V

4V

0V

Time

ADE7754

Power-on

Active

Inactive

GAIN[7:0]

RESET flag in the

Interrupt Status register

Read RSTATUS register

Gain (k)

selection

IAP, IBP, ICP

Figure 2 - On chip Power supply monitoring

+

-

The RESET bit in the Interrupt Status register is set to logic

V

in

k·V

in

one when AVDD drops below 4V

5%. The RESET flag is

always masked by the Interrupt Mask register and cannot

cause the IRQ pin to go low. The Power supply and

decoupling for the part should be such that the ripple at

IAN, IBN, ICN

AVDD does not exceed 5V

operation.

5% as specified for normal

Figure 3— PGA in current channel

Figure 4 shows how the gain settings in PGA 1 (current

channel) and PGA 2 (voltage channel) are selected by various

bits in the Gain register. The no load threshold and sum of

the absolute value can also be selected in the Gain register -

see Table X.

GAIN REGISTER*

current & voltage Channel PGA Control

7

6

5

4

3

2

1

0

ADDR: 18h

0

RESERVED=0

RESERVED

=0

PGA 1 Gain Select

00 = x1

01 = x2

10 = x4

ABS

No

Load

PGA 2 Gain Select

00 = x1

01 = x2

10 = x4

*Register contents show power on defaults

Figure 4 — ADE7754 Analog Gain register

–10–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Antialias filter (RC)

ADE7754 ANALOG TO DIGITAL CONVERSION

Sampling

Frequency

Digital filter

Shaped

Noise

The analog-to-digital conversion in the ADE7754 is carried

out using second order sigma-delta ADCs. The block dia-

gram in Figure 5 shows a first order (for simplicity)

sigma-delta ADC. The converter is made up of two parts,

first the sigma-delta modulator and secondly the digital low

pass filter.

Signal

Noise

0

2kHz

417kHz

833kHz

Frequency (Hz)

MCLK/12

High resolution

Signal

output from Digital

LPF

INTEGRATOR

Digital Low Pass Filter

Analog Low Pass Filter

LATCHED

COMPARATOR

+

-

͐

Σ

R

V

Noise

REF

-

1

24

C

0

2kHz

417kHz

833kHz

....10100101......

1-Bit DAC

Frequency (Hz)

Figure 6– Noise reduction due to Oversampling & Noise

shaping in the analog modulator

Figure 5 - First order Sigma-Delta (Σ−∆) ADC

A sigma-delta modulator converts the input signal into a

continuous serial stream of 1's and 0's at a rate determined by

the sampling clock. In the ADE7754 the sampling clock is

equal to CLKIN/12. The 1-bit DAC in the feedback loop is

driven by the serial data stream. The DAC output is sub-

tracted from the input signal. If the loop gain is high enough

the average value of the DAC output (and therefore the bit

stream) will approach that of the input signal level. For any

given input value in a single sampling interval, the data from

the 1-bit ADC is virtually meaningless. Only when a large

number of samples are averaged, will a meaningful result be

obtained. This averaging is carried out in the second part of

the ADC, the digital low pass filter. By averaging a large

number of bits from the modulator the low pass filter can

produce 24-bit data words which are proportional to the input

signal level. The sigma-delta converter uses two techniques

to achieve high resolution from what is essentially a 1-bit

conversion technique. The first is oversampling. By over

sampling we mean that the signal is sampled at a rate

(frequency) which is many times higher than the bandwidth

of interest. For example the sampling rate in the ADE7754

is CLKIN/12 (833kHz) and the band of interest is 40Hz to

2kHz. Oversampling has the effect of spreading the quanti-

zation noise (noise due to sampling) over a wider bandwidth.

With the noise spread more thinly over a wider bandwidth,

the quantization noise in the band of interest is lowered—see

Figure 6.

Antialias Filter

Figure 5 also shows an analog low pass filter (RC) on the

input to the modulator. This filter is present to prevent

aliasing. Aliasing is an artifact of all sampled systems.

Basically it means that frequency components in the input

signal to the ADC which are higher than half the sampling

rate of the ADC will appear in the sampled signal at a

frequency below half the sampling rate. Figure 7 illustrates

the effect, frequency components (arrows shown in black)

above half the sampling frequency (also know as the Nyquist

frequency), i.e., 417kHz get imaged or folded back down

below 417kHz (arrows shown in grey). This will happen with

all ADCs no matter what the architecture. In the example

shown it can be seen that only frequencies near the sampling

frequency, i.e., 833kHz, will move into the band of interest

for metering, i.e, 40Hz - 2kHz. This fact allows us to use a

very simple LPF (Low Pass Filter) to attenuate these high

frequencies (near 900kHz) and so prevent distortion in the

band of interest. A simple RC filter (single pole) with a

corner frequency of 10kHz produces an attenuation of ap-

proximately 40dBs at 833kHz—see Figure 7. This is sufficient

to eliminate the effects of aliasing.

Aliasing Effects

Sampling Frequency

Image

frequencies

However oversampling alone is not an efficient enough

method to improve the signal to noise ratio (SNR) in the band

of interest. For example, an oversampling ratio of 4 is

required just to increase the SNR by only 6dB (1-Bit). To

keep the oversampling ratio at a reasonable level, it is

possible to shape the quantization noise so that the majority

of the noise lies at the higher frequencies. This is what

happens in the sigma-delta modulator, the noise is shaped by

the integrator which has a high pass type response for the

quantization noise. The result is that most of the noise is at

the higher frequencies where it can be removed by the digital

low pass filter. This noise shaping is also shown in Figure 6.

417kHz

0

2kHz

833kHz

Frequency (Hz)

Figure 7– ADC and signal processing

in current channel or voltage channel

REV. PrG 01/03

–11–

PRELIMINARY TECHNICAL DATA

ADE7754

CURRENT CHANNEL ADC

Current channel Sampling

Figure 8 shows the ADC and signal processing chain for the

input IA of the current channels (same for IB and IC). In

waveform sampling mode the ADC outputs are signed 2’s

Complement 24-bit data word at a maximum of 26.0kSPS

(kilo Samples Per Second). The output of the ADC can be

scaled by 50% by using the APGAINs register. While the

ADC outputs are 24-bit 2's complement value the maximum

full-scale positive value from the ADC is limited to 400000h

(+4,194,304d). The maximum full-scale negative value is

limited to C00000h (-4,194,304d). If the analog inputs are

over-ranged, the ADC output code clamps at these values.

With the specified full scale analog input signal of 0.5V, the

ADC produces an output code between D70A3Eh (-

2,684,354) and 28F5C2h (+2,684,354). This is illustrated

in Figure 8. The diagram in Figure 8 shows a full-scale

voltage signal being applied to the differential inputs IAP and

IAN.

The waveform samples of the current channel inputs may

also be routed to the WAVEFORM register (WAVMODE

register to select the speed and the phase) to be read by the

system master (MCU). The Active Energy and Apparent

Energy calculation will remain uninterrupted during wave-

form sampling.

When in waveform sample mode, one of four output sample

rates may be chosen by using bits 3 and 4 of the WAVMode

register (DTRT[1:0] mnemonic). The output sample rate

may be 26.0kSPS, 13.0kSPS, 6.5kSPS or 3.3kSPS—see

WAVMode register. By setting the WSMP bit in the Interrupt

Mask register to logic one, the interrupt request output IRQ

will go active low when a sample is available. The timing is

shown in Figure 9. The 24-bit waveform samples are trans-

ferred from the ADE7754 one byte (8-bits) at a time, with the

most significant byte shifted out first.

IRQ

Current channel ADC Gain Adjust

SCLK

The ADC gain in each phase of the Current Channel can be

adjusted by using the multiplier and Active Power Gain

register (AAPGAIN[11:0], BAPGAIN and CAPGAIN).

The gain of the ADC is adjusted by writing a 2’s complement

12-bit word to the Active Power Gain register. Below is the

expression that shows how the gain adjustment is related to

the contents of the Active Power Gain register.

Read from WAVEFORM

0

09 Hex

DIN

SGN

Current channel DATA - 24 bits

DOUT

Figure 9 – Waveform sampling current channel

The interrupt request output IRQ stays low until the interrupt

routine reads the Reset Status register - see ADE7754 Inter-

rupt.





AAPGAIN 





Code = ADC × 1 +







2¹²









Note: If the WSMP bit in the interrupt MASK register is not

For example when 7FFh is written to the Active Power Gain

register the ADC output is scaled up by 50%. 7FFh = 2047d,

2047/2¹²= 0.5. Similarly, 800h = -2047 Dec (signed 2’s

Complement) and ADC output is scaled by –50%. These two

examples are illustrated graphically in Figure 8.

set to logic one, no data is available in the Waveform register.

CURRENT RMS

CALCULATION

REFERENCE

WAVEFORM SAMPLE

Digital LPF

x1, x2, x4

MULTIPLIER

IAP

IAN

REGISTER

HPF

GAIN[1:0]

1

24

ACTIVE AND REACTIVE

POWER CALCULATION

3

Sinc

Vin

PGA1

ADC

12

Channel 1

Vin

800Hex - 7FFHex

AAPGAIN[11:0]

100% FS

3D70A3h

+ 150% FS

0.5 V / GAIN1

400000h

+ 100% FS

+ 50% FS

AAPGAIN[11:0]

28F5C2h

147AE1h

00000h

0V

+ 100% FS

- 100% FS

28F5C2h

- 50% FS

- 100% FS

- 150% FS

EB851Fh

D70A3Eh

C28F5Dh

Analog

Input

Range

000000h

000h

7FFh

800h

D70A3Eh

C00000h

ADC Output

word Range

Figure 8 - ADC and signal processing in current channel

–12–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

VOLTAGE CHANNEL ADC

Figure 10 shows the ADC and signal processing chain for the

Input VA in voltage channel (same for VB and VC).

Note LPF1 does not affect the power calculation since it is

used only in the Waveform sample mode.

When in waveform sample mode, one of four output sample

rates can be chosen by using bits 3 and 4 of the WAVMode

register. The available output sample rates are 26.0kSPS,

13.5kSPS, 6.5kSPS or 3.3kSPS. The interrupt request

output IRQ signals a new sample availability by going active

low. The voltage waveform register is a 2-complement 16-bit

register. As the Waveform register is a 24-bit signed register,

the waveform data from the voltage input is located in the 16

LSB of the Waveform register. The sign of the 16-bit voltage

input value is not extended to the upper byte of the waveform

register. The upper byte is instead filled with zeros. 24-bit

waveform samples are transferred from the ADE7754 one

byte (8-bits) at a time, with the most significant byte shifted

out first. The timing is the same as that for the current

channels and is shown in Figure 9.

x1, x2, x4

VAP

GAIN[6:5]

1

-100% to +100% FS

TO ACTIVE &

REACTIVE ENERGY

CALCULATION

VA

ADC

LPF1

16

VN

TO VOLTAGE RMS AND

WAVEFORM SAMPLING

VA

27E9h

LPF Output

word Range

0.5V

GAIN

0V

60Hz

D817h

2838h

60Hz

Analog

Input Range

50Hz

D7C8h

ZERO CROSSING DETECTION

The ADE7754 has rising edge zero crossing detection

circuits for each of voltage channels (V_AP, V_BP, or V_CP).

Figure 12 shows how the zero cross signal is generated from

the output of the ADC of the voltage channel.

Figure 10 – ADC and signal processing in voltage

channel

For Energy measurements, the output of the ADC (1 bit) is

passed directly to the multiplier and is not filtered. This

solution avoids a wide bits multiplier and does not affect the

accuracy of the measurement. A HPF is not required to

remove any DC offset since it is only required to remove the

offset from one channel to eliminate errors in the Power

calculation.

REFERENCE

x1, x2, x4

GAIN[6:5]

TO

V_AP, V_BP, V_CP

MULTIPLIER

1

-100% to +100% FS

V

PGA

ADC

V_N

In the voltage channel, the samples may also be routed to the

WFORM register (WAVMODE to select VA, VB or VC and

sampling frequency). However before being passed to the

Waveform register, the ADC output is passed through a

single pole, low pass filter with a cutoff frequency of 260Hz.

The plots in Figure 11 show the magnitude and phase

response of this filter. The filter output code of any inputs of

the voltage channel swings between D70Bh (-10,485d) and

28F5h (+10,485d) for full scale sinewave inputs.

Zero Crossing

Detection

ZERO

CROSS

LPF1

f

= 260Hz

-3dB

13 degrees @ 60Hz

1.0

0.95

IRQ

V

This has the effect of attenuating the signal. For example if

the line frequency is 60Hz, then the signal at the output of

LPF1 will be attenuated by 3%.

Read RSTATUS

1

Figure 12– Zero cross detection on Voltage Channel

H( f ) =

= 0.974 = −0.2dBs

2

60Hz

1+

The zero crossing interrupt is generated from the output of

LPF1. LPF1 has a single pole at 260Hz (CLKIN = 10MHz).

As a result there will be a phase lag between the analog input

signal of the voltage channel and the output of LPF1. The

phase response of this filter is shown in the Voltage channel

Sampling section of this data sheet. The phase lag response

of LPF1 results in a time delay of approximately 0.6ms (@

60Hz) between the zero crossing on the analog inputs of

Voltage channel and the falling of IRQ.

(

)

260 Hz

0°

0

(60Hz ; −0.2dB)

−20°

−40°

−60°

(60Hz ; −13°)

−20

When one phase crosses zero from negative to positive values

(rising edge), the corresponding flag in the Interrupt Status

register (bit 7-9) is set to logic one. An active-low in the IRQ

output will also appear if the corresponding ZX bit in the

Interrupt Mask register is set to logic one.

The flag in the Interrupt status register is reset to 0 when the

Interrupt status register with reset (RSTATUS) is read. Each

phase has its own interrupt flag and mask bit in the interrupt

register.

−40

10³

10¹

10²

Frequency (Hz)

Figure 11 – Magnitude & Phase response of LPF1

REV. PrG 01/03

–13–

PRELIMINARY TECHNICAL DATA

ADE7754

In addition to the MASK bits, the Zero crossing detection

interrupt of each phase is enabled/disabled by setting the

ZXSEL bits of the MMODE register (Addr. 0x0B) to logic

one or zero respectively.

The resolution of this register is 2.4µs/LSB when

CLKIN=10MHz, which represents 0.014% when the line

frequency is 60Hz. When the line frequency is 60Hz, the

value of the Period register is approximately 6944d. The

length of the register enables the measurement of line

frequencies as low as 12.7Hz.

Zero crossing Time out

Each zero crossing detection has an associated internal time-

out register (not accessible to the user). This unsigned,

16-bit register is decremented (1 LSB) every 384/CLKIN

seconds. The registers are reset to a common user pro-

grammed value -i.e. Zero Cross Time Out register

(ZXTOUT, Addr. 0x12) every time a zero crossing is

detected on its associated input. The default value of ZXTOUT

is FFFFh. If the internal register decrements to zero before

a zero crossing at the corresponding input is detected, it

indicates an absence of a zero crossing in the time determined

by the ZXTOUT. The ZXTO detection bit of the corre-

sponding phase in the Interrupt Status Register is then

switched on (bit 4-6). An active-low on the IRQ output will

also appear if the SAG mask bit for the corresponding phase

in the Interrupt Mask register is set to logic one.

LINE VOLTAGE SAG DETECTION

The ADE7754 can be programmed to detect when the

absolute value of the line voltage of any phase drops below a

certain peak value, for a number of half cycles. Each phase of

the voltage channel is controlled simultaneously. This con-

dition is illustrated in Figure 14 below.

V

, V , or V

AP BP

CP

Full Scale

SAGLVL[7:0]

SAG event reset low

when voltage channel

exceeds SAGLVL[7:0]

SAGCYC[7:0] = 06h

6 half cycles

In addition to the MASK bits, the Zero crossing Time out

detection interrupt of each phase is enabled/disabled by

setting the ZXSEL bits of the MMODE register (Addr.

0x0B) to logic one or zero respectively. When the zero

crossing Time out detection is disabled by this method, the

ZXTO flag of the corresponding phase is switched ON all the

time.

SAG Interrupt Flag

(Bit 1 to 3 of STATUS register)

Read RSTATUS register

Figure 13 shows the mechanism of the zero crossing time out

detection when the line voltage A stays at a fixed DC level for

more than CLKIN/384 x ZXTOUT seconds.

Figure 14 – ADE7754 Sag detection

Figure 14 shows a line voltage falling below a threshold

which is set in the Sag Level register (SAGLVL[7:0]) for

nine half cycles. Since the Sag Cycle register indicates a 6

half-cycle threshold (SAGCYC[7:0]=06h), the SAG event is

recorded at the end of the sixth half-cycle by setting the SAG

flag of the corresponding phase in the Interrupt status register

(bit 1 to 3 in the Interrupt Status register). If the SAG enable

bit is set to logic one for this phase (bit 1 to 3 in the Interrupt

Mask register), the IRQ logic output will go active low - see

ADE7754 Interrupts. All the phases are compared to the same

parameters defined in the SAGLVL and SAGCYC registers.

16-bit internal

register value

ZXTOUT

Voltage

channel A

ZXTOA

detection bit

Sag Level Set

The content of the Sag Level register (1 byte) is compared to

the absolute value of the most significant byte output from the

voltage channel ADC. Thus, for example, the nominal

maximum code from the voltage channel ADC with a full

scale signal is 28F5h —see Voltage Channel Sampling.

Therefore, writing 28h to the Sag Level register will put the

sag detection level at full scale and set the SAG detection to

its most sensitive value.

Writing 00h will put the Sag detection level at zero. The

detection of a decrease of an input voltage is in this case

hardly possible. The detection is made when the content of

the SAGLVL register is greater than the incoming sample.

Figure 13 - Zero crossingTime out detection

PERIOD MEASUREMENT

The ADE7754 provides also the period measurement of the

line voltage. The period is measured on the phase specified

by bit 0-1 of the MMODE register. The period register is an

unsigned 15-bit register and is updated every period of the

selected phase. Bit 0-1 and bit 4-6 of the MMODE register

select the phase for the period measurement, both selection

should indicate the same phase. The ZXSEL bits of the

MMODE register (bit 4-6) enable the phases on which the

Period measurement can be done. The PERDSEL bits select

the phase for Period measurement within the phases selected

by the ZXSEL bits.

–14–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

processed and placed in the Temperature register

(TEMP[7:0]). This register can be read by the user and has

an address of 08h -see ADE7754 Serial Interface section.

The contents of the Temperature register are signed (2's

complement) with a resolution of 4°C/LSB. The tempera-

ture register will produce a code of 00h when the ambient

temperature is approximately 129°C. The value of the

register will be : Temperature register = (Temperature (°C)

- 129)/4.

PEAK DETECTION

The ADE7754 can also be programmed to detect when the

absolute value of the voltage or the current channel of one

phase exceeds a certain peak value. Figure 15 illustrates the

behavior of the PEAK detection for the voltage channel.

V

, V , or V

AP BP

CP

VPEAK[7:0]

The temperature in the ADE7754 has an offset tolerance of

approximately 5°C. The error can be easily calibrated out

by an MCU.

PKV reset low

when RSTATUS register

is read

PKV Interrupt Flag

(Bit C of STATUS register)

Read RSTATUS register

Figure 15 - ADE7754 Peak detection

Bits 2-3 of the Measurement Mode register define the phase

supporting the peak detection. Both current and voltage of

this phase can be monitored at the same time. Figure 15

shows a line voltage exceeding a threshold which is set in the

Voltage peak register (VPEAK[7:0]). The Voltage Peak

event is recorded by setting the PKV flag in the Interrupt

Status register. If the PKV enable bit is set to logic one in the

Interrupt Mask register, the IRQ logic output will go active

low - see ADE7754 Interrupts.

Peak Level Set

The contents of the VPEAK and IPEAK registers are respec-

tively compared to the absolute value of the most significant

byte output of the selected voltage and current channels.

Thus, for example, the nominal maximum code from the

current channel ADC with a full scale signal is 28F5C2h —

see Current Channel Sampling.

Therefore, writing 28h to the IPEAK register will put the

current channel peak detection level at full scale and set the

current peak detection to its least sensitive value.

Writing 00h will put the current channel detection level at

zero. The detection is done when the content of the IPEAK

register is smaller than the incoming current channel sample.

TEMPERATURE MEASUREMENT

The ADE7754 also includes an on-chip temperature sensor.

A temperature measurement is made every 4/CLKIN sec-

onds. The output from the temperature sensing circuit is

connected to an ADC for digitizing. The resultant code is

REV. PrG 01/03

–15–

PRELIMINARY TECHNICAL DATA

ADE7754

PHASE COMPENSATION

However despite being internally phase compensated, the

ADE7754 must work with transducers which may have

inherent phase errors. For example a phase error of 0.1° to

0.3° is not uncommon for a CT (Current Transformer).

These phase errors can vary from part to part and they must

be corrected in order to perform accurate power calculations.

The errors associated with phase mismatch are particularly

noticeable at low power factors. The ADE7754 provides a

means of digitally calibrating these small phase errors. The

ADE7754 allows a small time delay or time advance to be

introduced into the signal processing chain in order to

compensate for small phase errors. Because the compensa-

tion is in time, this technique should only be used for small

phase errors in the range of 0.1° to 0.5°. Correcting large

phase errors using a time shift technique can introduce

significant phase errors at higher harmonics.

When the HPFs are disabled the phase error between the

current channel (IA, IB and IC) and the voltage channel (VA,

VB and VC) is zero from DC to 3.3kHz. When the HPFs are

enabled, the current channels have a phase response illus-

trated in Figure 16a & 16b. Also shown in Figure 16c is the

magnitude response of the filter. As can be seen from the

plots, the phase response is almost zero from 45Hz to 1kHz,

This is all that is required in typical energy measurement

applications.

0.07

0.06

0.05

0.04

Phase

(Degree)

0.03

The Phase Calibration registers (APHCAL, BPHCAL and

CPHCAL) are 2’s complement 5-bit signed registers which

can vary the time delay in the voltage channel signal path from

–19.2µs to +19.2µs (CLKIN = 10MHz). One LSB is

equivalent to 1.2µs. With a line frequency of 50Hz this gives

a phase resolution of 0.022° at the fundamental (i.e., 360° x

1.2µs x 50Hz).

0.02

0.01

0

-0.01

0

100 200 300 400 500 600 700 800 900 1000

Frequency (Hz)

Figure 17 illustrates how the phase compensation is used to

remove a 0.091° phase lead in IA of the current channel due

to some external transducer. In order to cancel the lead

(0.091°) in IA of the current channel, a phase lead must also

be introduced into VA of the voltage channel. The resolution

of the phase adjustment allows the introduction of a phase

lead of 0.086°. The phase lead is achieved by introducing a

time advance into VA. A time advance of 4.8µs is made by

writing -4 (1Ch) to the time delay block (APHCAL[4:0]),

thus reducing the amount of time delay by 4.8µs - see

Calibration of a 3-phase meter based on the ADE7754.

Figure 16a – Phase response of the HPF & Phase

Compensation (10Hz to 1kHz)

0.01

0.008

0.006

0.004

Phase

(Degree)

0.002

0

IAP

HPF

24

IA

PGA1

ADC

LPF2

IAN

-0.002

-0.004

24

PHASE

CALIBRATION

VAP

1

40

45

50

55

60

65

70

0.69Њ @ 50Hz, 0.022Њ

0.83Њ @ 60Hz, 0.024Њ

VA

PGA2

Frequency (Hz)

VN

V2

7

0

VA

0

0 0 1 1

1

0 0

IA

VA delayed by 4.8µs

(-0.086Њ @ 50Hz)

1Ch

APHCAL[4:0]

-19.2µs to +19.2µs

V1

Figure 16b - Phase response of the HPF & Phase

compensation (40Hz to 70Hz)

0.1Њ

0.01

0.008

0.006

0.004

50Hz

Figure 17 – Phase Calibration

Phase

(Degree)

0.002

0

-0.002

-0.004

44

46

48

50

52

54

56

Frequency (Hz)

Figure 16c – Gain response of HPF & Phase Compensation

(deviation of Gain as % of Gain at 54Hz)

–16–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

ROOT MEAN SQUARE MEASUREMENT

One LSB of the current RMS register is equivalent to one

LSB of a current waveform sample. The update rate of the

current RMS measurement is CLKIN/12.

With the specified full scale analog input signal of 0.5V, the

ADC will produce an output code which is approximately

2,684,354d - see Current channel ADC. The equivalent

RMS values of a full-scale AC signal and full scale DC signal

are respectively 1,898,124d (1CF68Ch) and 2,684,354d

(28F5C2h).

Root Mean Square (RMS) is a fundamental measurement of

the magnitude of an AC signal. Its definition can be both

practical and mathematical. Defined practically, the RMS

value assigned to an AC signal is the amount of DC required

to produce an equivalent amount of heat in the same load.

Mathematically: the RMS value of a continuous signal f(t) is

defined as:

With offset calibration, the current rms measurement pro-

vided in the ADE7754 is accurate within +/-2% for signal

input between Full scale and Full scale/100.

T

1

F

=

⋅ f ²t dt

( )

rms

(1)

∫

T

0

Note: A crosstalk between phases can appear in the ADE7754

current rms measurements. This crosstalk follows a specific

pattern: Current rms measurements of Phase A are corrupted

by the signal on the Phase C current input, Current rms

measurements of Phase B are corrupted by the signal on the

Phase A current input and Current rms measurements of

Phase C are corrupted by the signal on the Phase B current

input. This crosstalk is only present on the current rms

measurements and does not affect the regular Active power

measurements. The level of the crosstalk is dependent on the

level of the noise source and the phase angle between the noise

source and the corrupted signal. The level of the crosstalk can

be reduced by writing 0x01F7 to the address 0x3D. This 16-

bit register is reserved for factory operation and should not be

written to any other value.

For time sampling signals, rms calculation involves squaring

the signal, taking the average and obtaining the square root:

N

1

F

=

⋅

f ²(i)

(2)

∑

rms

N

i=1

The method used to calculate the RMS value in the ADE7754

is to low-pass filter the square of the input signal (LPF3) and

take the square root of the result.

With

then

V(t) = V_rms

⋅

2 ⋅sin ωt

(

)

2

V(t) × V(t) = V_rms− V_rms²⋅ cos 2ωt

(

)

The RMS calculation is simultaneously processed on the six

analog input channels. Each result is available on separate

registers.

When the current inputs are 120° out of phase and the register

0x3D is set to 0x01F7, the level of the current rms crosstalk

is below 2%.

Current RMS calculation

Figure 18 shows the detail of the signal processing chain for

the RMS calculation on one of the phases of the current

channel. The current channel RMS value is processed from

the samples used in the current channel waveform sampling

mode. It should be noticed that the APGAIN adjustment

affects the result of the RMS calculation - see Current RMS

Gain adjust. The current RMS values are stored in an

unsigned 24-bit registers (AIRMS, BIRMS and CIRMS).

I

(t)

rms

-100% to +100% FS

IRMSOS[11:0]

1CF68Ch

11 10

2

9

2

1

0

2

SGN

2

00h

+

LPF3

HPF

24

IA

IRMS

S

AAPGAIN

Current Channel (RMS)

2378EDh

Current Signal - i(t)

FS

+ 122.5% FS

+ 100% FS

+ 70.7% FS

1CF68Ch

147AE0h

0000h

400000h

28F5C2h

AAPGAIN[11:0]

- 70.7% FS

- 100% FS

- 122.5% FS

+ FS

- FS

EB8520h

E30974h

DC8713h

00000h

000h

7FFh

800h

D70A3Eh

C00000h

ADC Output

word Range

Figure 18 - Current RMS signal processing

REV. PrG 01/03

–17–

PRELIMINARY TECHNICAL DATA

ADE7754

that the maximum value from the Current RMS calculation

Current RMS Gain Adjust

is 1,898,124d with full scale AC inputs, then 1 LSB of the

current RMS offset represents 0.0058% of measurement

error at -40dB down of full scale.

The Active power Gain registers (AAPGAIN[11:0],

BAPGAIN and CAPGAIN) have an effect on the Active

Power and current rms values. It is not recommended to

calibrate the current rms measurements with these registers.

The conversion of the current rms registers values to Am-

peres has to be done in an external Micro-controller with a

specific Ampere/LSB constant for each phase - see Calibration

of a 3-phase meter based on the ADE7754. Due to gain

mismatches between phases, the calibration of the Ampere/

LSB constant has to be done for each phase separately. One

point calibration is sufficient for this calibration. The Active

Power Gain registers are aimed to ease the calibration of the

Active energy calculation in MODE 1 and 2 of the VAMODE

register.

I_rms

=

I_rms²+ IRMSOS × 32768

0

where I_rmsois the RMS measurement without offset correc-

tion.

The current rms offset compensation should be done by

testing the rms results at two non-zero input levels. One

measurement can be done close to full scale and the other at

approximately Full scale/100. The current offset compensa-

tion can then be derived from these measurements - see

Calibration of a 3-phase meter based on the ADE7754.

If the APGAIN registers are used for Active Power calibra-

tion (WATMOD bits in WATTMode register = 1 or 2), the

current rms values are changed by Active Power Gain register

value as described in the expression below:

Voltage RMS calculation

Figure 19 shows the details of the signal processing chain for

the RMS calculation on one of the phases of the voltage

channel. The voltage channel RMS value is processed from

the samples used in the voltage channel waveform sampling

mode. The output of the voltage channel ADC can be scaled

by 50% by changing VGAIN registers to perform an overall

Apparent power calibration -see Apparent Power calculation.

The VGAIN adjustment affects the RMS calculation as it is

done before the RMS signal processing. The voltage RMS

values are stored in unsigned 24-bit registers (AVRMS,

BVRMS and CVRMS). 256 LSB of the voltage RMS register

is approximately equivalent to one LSB of a voltage wave-

form sample. The update rate of the voltage RMS measurement

is CLKIN/12.

With the specified full scale AC analog input signal of 0.5V,

the LPF1 produces an output code which is approximately

10,217d at 60 Hz- see Voltage channel ADC. The equivalent

RMS value of a full-scale AC signal is approximately 7,221d

(1C35h), which gives a voltage RMS value of 1,848,772

(1C35C4h) in the VRMS register.





AAPGAIN

Current RMS Register phase A = RMS × 1 +

2¹²









For example, when 7FFh is written to the Active Power Gain

register, the ADC output is scaled up by 22.5%. Similarly,

800h = -2047d (signed 2’s Complement) and ADC output is

scaled by 29.3%. These two examples are illustrated graphi-

cally in Figure 18.

Current RMS offset compensation

The ADE7754 incorporates a current RMS offset compen-

sation for each phase (AIRMSOS, BIRMSOS and

CIRMSOS). These are 12-bit 2-complement signed regis-

ters which can be used to remove offsets in the current RMS

calculations. An offset may exist in the RMS calculation due

to input noises that are integrated in the DC component of

V²(t). The offset calibration will allow the contents of the

IRMS registers to be maintained at zero when no current is

being consumed.

With offset calibration, the voltage rms measurement pro-

vided in the ADE7754 is accurate within +/-0.5% for signal

input between Full scale and Full scale/20.

n LSB of the Current RMS offset are equivalent to 32768 x

n LSB of the square of the Current RMS register. Assuming

Voltage Signal - V(t)

VRMSOS[11:0]

0.5/GAIN2

11

8

2

1

0

2

SGN

2

LPF1

LPF3

⁺⁺S

24

V

A

12

800Hex - 7FFHex

AVGAIN[11:0]

Voltage Channel (RMS)

2A50A6h

Voltage Signal - v(t)

FS

+ 150% FS

+ 100% FS

+ 50% FS

1C35C4h

E1AE2h

0000h

4000h

28F5h

AVGAIN[11:0]

- 50% FS

- 100% FS

- 150% FS

+ FS

- FS

F1E51Eh

E3CA3Ch

D5AF5Ah

00000h

000h

7FFh

800h

D70Ah

C000h

ADC Output

word Range

Figure 19 -Voltage RMS signal processing

–18–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Voltage RMS Gain Adjust

ACTIVE POWER CALCULATION

The Voltage Gain register (AVGAIN[11:0], BVGAIN and

CVGAIN) have an effect on the Apparent Power and voltage

rms values. It is not recommended to calibrate the voltage

rms measurements with these registers. The conversion of

the voltage rms registers values to Volts has to be done in an

external Micro-controller with a specific Volt/LSB constant

for each phase - see Calibration of a 3-phase meter based on the

ADE7754. Due to gain mismatches between phases, the

calibration of the Volt/LSB constant has to be done for each

phase separately. One point calibration is sufficient for this

calibration. The Voltage Gain registers are aimed to ease the

calibration of the apparent energy calculation in MODE 1

and 2 of the VAMODE register.

Electrical power is defined as the rate of energy flow from

source to load. It is given by the product of the voltage and

current waveforms. The resulting waveform is called the

instantaneous power signal and it is equal to the rate of energy

flow at every instant of time. The unit of power is the watt or

joules/sec. Equation 5 gives an expression for the instanta-

neous power signal in an ac system.

(3)

(4)

v(t) = 2V sin(ωt)

i(t) = 2I sin(ωt)

where V = rms voltage, I = rms current.

p(t) = v(t) × i(t)

If the VGAIN registers are used for Apparent Power calibra-

tion (VAMOD bits in VAMode register = 1 or 2), the voltage

rms values are changed by Voltage Gain register value as

described in the expression below:

(5)

p(t) = VI - VI cos(2ωt)

The average power over an integral number of line cycles (n)

is given by the expression in Equation 6.





AVGAIN 







Voltage RMS Re gister Phase A = RMS × 1 +







2¹²







nT

1

nT

For example, when 7FFh is written to the Voltage Gain

register, the ADC output is scaled up by +50%. 7FFh =

2047d, 2047/2¹²= 0.5. Similarly, 800h = -2047 Dec (signed

2’s Complement) and ADC output is scaled by –50%. These

two examples are illustrated graphically in Figure 19.

P =

p(t)dt=VI

(6)

∫

0

where T is the line cycle period.

P is referred to as the Active or Real Power. Note that the

active power is equal to the DC component of the instanta-

neous power signal p(t) in Equation 5 , i.e., VI. This is the

relationship used to calculate active power in the ADE7754

for each phase. The instantaneous power signal p(t) is

generated by multiplying the current and voltage signals in

each phase. The DC component of the instantaneous power

signal in each phase (A, B and C) is then extracted by LPF2

(Low Pass Filter) to obtain the active power information on

each phase. This process is illustrated graphically on Figure

20. In a polyphase system, the total electrical power is simply

the sum of the real power in all active phases. The different

solutions available to process the total active power are

discussed in the following paragraph.

Voltage RMS offset compensation

The ADE7754 incorporates a voltage RMS offset compen-

sation for each phase (AVRMSOS, BVRMSOS and

CVRMSOS). These are 12-bit 2-complement signed regis-

ters which can be used to remove offsets in the voltage RMS

calculations. An offset may exist in the RMS calculation due

to input noises and offsets in the input samples. The offset

calibration allows the contents of the VRMS registers to be

maintained at zero when no voltage is applied.

n LSB of the Voltage RMS offset are equivalent to 64 x n LSB

of the voltage RMS register. Assuming that the maximum

value from the Voltage RMS calculation is 1,898,124d with

full scale AC inputs, then 1 LSB of the voltage RMS offset

represents 0.07% of measurement error at -26dB down of full

scale.

Instantaneous p(t)

V

I

V

I cos(2 t)

× ω

=

×

−

Power Signal

1A36E2Eh

Active Real Power

Signal = V x I

V_rms= V_rms+VRMSOS × 64

0

where V_rmsois the RMS measurement without offset correc-

tion.

V. I.

D1B717h

The voltage rms offset compensation should be done by

testing the rms results at two non-zero input levels. One

measurement can be done close to full scale and the other at

approximately Full scale/10. The voltage offset compensa-

tion can then be derived from these measurements - see

Calibration of a 3-phase meter based on the ADE7754.

00000h

Current

i(t)

2I sin( t )

ω

=

Voltage

2V sin( t )

v(t)

=

ω

Figure 20– Active Power Calculation

REV. PrG 01/03

–19–

PRELIMINARY TECHNICAL DATA

ADE7754

Since LPF2 does not have an ideal “brick wall” frequency

response—see Figure 21, the Active Power signal will have

some ripple due to the instantaneous power signal. This

ripple is sinusoidal and has a frequency equal to twice the line

frequency. Since the ripple is sinusoidal in nature, it is

removed when the Active Power signal is integrated to

calculate the Energy – see Energy Calculation.

Voltage channel 0.5V / GAIN2

Current channel 0.5V / GAIN1

Active Power

13A92A4h

+ 150% FS

D1B717h

+ 100% F5

+ 50% FS

68DB8Ch

0000000h

972474h

AAPGAIN[11:0] or

8Hz

AWGAIN[11:0]

0

- 50% FS

2E48E9h

EC56D5Ch

- 100% FS

- 150% FS

-4

-8

000h

7FFh 800h

-12

-16

-20

-24

Figure 23 – Active Power Calculation Output Range

Power Offset Calibration

The ADE7754 also incorporates an Active Offset register on

each phase (AAPOS, BAPOS and CAPOS). These are

signed 2’s complement 12-bit registers which can be used to

remove offsets in the active power calculations. An offset may

exist in the power calculation due to cross talk between

channels on the PCB or in the IC itself. The offset calibration

allows the contents of the Active Power register to be

maintained at zero when no power is being consumed.

1 LSBs in the Active Power Offset register is equivalent to 1

LSB in the 28-bit Energy bus displayed on Figure 22. Each

time power is added to the internal Active Energy register, the

content of the Active Power Offset register is added -see Total

Active Power calculation. Assuming the average value from

LPF2 is 8637BCh (8,796,092d) with full AC scale inputs on

current channel and voltage channel, then 1 LSB in the LPF2

output is equivalent to 0.011% of measurement error at -

60dB down of full scale - see Calibration of a 3-phase meter

based on the ADE7754.

3.0Hz

10Hz

Frequency

30Hz

1.0Hz

Figure 21– Frequency response of the LPF used to filter

Instantaneous Power in each phase

Figure 22 shows the signal processing in each phase for the

Active Power in the ADE7754.

Figure 23 shows the maximum code (Hexadecimal) output

range of the Active Power signal (after AWG). Note that the

output range changes depending on the contents of the Active

Power Gain and Watt Gain registers – see Current channel

ADC. The minimum output range is given when the Active

Power Gain and Watt Gain registers contents are equal to

800h and the maximum range is given by writing 7FFh to the

Active Power Gain and Watt Gain registers. These can be

used to calibrate the Active Power (or Energy) calculation in

the ADE7754 for each phase and also the Total Active

Energy -see Total Active Power calculation.

HPF

APOS[11:0]

Active Power

Signal - P

10

4

3

2

1

0

2

sgn sgn sgn sgn sgn

2

I

MULTIPLIER

24

Current Signal - i(t)

-100% to +100% FS

D1B717h

+

LPF2

28F5C2h

28

1V / GAIN1

00h

S

D70A3Eh

12

AWG

Instantaneous Power Signal - p(t)

1

V

Voltage Signal - v(t)

-100% to + 100% FS

28F5h

1V / GAIN2

00h

D70Bh

Figure 22 – Active Power Signal Processing

–20–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

*

Reverse Power Information

Note: I_A, I_Band I_Crepresent the current channels samples

after APGAIN correction and High-Pass Filtering.

The ADE7754 detects when the current and voltage channels

of any of the three phase inputs have a phase difference greater

than 90° i.e. |Φ_A| or |Φ_B| or |Φ_C| > 90°. This mechanism can

detect wrong connection of the meter or generation of Active

Energy.

For example, for WATMOD = 1, when all the gains and

offsets corrections are taken into consideration, the exact

formula that is used to process the Active Power is:

The Reverse power information is available for Phase A - B

and C respectively by reading bit12-14 of the CFNUM

register - see Table XI. The state of these bits represent the

sign of the active power of the corresponding phase. Logic

one corresponds to negative active power.

Total Active Power

=













AAPGAIN

BAPGAIN





AWG









V_A

⋅

1 +

⋅ I_A

−

1 +

⋅ I_B+ AAPOS ⋅ 1 +

























2¹²



















CAPGAIN

BAPGAIN



CWG

2¹²









+ V_C

⋅

1 +

⋅ I_C

−

1 +

⋅ I_B+ CAPOS ⋅ 1 +





















2¹²









The AENERGY phase selection bits (WATSEL bits of the

WATMode register) enable the negative power detection per

phase. If Phase A is enabled in the AENERGY accumulation

-bit 5 of WATMode register sets to logic one- the negative

power detection for Phase A -bit 12 of CFNUM register-

indicates the direction of the active energy. If Phase A is

disabled in the AENERGY register, the negative power bit

for Phase A is set to logic zero.

Depending on the polyphase meter service, the appropriate

formula should be chosen to calculate the Active power. The

American ANSI C12.10 standard defines the different con-

figurations of the meter. Table II describes which mode

should be chosen in these different configurations.

ANSI Meter Form

WATMOD

WATSEL

5S/13S

3-wire Delta

4-wire Wye

4-wire Delta

4-wire Wye

0

1

2

0

3 or 5 or 6

6S/14S

8S/15S

9S/16S

5

7

TOTAL ACTIVE POWER CALCULATION

The sum of the active powers coming from each phase gives

the total active Power consumption. Different combinations

of the three phases can be selected in the sum by setting bits

7-6 of the WATMode register (mnemonic WATMOD[1:0]).

Figure 24 demonstrates the calculation of the total active

power.

The total active power calculated by the ADE7754 depends

on the configuration of the WATMOD bits in the WATMode

register. Each term of the formula can be disabled or enabled

by setting WATSEL bits respectively to logic 0 or logic 1 in

the WATMode register. The different configurations are

described in Table I.

Table II - Meter form configuration

Different gain calibration parameters are offered in the

ADE7754 to cover the calibration of the meter in different

configurations. It should be noticed that in Mode 0, APGAIN

and WGAIN registers have the same effect on the end result.

In this case, APGAIN registers should be set at their default

value and the gain adjustment should be done with the

WGAIN registers.

WATMOD WATSEL0

WATSEL1

WATSEL2

*

0d

1d

2d

V_Ax I_A

+ V_Bx I_B

+ V_Cx I_C

V_Ax (I_A^*-I_B^*) + 0

+ V_Cx (I_C^*-I_B)

*

+ V_Cx I_C

Table I -Total Active Power calculation

0

*

I_B

-

AAPOS

HPF

I_A

S

+

LPF2

+

28

PHASE A*

AAPGAIN

S

1

V_A

AWGAIN

LPF2

Total Instantaneous

Power Signal

BAPOS

*

I_B

HPF

Active Power

Signal - P

+

I_B

28

2752545h

PHASE B*

S

1

BAPGAIN

V_B

BWGAIN

0

*

I_B

-

CAPOS

HPF

I_C

S

+

LPF2

+

28

PHASE C*

CAPGAIN

S

1

V_C

CWGAIN

Figure 24 –Total Active Power Consumption Calculation

REV. PrG 01/03

–21–

PRELIMINARY TECHNICAL DATA

ADE7754

ENERGY CALCULATION

register after a read. Two operations are held when reading

the RAENERGY register: Read and reset to zero the internal

Active Energy register. Only one operation is held when

reading the AENERGY register: read the internal Active

Energy register.

Figure 26 shows the energy accumulation for full scale

signals (sinusoidal) on the analog inputs. The three displayed

curves, illustrate the minimum time it takes the energy

register to roll-over, when the individual Watt Gain registers

contents are all equal to 3FFh, 000h and 800h. The Watt

Gain registers are used to carry out a power calibration in the

ADE7754. As shown, the fastest integration time occurs

when the Watt Gain registers are set to maximum full scale,

i.e., 3FFh.

As stated earlier, power is defined as the rate of energy flow.

This relationship can be expressed mathematically as

Equation 7.

dE

P =

(7)

dt

Where P = Power and E = Energy.

Conversely Energy is given as the integral of Power.

E= Pdt

(8)

∫

The ADE7754 achieves the integration of the Active Power

signal by continuously accumulating the Active Power signal

in an internal non-readable 54-bit Energy register. The

Active Energy register (AENERGY[23:0]) represents the

upper 24 bits of this internal register. This discrete time

accumulation or summation is equivalent to integration in

continuous time. Equation 9 below expresses the relationship

AENERGY[23:0]

7F,FFFFh

3F,FFFFh

00,0000h

AWG = BWG = CWG = 3FFh

AWG = BWG = CWG = 000h

AWG = BWG = CWG = 800h

∞













E= p(t)dt = Lim

p(nT)×T

∑

(9)

∫

T→0

n=0

Where n is the discrete time sample number and T is the

sample period.

44

88

176

132

220

264

The discrete time sample period (T) for the accumulation

register in the ADE7754 is 0.4µs (4/10MHz). As well as

calculating the Energy, this integration removes any sinusoi-

dal component which may be in the Active Power signal.

Figure 26 shows a graphical representation of this discrete

time integration or accumulation. The Active Power signal

is continuously added to the internal Energy register. This

addition is a signed addition, therefore negative energy will

be subtracted from the Active Energy contents.

40,0000h

80,0000h

Time

(seconds)

Figure 26 –Energy register roll-over time for full-scale

power (Minimum & Maximum Power Gain)

AENERGY[23:0]

23

0

Note that the Active Energy register contents roll over to full-

scale negative (80,0000h) and continue increasing in value

when the power or energy flow is positive -See Figure 26.

Conversely if the power is negative the energy register would

under flow to full scale positive (7F,FFFFh) and continue

decreasing in value.

53

0

WDIV

53

By using the Interrupt Enable register, the ADE7754 can be

configured to issue an interrupt (IRQ) when the Active

Energy register is half full (positive or negative).

T

0

+

TOTAL ACTIVE POWER

Σ

+

Active Power

Signal - P

TOTAL ACTIVE POWER ARE

ACCUMULATED (INTEGRATED) IN

THE ACTIVE ENERGY REGISTER

T

26667h

00000h

time (nT)

Figure 25 –ADE7754 Active Energy calculation

The 54-bit of the internal Energy register are divided by

WDIV. If the value in the WDIV register is equal to 0 then

the internal Active Energy register is divided by 1. WDIV is

an 8-bit unsigned register. The upper 24-bit of the result of

the division are then available in the 24-bit Active Energy

register. The AENERGY and RAENERGY registers read

the same internal Active energy register. They differ by the

the state in which they are leaving the internal Active energy

–22–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Integration times under steady load

If the value zero is written to any of these registers, the value

one would be applied to the register. The ratio CFNUM/

CFDEN should be smaller than one to assure proper opera-

tion. If the ratio of the registers CFNUM/CFDEN is greater

than one, the CF frequency can no longer be guaranteed to

be a consistent value.

For example if the output frequency is 18.744kHz while the

contents of CFDEN are zero (000h), then the output frequency

can be set to 6.103Hz by writing BFFh to the CFDEN

register.

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 0.4µs (4/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

Watt Gain registers set to 000h, the average word value from

each LPF2 is D1B717h - see Figures 20 and 22. The

maximum value which can be stored in the Active Energy

register before it over flows is 2²³-1 or 7F,FFFFh. As the

average word value is added to the internal register, which can

store 2⁵³- 1 or 1F,FFFF,FFFF,FFFFh before it overflows,

the integration time under these conditions with WDIV=0 is

calculated as follows:

The output frequency will have a slight ripple at a frequency

equal to twice the line frequency. This is due to imperfect

filtering of the instantaneous power signal to generate the

Active Power signal – see ACTIVE POWER CALCULATION.

Equation 5 gives an expression for the instantaneous power

signal. This is filtered by LPF2 which has a magnitude

response given by Equation 11.

1F,FFFF,FFFF,FFFFh

Time =

× 0.4µs = 88 s

3 × D1B717h

When WDIV is set to a value different from 0, the integration

time varies as shown on Equation 10.

1

Time = Time_WDIV=0x WDIV

(10)

H( f ) =

f ²

8²

The WDIV register can be used to increase the time before

the active energy register overflows, therefore reducing the

communication needs with the ADE7754.

(11)

1 +

The Active Power signal (output of the LPF2) can be

rewritten as.

Energy to Frequency Conversion

The ADE7754 also provides energy to frequency conversion

for calibration purposes. After initial calibration at manufac-

ture, the manufacturer or end customer will often verify the

energy meter calibration. One convenient way to verify the

meter calibration is for the manufacturer to provide an output

frequency which is proportional to the energy or active power

under steady load conditions. This output frequency can

provide a simple, single wire, optically isolated interface to

external calibration equipment. Figure 27 illustrates the

Energy to frequency conversion in the ADE7754.













VI

p(t) = VI −

⋅cos 4π f t

(

)

l

2

(12)

2f







1 +





^l











8

where f is the line frequency (e.g., 60Hz)

l

From Equation 8







CFNUM[11:0]

11

0





VI

Active Power

Phase A

E(t) = VIt −

⋅sin 4π f t

(

)



l

+

2

(13)

+

Active Power

Phase B

2f

8











^l

DFC

CF

Σ

4π f_l1 +









53 Total Active

Power

0



Active Power

Phase C

From Equation 13 it can be seen that there is a small ripple

in the energy calculation due to a sin(2ωt) component. This

is shown graphically in Figure 28. The ripple will get larger

as a percentage of the frequency at larger loads and higher

output frequencies. Choosing a lower output frequency at CF

for calibration can significantly reduce the ripple. Also

averaging the output frequency by using a longer gate time for

the counter will achieve the same results.

CFDEN[11:0]

11

0

Figure 27– ADE7754 Energy to Frequency Conversion

A Digital to Frequency Converter (DFC) is used to generate

the CF pulsed output. The DFC generates a pulse each time

one LSB in the Active Energy register is accumulated. An

output pulse is generated when CFDEN/CFNUM pulses are

generated at the DFC output. Under steady load conditions

the output frequency is proportional to the Active Power.

E(t)

VIt

The maximum output frequency (CFNUM=00h

&

CFDEN=00h) with full scale AC signals on the three phases

i.e. current channel and voltage channel is approximately

96kHz.

The ADE7754 incorporates two registers to set the frequency

of CF (CFNUM[11:0] and CFDEN[11:0]). These are

unsigned 12-bit registers which can be used to adjust the

frequency of CF to a wide range of values. These Frequency

scaling registers are 12-bit registers which can scale the

output frequency by 1/2¹²to 1 with a step of 1/2¹².









VI









sin 4 f_l

t

−

⋅

(

π

)

²

2f











^l



4

f 1

+

l

π









8

t

Figure 28 – Output frequency ripple

REV. PrG 01/03

–23–

PRELIMINARY TECHNICAL DATA

ADE7754

In this mode, the Reverse Power information available in the

No Load Threshold

CFNUM register is still detecting when negative active

power is present on any of the three phase inputs.

The ADE7754 includes a selectable “no load threshold” or

“start up current” feature that will eliminate any creep effects

in the active energy measurement of the meter. When

enabled, this function is independently applied on each

phase’s active power calculation. This mode is selected by

default and can be disabled by setting to logic one bit3 of the

GAIN register (Address 18h) - see Table X. Any load

generating an active power amplitude lower than the mini-

mum amplitude specified, will not be taken into account

when accumulating the active power from this phase.

The minimum instantaneous active power allowed in this

mode is 0.005% of the full scale amplitude. As the maximum

active power value is 13,743,895d with full scale analog

input, the no-load threshold is 687d. For example, an energy

meter with maximum inputs of 220V and 40A and Ib=10A,

the maximum instantaneous active power is 3,435,974d

assuming that both inputs represent half of the analog input

full scale . As the no-load threshold represents 687d, the start

up current represents 8mA or 0.08% of Ib.

LINE ENERGY ACCUMULATION

The ADE7754 is designed with a special energy accumula-

tion mode which simplifies the calibration process. By using

the on-chip zero-crossing detection, the ADE7754 accumu-

lates the Active Power signal in the LAENERGY register for

an integer number of half cycles, as shown in Figure 29. The

line active energy accumulation mode is always active.

Important: It is recommended to use this mode with only

one phase selected. If several phases are selected, the amount

accumulated can be smaller than it is supposed to be.

Each one of three phases zero-crossing detection can contrib-

ute to the accumulation of the half line cycles. Phase A, B and

C zero crossings are respectively taken into account when

counting the number of half line cycles by setting to logic one

bits 4-6 of the MMODE register. Selecting phases for the

Zero crossing counting has also the effect of enabling the

Zero-crossing detection, Zero-crossing Time-Out and Pe-

riod Measurement for the corresponding phase as described

in the Zero-crossing Detection paragraph.

The number of half line cycles is specified in the LINCYC

register. LINCYC is an unsigned 16-bit register. The

ADE7754 can accumulate Active Power for up to 65535

combined half cycles. Because the Active Power is integrated

on an integer number of line cycles, the sinusoidal compo-

nent is reduced to zero. This eliminates any ripple in the

energy calculation. Energy is calculated more accurately

because of this precise timing control. At the end of an energy

calibration cycle the LINCYC flag in the Interrupt Status

register is set. If the LINCYC mask bit in the Interrupt Mask

register is enabled, the IRQ output will also go active low.

Mode selection of the sum of the three active energies

The ADE7754 can be configured to execute the arithmetic

sum of the three active energies, Wh = Wh_φA

or the sum of the absolute value of these energies, Wh =

+ Wh_φΒ+ Wh_φC,

|

modes can be made by setting bit2 of the GAIN register

(Address 18h) - see Table X. Logic high and logic low of this

bit correspond respectively to the sum of absolute values and

the arithmetic sum. This selection affects the active energy

accumulation in the AENERGY, RAENERGY, LAENERGY

registers as well as for the CF frequency output.

When the sum of the absolute values is selected, the active

energy from each phase is always counted positive in the total

active energy. It is particularly useful in 3-phase 4-wire

installation where the sign of the active power should always

be the same. If the meter is misconnected to the power lines

i.e. CT connected in the wrong direction, the total active

energy recorded without this solution can be reduced by two

third. The sum of the absolute values assures that the active

energy recorded represents the actual active energy delivered.

LAENERGY[23:0]

23

0

51

0

ACCUMULATE ACTIVE POWER DURING

LINCYC ZERO-CROSSINGS

WDIV

Power Phase A

+

51

0

+

Power Phase B

Power Phase C

Σ

+

MMODE register

bit 4

LPF1

FROM VA

ADC

ZEROCROSS

DETECT

MMODE register

bit 5

LPF1

FROM VB

ADC

ZEROCROSS

DETECT

CALIBRATION

CONTROL

FROM VC

ADC

ZEROCROSS

DETECT

LINCYC[15:0]

MMODE register

bit 6

Figure 29 - ADE7754 Active Energy Calibration

–24–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Thus the IRQ line can also be used to signal the end of a

calibration. From Equations 8 and 12.

In normal mode, bit5 of WAVMODE register equals 0 the

type of active power summation in the LAENERGY register

(sum of absolute active power or arithmetic sum) is selected

by bit2 of the GAIN register.

In the mode where the Active powers are accumulated in the

LVAENERGY register, bit5 of WAVMODE register equals

1, it should be noticed that the sum of several active power is

always done ignoring the sign of the active powers. This is

due to the unsigned nature of the LVAENERGY register that

does not allow signed addition.













nT

VI

E(t) = VI dt −

⋅

cos 2π f t dt

(

)

∫

2

(14)

0

f

8







1 +

















where n is a integer and T is the line cycle period.

Since the sinusoidal component is integrated over an integer

number of line cycles, its value is always zero.

Therefore:

REACTIVE POWER CALCULATION

Reactive power is defined as the product of the voltage and

current waveforms when one of this signal is phase shifted by

90º at each frequency. It is defined mathematically in the

IEEE Standard Dictionary 100 as:

nT

E(t) = VI dt + 0

(15)

(16)

∫

0

∞

E(t) = VInT

Reactive Power = V ⋅ I ⋅sin ϕ

(

)

∑

n

n=1

The total active power calculated by the ADE7754 in the Line

accumulation mode depends on the configuration of the

WATMOD bits in the WATMode register. Each term of the

formula can be disabled or enabled by the LWATSEL bits of

the WATMode register. The different configurations are

described in Table III.

where V_nand I_nare respectively the voltage and current rms

values of the n^thharmonics of the line frequency, and ϕ_nis the

phase difference between the voltage and current n^thharmon-

ics. The resulting waveform is called the instantaneous

reactive power signal (VAR).

Equation 19 gives an expression for the instantaneous reac-

tive power signal in an ac system without harmonics when the

phase of the current channel is shifted by -90º.

WATMOD LWATSEL0

LWATSEL1 LWATSEL2

*

0

1

2

V_Ax I_A

+ V_Bx I_B

+ 0

+ V_Cx I_C

V_Ax (I_A^*-I_B

)

+ V_Cx (I_C^*-I_B

)

*

(17)

v(t) = 2 V₁sin(ωt − ϕ₁)

*

+ 0

+ V_Cx I_C

Π

2

i(t) = 2 I₁sin(ωt) i ’(t) = 2 I₁sin(ωt −

)

(18)

(19)

Table III -Total Line Active Energy calculation

VAR(t) = v(t) × i ’(t)

*

Note: I_A^*, I_Band I_Crepresent the current channels samples

VAR(t) = V₁I₁sin(ϕ₁) + V₁I₁sin(2ωt + ϕ₁)

after APGAIN correction and High-Pass Filtering.

Important: The Line Active Energy accumulation uses the

same signal path as the Active Energy accumulation. How-

ever, the LSB size of these two registers is different. If the

Line Active energy register and Active energy register are

accumulated during the same amount of time, the Line Active

energy register will be 4 times bigger than the Active Energy

register.

The average power over an integral number of line cycles (n)

is given by the expression in Equation 19.

nT

1

VAR =

VAR(t)dt = V₁I₁sin(ϕ₁)

(20)

∫

nT

0

where T is the line cycle period.

The LAENERGY register is also used to accumulate the

reactive energy by setting to logic one bit5 of the WAVMode

register (Add. 0Ch) - see reactive power calculation. When

this bit is set to one, the accumulation of the Active Energy

over half line cycles in the LAENERGY register is disabled

and is done instead in the LVAENERGY register. As the

LVAENERGY register is an unsigned value, the accumula-

tion of the active energy in the LVAENERGY register is

unsigned in this mode. The reactive energy is then accumu-

lated in the LAENERGY register - see Figure 31. In this

mode (reactive energy), the selection of the phases accumu-

lated in the LAENERGY and LVAENERGY registers is

done by the LWATSEL selection bits of the WATTMode

register.

VAR is referred to as the Reactive Power. Note that the

reactive power is equal to the DC component of the instan-

taneous reactive power signal VAR(t) in Equation 19. This is

the relationship used to calculate reactive power in the

ADE7754 for each phase. The instantaneous reactive power

signal VAR(t) is generated by multiplying the current and

voltage signals in each phase. In this case, the phase of the

current channel is shifted by -89º. The DC component of the

instantaneous reactive power signal in each phase (A, B and

C) is then extracted by a low pass filter to obtain the reactive

power information on each phase. In a polyphase system, the

total reactive power is simply the sum of the reactive power

in all active phases. The different solutions available to

process the total reactive power from the individual calcula-

tion are discussed in the following paragraph.

Figure 30 shows the signal processing in each phase for the

Reactive Power calculation in the ADE7754.

REV. PrG 01/03

–25–

PRELIMINARY TECHNICAL DATA

ADE7754

0

Important: As the phase shift applied on the current channel

is not -90º as it should be ideally, the reactive power

calculation done in the ADE7754 cannot be used directly for

the reactive power calculation. Consequently, it is recom-

mended to use the ADE7754 reactive power measurement

only to get the sign of the reactive power. The reactive power

can be processed using the power triangle method.

Active Power

LAENERGY

Register

1

Reactive Power

Apparent Power

0

1

LVAENERGY

Register

Bit5 WAVMode

Register

HPF

-89º

Reactive Power

Signal - P

I

Figure 31 - Selection of Reactive energy accumulation

MULTIPLIER

24

LPF

28

The features of the Reactive Energy accumulation are the

same as the Line Active Energy accumulation:

Each one of three phases zero-crossing detection can contrib-

ute to the accumulation of the half line cycles. Phase A, B and

C zero crossings are respectively taken into account when

counting the number of half line cycles by setting to logic one

bits 4-6 of the MMODE register. Selecting phases for the

Zero crossing counting has also the effect of enabling the

Zero-crossing detection, Zero-crossing Time-Out and Pe-

riod Measurement for the corresponding phase as described

int he Zero-crossing Detection paragraph.

The number of half line cycles is specified in the LINCYC

register. LINCYC is an unsigned 16-bit register. The

ADE7754 can accumulate Active Power for up to 65535

combined half cycles. At the end of an energy calibration

cycle the LINCYC flag in the Interrupt Status register is set.

If the LINCYC mask bit in the Interrupt Mask register is

enabled, the IRQ output will also go active low. Thus the IRQ

line can also be used to signal the end of a calibration.

Instantaneous Reactive

Power Signal - p(t)

1

V

Figure 30 - Reactive Power Signal Processing

TOTAL REACTIVE POWER CALCULATION

The sum of the Reactive powers coming from each phase

gives the Total Reactive Power consumption. Different

combinations of the three phases can be selected in the sum

by setting bits 7-6 of the WATMode register (mnemonic

WATMOD[1:0]). Each term of the formula can be disabled

or enabled by the LWATSEL bits of the WATMode register.

It should be noticed that in this mode, the LWATSEL bits

are also used to select the terms of the LVAENERGY

register. The different configurations are described in Table

III.

As explained in the Reactive Power paragraph, the purpose

of the reactive Energy calculation in the ADE7754 is not to

give an accurate measurement of this value but to to provide

the sign of the the reactive energy. The ADE7754 provides

an accurate measurement of the Apparent Energy. As the

active energy is also measured in the ADE7754, a simple

mathematical formula can be used to extract the Reactive

energy. The evaluation of the sign of the Reactive Energy

makes up the calculation of the Reactive Energy.

The accumulation of the Reactive Power in the LAENERGY

register is different from the accumulation of the Active

Power in the LAENERGY register. Under the same signal

conditions (e.g. Current and voltage channels at full scale),

if the accumulation of the active power with PF = 1 during

1 second is Wh₁and the accumulation of the reactive power

with PF = 0 during the same time is VARh₁, then Wh₁

=

9.546 x VAR₁.

*

Note: I_A^*, I_B^*and I_Crepresent the current channels samples

after APGAIN correction, High-Pass Filtering and -89º

phase shift in the case of Reactive Energy accumulation.

Reactive Energy =

sign Reactive Power × Apparent Energy²− Active Energy²

(

)

Reactive Energy accumulation selection

The ADE7754 accumulates the Total Reactive Power signal

in the LAENERGY register for an integer number of half

cycles, as shown in Figure 29. This mode is selected by

setting to logic one bit5 of the WAVMode register (Add.

0Ch). When this bit is set the accumulation of the Active

Energy over half line cycles in the LAENERGY register is

disabled and is done instead in the LVAENERGY register.

In this mode, the accumulation of the Apparent Energy over

half line cycles in the LVAENERGY is no-longer available

- See Figure 31.

–26–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

APPARENT POWER CALCULATION

Apparent Power

Apparent power is defined as the maximum active power that

can be delivered to a load. As Vrms and Irms are the effective

voltage and current delivered to the load, the Apparent Power

Voltage channel and Current channel 0.5V / GAIN

13A929h

D1B71h

+ 150% FS

+ 100% FS

+ 50% FS

(AP) is defined as V_rmsx I_rms

.

Note that the Apparent power is equal to the multiplication

of the RMS values of the voltage and current inputs. For a

poly-phase system, the RMS values of the current and voltage

inputs of each phase (A, B and C) are multiplied together to

obtain the apparent power information of each phase. The

total apparent power is the sum of the apparent powers of all

the phases. The different solutions available to process the

total apparent power are discussed in the following para-

graph.

68DB9h

AVAGAIN[11:0]

- 50% FS

00000h

F97247h

F2E48Fh

EC56D7h

- 100% FS

- 150% FS

000h

7FFh 800h

Figure 32 illustrates graphically the signal processing in each

phase for the calculation of the Apparent Power in the

ADE7754.

Figure 33 - Apparent Power Calculation Output range

Apparent Power Offset Calibration

24

I

Apparent Power

Signal - P

rms

Each RMS measurement includes an offset compensation

register to calibrate and eliminate the DC component in the

RMS value -see Current RMS calculation and Voltage RMS

calculation. The Voltage and Current RMS values are then

multiplied together in the Apparent Power signal processing.

As no additional offsets are created in the multiplication of

the RMS values, there is no specific offset compensation in

the Apparent Power signal processing. The offset compensa-

tion of the Apparent Power measurement in each phase is

done by calibrating each individual RMS measurements.

Current RMS Signal - i(t)

0.5V / GAIN1

D1B71h

1CF68Ch

24

00h

MULTIPLIER

12

24

AVAG

V

rms

Voltage RMS Signal - v(t)

0.5V / GAIN2

1CF68Ch

00h

TOTAL APPARENT POWER CALCULATION

The sum of the Apparent powers coming from each phase

gives the total Apparent Power consumption. Different com-

binations of the three phases can be selected in the sum by

setting bits 7-6 of the VAMode register (mnemonic

VAMOD[1:0]). Figure 34 demonstrates the calculation of

the total apparent power.

Figure 32 - Apparent Power Signal Processing

The Apparent Power is calculated with the Current and

Voltage RMS values obtained in the RMS blocks of the

ADE7754. Shown in Figure 33 is the maximum code

(Hexadecimal) output range of the Apparent Power signal for

each phase. Note that the output range changes depending on

the contents of the Apparent Power Gain registers but also on

the contents of the Active Power Gain and Voltage Gain

registers – see Current RMS calculation and Voltage RMS

calculation. Only the effect of the Apparent Power Gain is

shown on Figure 33. The minimum output range is given

when the Apparent Power Gain register content is equal to

800h and the maximum range is given by writing 7FFh to the

Apparent Power Gain register. This can be used to calibrate

the Apparent Power (or Energy) calculation in the ADE7754

for each phase and also the Total Apparent Energy -see Total

ApparentPowercalculation.

PHASE A*

I_A

RMS

24

AAPGAIN

AVGAIN

V_Arms

V_A

AVAGAIN

PHASE B*

I_B

RMS

Total Apparent

Power Signal

24

BAPGAIN

V_B

BVAGAIN

BVGAIN

V_Arms

+

S

+

V_Crms

2

PHASE C*

I_C

RMS

24

CAPGAIN

CVGAIN

V_Crms

V_C

CVAGAIN

Figure 34-Total Apparent Power calculation

REV. PrG 01/03

–27–

PRELIMINARY TECHNICAL DATA

ADE7754

The total apparent power calculated by the ADE7754 de-

pends on the configuration of the VAMOD bits in the

VAMode register. Each term of the formula can be disabled

or enabled by the setting VASEL bits respectively to logic 0

or logic 1 in the VAMode register. The different configura-

tions are described in Table IV.

APPARENT ENERGY CALCULATION

The Apparent Energy is given as the integral of the Apparent

Power.

Apparent Energy = Apparent Power(t) dt

(21)

∫

The ADE7754 achieves the integration of the Apparent

Power signal by continuously accumulating the Apparent

Power signal in an internal non-readable 49-bit register. The

Apparent Energy register (VAENERGY[23:0]) represents

the upper 24 bits of this internal register. This discrete time

accumulation or summation is equivalent to integration in

continuous time. Equation 22 below expresses the relation-

ship

VA-

VASEL0

VASEL1

VASEL2

MOD

0d

1d

2d

V_Armsx I_Arms+ V_Brmsx I_Brms

V_ArmsxI_Arms

V_Armsx I_Arms+ V_Armsx I_Brms

Table IV -Total Apparent Power calculation

+ V_Crmsx I_Crms

+(V_Arms+V_Crms)/2xI_Brms+ V_Crmsx I_Crms

+ V_Crmsx I_Crms

∞













Apparent Energy =Lim

Apparent Power(nT )×T

∑

(22)

Note: V_Arms, V_Brms, V_Crms, I_Arms, I_Brmsand I_Crmsrepresent

respectively the voltage and current channels RMS values of

the corresponding registers.

T→0

n=0

Where n is the discrete time sample number and T is the

sample period.

For example, for VAMOD = 1, the exact formula that is used

to process the Apparent Power is:

The discrete time sample period (T) for the accumulation

register in the ADE7754 is 1.2µs (12/10MHz).

Figure 35 shows a graphical representation of this discrete

time integration or accumulation. The Apparent Power

signal is continuously added to the internal register. This

addition is a signed addition even if the Apparent Energy

remains theoretically always positive.

AVAG





Total Apparent Power = V_Arms⋅ I_Arms⋅ 1 +







2¹²



V

(

+ V_Crms

)

BVAG

2¹²







Arms

+

⋅ I_Brms⋅ 1 +







2

CVAG

2¹²





VAENERGY[23:0]

+ V_Crms⋅ I_Crms⋅ 1 +







23

0



48

0

Depending on the polyphase meter configuration, the appro-

priate formula should be chosen to calculate the Apparent

Energy. The American ANSI C12.10 standard defines the

different configurations of the meter. Table V describes

which mode should be chosen in these different configura-

tions.

VADIV

48

T

0

TOTAL APPARENT POWER

+

Σ

+

ANSI Meter Form

VAMOD

VASEL

5S/13S

3-wire Delta

4-wire Wye

4-wire Delta

4-wire Wye

0

1

2

0

3 or 5 or 6

Apparent Power

Signal - P

6S/14S

8S/15S

9S/16S

7

TOTAL APPARENT POWER ARE

ACCUMULATED (INTEGRATED) IN

THE APPARENT ENERGY REGISTER

T

D1B71h

TableV - Meter form configuration

00000h

time (nT)

Different gain calibration parameters are offered in the

ADE7754 to cover the calibration of the meter in different

configurations. These registers, APGAIN, VGAIN and

VAGAIN, have different purposes in the signal processing of

the ADE7754.

APGAIN registers affect the Apparent power calculation but

should be used only for Active Power calibration. VAGAIN

registers are used to calibrate the Apparent Power calcula-

tion.

VGAIN registers have the same effect as VAGAIN registers

when VAMOD=0 or 2. They should be left at their default

value in these modes. VGAIN registers should be used to

compensate gain mismatches between channels in

VAMOD=1.

Figure 35-ADE7754 Apparent Energy calculation

The upper 49-bit of the internal register are divided by

VADIV. If the value in the VADIV register is equal to 0 then

the internal active Energy register is divided by 1. VADIV is

an 8-bit unsigned register. The upper 24-bit are then written

in the 24-bit Apparent Energy register (VAENERGY[23:0]).

RVAENERGY register (24 bits long) is provided to read the

Apparent Energy. This register is reset to zero after a read

operation.

As mentioned before, the offset compensation of the Phase

Apparent Power calculation is done in each individual RMS

measurement signal processing -see Apparent Power Offset com-

pensation.

–28–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Figure 36 shows this Apparent Energy accumulation for full

scale signals (sinusoidal) on the analog inputs. The three

curves displayed, illustrate the minimum time it takes the

energy register to roll-over when the individual VA Gain

registers contents are all equal to 3FFh, 000h and 800h. The

VA Gain registers are used to carry out an apparent power

calibration in the ADE7754. As shown, the fastest integration

time will occur when the VA Gain registers are set to

maximum full scale, i.e., 3FFh.

FFFF,FFFF,FFFFh before it overflows, the integration

time under these conditions with VADIV=0 is calculated as

follows:

FFFF,FFFF,FFFFh

Time =

× 1.2µs = 131 s = 2 min 11 s

3 × D1B71h

When VADIV is set to a value different from 0, the integra-

tion time varies as shown on Equation 23.

Time = Time_WDIV=0x VADIV

(23)

AVAG = BVAG = CVAG = 3FFh

AVAG = BVAG = CVAG = 000h

VAENERGY[23:0]

LINE APPARENT ENERGY ACCUMULATION

The ADE7754 is designed with a special Apparent Energy

accumulation mode which simplifies the calibration process.

By using the on-chip zero-crossing detection, the ADE7754

accumulates the Apparent Power signal in the LVAENERGY

register for an integral number of half cycles, as shown in

Figure 37. The line Apparent energy accumulation mode is

always active.

AVAG = BVAG = CVAG = 800h

7F,FFFFh

3F,FFFFh

00,0000h

65.5

131

262

196.5

327.5

393

40,0000h

80,0000h

Each one of three phases zero-crossing detection can contrib-

ute to the accumulation of the half line cycles. Phase A, B and

C zero crossings are taken into account when counting the

number of half line cycle by setting to logic one bits 4-6 of

the MMODE register. Selecting phases for the Zero crossing

counting has also the effect of enabling the Zero-crossing

detection, Zero-crossing Time-Out and Period Measure-

ment for the corresponding phase as described in the

Zero-crossing Detection paragraph.

The number of half line cycles is specified in the LINCYC

register. LINCYC is an unsigned 16-bit register. The

ADE7754 can accumulate Apparent Power for up to 65535

combined half cycles. Because the Apparent Power is inte-

grated on the same integral number of line cycles as the Line

Active Energy register, these two values can be compared

easily - see Energy Scaling. The active and apparent Energy

are calculated more accurately because of this precise timing

control and provide all the information needed for Reactive

Power and Power Factor calculation. At the end of an energy

calibration cycle the LINCYC flag in the Interrupt Status

register is set. If the LINCYC mask bit in the Interrupt Mask

register is enabled, the IRQ output will also go active low.

Thus the IRQ line can also be used to signal the end of a

calibration.

Time

(seconds)

Figure 36 - Energy register roll-over time for full-scale

power (Minimum & Maximum Power Gain)

Note that the Apparent Energy register contents roll-over to

full-scale negative (80,0000h) and continue increasing in

value when the power or energy flow is positive - see Figure

36.

By using the Interrupt Enable register, the ADE7754 can be

configured to issue an interrupt (IRQ) when the Apparent

Energy register is half full (positive or negative).

Integration times under steady load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.2µs (12/

CLKIN). With full-scale sinusoidal signals on the analog

inputs and the VA Gain registers set to 000h, the average

word value from each Apparent Power stage is D1B71h - see

Apparent Power output range. The maximum value which can be

2^st²^o³^re-^d1oⁱⁿr ^tF^hF^e,F^AF^pF^pF^arh^e.^ntAs^Enth^ere^gyav^re^er^gaⁱg^se^terwo^br^ed^forv^ealu^ite^oi^vs^era^-d^fld^oe^wd^stⁱo^s

the internal register which can store 2⁴⁸

-

1

or

ACCUMULATE APPARENT POWER DURING

LINCYC ZERO-CROSSINGS

LVAENERGY[23:0]

23

0

Apparent Power

Phase A

+

48

0

+

Apparent Power

Phase B

Σ

+

Apparent Power

Phase C

MMODE register

bit 4

LPF1

VADIV

FROM VA

ADC

ZEROCROSS

DETECT

MMODE register

bit 5

LPF1

FROM VB

ADC

ZEROCROSS

DETECT

CALIBRATION

CONTROL

FROM VC

ADC

ZEROCROSS

DETECT

LINCYC[15:0]

MMODE register

bit 6

Figure 37 - ADE7754 Apparent Energy Calibration

REV. PrG 01/03

–29–

PRELIMINARY TECHNICAL DATA

ADE7754

CHECK SUM REGISTER

The total apparent power calculated by the ADE7754 in the

Line accumulation mode depends on the configuration of the

VAMOD bits in the VAMode register. Each term of the

formula can be disabled or enabled by the LVASEL bits of

the VAMode register. The different configurations are de-

scribed in Table VI.

The ADE7754 has a check sum register (CHECKSUM[5:0])

to ensure the data bits received in the last serial read

operation are not corrupted. The 6-bit Checksum register is

reset before the first bit (MSB of the register to be read) is

put on the DOUT pin. During a serial read operation, when

each data bit becomes available on the rising edge of SCLK,

the bit will be added to the Checksum register. In the end of

the serial read operation, the content of the Checksum

register will equal to the sum of all ones in the register

previously read. Using the Checksum register, the user can

determine if an error has occurred during the last read

operation.

VA-

VASEL0

VASEL1

VASEL2

MOD

0d

1d

2d

V

_Armsx I_Arms+ V_Brmsx I_Brms

+ V_Crmsx I_Crms

V_ArmsxI_Arms+(V_Arms+V_Crms)/2xI_Brms+ V_Crmsx I_Crms

V_Armsx I_Arms+ V_Armsx I_Brms+ V_Crmsx I_Crms

TableVI -Total Line Apparent Energy calculation

Note that a read to the Checksum register will also generate

a checksum of the Checksum register itself.

The Line Apparent Energy accumulation uses the same

signal path as the Apparent Energy accumulation. The LSB

size of these two registers is equivalent.

CONTENT OF REGISTER (n-bytes)

DOUT

CHECKSUM REGISTER ADDR: 3EH

The ADE7754 accumulates the Total Reactive Power signal

in the LAENERGY register. This mode is selected by setting

to logic one bit5 of the WAVMode register (Add. 0Ch).

When this bit is set the accumulation of the Active Energy

over half line cycles in the LAENERGY register is disabled

and is done instead in the LVAENERGY register. In this

mode, the accumulation of the Apparent Energy over half line

cycles in the LVAENERGY is no-longer available - see

Figure 31. As the LVAENERGY register is an unsigned

value, the accumulation of the active energy in the

LVAENERGY register is unsigned. In this mode (reactive

energy), the selection of the phases accumulated in the

LAENERGY and LVAENERGY registers is done by the

LWATSEL selection bits of the WATMode register.

Σ

Figure 38 - Checksum register for Serial Interface Read

ENERGIES SCALING

The ADE7754 provides measurements of the Active, Reac-

tive and Apparent energies. These measurements do not have

the same scaling and cannot be compared directly to each

others.

When measuring the different energies with the ADE7754

with 50Hz signals at different power factor, the ratio between

the energies is:

PF=1

PF=0.707

PF=0

Active

Energy

Wh

Wh x 0.707

0

Reactive

Energy

0

Wh x 0.707 / 9.546 Wh / 9.546

Apparent Wh / 3.657 Wh / 3.657

Wh / 3.657

Energy

–30–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

struction followed must be a write to the Communications

register.

ADE7754 SERIAL INTERFACE

ADE7754 has a built-in SPI interface. The Serial Interface

of the ADE7754 is made of four signals SCLK, DIN,

DOUT and CS. The serial clock for a data transfer is applied

at the SCLK logic input. This logic input has a Schmidt-

trigger input structure, which allows slow rising (and falling)

clock edges to be used. All data transfer operations are

synchronized to the serial clock. Data is shifted into the

ADE7754 at the DIN logic input on the falling edge of

SCLK. Data is shifted out of the ADE7754 at the DOUT

logic output on a rising edge of SCLK. The CS logic input

is the chip select input. This input is used when multiple

devices share the serial bus. A falling edge on CS also resets

the serial interface and places the ADE7754 in communica-

tions mode. The CS input should be driven low for the entire

data transfer operation. Bringing CS high during a data

transfer operation will abort the transfer and place the serial

bus in a high impedance state. The CS logic input may be tied

low if the ADE7754 is the only device on the serial bus.

However with CS tied low, all initiated data transfer opera-

tions must be fully completed, i.e., the LSB of each register

must be transferred as there is no other way of bringing the

ADE7754 back into communications mode without resetting

the entire device, i.e., setting the RESET pin logic low.

All the ADE7754 functionality is accessible via several on-

chip registers – see Figure 39. The contents of these registers

can be updated or read using the on-chip serial interface.

After power-on or toggling the RESET pin low or a falling

edge on CS, the ADE7754 is placed in communications

mode. In communications mode the ADE7754 expects the

first communication to be a write to the internal Communi-

cations register. The data written to the Communications

register contains the address and specifies the next data

transfer to be a read or a write command. Therefore all data

transfer operations with the ADE7754, whether a read or a

write, must begin with a write to the Communications

register.

CS

SCLK

COMMUNICATIONS REGISTER WRITE

DIN

0

ADDRESS

MULTIBYTE READ DATA

DOUT

Figure 40 – Reading data from the ADE7754 via the

serial interface

CS

SCLK

COMMUNICATIONS REGISTER WRITE

DIN

1

0

MULTIBYTE WRITE DATA

ADDRESS

Figure 41 – Writing data to the ADE7754 via the

serial interface

A data transfer is completed when the LSB of the ADE7754

register being addressed (for a write or a read) is transferred

to or from the ADE7754.

ADE7754 Serial Write Operation

The serial write sequence takes place as follows: with the

ADE7754 in communications mode and the CS input logic

low, a write to the communications register first takes place.

The MSB of this byte transfer must be set to 1, indicating that

the next data transfer operation is a write to the register. The

six LSBs of this byte contain the address of the register to be

written to. The ADE7754 starts shifting in the register data

on the next falling edge of SCLK. All remaining bits of

register data are shifted in on the falling edge of subsequent

SCLK pulses – see Figure 42.

As explained earlier the data write is initiated by a write to the

Communications register followed by the data. During a data

write operation to the ADE7754, data is transferred to all on-

chip registers one byte at a time. After a byte is transferred

into the serial port, there is a finite time duration before the

content in the serial port buffer is transferred to one of the

ADE7754 on-chip registers. Although another byte transfer

to the serial port can start while the previous byte is being

transferred to the destination register, this second byte

transfer should not finish until at least TBD after the end of

the previous byte transfer. This functionality is expressed in

the timing specification t₆- see Figure 42. If a write operation

is aborted during a byte transfer (CS brought high), then that

byte will not be written to the destination register.

Destination registers may be up to 3 bytes wide – see

ADE7754 Register Descriptions. Hence the first byte shifted

into the serial port at DIN is transferred to the MSB (Most

significant Byte) of the destination register. If the destination

register is 12 bits wide, for example, a two-byte data transfer

must take place. The data is always assumed to be right

justified, therefore in this case, the four MSBs of the first byte

would be ignored and the 4 LSBs of the first byte written to

the ADE7754 would be the 4MSBs of the 12-bit word.

Figure 43 illustrates this example.

DIN

COMMUNICATIONS REGISTER

REGISTER # 1

IN

DOUT

OUT

IN

OUT

REGISTER # 2

IN

OUT

REGISTER # 3

IN

OUT

REGISTER # n-1

REGISTER # n

IN

OUT

Figure 39– Addressing ADE7754 Registers via the

CommunicationsRegister

The Communications register is an eight bit write only

register. The MSB determines whether the next data transfer

operation is a read or a write. The 6 LSBs contain the address

of the register to be accessed. See ADE7754 Communications

Register for a more detailed description.

Figure 40 and Figure 41 show the data transfer sequences for

a read and write operation respectively.

On completion of a data transfer (read or write) the ADE7754

once again enters communications mode, i.e. the next in-

REV. PrG 01/03

–31–

PRELIMINARY TECHNICAL DATA

ADE7754

t

8

CS

t

1

6

2

3

t

7

SCLK

DIN

t

4

t

5

DB0

Most Significant Byte

DB7

0

DB7

DB0

A1

1

A5 A4 A3 A2

Command Byte

A0

Least Significant Byte

Figure 42– Serial Interface Write Timing Diagram

SCLK

DIN

DB9

DB11

DB8

DB4

DB10

DB5

DB0

DB1

DB6

DB3

X

DB7

DB2

Most Significant Byte

Least Significant Byte

Figure 43—12 bit Serial Write Operation

ADE7754 Serial Read Operation

again as soon as the read has been completed. The DOUT

logic output enters a high impedance state on the falling edge

of the last SCLK pulse. The read operation may be aborted

by bringing the CS logic input high before the data transfer

is completed. The DOUT output enters a high impedance

state on the rising edge of CS.

During a data read operation from the ADE7754 data is

shifted out at the DOUT logic output on the rising edge of

SCLK. As was the case with the data write operation, a data

read must be preceded with a write to the Communications

register.

With the ADE7754 in communications mode and CS logic

low an eight bit write to the Communications register first

takes place. The MSB of this byte transfer must be a 0,

indicating that the next data transfer operation is a read. The

six LSBs of this byte contain the address of the register which

is to be read. The ADE7754 starts shifting out of the register

data on the next rising edge of SCLK – see Figure 44. At this

point the DOUT logic output switches from high impedance

state and starts driving the data bus. All remaining bits of

register data are shifted out on subsequent SCLK rising

edges. The serial interface enters communications mode

When an ADE7754 register is addressed for a read operation,

the entire contents of that register are transferred to the Serial

port. This allows the ADE7754 to modify its on-chip

registers without the risk of corrupting data during a multi

byte transfer.

Note: when a read operation follows a write operation, the

read command (i.e., write to communications register)

should not happen for at least TBD after the end of the write

operation. If the read command is sent within TBD of the

write operation, the last byte of the write operation may be

lost. The is given as timing specification t¹⁵

.

CS

t

1

t

14

t

10

9

SCLK

DIN

0

A1

A5 A4 A3 A2

A0

t

13

t

12

11

DB0

DB7

DB0

DB7

DOUT

Least Significant

Byte

Most Significant

Byte

Command

Byte

Figure 44– Serial Interface Read Timing Diagram

–32–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

using the global interrupt mask bit. At this point the MCU

external interrupt flag can be cleared in order to capture

interrupt events which occur during the current ISR. When

the MCU interrupt flag is cleared, a read from the Reset

Interrupt Status register with reset is carried out. This will

cause the IRQ line to be reset logic high (t₂)—see Interrupt

timing. The Reset Interrupt Status register contents are used

to determine the source of the interrupt(s) and hence the

appropriate action to be taken. If a subsequent interrupt event

occurs during the ISR (t₃), that event will be recorded by the

MCU external interrupt flag being set again. On returning

from the ISR, the global interrupt mask bit will be cleared

(same instruction cycle) and the external interrupt flag will

cause the MCU to jump to its ISR once again. This will

ensure that the MCU does not miss any external interrupts.

ADE7754 INTERRUPTS

ADE7754 Interrupts are managed through the Interrupt

Status register (STATUS[15:0], Address 10h) and the Inter-

rupt Mask register (MASK[15:0], Address 0Fh). When an

interrupt event occurs in the ADE7754, the corresponding

flag in the Interrupt Status register is set to a logic one - see

ADE7754 Interrupt Status register. If the mask bit for this interrupt

in the Interrupt Mask register is logic one, then the IRQ logic

output goes active low. The flag bits in the Interrupt Status

register are set irrespective of the state of the mask bits.

In order to determine the source of the interrupt, the system

master (MCU) should perform a read from the Reset Inter-

rupt Status register with reset. This is achieved by carrying

out a read from address 11h. The IRQ output will go logic

high on completion of the Interrupt Status register read

command—see Interrupt timing. When carrying out a read with

reset the ADE7754 is designed to ensure that no interrupt

events are missed. If an interrupt event occurs just as the

Interrupt Status register is being read, the event will not be

lost and the IRQ logic output is guaranteed to go high for the

duration of the Interrupt Status register data transfer before

going logic low again to indicate the pending interrupt.

Interrupt timing

The ADE7754 Serial Interface section should be reviewed first

before reviewing the interrupt timing. As previously de-

scribed, when the IRQ output goes low the MCU ISR must

read the Interrupt Status register in order to determine the

source of the interrupt. When reading the Interrupt Status

register contents, the IRQ output is set high on the last falling

edge of SCLK of the first byte transfer (read Interrupt Status

register command). The IRQ output is held high until the last

bit of the next 8-bit transfer is shifted out (Interrupt Status

register contents). See Figure 46. If an interrupt is pending

at this time, the IRQ output will go low again. If no interrupt

is pending the IRQ output will remain high.

Using the ADE7754 Interrupts with an MCU

Shown in Figure 45 is a timing diagram which illustrates a

suggested implementation of ADE7754 interrupt manage-

ment using an MCU. At time t₁the IRQ line will go active

low indicating that one or more interrupt events have oc-

curred in the ADE7754. The IRQ logic output should be tied

to a negative edge triggered external interrupt on the MCU.

On detection of the negative edge, the MCU should be

configured to start executing its Interrupt Service Routine

(ISR). On entering the ISR, all interrupts should be disabled

MCU

int. flag set

t

3

t

2

t

1

IRQ

Read

Status with

Reset (11h)

ISR Return

Program

Sequence

ISR Action

Jump to

Global int.

Mask

Clear MCU

int. flag

Jump to

ISR

Global int. Mask

( Based on Status contents)

ISR

Reset

Figure 45– ADE7754 interrupt management

CS

t

1

t

9

SCLK

DIN

0

1

t

12

11

DB0

DB15

DB8

DB7

DOUT

Read Status Register Command

Status Register Contents

IRQ

Figure 46– ADE7754 interrupt timing

–33–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

ACCESSING THE ADE7754 ON-CHIP REGISTERS

All ADE7754 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the

communications register and then transferring the register data. For a full description of the serial interface protocol, see Serial

Interface section of this data sheet.

Communications Register

The Communications register is an eight bit, write-only register which controls the serial data transfer between the ADE7754

and the host processor. All data transfer operations must begin with a write to the communications register. The data written

to the communications register determines whether the next operation is a read or a write and which register is being accessed.

Table VII below outlines the bit designations for the Communications register.

Table VII : Communications Register

Bit

Location

Bit

Mnemonic

Description

0 to 5

A0 to A5

The six LSBs of the Communications register specify the register for the data transfer

operation. Table VIII lists the address of each ADE7754 on-chip register.

6

7

RESERVED

This bit is unused and should be set to zero.

W/R

When this bit is a logic one the data transfer operation immediately following the write to the

Communications register will be interpreted as a write to the ADE7754. When this bit is a logic

zero the data transfer operation immediately following the write to the Communications

register will be interpreted as a read operation.

DB6

0

DB5

A5

DB4

A4

DB1

A1

DB0

A0

DB7

W/R

DB3

A3

DB2

A2

–34–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Table VIII. ADE7754 REGISTER LIST

Default

Address

[A5:A0] Name

R/W* Length Value

Description

00h

01h

Reserved

AENERGY

-

R

Reserved.

24

0

Active Energy register. Active power is accumulated over time in

an internal register. The AENERGY register is a read only regis-

ter that reads this internal register and can hold a minimum of 88

seconds of active energy information with full-scale analog inputs

before it overflows - See Energy Calculation. Bit 7 to 3 of the

WATMODE register determine how the Active energy is pro-

cessed from the six Analog inputs - see Table XIV.

02h

03h

RAENERGY

LAENERGY

R

24

0

Same as the AENERGY register, except that the internal register

is reset to zero following a read operation.

Line Accumulation Active Energy register. The instantaneous

active power is accumulated in this read-only register over the

LINCYC number of half line cycles. Bit 2 to 0 of the

WATMODE register determines, how the Line Accumulation

Active energy is processed from the six Analog inputs - see Table

XIV.

04h

VAENERGY

R

24

0

VA Energy register. Apparent power is accumulated over time in

this read-only register. Bit 7 to 3 of the VAMODE register deter-

mines, how the Apparent energy is processed from the six Analog

inputs - see Table XV.

05h

06h

RVAENERGY R

LVAENERGY R

24

0

Same as the VAENERGY register except that the register is reset

to zero following a read operation.

Apparent Energy register. The instantaneous Apparent power is

accumulated in this read-only register over the LINCYC number

of half line cycles. Bit 2 to 0 of the VAMODE register determines

how the Apparent energy is processed from the six Analog inputs

- see Table XV.

07h

08h

PERIOD

TEMP

R

15

8

0

Period of the line input estimated by Zero-crossing processing.

Data bits 0 to 1 and 4 to 6 of the MMODE register determines

the voltage channel used for Period calculation - see table XII.

Temperature register. This register contains the result of the lat-

est temperature conversion. Please refer to Temperature Measurement

section on this datasheet for details on how to interpret the con-

tent of this register.

09h

WFORM

R

24

0

Waveform register. This register contains the digitized waveform

of one of the six analog inputs. The source is selected by data

bits 0 to 2 in the WAVMode register - see Table XIII.

Operational Mode Register. This register defines the general

configuration of the ADE7754. See Table IX.

Measurement Mode register. This register defines the channel

used for Period and Peak detection measurements. See Table XII.

Waveform Mode register. This register defines the channel and

the sampling frequency used in Waveform sampling mode. See

TableXIII.

0Ah

0Bh

0Ch

OPMODE

MMODE

R/W

8

4

70h

0

WAVMODE R/W

0Dh

0Eh

0Fh

10h

11h

WATMODE R/W

8

3Fh

0

This register configures the formula applied for the Active Energy

and Line active energy measurements. See Table XIV.

This register configures the formula applied for the Apparent

Energy and Line Apparent Energy measurements. See Table XV.

IRQ Mask register. It determines if an interrupt event will gener-

ate an active-low output at IRQ pin - see Table XVI.

IRQ Status register. This register contains information regarding

the source of ADE7754 interrupts - see Table XVII.

Same as the STATUS register. Except that its contents are reset

to zero (all flags cleared) after a read operation.

VAMODE

MASK

R/W

R

8

16

STATUS

RSTATUS

0

R

0

REV. PrG 01/03

–35–

PRELIMINARY TECHNICAL DATA

ADE7754

Address

[A5:A0] Name

Default

R/W* Length Value

Description

12h

ZXTOUT

R/W

16

FFFFh

Zero Cross Time Out register. If no zero crossing is detected

within a time period specified by this register the interrupt request

line (IRQ) will go active low for the corresponding line voltage.

The maximum time-out period is 2.3 seconds - see Zero Crossing

Detection.

13h

14h

LINCYC

SAGCYC

R/W

16

8

FFFFh

FFh

Line Cycle register. The content of this register sets the

number of half line cycles while the active energy and the appar-

ent energy are accumulated in the LAENERGY and

LVAENERGY registers - See Energy Calibration.

Sag Line Cycle register. This register specifies the number of

consecutive half-line cycles where voltage channel input falls be-

low a threshold level. This register is common to the three line

voltage SAG detection. The detection threshold is specified by

SAGLVL register - See Voltage SAG Detection.

15h

SAGLVL

R/W

8

0

SAG Voltage Level. This register specifies the detection threshold

for SAG event. This register is common to the three line voltage

SAG detection. See the description of SAGCYC register for de-

tails.

16h

17h

18h

VPEAK

IPEAK

GAIN

R/W

8

FFh

0

Voltage Peak Level. This register sets the level of the voltage

peak detection. If the selected voltage phase exceeds this level, the

PKV flag in the status register is set - See Table XII.

Current Peak Level. This register sets the level of the current

peak detection. If the selected current phase exceeds this level, the

PKI flag in the status register is set - See Table XII.

PGA Gain register. This register is used to adjust the gain selec-

tion for the PGA in current and voltage channels - See Analog

Inputs and Table X. This register is also used to configuration of

the active energy accumulation - No-load threshold and sum of

absolute values.

19h

AWG

R/W

12

0

Phase A Active Power Gain register. This register calculation can

be calibrated by writing to this register. The calibration range is

50% of the nominal full scale active power. The resolution of the

gain adjust is 0.0244% / LSB.

1Ah

1Bh

1Ch

BWG

CWG

AVAG

R/W

12

0

Phase B Active Power Gain

Phase C Active Power Gain

VA Gain register. This register calculation can be calibrated by

writing this register. The calibration range is 50% of the nominal

full scale real power. The resolution of the gain adjust is

0.02444% / LSB.

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

BVAG

CVAG

R/W

12

5

12

0

Phase B VA Gain

Phase C VA Gain

Phase A Phase Calibration Register

Phase B Phase Calibration Register

Phase C Phase Calibration Register

Phase A Power Offset Calibration Register

Phase B Power Offset Calibration Register

Phase C Power Offset Calibration Register

APHCAL

BPHCAL

CPHCAL

AAPOS

BAPOS

CAPOS

CFNUM

0h

CF Scaling Numerator register. The content of this register is

used in the numerator of CF output scaling.

26h

CFDEN

R/W

12

3Fh

CF Scaling Denominator register. The content of this register

is used in the denominator of CF output scaling.

Active Energy register divider

27h

28h

29h

WDIV

VADIV

AIRMS

R/W

R

8

24

0

Apparent Energy register divider

Phase A Current channel RMS register. The register contains the

RMS component of one input of the current channel. The source

is selected by data bits in the mode register.

2Ah

2Bh

BIRMS

CIRMS

R

24

0

Phase B Current channel RMS register.

Phase C Current channel RMS register.

–36–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Address

[A5:A0] Name

Default

R/W* Length Value

Description

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

AVRMS

BVRMS

CVRMS

AIRMSOS

BIRMSOS

CIRMSOS

AVRMSOS

BVRMSOS

CVRMSOS

AAPGAIN

R

R/W

24

12

0

Phase A Voltage channel RMS register.

Phase B Voltage channel RMS register.

Phase C Voltage channel RMS register.

Phase A Current RMS offset correction register.

Phase B Current RMS offset correction register.

Phase C Current RMS offset correction register.

Phase A Voltage RMS offset correction register.

Phase B Voltage RMS offset correction register.

Phase C Voltage RMS offset correction register.

Phase A Active Power Gain Adjust. The Active Power accu-

mulation of the phase A can be calibrated by writing to this

register. The calibration range is 50% of the nominal full

scale of the Active Power. The resolution of the gain is

0.0244% / LSB - see Current channel Gain Adjust

Phase B Active Power Gain Adjust

36h

37h

38h

BAPGAIN

CAPGAIN

AVGAIN

R/W

12

0

Phase C Active Power Gain Adjust

Phase A voltage RMS gain. The Apparent Power accumula-

tion of the phase A can be calibrated by writing to this

register. The calibration range is 50% of the nominal full

scale of the Apparent Power. The resolution of the gain is

0.0244% / LSB - see Voltage RMS Gain Adjust

Phase B voltage RMS gain

39h

3Ah

BVGAIN

CVGAIN

R/W

12

0

Phase C voltage RMS gain

3Bh

3Dh

3Eh

Reserved

CHKSUM

R

8

Check sum register. The content of this register represents

the sum of all ones of the latest register read from the SPI

port.

Version of the Die

3Fh VERSION

1

*R/W: Read/Write capability of the register.

R: Read only register.

R/W: Register that can be both read and written.

REV. PrG 01/03

–37–

PRELIMINARY TECHNICAL DATA

ADE7754

Operational Mode Register (0Ah)

The general configuration of the ADE7754 is defined by writing to the OPMODE register. Table IX below summarizes the

functionality of each bit in the OPMODE register .

Table IX OPMODE Register

Bit

Default

Value

Location Mnemonic

Description

0

DISHPF

DISLPF

DISCF

0

1

0

The HPF (High Pass Filter) in all current channel inputs are disabled when this bit is set.

The LPFs (Low Pass Filter) in all current channel inputs are disabled when this bit is set.

The Frequency output CF is disabled when this bit is set.

1

2

3-5

DISMOD

By setting these bits, ADE7754’s A/D converters can be turned off. In normal operation,

these bits should be left at logic zero.

DISMOD2 DISMOD1 DISMOD0

0

1

0

Normal operation

Normal operation, by setting this bit to logic 1 the

analog inputs to current channel are connected to the ADC

for voltage channel and the analog inputs to voltage

channel are connected to the ADC for current channel

0

1

0

1

Current channel A/D converters OFF

Current channel A/D converters OFF + chan

nels swapped

0

1

0

Voltage Channel A/D converters OFF

Voltage Channel A/D converters OFF + chan

nels swapped

0

1

ADE7754 in Sleep Mode

ADE7754 powered down

6

7

SWRST

0

Software chip reset. A data transfer to the ADE7754 should not take place for at least 18µs

after a software reset.

RESERVED -

This is intended for factory testing only and should be left at zero.

–38–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Gain Register (18h)

The Gain of the analog inputs and the mode of accumulation of the active energies in the ADE7754 are defined by writing

to the GAIN register. Table X below summarizes the functionality of each bit in the GAIN register .

Table X GAIN Register

Bit

Default

Value

Location Mnemonic

Description

0-1

PGA1

0

These bits are used to select the Gain of the current channels inputs.

bit 1

bit 0

0

1

0

1

0

PGA1=1

PGA1=2

PGA1=4

Reserved

2

3

ABS

0

The sum of the absolute active energies is done in the ANERGY and LAENERGY

registers when this bit is set to logic one. The regular sum is done when this bit is set to

logic zero - default mode.

NOLOAD

The active energy of each phase is not accumulated in the total active energy registers if

the instantaneous active power is lower than the no-load threshold when this bit is set to

logic zero, this mode is selected by default.

4

RESERVED -

This is intended for factory testing only and should be left at zero.

These bits are used to select the Gain of the voltage channels inputs.

5-6

PGA2

0

bit 6

bit 5

0

1

0

1

0

PGA2=1

PGA2=2

PGA2=4

Reserved

7

RESERVED -

This is intended for factory testing only and should be left at zero.

CFNUM Register (25h)

The CF scaling numerator and the sign of the active energy per phase are defined by writing/reading to the CFNUM register.

Table XI below summarizes the functionality of each bit in the CFNUM register .

Table XI CFNUM Register

Bit

Default

Value

Location Mnemonic

Description

0-Bh

Ch

CFN

0

CF Scaling Numerator register. The content of this register is used in the numerator of

CF output scaling.

NEGA

The sign of the phase A instantaneous active power is available in this bit. Logic zero and

Logic one correspond to Positive and negative active power respectively. The functionality

of this bit is enabled by setting bit 5 of the WATMode register to logic one. When disabled

NEGA is equal to its default value.

Dh

Eh

Fh

NEGB

0

The sign of the phase B instantaneous active power is available in this bit. Logic zero and

Logic one correspond to Positive and negative active power respectively. The functionality

of this bit is enabled by setting bit 4 of the WATMode register to logic one. When disabled

NEGB is equal to its default value.

NEGC

The sign of the phase C instantaneous active power is available in this bit. Logic zero and

Logic one correspond to Positive and negative active power respectively. The functionality

of this bit is enabled by setting bit 3 of the WATMode register to logic one. When disabled

NEGC is equal to its default value.

RESERVED

REV. PrG 01/03

–39–

PRELIMINARY TECHNICAL DATA

ADE7754

Measurement Mode Register (0Bh)

The configuration of the period and Peak measurements made by the ADE7754 are defined by writing to the MMODE

register. Table XII below summarizes the functionality of each bit in the MMODE register .

Table XII MMODE Register

Bit

Default

Value

Location Mnemonic

Description

0-1

PERDSEL

0

These bits are used to select the source of the measurement of the voltage line period.

bit 1

bit 0

Source

0

1

0

1

0

1

Phase A

Phase B

Phase C

Reserved

2-3

PEAKSEL

These bits select the line voltage and current phase used for the PEAK detection. If the

selected line voltage is above the level defined in the PKVLVL register, the PKV flag in

the Interrupt Status register is set. If the selected current input is above the level defined

in the PKILVL register, the PKI flag in the Interrupt Status register is set.

bit 3

bit 2

Source

0

1

0

Phase A

Phase B

Phase C

Reserved

1

0

1

4-6

7

ZXSEL

7

These bits select the phases used for counting the number of zero crossing in the Line

Active and Apparent accumulation modes as well as enabling these phases for the Zero-

Crossing Time out detection, Zero-crossing, Period measurement and SAG detection. bit

4, 5 and 6 select Phase A, Phase B and Phase C respectively.

Reserved

Waveform Mode Register (0Ch)

The Waveform sampling mode of the ADE7754 is defined by writing to the WAVMODE register. Table XIII below

summarizes the functionality of each bit in the WAVMODE register .

Table XIII WAVMODE Register

Bit

Default

Value

Location Mnemonic

Description

0-2

WAVSEL

0

These bits are used to select the source of the Waveform sample

bit 2

bit 1

bit 0

Source

0

1

0

1

0

1

0

Voltage Phase A

Voltage Phase B

Voltage Phase C

Current Phase A

Current Phase B

Current Phase C

Reserved

1

0

1

0

1

0 or 1

3-4

DTRT

0

These bits are used to select the Waveform sampling update rate

bit 4

bit 3

Update rate

0

1

0

1

0

1

26.0ksps (CLKIN/3/128)

13.0ksps (CLKIN/3/256)

6.5ksps (CLKIN/3/512)

3.3ksps (CLKIN/3/1024)

5

LVARSEL

This bit is used to enable the accumulation of the Line VAR energy into the LAENERGY

register and of the Line Active Energy into the LVAENERGY register.

–40–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Watt Mode Register (0Dh)

The phases involved in the Active Energy measurement of the ADE7754 are defined by writing to the WATMODE register.

Table XIV below summarizes the functionality of each bit in the WATMODE register .

Table XIV WATMODE Register

Bit

Default

Location Mnemonic Value

Description

0-2

3-5

LWATSEL

WATSEL

7

These bits are used to select separately each part of the formula, depending on the Line

Active Energy measurement method. The behavior of these bits is the same as WATSEL

bits. Bit 2 selects the first term of the formula and so on.

These bits are used to select separately each part of the formula, depending on the Active

Energy measurement method. These bits are also used to enable the Negative power

detection available in bits 12-14 of CFNUM register - see Table XI. Setting bit 5 to logic

one selects the first term of the formula (VAxIA or VAx(IA-IB)). Setting bit 4 to logic one

selects the second term of the formula (VBxIB or 0 depending on WATMOD configu-

ration). Setting bit 3 to logic one selects the last term of the formula (VCxIC or

VCx(IC-IB)). Any combination of these bits are possible to address calibration and

operational needs.

6-7

WATM

0

These bits are used to select the formula used for Active Energy calculation

WATM1

WAVM0

Active Energy calculation

0

1

0

1

0

1

VAxIA

+

VBxIB

+

VCxIC

VAx(IA-IB)

Reserved

0

VCx(IC-IB)

VCxIC

VA Mode Register (0Eh)

The phases involved in the Apparent Energy measurement of the ADE7754 are defined by writing to the VAMODE register.

Table XV below summarizes the functionality of each bit in the VAMODE register .

Table XV VAMode Register

Bit

Default

Location Mnemonic Value

Description

0-2

3-5

LVASEL

VASEL

7

These bits are used to select separately each part of the formula, depending on the Line

Apparent Energy measurement method. The behavior of these bits is the same as VASEL

bits. Bit 2 selects the first term of the formula and so on.

These bits are used to select separately each part of the formula, depending on the Apparent

Energy measurement method. Setting bit 5 to logic one selects the first term of the formula

(VA_rmsxIA_rms). Setting bit 4 to logic one selects the second term of the formula

(VB_rmsxIB_rmsor (VA_rms+VC_rms)/2xIB_rmsor VA_rmsxIB_rmsdepending on VAMOD configu-

ration). Setting bit 3 to logic one selects the first term of the formula (VC_rmsxIC_rms). Any

combination of these bits are possible to address calibration and operational needs.

6-7

VAMOD

0

These bits are used to select the formula used for Active Energy calculation

VAMOD1

VAMOD0 Apparent Energy calculation

0

1

0

1

0

1

VA_rmsxIA_rms+VB_rmsxIB_rms+VC_rmsxIC_rms

VA_rmsxIA_rms+(VA_rms+VC_rms)/2xIB_rms+VC_rmsxIC_rms

VA_rmsxIA_rms+VA_rmsxIB_rms+VC_rmsxIC_rm

Reserved

REV. PrG 01/03

–41–

PRELIMINARY TECHNICAL DATA

ADE7754

Interrupt Mask Register (0Fh)

When an interrupt event occurs in the ADE7754, the IRQ logic output goes active low if the mask bit for this event is logic

one in this register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. The

following describes the function of each bit in the Interrupt Mask Register.

Table XVI MASK Register

Bit

Interrupt

Default

Value

Location Flag

Description

0

AEHF

0

Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY register

(i.e. the AENERGY register is half-full)

1

2

3

4

5

6

7

SAGA

0

Enables an interrupt when there is a SAG on the line voltage of the Phase A

Enables an interrupt when there is a SAG on the line voltage of the Phase B

Enables an interrupt when there is a SAG on the line voltage of the Phase C

Enables an interrupt when there is a zero crossing time out detection on Phase A

Enables an interrupt when there is a zero crossing time out detection on Phase B

Enables an interrupt when there is a zero crossing time out detection on Phase C

SAGB

SAGC

ZXTOA

ZXTOB

ZXTOC

ZXA

Enables an interrupt when there is a rising zero crossing in voltage channel of the phase

A —Zero Crossing Detection

8

ZXB

0

Enables an interrupt when there is a rising zero crossing in voltage channel of the phase

B —Zero Crossing Detection

9

ZXC

Enables an interrupt when there is a rising zero crossing in voltage channel of the phase

C —Zero Crossing Detection

Ah

LENERGY

Enables an interrupt when the LAENERGY and LVAENERGY accumulations over

LINCYC are finished

Bh

Ch

Reserved

PKV

PKI

0

Enables an interrupt when the voltage input selected in the MMODE register is above the

value in the PKVLVL register

Dh

Enables an interrupt when the current input selected in the MMODE register is above the

value in the PKILVL register.

Eh

Fh

WFSM

VAEHF

0

Enables an interrupt when a data is present in the Waveform Register.

Enables an interrupt when there is a 0 to 1 transition of the MSB of the VAENERGY

register (i.e. the VAENERGY register is half-full)

INTERRUPT MASK REGISTER*

F

E

D

C

B

0

A

9

8

7

6

5

4

3

2

1

0

ADDR: 0Fh

AEHF

0

VAEHF

(Active Energy Register Half Full)

(Apparent Energy Register Half Full)

WFMP

SAG

(New Waveform Sample Ready)

(SAG Event Detect)

PKI

ZX

(Current channel Peak detection)

(Zero Crossing Time out Detection)

PKV

(Voltage channel Peak detection)

Reserved

ZX

(Zero Crossing Detection)

LENERGY

(End of the LAENERGY and LVAENERGY accumulation)

*Register contents show power on defaults

–42–

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

Interrupt Status Register (10h) / Reset Interrupt Status Register (11h)

The Interrupt Status Register is used to determine the source of an interrupt event. When an interrupt event occurs in the

ADE7754, the corresponding flag in the Interrupt Status Register is set logic high. The IRQ pin will go active low if the

corresponding bit in the Interrupt Mask register is set logic high. When the MCU services the interrupt, it must first carry

out a read from the Interrupt Status Register to determine the source of the interrupt. All the interrupts in the Interrupt Status

Register stay at their logic high state after an event occurs. The state of the interrupt bit in the Interrupt Status register is reset

to its default value once the Reset Interrupt Status register is read.

Table XVII STATUS Register

Bit

Interrupt

Default Event

Location Flag

Value

Description

0

AEHF

0

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the AENERGY

register (i.e. the AENERGY register is half-full)

1

2

3

4

SAGA

SAGB

SAGC

ZXTOA

0

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the

Phase A

5

6

ZXTOB

ZXTOC

0

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the

Phase B

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the

Phase C

7

ZXA

0

Indicates a detection of rising zero crossing in the voltage channel of the phase A

Indicates a detection of rising zero crossing in the voltage channel of the phase B

Indicates a detection of rising zero crossing in the voltage channel of the phase C

8

ZXB

9

ZXC

Ah

LENERGY

In Line energy accumulation, it indicates the end of an integration over an integer number

of half line cycles (LINCYC) —see Energy Calibration

Bh

Ch

RESET

PKV

0

Indicates that the ADE7754 has been reset

Indicates that an interrupt was caused when the selected voltage input is above the value

in the PKVLV register.

Dh

PKI

0

Indicates that an interrupt was caused when the selected current input is above the value

in the PKILV register.

Eh

Fh

WFSM

VAEHF

0

Indicates that new data is present in the Waveform Register.

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the

VAENERGY register (i.e. the VAENERGY register is half-full)

INTERRUPT STATUS REGISTER*

F

E

D

C

B

0

A

9

8

7

6

5

4

3

2

1

0

ADDR: 10h

AEHF

0

VAEHF

(Active Energy Register Half Full)

(Apparent Energy Register Half Full)

WFMP

SAG

(New Waveform Sample Ready)

(SAG Event Detect)

PKI

ZX

(Current channel Peak detection)

(Zero Crossing Time out Detection)

PKV

(Voltage channel Peak detection)

RESET

ZX

(Zero Crossing Detection)

LENERGY

(End of the LAENERGY and LVAENERGY accumulation)

*Register contents show power on defaults

REV. PrG 01/03

–43–

PRELIMINARY TECHNICAL DATA

ADE7754

OUTLINE DIMENSIONS

shown in inches and (mm)

24-LEAD SOIC

(RW-24)

0.6141 (15.60)

0.5985 (15.20)

24

1

13

12

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25)

؋

45؇

8؇

0؇

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0118 (0.30)

0.0040 (0.10)

0.0500 (1.27)

0.0157 (0.40)

0.0125 (0.32)

0.0091 (0.23)

–44–

REV. PrG 01/03


型号：	ADE7754ARZRL
厂家：	ADI
描述：	Poly Phase Multi-functional Metering IC With Serial Port
文件：	总44页 (文件大小：635K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADE7754ARZRL [ADI]

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