ADE7756_技术文档

Active Energy Metering IC

with Serial Interface

a

ADE7756*

FEATURES

The ADE7756 contains a sampled Waveform register and an

Active Energy register capable of holding at least five seconds of

accumulated power at full load. Data is read from the ADE7756

via the serial interface. The ADE7756 also provides a pulse output

(CF) with a frequency that is proportional to the active power.

High Accuracy, Supports IEC 687/1036

Less than 0.1% Error over a Dynamic Range of 1000 to 1

An On-Chip User Programmable Threshold for Line

Voltage SAG Detection and PSU Supervisory

The ADE7756 Supplies Sampled Waveform Data

(20 Bits) and Active Energy (40 Bits)

Digital Power, Phase and Input Offset Calibration

An On-Chip Temperature Sensor (ꢂ3ꢃC Typical after

Calibration)

In addition to real power information, the ADE7756 also provides

system calibration features, i.e., channel offset correction, phase

calibration, and power calibration. The part also incorporates a

detection circuit for short duration low voltage variations or sags.

The voltage threshold level and the duration (in number of half-

line cycles) of the variation are user programmable. An open drain

logic output (SAG) goes active low when a sag event occurs.

An SPI-Compatible Serial Interface

A Pulse Output with Programmable Frequency

An Interrupt Request Pin (IRQ) and Status Register

Provide Early Warning of Register Overflow and

Other Conditions

Proprietary ADCs and DSP Provide High Accuracy

over Large Variations in Environmental Conditions

and Time

Reference 2.4 V ꢂ 8% (20 ppm/ꢃC Typical) with External

Overdrive Capability

Single 5 V Supply, Low Power (25 mW Typical)

A zero crossing output (ZX) produces an output that is synchro-

nized to the zero crossing point of the line voltage. This output can

be used to extract timing or frequency information from the line.

The signal is also used internally to the chip in the calibration

mode. This permits faster and more accurate calibration of the

real power calculation. This signal is also useful for synchronization

of relay switching with a voltage zero crossing, thus improving

the relay life by reducing the risk of arcing.

The interrupt request output is an open drain, active low logic

output. The IRQ output will become active when the accumu-

lated real power register is half-full and also when the register

overflows. A status register indicates the nature of the interrupt.

GENERAL DESCRIPTION

The ADE7756 is a high-accuracy electrical power measurement

IC with a serial interface and a pulse output. The ADE7756

incorporates two second-order sigma-delta ADCs, reference

circuitry, temperature sensor, and all the signal processing

required to perform active power and energy measurement.

The ADE7756 is available in 20-lead DIP and 20-lead

SSOP packages.

FUNCTIONAL BLOCK DIAGRAM

DV

AV

DD

RESET

DGND

DD

PGA

HPF1

LPF2

MULTIPLIER

ADE7756

ZX

MULTIPLIER

V1P

V1N

ADC

SAG

APGAIN[11:0]

TEMP

SENSOR

APOS[11:0]

DFC

PHCAL[5:0]

V2P

V2N

ADC

ꢁ

CF

ADE7756 REGISTERS

AND

4kꢀ

2.4V

REFERENCE

AGND

SERIAL INTERFACE

LPF1

CFDIV[11:0]

SCLK CS IRQ

CLKOUT

DIN DOUT

CLKIN

REF

IN/OUT

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; other pending.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADE7756

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

ADE7756–SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8

PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8

POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8

ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . . 13

LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . . 14

Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . 14

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Using the ADE7756 Interrupts with an MCU . . . . . . . . . 15

Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . . 16

ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . . 16

Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . . 18

Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . 20

ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . . 21

ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . 22

Integration Times under Steady Load . . . . . . . . . . . . . . . 23

POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . . 23

ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . . 23

ENERGY CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . 24

CALIBRATING THE ENERGY METER . . . . . . . . . . . . . 24

Calculating the Average Active Power . . . . . . . . . . . . . . . 24

Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . . 24

Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . 25

SUSPENDING THE ADE7756 FUNCTIONALITY . . . . 26

SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 29

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Interrupt Status Register (04H)/Reset Interrupt

Status Register (05H) . . . . . . . . . . . . . . . . . . . . . . . . . . 31

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32

–2–

REV. 0

ADE7756

(AV_DD= DV_DD= 5 V ꢂ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,

T_MINto T_MAX= –40ꢃC to +85ꢃC, unless otherwise noted.)

SPECIFICATIONS¹

Parameter

A Version

B Version Unit

Test Conditions/Comments

ENERGY MEASUREMENT ACCURACY

Measurement Bandwidth

14

kHz

CLKIN = 3.579545 MHz

Channel 2 = 300 mV rms/60 Hz, Gain = 2

Measurement Error¹on Channel 1

Channel 1 Range = 1 V Full Scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

0.1

% typ

Over a Dynamic Range 1000 to 1

Gain = 16

Channel 1 Range = 0.5 V Full Scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

0.1

0.2

0.1

0.2

% typ

Over a Dynamic Range 1000 to 1

Gain = 16

Channel 1 Range = 0.25 V Full Scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

0.1

0.2

0.05

0.1

0.2

% typ

° max

Over a Dynamic Range 1000 to 1

Line Frequency = 45 Hz to 65 Hz, HPF On

AV_DD= DV_DD= 5 V + 175 mV rms/120 Hz

Channel 1 = 20 mV rms/60 Hz, Gain = 16,

Range = 0.5 V

Gain = 16

Phase Error¹Between Channels

AC Power Supply Rejection¹

Output Frequency Variation (CF)

0.05

0.2

% typ

Channel 2 = 175 mV rms/60 Hz, Gain = 4

AV_DD= DV_DD= 5 V 250 mV dc

Channel 1 = 20 mV rms/60 Hz, Gain = 16,

Range = 0.5 V

DC Power Supply Rejection¹

Output Frequency Variation (CF)

0.3

% typ

Channel 2 = 175 mV rms/60 Hz, Gain = 4

ANALOG INPUTS

Maximum Signal Levels

Input Impedance (dc)

Bandwidth

See Analog Inputs Section

V1P, V1N, V2N and V2P to AGND

1

390

14

1

390

14

V max

kΩ min

kHz

CLKIN/256, CLKIN = 3.579545 MHz

External 2.5 V Reference, Gain = 1 on

Channel 1 and 2

Gain Error^{1, 2}

Channel 1

Range = 1 V Full Scale

Range = 0.5 V Full Scale

Range = 0.25 V Full Scale

Channel 2

4

% typ

V1 = 1 V dc

V1 = 0.5 V dc

V1 = 0.25 V dc

V2 = 1 V dc

External 2.5 V Reference

Gain Error Match¹

Channel 1

Range = 1 V Full Scale

Range = 0.5 V Full Scale

Range = 0.25 V Full Scale

Channel 2

0.3

% typ

Gain = 1, 2, 4, 8, 16

0.3

Offset Error¹

Channel 1

Channel 2

20

mV max

Range = 1 V, Gain = 1

Gain = 1

WAVEFORM SAMPLING

Sampling CLKIN/128, 3.579545 MHz/128 =

27.9 kSPS

Channel 1

See Channel 1 Sampling

Signal-to-Noise Plus Distortion

Bandwidth (–3 dB)

Channel 2

62

14

62

14

dB typ

kHz

700 mV rms/60 Hz, Range = 1 V, Gain = 1

CLKIN = 3.579545 MHz

See Channel 2 Sampling

Signal-to-Noise Plus Distortion

Bandwidth (–3 dB)

52

156

52

156

dB typ

Hz

300 mV rms/60 Hz, Gain = 2

CLKIN = 3.579545 MHz

–3–

REV. 0

ADE7756–SPECIFICATIONS

Parameter

A Version

B Version Unit

Test Conditions/Comments

REFERENCE INPUT

REF_IN/OUTInput Voltage Range

2.6

2.2

10

2.6

2.2

10

V max

V min

pF max

2.4 V + 8%

2.4 V – 8%

Input Capacitance

ON-CHIP REFERENCE

Reference Error

Load Current

Output Impedance

Temperature Coefficient

Nominal 2.4 V at REF_IN/OUTPin

200

10

4

200

10

4

20

80

mV max

µA max

kΩ min

ppm/°C typ

ppm/°C max

20

CLKIN

Note All Specifications CLKIN of 3.579545 MHz

Input Clock Frequency

10

1

10

1

MHz max

MHz min

LOGIC INPUTS

RESET, DIN, SCLK, CLKIN and CS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

3

2.4

0.8

3

V min

DV_DD= 5 V 5%

Typically 10 nA, V_IN= 0 V to DV_DD

V max

µA max

pF max

Input Capacitance, C_IN

10

LOGIC OUTPUTS

SAG and IRQ

Output High Voltage, V_OH

Output Low Voltage, V_OL

ZX and DOUT

Open Drain Outputs, 10 kΩ Pull-Up Resistor

I_SOURCE= 5 mA

I_SINK= 0.8 mA

4

0.4

4

0.4

V min

V max

Output High Voltage, V_OH

Output Low Voltage, V_OL

CF

4

0.4

4

0.4

V min

V max

I_SOURCE= 5 mA

I_SINK= 0.8 mA

Output High Voltage, V_OH

Output Low Voltage, V_OL

4

0.4

4

0.4

V min

V max

I_SOURCE= 5 mA

I_SINK= 7 mA

POWER SUPPLY

AV_DD

For Specified Performance

5 V – 5%

5 V + 5%

5 V – 5%

5 V + 5%

Typically 2.0 mA

Typically 3.0 mA

4.75

5.25

4.75

5.25

3

4.75

5.25

4.75

5.25

3

V min

V max

V min

V max

mA max

DV_DD

AI_DD

DI_DD

4

NOTES

¹See Terminology section for explanation of specifications.

²See plots in Typical Performance Characteristic curves.

³See Analog Inputs section.

Specifications subject to change without notice

–4–

REV. 0

ADE7756

(AV_DD= DV_DD= 5 V ꢂ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz

TIMING CHARACTERISTICS^{1, 2}

XTAL, T_MINto T_MAX= –40ꢃC to +85ꢃC, unless otherwise noted.)

Parameter

A, B Versions

Unit

Test Conditions/Comments

Write Timing

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

20

150

10

5

6.4

4

100

ns (min)

µs (min)

ns (min)

CS falling edge to first SCLK falling edge.

SCLK logic high pulsewidth.

SCLK logic low pulsewidth.

Valid Data Setup time before falling edge of SCLK.

Data Hold time after SCLK falling edge.

Minimum time between the end of data byte transfers.

Minimum time between byte transfers during a serial write.

CS Hold time after SCLK falling edge.

Read Timing

t₉

4

µs (min)

Minimum time between read command (i.e., a write to Communication

Register) and data read.

t₁₀

t₁₁

4

30

µs (min)

Minimum time between data byte transfers during a multibyte read.

Data access time after SCLK rising edge following a write to the

Communications Register.

3

ns (min)

4

t₁₂

100

10

100

ns (max)

ns (min)

ns (max)

ns (min)

Bus relinquish time after falling edge of SCLK.

4

t₁₃

Bus relinquish time after rising edge of CS.

10

NOTES

¹Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to

90%) and timed from a voltage level of 1.6 V.

²See timing diagram below and Serial Interface section of this data sheet.

³Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V.

⁴Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured

number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics

is the true bus relinquish time of the part and is independent of the bus loading.

Specifications subject to change without notice.

I

200ꢄA

OL

TO

OUTPUT

2.1V

C

L

50pF

I

1.6mA

OH

Figure 1. Load Circuit for Timing Specifications

t₈

CS

t₂

t₆

t₁

t₃

t₇

SCLK

t₄

t₅

DIN

1

0

A4

A3

A2 A1

A0

DB7

DB0

DB7

DB0

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 2. Serial Write Timing

CS

t₁

t₁₃

t₉

t₁₀

SCLK

DIN

0

A4

A3

A2 A1

A0

t₁₂

t₁₁

DOUT

DB0

DB7

DB0

DB7

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 3. Serial Read Timing

–5–

REV. 0

ADE7756

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

20-Lead Plastic DIP, Power Dissipation . . . . . . . . . 450 mW

ABSOLUTE MAXIMUM RATINGS*

(T_A= 25°C unless otherwise noted)

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto AV_DD. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND

V_1P, V_1N, V_2Pand V_2N. . . . . . . . . . . . . . . . . . –6 V to +6 V

Reference Input Voltage to AGND . . . –0.3 V to AV_DD+ 0.3 V

Digital Input Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

Operating Temperature Range

Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . 260°C

20-Lead SSOP, Power Dissipation . . . . . . . . . . . . . 450 mW

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . 112°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADE7756 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model

Package Description

Package Option

ADE7756AN

Plastic DIP

N-20

ADE7756BN

Plastic DIP

N-20

ADE7756ARS

ADE7756ARSRL

ADE7756BRS

ADE7756BRSRL

EVAL-ADE7756EB

ADE7756AN-REF

Shrink Small Outline Package in Tubes

Shrink Small Outline Package in Reel

ADE7756 Evaluation Board

ADE7756 Reference Design

RS-20

PIN CONFIGURATION

DIP and SSOP Packages

1

2

20

19

18

17

16

15

14

13

12

11

DIN

RESET

DOUT

SCLK

DV

DD

3

AV

4

V1P

V1N

CS

5

CLKOUT

CLKIN

ADE7756

TOP VIEW

(Not to Scale)

6

V2N

7

V2P

IRQ

SAG

ZX

8

AGND

9

REF

IN/OUT

10

DGND

CF

–6–

REV. 0

ADE7756

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

1

RESET

Reset Pin for the ADE7756. A logic low on this pin will hold the ADCs and digital circuitry (including

the Serial Interface) in a reset condition.

2

3

DV_DD

AV_DD

Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7756.

The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be

decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7756.

The supply should be maintained at 5 V 5% for specified operation. Every effort should be made to

minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical per-

formance graphs in this data sheet show the power supply rejection performance. This pin should be

decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

4, 5

V1P, V1N

Analog Inputs for Channel 1. This channel is intended for use with the current transducer. These

inputs are fully differential voltage inputs with maximum differential input signal levels of 1 V, 0.5 V

and 0.25 V, depending on the full-scale selection. See Analog Inputs section. Channel 1 also has a

PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to

AGND is 1 V. Both inputs have internal ESD protection circuitry and in addition an overvoltage of

6 V can be sustained on these inputs without risk of permanent damage.

6, 7

V2N, V2P

AGND

Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These

inputs are fully differential voltage inputs with a maximum differential signal level of 1 V. Channel 2

also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with

respect to AGND is 1 V. Both inputs have internal ESD protection circuitry, and an overvoltage of

6 V can be sustained on these inputs without risk of permanent damage.

This pin provides the ground reference for the analog circuitry in the ADE7756, i.e., ADCs and refer-

ence. This pin should be tied to the analog ground plane or the quietest ground reference in the system.

This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current

and voltage transducers, etc. In order to keep ground noise around the ADE7756 to a minimum, the

quiet ground plane should only be connected to the digital ground plane at one point. It is acceptable

to place the entire device on the analog ground plane—see Applications Information section.

8

9

REF_IN/OUT

DGND

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value

of 2.4 V 8% and a typical temperature coefficient of 20 ppm/°C. An external reference source may

also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 µF

ceramic capacitor.

This provides the ground reference for the digital circuitry in the ADE7756, i.e., multiplier, filters, and

digital-to-frequency converter. Because the digital return currents in the ADE7756 are small, it is

acceptable to connect this pin to the analog ground plane of the system—see Applications Information

section. However, high bus capacitance on the DOUT pin may result in noisy digital current which

could affect performance.

10

11

CF

Calibration Frequency Logic Output. The CF logic output gives Active Power information. This out-

put is intended to be used for operational and calibration purposes. The full-scale output frequency

can be adjusted by writing to the CFDIV Register—see Energy To Frequency Conversion section.

12

13

14

ZX

Voltage Waveform (Channel 2) Zero Crossing Output. This output toggles logic high and low at the

zero crossing of the differential signal on Channel 2—see Zero Crossing Detection section.

This open drain logic output goes active low when either no zero crossings are detected or a low volt-

age threshold (Channel 2) is crossed for a specified duration. See Line Voltage Sag Detection section.

Interrupt Request Output. This is an active low open drain logic output. Maskable interrupts include:

Active Energy Register roll-over, Active Energy Register at half level, and arrivals of new waveform

samples—see Interrupts section.

SAG

IRQ

15

16

CLKIN

Master clock for ADCs and digital signal processing. An external clock can be provided at this logic

input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to

provide a clock source for the ADE7756. The clock frequency for specified operation is 3.579545 MHz.

Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit.

Refer to crystal manufacturers data sheet for load capacitance requirements.

A crystal can be connected across this pin and CLKIN as described above to provide a clock source

for the ADE7756. The CLKOUT pin can drive one CMOS load when either an external clock is

supplied at CLKIN or a crystal is being used.

CLKOUT

REV. 0

–7–

ADE7756

Pin No.

Mnemonic

Description

17

CS

Chip Select. Part of the 4-Wire SPI Serial Interface. This active low logic input allows the ADE7756

to share the serial bus with several other devices—see Serial Interface section.

18

19

20

SCLK

DOUT

DIN

Serial Clock Input for the Synchronous Serial Interface. All Serial data transfers are synchronized to

this clock. See Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock

source that has a slow edge transition time, e.g., opto-isolator outputs.

Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This

logic output is normally in a high impedance state unless it is driving data onto the serial data bus—

see Serial Interface section.

Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see

Serial Interface section.

TERMINOLOGY

MEASUREMENT ERROR

The error associated with the energy measurement made by the

ADE7756 is defined by the following formula:

ADC OFFSET ERROR

This refers to the dc offset associated with the analog inputs to

the ADCs. It means that with the analog inputs connected to

AGND the ADCs still see a dc analog input signal. The magni-

tude of the offset depends on the gain and input range selection

—see Typical Performance Characteristics. However, when HPF1

is switched on the offset is removed from Channel 1 (current)

and the power calculation is not affected by this offset. The

offsets may be removed by performing an offset calibration—see

Analog Inputs section.

Percentage Error =





Energy Registered by ADE7756 –True Energy

×100%









True Energy

PHASE ERROR BETWEEN CHANNELS

The HPF (High-Pass Filter) in Channel 1 has a phase lead

response. To offset this phase response and equalize the phase

response between channels, a phase correction network is also

placed in Channel 1. The phase correction network ensures a

phase match between Channel 1 (current) and Channel 2 (volt-

age) to within 0.1° over a range of 45 Hz to 65 Hz and 0.2°

over a range 40 Hz to 1 kHz.

GAIN ERROR

The gain error in the ADE7756 ADCs is defined as the differ-

ence between the measured ADC output code (minus the offset)

and the ideal output code—see Channel 1 ADC and Channel 2

ADC section. It is measured for each of the input ranges on

Channel 1 (1 V, 0.5 V and 0.25 V ). The difference is expressed

as a percentage of the ideal code.

POWER SUPPLY REJECTION

This quantifies the ADE7756 measurement error as a percent-

age of reading when the power supplies are varied. For the ac

PSR measurement, a reading at nominal supplies (5 V) is taken.

A second reading is obtained with the same input signal levels

when an ac (175 mV rms/120 Hz) signal is introduced onto the

supplies. Any error introduced by this ac signal is expressed as a

percentage of reading—see Measurement Error definition above.

GAIN ERROR MATCH

The Gain Error Match is defined as the gain error (minus the

offset) obtained when switching between a gain of 1 (for each of

the input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a

percentage of the output ADC code obtained under a gain of 1.

This gives the gain error observed when the gain selection is

changed from 1 to 2, 4, 8, or 16.

For the dc PSR measurement, a reading at nominal supplies

(5 V) is taken. A second reading is obtained with the same input

signal levels when the supplies are varied 5%. Any error intro-

duced is again expressed as a percentage of reading.

–8–

REV. 0

Typical Performance Characteristics–ADE7756

0.50

0.40

0.30

0.20

0.10

0

0.50

0.40

–40ꢃC, PF = 0.5

–40ꢃC

0.30

+85ꢃC, PF = 0.5

0.20

+25ꢃC, PF = 0.5

+25ꢃC, PF = 1.0

0.10

0

+85ꢃC

+25ꢃC

–0.10

–0.20

–0.30

–0.40

–0.50

–0.10

–0.20

–0.30

–0.40

–0.50

PF = 1

GAIN = 1

PF = 0.5

ON-CHIP REFERENCE

GAIN = 1

ON-CHIP REFERENCE

0.01

0.10

1.0

AMPS

10.0

100.0

0.01

0.10

1.0

10.0

100.0

AMPS

TPC 1. Error as a % of Reading (Power Factor = 1, Internal

Reference, Gain = 1)

TPC 4. Error as a % of Reading (Power Factor = 0.5, Internal

Reference, Gain = 1)

0.50

PF = 1

PF = 0.5

GAIN = 2

ON-CHIP REFERENCE

GAIN = 2

0.40

0.30

0.20

0.10

0

0.40

0.30

0.20

0.10

0

ON-CHIP REFERENCE

–40ꢃC

–40ꢃC, PF = 0.5

+25ꢃC, PF = 1.0

+85ꢃC

+85ꢃC, PF = 0.5

+25ꢃC

–0.10

–0.20

–0.30

–0.40

–0.50

–0.10

–0.20

–0.30

–0.40

–0.50

+25ꢃC, PF = 0.5

0.01

0.10

1.0

AMPS

10.0

100.0

0.01

0.10

1.0

AMPS

10.0

100.0

TPC 2. Error as a % of Reading (Power Factor = 1, Internal

Reference, Gain = 2)

TPC 5. Error as a % of Reading (Power Factor = 0.5, Internal

Reference, Gain = 2)

0.50

PF = 1

PF = 0.5

GAIN = 4

ON-CHIP REFERENCE

GAIN = 4

0.40

0.30

0.20

0.10

0

0.40

0.30

0.20

0.10

0

ON-CHIP REFERENCE

–40ꢃC

–40ꢃC, PF = 0.5

+85ꢃC, PF = 0.5

+85ꢃC

+25ꢃC

+25ꢃC, PF = 1.0

+25ꢃC, PF = 0.5

–0.10

–0.20

–0.30

–0.40

–0.50

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

0.10

1.0

10.0

100.0

0.01

0.10

1.0

10.0

100.0

AMPS

TPC 3. Error as a % of Reading (Power Factor = 1, Internal

Reference, Gain = 4)

TPC 6. Error as a % of Reading (Power Factor = 0.5, Internal

Reference, Gain = 4)

–9–

REV. 0

ADE7756

0.50

0.40

0.30

0.20

0.10

0

0.50

0.40

0.30

0.20

0.10

0

PF = 1

PF = 0.5

GAIN = 8

ON-CHIP REFERENCE

GAIN = 8

ON-CHIP REFERENCE

+25ꢃC, PF = 1.0

+85ꢃC

+85ꢃC, PF = 0.5

–40ꢃC

+25ꢃC

–0.10

–0.20

–0.30

–0.40

–0.50

–0.10

–0.20

–0.30

–0.40

+25ꢃC, PF = 0.5

–40ꢃC, PF = 0.5

–0.50

0.01

0.10

1.0

AMPS

10.0

100.0

0.01

0.10

1.0

AMPS

10.0

100.0

TPC 10. Error as a % of Reading (Power Factor = 0.5,

Internal Reference, Gain = 8)

TPC 7. Error as a % of Reading (Power Factor = 1, Internal

Reference, Gain = 8)

0.50

PF = 1

PF = 0.5

GAIN = 16

0.40

0.30

0.40

0.30

0.20

0.10

0

GAIN = 16

ON-CHIP REFERENCE

–40ꢃC, PF = 0.5

+85ꢃC

0.20

+85ꢃC, PF = 0.5

0.10

–40ꢃC

+25ꢃC

0

+25ꢃC, PF = 1.0

–0.10

–0.20

–0.30

–0.40

–0.50

–0.10

–0.20

–0.30

–0.40

–0.50

+25ꢃC, PF = 0.5

0.01

0.10

1.0

AMPS

10.0

100.0

0.01

0.10

1.0

AMPS

10.0

100.0

TPC 8. Error as a % of Reading (Power Factor = 1, Internal

Reference, Gain = 16)

TPC 11. Error as a % of Reading (Power Factor = 0.5,

Internal Reference, Gain = 16)

0.50

PF = 1

GAIN = 1

0.40

0.30

0.20

0.10

0

0.40

0.30

0.20

0.10

0

GAIN = 2

EXTERNAL REFERENCE

+85ꢃC

+25ꢃC

+85ꢃC

–0.10

–0.20

–0.30

–0.40

–0.50

–40ꢃC

–0.10

–0.20

–0.30

–0.40

–0.50

–40ꢃC

+25ꢃC

0.01

0.10

1.0

AMPS

10.0

100.0

0.01

0.10

1.0

AMPS

10.0

100.0

TPC 9. Error as a % of Reading (Power Factor = 1,

External Reference, Gain = 1)

TPC 12. Error as a % of Reading (Power Factor = 1,

External Reference, Gain = 2)

–10–

REV. 0

ADE7756

0.8

V

DD

100nF

AV

40A

TO

0.6

0.4

0.2

0

40mA

100nF

RESET

10ꢄF

1kꢀ

10ꢄF

DV

DD

DIN

DOUT

SCLK

CS

PF = 1

RB

TO

SPI BUS (USED

ONLY FOR

CALIBRATION)

V1P

V1N

PF = 0.5

U1

33nF

1kꢀ

RB

ADE7756

Y1

3.58MHz

33nF

CLKOUT

CLKIN

IRQ

–0.2

22pF

V2N

33nF

1kꢀ

–0.4

–0.6

1Mꢀ

1kꢀ

NOT CONNECTED

SAG

V2P

REF

33nF

110V

45

50

55

60

65

70

75

ZX

FREQUENCY – Hz

CF

IN/OUT

100nF

10ꢄF

AGND

DGND

TPC 15. Error as a % of Reading over Frequency

CT TURN RATIO = 1800:1

CHANNEL 2 GAIN = 4

U3

0.50

0.40

0.30

GAIN(CH1)

RB

TO

1

2

15.8ꢀ

7.5ꢀ

4.0ꢀ

2.0ꢀ

1.0ꢀ

FREQUENCY

COUNTER

4

8

16

PS2501-1

0.20

5.25V

0.10

TPC 13. Test Circuit for Performance Curves

5.0V

0

0.50

–0.10

4.75V

0.40

0.30

0.20

0.10

0

–0.20

–0.30

–0.40

–0.50

5.25V

0.01

0.10

1.0

AMPS

10.0

100.0

5.0V

–0.10

–0.20

–0.30

–0.40

–0.50

4.75V

TPC 16. PSR with External Reference

0.01

0.10

1.0

10.0

100.0

AMPS

TPC 14. PSR with Internal Reference

REV. 0

–11–

ADE7756

ANALOG INPUTS

*

GAIN REGISTER

CHANNEL 1 AND CHANNEL 2 PGA CONTROL

The ADE7756 has two fully differential voltage input channels.

The maximum differential input voltage for each input pair

(V1P/V1N and V2P/V2N) is 1 V. In addition, the maximum

signal level on each analog input (V1P, V1N, V2P, and V2N) is

also 1 V with respect to AGND.

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ADDR: 0AH

PGA 1 GAIN SELECT

000 = x1

PGA 2 GAIN SELECT

000 = x1

001 = x2

010 = x4

Each analog input channel has a PGA (Programmable Gain

Amplifier) with possible gain selections of 1, 2, 4, 8, and 16.

The gain selections are made by writing to the Gain regis-

ter—see Figure 5. Bits 0 to 2 select the gain for the PGA in

Channel 1 and the gain selection for the PGA in Channel 2 is

made via bits 5 to 7. Figure 4 shows how a gain selection for

Channel 1 is made using the Gain register.

001 = x2

011 = x8

010 = x4

100 = x16

011 = x8

100 = x16

CHANNEL 1 FS

SELECT

00 = 1V

01 = 0.5V

10 = 0.25V

*

REGISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 5. Analog Gain Register

GAIN[7:0]

It is also possible to adjust offset errors on Channel 1 and Channel

2 by writing to the Offset Correction Registers (CH1OS and

CH2OS respectively). These registers allow channel offsets in the

range 20 mV to 60 mV (depending on the gain setting) to be

removed. Note that it is not necessary to perform an offset correc-

tion in an Energy measurement application if HPF1 in Channel 1

is switched on. Figure 6 shows the effect of offsets on the real

power calculation. As can be seen from Figure 6, an offset on

Channel 1 and Channel 2 will contribute a dc component after

multiplication. Since this dc component is extracted by LPF2 to

generate the Active (Real) Power information, the offsets will

have contributed an error to the Active Power calculation. This

problem is easily avoided by enabling HPF1 in Channel 1. By

removing the offset from at least one channel, no error compo-

nent can be generated at dc by the multiplication. Error terms at

Cos(ωt) are removed by LPF2 and by integration of the Active

Power signal in the Active Energy register (AENERGY[39:0]).

See Energy Calculation section.

GAIN (k) SELECTION

V1P

kꢅV

IN

V

IN

V1N

OFFSET ADJUST

(ꢂ32mV)

CH1OS[7:0]

Figure 4. PGA in Channel 1

In addition to the PGA, Channel 1 also has a full-scale input

range selection for the ADC. The ADC analog input range selec-

tion is also made using the Gain register—see Figure 5. As

mentioned previously, the maximum differential input voltage is

1 V However, by using Bits 3 and 4 in the Gain register, the

maximum ADC input voltage can be set to 1 V, 0.5 V, or 0.25 V.

This is achieved by adjusting the ADC reference—see Reference

Circuit section. Table I summarizes the maximum differential

input signal level on Channel 1 for the various ADC range and

gain selections.

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

V

ꢅI

OS OS

VꢅI

2

Table I. Maximum Input Signal Levels for Channel 1

Max Signal

Channel 1

ADC Input Range Selection

1 V

0.5 V

0.25 V

I

ꢅV

OS

V

ꢅI

OS

1 V

0.5 V

0.25 V

0.125 V

0.0625 V

0.0313 V

0.0156 V

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

ꢆ

2ꢆ

FREQUENCY – RADS/Sec

0

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Figure 6. Effect of Channel Offsets on the Real Power

Calculation

–12–

REV. 0

ADE7756

The contents of the Offset Correction registers are 6-bit, sign

and magnitude coded. The weighting of the LSB size depends

on the gain setting, i.e., 1, 2, 4, 8, or 16. Table II below shows

the correctable offset span for each of the gain settings and the

LSB weight (mV) for the Offset Correction registers. The

maximum value that can be written to the Offset Correction

registers is 31 decimal—see Figure 7.

x1, x2, x4,

x8, x16

REFERENCE

ADC 2

TO

GAIN[7:5]

PGA2

MULTIPLIER

V2P

V2N

–63% TO +63% FS

1

V2

ZERO

CROSS

LPF1

f_–3dB= 156Hz

ZX

21.04ꢃ @ 60Hz

1.0

0.93

ZX

Table II. Offset Correction Range

Gain

Correctable Span

LSB Size

V2

LPF1

1

2

4

8

60 mV

40 mV

25 mV

23 mV

20 mV

1.88 mV/LSB

1.25 mV/LSB

0.78 mV/LSB

0.72 mV/LSB

0.63 mV/LSB

Figure 8. Zero Cross Detection on Channel 2

The ZX signal will go logic high on a positive going zero crossing

and logic low on a negative going zero crossing on Channel 2.

The zero crossing signal ZX is generated from the output of LPF1.

LPF1 has a single pole at 156 Hz (at CLKIN = 3.579545 MHz).

As a result there will be a phase lag between the analog input

signal V2 and the output of LPF1. The phase response of this

filter is shown in the Channel 2 Sampling section of this data

sheet. The phase lag response of LPF1 results in a time delay of

approximately 0.97 ms (@ 60 Hz) between the zero crossing on

the analog inputs of Channel 2 and the rising or falling edge of ZX.

16

Figure 7 shows the relationship between the Offset Correction

register contents and the offset (mV) on the analog inputs for a

gain setting of one. In order to perform an offset adjustment, The

analog inputs should be first connected to AGND. There should

be no signal on either Channel 1 or Channel 2. A read from

Channel 1 or Channel 2 using the waveform register will give an

indication of the offset in the channel. This offset can be canceled

by writing an equal and opposite offset value to the relevant offset

register. The offset correction can be confirmed by performing

another read. Note when adjusting the offset of Channel 1, one

needs to ensure the HPF has been disabled in the Mode Register.

The zero crossing detection also has an associated time-out

register ZXTOUT. This unsigned, 12-bit register is decre-

mented (1 LSB) every 128/CLKIN seconds. The register is

reset to its user-programmed full-scale value every time a zero

crossing on Channel 2 is detected. The default power-on value

in this register is FFFh. If the register decrements to zero before

a zero crossing is detected, and the DISSAG bit in the Mode

register is Logic 0, the SAG pin will go active low. The absence of

a zero crossing is also indicated on the IRQ output if the SAG

enable bit in the Interrupt Enable register is set to Logic 1.

Irrespective of the enable bit setting, the SAG flag in the Inter-

rupt Status register is always set when the ZXTOUT register is

decremented to zero—see ADE7756 Interrupts section.

CH1OS[7:0]

00 01, 1111B SIGN + 5 BITS

1Fh

00h

0mV

–60mV

+60mV

OFFSET ADJUST

The Zero-Cross Time-Out register can be written/read by the

user and has an address of 0Eh—see Serial Interface section.

The resolution of the register is 128/CLKIN seconds per LSB.

Thus the maximum delay for an interrupt is 0.15 second (128/

CLKIN × 2¹²).

SIGN + 5 BITS

3Fh 00 11, 1111B

Figure 7. Channel Offset Correction Range (Gain = 1)

ZERO CROSSING DETECTION

The ADE7756 has a zero crossing detection circuit on Channel

2. This zero crossing is used to produce an external zero cross

signal (ZX) and it is also used in the calibration mode—see

Energy Calibration section. The zero crossing signal is also used

to initiate a temperature measurement on the ADE7756—see

Temperature Measurement section.

Figure 8 shows how the zero cross signal is generated from the

output of LPF1.

REV. 0

–13–

ADE7756

LINE VOLTAGE SAG DETECTION

1000, 0111, 0010, 1100b or 3872Ch. Therefore writing 38h to

the Sag Level register will put the sag detection level at full

scale. Writing 00h will put the sag detection level at zero. The

Sag Level register is compared to the most significant byte of a

waveform sample after the shift left and detection is made when

the contents of the sag level register are greater.

In addition to the detection of the loss of the line voltage signal

(zero crossing), the ADE7756 can also be programmed to detect

when the absolute value of the line voltage drops below a certain

peak value, for a number of half-cycles. This condition is illus-

trated in Figure 9.

POWER SUPPLY MONITOR

CHANNEL 2

FULL SCALE

The ADE7756 also contains an on-chip power supply monitor.

The Analog Supply (AV_DD) is continuously monitored by the

ADE7756. If the supply is less than 4 V 5%, the ADE7756 will

be inactive, i.e., no energy will accumulate regardless of the

input signals at Channel 1 and Channel 2. This is useful to ensure

correct device operation at power-up and during power-down.

The power supply monitor has built-in hysteresis and filtering.

This gives a high degree of immunity to false triggering due to

noisy supplies.

SAGLVL[7:0]

SAG RESET HIGH

WHEN CHANNEL 2

EXCEEDS SAGLVL[7:0]

SAGCYC[7:0] = 06H

6 HALF-CYCLES

SAG

AV

DD

Figure 9. ADE7756 Sag Detection

5V

4V

Figure 9 shows the line voltage fall below a threshold that is set

in the Sag Level register (SAGLVL[7:0]) for nine half-cycles.

Since the Sag Cycle register (SAGCYC[7:0]) contains 06h, the

SAG pin will go active low at the end of the sixth half-cycle for

which the line voltage falls below the threshold, if the DISSAG

bit in the Mode register is Logic 0. As is the case when zero-

crossings are no longer detected, the sag event is also recorded

by setting the SAG flag in the Interrupt Status register. If the

SAG enable bit is set to Logic 1, the IRQ logic output will go

active low—see ADE7756 Interrupts section.

0V

TIME

INACTIVE

ADE7756

POWER-ON

RESET

ACTIVE

SAG

The SAG pin will go logic high again when the absolute value

of the signal on Channel 2 exceeds the sag level set in the Sag

Level register. This is shown in Figure 9 when the SAG pin goes

high during the tenth half-cycle from the time when the signal

on Channel 2 first dropped below the threshold level.

Figure 10. On-Chip Power Supply Monitor

As can be seen from Figure 10, the trigger level is nominally set

at 4 V. The tolerance on this trigger level is about 5%. The

SAG pin can also be used as a power supply monitor input to

the MCU. The SAG pin will go logic low when the ADE7756 is

reset. The power supply and decoupling for the part should

be such that the ripple at AV_DDdoes not exceed 5 V 5% as

specified for normal operation.

Sag Level Set

The contents of the Sag Level register (1 byte) are compared to

the absolute value of the most significant byte output from

LPF1, after it is shifted left by one bit. Thus for example the

nominal maximum code from LPF1 with a full scale signal on

Channel 2 is 1C396h or (0001, 1100, 0011, 1001, 0110b)—see

Channel 2 Sampling section. Shifting one bit left will give 0011,

–14–

REV. 0

ADE7756

the negative edge, the MCU should be configured to start execut-

ing its Interrupt Service Routine (ISR). On entering the ISR, all

interrupts should be disabled using the global interrupt enable

bit. At this point the MCU external interrupt flag can be cleared

in order to capture interrupt events that occur during the current

ISR. When the MCU interrupt flag is cleared a read from the

Status register with reset is carried out. This will cause the IRQ

line to be reset logic high (t₂)—see Interrupt timing section. The

Status register contents are used to determine the source of the

interrupt(s) and hence the appropriate action to be taken. If a

subsequent interrupt event occurs during the ISR, that event will

be recorded by the MCU external interrupt flag being set again

(t₃). On returning from the ISR, the global interrupt mask will

be cleared (same instruction cycle) and the external interrupt

flag will cause the MCU to jump to its ISR once again. This will

ensure that the MCU does not miss any external interrupts.

INTERRUPTS

Interrupts are managed through the Interrupt Status register

(STATUS[7:0]) and the Interrupt Enable register (IRQEN[7:0]).

When an interrupt event occurs in the ADE7756, the corre-

sponding flag in the Status register is set to a Logic 1—see

Interrupt Status register. If the enable bit for this interrupt in

the Interrupt Enable register is Logic 1, the IRQ logic output

goes active low. The flag bits in the Status register are set irre-

spective of the state of the enable bits.

In order to determine the source of the interrupt, the system mas-

ter (MCU) should perform a read from the Status register with

reset (RSTATUS[7:0]). This is achieved by carrying out a read

from address 05h. The IRQ output will go logic high on comple-

tion of the Interrupt Status register read command—see Interrupt

Timing section. When carrying out a read with reset the ADE7756

is designed to ensure that no interrupt events are missed. If an

interrupt event occurs just as the Status register is being read,

the event will not be lost and the IRQ logic output is guaranteed

to go high for the duration of the Interrupt Status register data

transfer before going logic low again to indicate the pending

interrupt. See the next section for a more detailed description.

Interrupt Timing

The Serial Interface section should be reviewed first, before

reviewing the interrupt timing. As previously described, when

the IRQ output goes low the MCU ISR must read the Interrupt

Status register in order to determine the source of the interrupt.

When reading the Status register contents, the IRQ output is set

high on the last falling edge of SCLK of the first byte transfer

(read Interrupt Status register command). The IRQ output is

held high until the last bit of the next 8-bit transfer is shifted out

(Interrupt Status register contents). See Figure 12. If an inter-

rupt is pending at this time, the IRQ output will go low again. If

no interrupt is pending the IRQ output will stay high.

Using the ADE7756 Interrupts with an MCU

Shown in Figure 11 is a timing diagram that shows a sug-

gested implementation of ADE7756 interrupt management

using an MCU. At time t₁the IRQ line will go active low indi-

cating that one or more interrupt events have occurred in the

ADE7756. The IRQ logic output should be tied to a negative

edge-triggered external interrupt on the MCU. On detection of

MCU

INTERRUPT

FLAG SET

t₁

t₂

t₃

IRQ

ISR ACTION

(BASED ON

STATUS CONTENTS)

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

GLOBAL

INTERRUPT

MASK SET

CLEAR MCU

INTERRUPT

FLAG

READ

STATUS WITH

RESET (05h)

JUMP

TO

ISR

JUMP

TO

ISR

MCU

PROGRAM

SEQUENCE

Figure 11. Interrupt Management

CS

t₁

SCLK

t₉

0

1

0

1

DIN

t₁₁

DB7

DB0

DOUT

READ STATUS REGISTER COMMAND

STATUS REGISTER CONTENTS

IRQ

Figure 12. Interrupt Timing

REV. 0

–15–

ADE7756

sampling interval, the data from the 1-bit ADC is virtually mean-

ingless. Only when a large number of samples are averaged, will

a meaningful result be obtained. This averaging is carried out in

the second part of the ADC, the digital low-pass filter. By aver-

aging a large number of bits from the modulator the low-pass

filter can produce 20-bit data words that are proportional to the

input signal level.

TEMPERATURE MEASUREMENT

ADE7756 also includes an on-chip temperature sensor. A tem-

perature measurement can be made by setting Bit 5 in the Mode

register. When Bit 5 is set logic high in the Mode register, the

ADE7756 will initiate a temperature measurement on the next

zero crossing. When the zero crossing on Channel 2 is detected,

the voltage output from the temperature sensing circuit is con-

nected to ADC1 (Channel 1) for digitizing. The resultant code

is processed and placed in the Temperature register (TEMP[7:0])

approximately 26 µs later (24 CLKIN cycles). If enabled in the

Interrupt Enable register (Bit 5), the IRQ output will go active

low when the temperature conversion is finished. Please note

that temperature conversion will introduce a small amount of

noise in the energy calculation. If temperature conversion is

performed frequently (e.g., multiple times per second), a

noticeable error will accumulate in the resulting energy calcu-

lation over time.

The sigma-delta converter uses two techniques to achieve high

resolution from what is essentially a 1-bit conversion technique.

The first is oversampling. By oversampling we mean that the

signal is sampled at a rate (frequency) that is many times higher

than the bandwidth of interest. For example, the sampling rate

in the ADE7756 is CLKIN/4 (894 kHz) and the band of interest

is 40 Hz to 2 kHz. Oversampling has the effect of spreading

the quantization noise (noise due to sampling) over a wider

bandwidth. With the noise spread more thinly over a wider

bandwidth, the quantization noise in the band of interest is

lowered—see Figure 15. However oversampling alone is not an

efficient enough method to improve the signal to noise ratio

(SNR) in the band of interest. For example, an oversampling

ratio of 4 is required just to increase the SNR by only 6 dB

(1 bit). To keep the oversampling ratio at a reasonable level, it is

possible to shape the quantization noise so that the majority of

the noise lies at the higher frequencies. This is what happens in

the sigma-delta modulator, the noise is shaped by the integrator

which has a high-pass-type response for the quantization noise.

The result is that most of the noise is at the higher frequencies

where it can be removed by the digital low-pass filter. This noise

shaping is also shown in Figure 15.

The contents of the Temperature register are signed (two’s

complement) with a resolution of approximately 1 LSB/°C. The

temperature register will produce a code of 00h when the ambi-

ent temperature is approximately 70°C—see Figure 13. The

temperature measurement is uncalibrated in the ADE7756 and

has an offset tolerance that could be as high as 20°C.

40

FIVE PARTS

APGAIN = 00h

20

0

–20

–40

–60

–80

–110

–120

MCLK/4

ANALOG LOW-

PASS FILTER

DIGITAL LOW-

PASS FILTER

LATCHED

COMPARATOR

R

C

INTEGRATOR

REF

1

20

V

10100101

1-BIT DAC

–60

–40

–20

0

20

40

60

80

100

120

TEMPERATURE–

ꢃC

Figure 14. First Order Sigma-Delta (Σ-∆) ADC

Figure 13. Temperature Register

ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7756 is carried out

using two second-order sigma-delta ADCs. The block diagram

in Figure 14 shows a first-order (for simplicity) sigma-delta

ADC. The converter is made up of two parts, first the sigma-

delta modulator and second the digital low-pass filter.

ANTIALIAS

FILTER (RC)

DIGITAL

FILTER

SAMPLING

FREQUENCY

SHAPED

NOISE

SIGNAL

NOISE

0

2

447

FREQUENCY – kHz

894

A sigma-delta modulator converts the input signal into a con-

tinuous serial stream of 1s and 0s at a rate determined by the

sampling clock. In the ADE7756 the sampling clock is equal to

CLKIN/4. The 1-bit DAC in the feedback loop is driven by the

serial data stream. The DAC output is subtracted from the input

signal. If the loop gain is high enough, the average value of the

DAC output (and therefore the bit stream) will approach that of

the input signal level. For any given input value in a single

HIGH RESOLUTION

OUTPUT FROM

DIGITAL LPF

SIGNAL

NOISE

2

0

447

FREQUENCY – kHz

894

Figure 15. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

–16–

REV. 0

ADE7756

Antialias Filter

Reference Circuit

Figure 21 also shows an analog low-pass filter (RC) on the input

to the modulator. This filter is present to prevent aliasing. Alias-

ing is an artifact of all sampled systems.

Shown in Figure 17 is a simplified version of the reference output

circuitry. The nominal reference voltage at the REF_IN/OUTpin

is 2.42 V. This is the reference voltage used for the ADCs in the

ADE7756. However, Channel 1 has three input range selections

that are selected by dividing down the reference value used for the

ADC in Channel 1. The reference value used for Channel 1 is

divided down to 1/2 and 1/4 of the nominal value by using an

internal resistor divider as shown in Figure 17.

Figure 16 illustrates the effect, frequency components (arrows

shown in black) above half the sampling frequency (also known

as the Nyquist frequency, i.e., 447 kHz) is imaged or folded

back down below 447 kHz (arrows shown in grey). This will

happen with all ADCs no matter what the architecture is. In the

example shown it can be seen that only frequencies near the

sampling frequency, i.e., 894 kHz, will move into the band of

interest for metering, i.e., 40 Hz–2 kHz. This fact will allow us

to use a very simple LPF (Low-Pass Filter) to attenuate these

high frequencies (near 900 kHz) and so prevent distortion in the

band of interest. A simple RC filter (single-pole) with a corner

frequency of 10 kHz will produce an attenuation of approxi-

mately 40 dBs at 894 kHz—see Figure 15. This is sufficient to

eliminate the effects of aliasing.

OUTPUT IMPEDANCE

4kꢀ

MAXIMUM

LOAD = 10ꢄA

REF

IN/OUT

2.42V

60ꢄA

2.5V

PTAT

1.7kꢀ

12.5kꢀ

REFERENCE INPUT TO ADC

CHANNEL 1 (RANGE SELECT)

2.42V, 1.21V, 0.6V

ALIASING EFFECTS

SAMPLING

FREQUENCY

IMAGE

FREQUENCIES

Figure 17. Reference Circuit Output

The REF_IN/OUTpin can be overdriven by an external source,

e.g., an external 2.5 V reference. Note that the nominal refer-

ence value supplied to the ADCs is now 2.5 V, not 2.42 V. This

has the effect of increasing the nominal analog input signal

range by 2.5/2.42 × 100% = 3%, or from 1 V to 1.03 V.

0

447

2

894

FREQUENCY – kHz

Figure 16. ADC and Signal Processing in Channel 1

ADC Transfer Function

The voltage of ADE7756 reference drifts slightly with temperature

—see ADE7756 Specifications for the temperature coefficient

specification (in ppm/°C). The value of the temperature drift varies

from part to part. On A-grade parts, the maximum temperature

drift is not guaranteed. Since the reference is used for the ADCs

in both Channel 1 and 2, any x% drift in the reference will result

in 2x% deviation of the meter accuracy. The reference drift

resulting from temperature changes is usually very small and it is

typically much smaller than the drift of other components on a

meter. However, if guaranteed temperature performance is

needed, one needs to use an external voltage reference or to use

B-grade parts. Alternatively, the meter can be calibrated at

multiple temperatures. Real-time compensation can be easily

achieved using the on the on-chip temperature sensor.

Below is an expression that relates the output of the LPF in the

sigma-delta ADC to the analog input signal level. Both ADCs in

the ADE7756 are designed to produce the same output code for

the same input signal level.

V_IN

V_REF

Code (ADC) = 1.512 ×

× 262,144

Therefore, with a full-scale signal on the input of 1 V, and an

internal reference of 2.4 V, the ADC output code is nominally

165,151 or 2851Fh. The maximum code from the ADC is

262,144, which is equivalent to an input signal level of 1.6 V.

However, for specified performance it is not recommended that

the full-scale input signal level of 1 V be exceeded.

REV. 0

–17–

ADE7756

CHANNEL 1 ADC

the expression that shows how the gain adjustment is related to

the contents of the Active Power Gain register.

Figure 18 shows the ADC and signal processing chain for Chan-

nel 1. In waveform sampling mode the ADC outputs a signed

two’s complement 20-bit data word at a maximum of 27.9 kSPS

(CLKIN/128). The output of the ADC can be scaled by 50% to

perform an overall power calibration or to calibrate the ADC out-

put. While the ADC outputs a 20-bit two’s complement value, the

maximum full-scale positive value from the ADC is limited to

40000h (+262,144 decimal). The maximum full-scale negative

value is limited to C0000h (–262,144 Decimal). If the analog

inputs are overranged, the ADC output code will clamp at these

values. With the specified full scale analog input signal of 1 V (or

0.5 V or 0.25 V—see Analog Inputs section) the ADC will produce

an output code which is approximately 63% of its full-scale value.

This is illustrated in Figure 18. The diagram in Figure 15 shows

a full-scale voltage signal being applied to the differential inputs

V1P and V1N. The ADC output swings between D7AE1h

(–165,151) and 2851Fh (+165,151). This is approximately 63%

of the full-scale value 40000h (262,144). Overranging the analog

inputs with more than 1 V differential (0.5 or 0.25, depending

on Channel 1 full-scale selection) will cause the ADC output to

increase towards its full-scale value. However for specified opera-

tion the differential signal on the analog inputs should not exceed

the recommended value of 1.0 V.





APGAIN 



Code = ADC × 1+









2¹²









For example when 7FFh is written to the Active Power Gain

register the ADC output is scaled up by 50%. 7FFh = 2047 deci-

mal, 2047/2¹²= 0.5. Similarly, 801h = –2047 decimal (signed

two’s complement) and ADC output is scaled by –50%. These

two examples are graphically illustrated in Figure 18.

Channel 1 Sampling

The waveform samples may also be routed to the Waveform

register (MODE[14:13] = 1, 0) to be read by the system master

(MCU). In waveform sampling mode the WSMP bit (Bit 3) in

the Interrupt Enable register must also be set to Logic 1. The

Active Power and Energy calculation will remain uninterrupted

during waveform sampling.

When in waveform sample mode, one of four output sample rates

may be chosen by using Bits 11 and 12 of the Mode register

(WAVSEL1, 0). The output sample rate may be 27.9 kSPS,

14 kSPS, 7 kSPS or 3.5 kSPS—see Mode Register section. The

interrupt request output IRQ signals a new sample availability

by going active low. The timing is shown in Figure 19. The

20-bit waveform samples are transferred from the ADE7756 one

byte (8 bits) at a time, with the most significant byte shifted out

first. The 20-bit data word is right-justified and sign extended

to 24 bits (three bytes)—see Serial Interface section.

Channel 1 ADC Gain Adjust

The ADC gain in Channel 1 can be adjusted by using the multi-

plier and Active Power Gain register (APGAIN[11:0]). The

gain of the ADC is adjusted by writing a two’s complement

12-bit word to the Active Power Gain register. Following is

x1, x2, x4,

TO

2.42V, 1.21V, 0.6V

x8, x16

WAVEFORM

REGISTER

GAIN[4:3]

REFERENCE

GAIN[2:0]

WAVEFORM[23:0]

DIGITAL

LPF

HPF

MULTIPLIER

V1P

V1N

TO

ADC

3

PGA1

V1

SINC

MULTIPLIER

1

20

12

CHANNEL 1 (ACTIVE POWER)

CALIBRATION RANGE

801Hex – 7FFHex

1V, 0.5V, 0.25V, 125mV,

62.5mV, 31.3mV, 15.6mV

APGAIN[11:0]

+94.5% FS

+63% FS

+31.5% FS

3C7AEh

2851Fh

1428Fh

00000h

EBD71h

D7AE1h

C3852h

+FS

+63% FS

40000h

2851Fh

0V

–31.5% FS

–63% FS

–94.5% FS

00000h

ANALOG INPUT

RANGE

–63% FS

–FS

D7AE1h

C0000h

000h

7FFh

801h

ADC OUTPUT

WORD RANGE

APGAIN[11:0]

Figure 18. ADC and Signal Processing in Channel 1

–18–

REV. 0

ADE7756

SAMPLING RATE

(27.9kSPS, 14kSPS, 7kSPS OR 3.5kSPS)

This has the effect of attenuating the signal. For example, if the

line frequency is 60 Hz, the signal at the output of LPF1 will be

attenuated by 30%.

1

IRQ

|H( f )|=

= 0.93 = –0.6 dB





²



16ꢄs

60 Hz

156 Hz

SCLK

DIN

1+





READ FROM WAVEFORM

01 HEX

0

0 0

Note that LPF1 does not affect the power calculation. The signal

processing chain in Channel 2 is illustrated in Figure 21. Unlike

Channel 1, Channel 2 has only one analog input range (1 V

differential). However, like Channel 1, Channel 2 does have a PGA

with gain selections of 1, 2, 4, 8, and 16. For energy measure-

ment, the output of the ADC is passed directly to the multiplier

and is not filtered. An HPF is not required to remove any dc

offset since it is only required to remove the offset from one chan-

nel to eliminate errors due to offsets in the power calculation.

When in waveform sample mode, one of four output sample

rates can be chosen by using Bits 11 and 12 of the Mode regis-

ter. The available output sample rates are 27.9 kSPS, 14 kSPS,

7 kSPS or 3.5 kSPS—see Mode Register section. The interrupt

request output IRQ signals a new sample availability by going

active low. The timing is the same as that for Channel 1 and is

shown in Figure 19.

DOUT

SIGN

CHANNEL 1 DATA – 20 BITS

Figure 19. Waveform Sampling Channel 1

CHANNEL 2 ADC

Channel 2 Sampling

In Channel 2 waveform sampling mode (MODE[14:13] = 1,1

and WSMP = 1) the ADC output code scaling for Channel 2 is

the same as Channel 1, i.e., the output swings between D7AE1h

(–165,151) and 2851Fh (+165,151)—see ADC Channel 1 sec-

tion. However, before being passed to the Waveform register, the

ADC output is passed through a single-pole, low-pass filter

with a cutoff frequency of 156 Hz. The plots in Figure 20

shows the magnitude and phase response of this filter.

x1, x2, x4,

x8, x16

2.42V

REFERENCE

0

GAIN[7:5]

(60Hz, –0.6dB)

–63% TO + 63% FS

V2P

V2N

1

TO

ADC2

PGA2

V2

–20

MULTIPLIER

LPF1

TO

WAVEFORM

REGISTER

20

V1

1V, 0.5V,

0.25V, 0.125V,

0.0625V

–40

–60

–80

–20

LPF OUTPUT

WORD RANGE

(60Hz, –21.04ꢃ)

40000h

2851Fh

1C396h

0V

+FS

+63% FS

+44% FS

60Hz

ANALOG INPUT

RANGE

00000h

60Hz

–44% FS

–63% FS

–FS

E3C6Ah

D7AE1h

C0000h

–40

3

1

2

10

FREQUENCY – Hz

Figure 21. ADC and Signal Processing in Channel 2

Figure 20. Magnitude and Phase Response of LPF1

REV. 0

–19–

ADE7756

0.30

0.25

0.20

0.15

0.10

0.05

0

PHASE COMPENSATION

When the HPF is disabled, the phase error between Channel 1

and Channel 2 is zero from dc to 3.5 kHz. When HPF1 is enabled,

Channel 1 has a phase response illustrated in Figures 23 and 24.

Also shown in Figure 25 is the magnitude response of the filter.

As can be seen from the plots, the phase response is almost zero

from 45 Hz to 1 kHz. This is all that is required in typical energy

measurement applications.

However, despite being internally phase compensated the

ADE7756 must work with transducers that may have inherent

phase errors. For example, a phase error of 0.1° to 0.3° is not

uncommon for a CT (Current Transformer). These phase errors

can vary from part to part and must be corrected in order to

perform accurate power calculations. The errors associated with

phase mismatch are particularly noticeable at low power factors.

The ADE7756 provides a means of digitally calibrating these

small phase errors. The ADE7756 allows a small time delay or

time advance to be introduced into the signal processing chain

in order to compensate for small phase errors. Because the

compensation is in time, this technique should only be used for

small phase errors in the range of 0.1° to 0.5°. Correcting large

phase errors using a time shift technique can introduce signifi-

cant phase errors at higher harmonics.

–0.05

–0.10

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY – Hz

Figure 23. Combined Phase Response of the HPF and

Phase Compensation (10 Hz to 1 kHz)

0.30

0.25

0.20

0.15

0.10

0.05

0

The Phase Calibration register (PHCAL[5:0]) is a two’s comple-

ment 6-bit signed register that can vary the time delay in the

Channel 2 signal path from –143 µs to +143 µs (CLKIN =

3.579545 MHz). One LSB is equivalent to 4.47 µs. With a line

frequency of 60 Hz, this gives a phase resolution of 0.097° at the

fundamental (i.e., 360° × 4.47 µs × 60 Hz). Figure 22 illustrates

how the phase compensation is used to remove a 0.097° phase

lead in Channel 1 due to some external transducer. In order to

cancel the lead (0.097°) in Channel 1, a phase lead must also be

introduced into Channel 2. The resolution of the phase adjustment

allows the introduction of a phase lead of 0.097°. The phase lead is

achieved by introducing a time advance into Channel 2. A time

advance of 4.47 µs is made by writing –1 (3Fh) to the time delay

block, thus reducing the amount of time delay by 4.47 µs.

–0.05

–0.10

40

45

50

55

60

65

70

Figure 24. Combined Phase Response of the HPF and

Phase Compensation (40 Hz to 70 Hz)

0.40

0.30

HPF

V1P

ADC1

PGA1

PGA2

0.20

V1

V2

20

LPF2

V1N

0.10

20

DELAY

V2P

V2N

ADC2

BLOCK

0.00

CHANNEL 2 DELAY

REDUCED BY 4.47ꢄs

(0.097ꢃ LEAD AT 60Hz)

3Fh IN PHCAL[5:0]

1

4.47ꢄs/LSB

5

0

–0.10

–0.20

–0.30

–0.40

1 1 1 1 1 1

V1

V2

PHCAL[5:0]

–143ꢄs TO +143ꢄs

V1

V2

0.097"

54

56

58

60

62

64

68

60Hz

FREQUENCY – Hz

Figure 22. Phase Calibration

Figure 25. Combined Phase Response of the HPF and

Phase Compensation (Deviation of Gain in % from

Gain at 60 Hz)

–20–

REV. 0

ADE7756

ACTIVE POWER CALCULATION

Figure 28 shows the signal processing chain for the Active

Power calculation in the ADE7756. As explained, the Active

Power is calculated by low-pass filtering the instantaneous

power signal.

Electrical power is defined as the rate of energy flow from source to

load. It is given by the product of the voltage and current wave-

forms. The resulting waveform is called the instantaneous power

signal and it is equal to the rate of energy flow at every instant of

time. The unit of power is the watt or joules/sec. Equation 3

gives an expression for the instantaneous power signal in an

ac system.

0

–4

–8

(1)

(2)

v(t) = 2 V sin(ωt)

i(t) = 2 I sin(ωt)

–12

–16

–20

where

V = rms voltage,

I = rms current.

p(t) = v(t)× i(t)

p(t) =VI –VI cos (2 ωt)

(3)

–24

1

3

10

30

100

FREQUENCY – Hz

The average power over an integral number of line cycles (n) is

given by the expression in Equation 4.

Figure 27. Frequency Response of LPF2

nT

1

nT

P =

p(t)dt =VI

∫

ACTIVE POWER

SIGNAL – P

(4)

0

HPF

CCCDh

where

I

20

CURRENT SIGNAL – I(t)

MULTIPLIER

LPF2

T is the line cycle period.

and

P is referred to as the Active or Real Power.

20

INSTANTANEOUS POWER SIGNAL

p(t) = –40%FS TO +40%FS

1

V

VOLTAGE SIGNAL – V(t)

1999Ah

Note that the active power is equal to the dc component of the

instantaneous power signal p(t) in Equation 3 , i.e., VI. This is

the relationship used to calculate active power in the ADE7756.

The instantaneous power signal p(t) is generated by multiplying

the current and voltage signals. The dc component of the instan-

taneous power signal is then extracted by LPF2 (Low-Pass Filter)

to obtain the active power information. This process is graphi-

cally illustrated in Figure 26. Since LPF2 does not have an ideal

“brick wall” frequency response—see Figure 27—the Active

Power signal will have some ripple due to the instantaneous

power signal. This ripple is sinusoidal and has a frequency equal

to twice the line frequency. Since the ripple is sinusoidal in

nature it will be removed when the Active Power signal is inte-

grated to calculate Energy—see Energy Calculation section.

00h

Figure 28. Active Power Signal Processing

Shown in Figure 29 is the maximum code (Hexadecimal) out-

put range for the Active Power signal (LPF2). Note that the

output range changes, depending on the contents of the Active

Power Gain register—see Channel 1 ADC section. The mini-

mum output range is given when the Active Power Gain register

contents are equal to 800h, and the maximum range is given

by writing 7FFh to the Active Power Gain register. This can

be used to calibrate the Active Power (or Energy) calculation

in the ADE7756.

INSTANTANEOUS

p(t) = V ꢅ 1 – V ꢅ 1 ꢅ COS(2ꢆt)

POWER SIGNAL

1999Ah

CCCDh

+30% FS

+20% FS

+10% FS

1999Ah

POSITIVE

POWER

ACTIVE REAL POWER

SIGNAL = V ꢅ I

6666h

00000h

F999Ah

F3333h

E6666h

V. I.

CCCDh

–10% FS

–20% FS

–30% FS

NEGATIVE

POWER

000h

7FFh

800h

00000h

APGAIN[11:0]

CURRENT

I(t) = 2 ꢅ I ꢅ SIN(ꢆt)

CHANNEL 1 (ACTIVE POWER)

CALIBRATION RANGE

VOLTAGE

V(t) = 2 ꢅ V ꢅ SIN(ꢆt)

Figure 29. Active Power Calculation Output Range

Figure 26. Active Power Calculation

REV. 0

–21–

ADE7756

ENERGY CALCULATION

The Active Power signal can be read from the Waveform regis-

ter by setting MODE[14:13] = 0,0 and setting the WSMP bit

(Bit 3) in the Interrupt Enable register to 1. Like the Channel 1

and Channel 2 waveform sampling modes, the waveform date

is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS or

3.5 kSPS—see Figure 19.

As stated earlier, power is defined as the rate of energy flow.

This relationship can be expressed mathematically as Equation 5.

dE

P =

(5)

dt

where

Figure 31 shows this energy accumulation for full-scale signals

(sinusoidal) on the analog inputs. The three curves displayed,

illustrate the minimum period of time it takes the energy register

to roll-over when the Active Power Gain register contents are

3FFh, 000h and 800h. The Active Power Gain register is used

to carry out power calibration in the ADE7756. As shown, the

fastest integration time will occur when the Active Power Gain

register is set to maximum full scale, i.e., 3FFh.

P = Power, and

E = Energy.

Conversely, Energy is given as the integral of Power.

(6)

E = ∫ Pdt

The ADE7756 achieves the integration of the Active Power signal

by continuously accumulating the Active Power signal in the 40-bit

Active Energy register (AENERGY[39:0]). This discrete time

accumulation or summation is equivalent to integration in con-

tinuous time. Equation 7 expresses the relationship

AENERGY[39:0]

7F,FFFF,FFFFh

∞

APGAIN = 3FFh













E = p(t)dt = Lim

p(nT)×T

∑

∫

(7)

T→0

n = 0

3F,FFFF,FFFFh

where

APGAIN = 000h

TIME

n is the discrete time sample number

and

T is the sample period.

00,0000,0000h

(SECONDS)

5.8s 11.5s

23s

40,0000,0000h

80,0000,0000h

APGAIN = 800h

The discrete time sample period (T) for the accumulation regis-

ter in the ADE7756 is 1.1 µs (4/CLKIN). As well as calculating

the Energy, this integration removes any sinusoidal components

that may be in the Active Power signal.

Figure 31. Energy Register Roll-Over Time for Full-Scale

Power (Minimum and Maximum Power Gain)

Figure 30 shows a graphical representation of this discrete time

integration or accumulation. The Active Power signal in the

Waveform register is continuously added to the Active Energy

register. This addition is a signed addition, therefore negative

energy will be subtracted from the Active Energy contents.

APOS [11:0]

Note that the energy register contents will roll over to full-scale

negative (80,0000,0000h) and continue increasing in value when

the power or energy flow is positive—see Figure 31. Conversely,

if the power is negative the energy register would underflow to

full-scale positive (7F, FFFF, FFFFh) and continue decreasing

in value.

0

11

CURRENT

CHANNEL

WAVEFORM [23:0]

AENERGY[39:0]

LPF2

0

23

By using the Interrupt Enable register, the ADE7756 can be

configured to issue an interrupt (IRQ) when the Active Energy

register is half-full (positive or negative) or when an over-/under-

flow occurs.

20

VOLTAGE

CHANNEL

39

ACTIVE POWER

SIGNAL – P

Integration Times under Steady Load

4

WAVEFOR

REGISTER

VALUES

T

CLKIN

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.1 µs (4/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

Active Power Gain register set to 000h, the average word value

from LPF2 is CCCDh—see Figure 34. The maximum value

that can be stored in the Active Energy register before it over-

flows is 2³⁹or 7F, FFFF, FFFFh. Therefore the integration

time under these conditions is calculated as follows:

WAVEFORM REGISTER VALUES ARE

ACCUMULATED (INTEGRATED) IN

THE ACTIVE ENERGY REGISTER

TIME – nT

Figure 30. Energy Calculation

As shown in Figure 30, the Active Power signal is accumulated

in a 40-bit signed register (AENERGY[39:0]).

7F, FFFF, FFFFh

Time =

×1.1µs = 11.53 seconds

CCCDh

–22–

REV. 0

ADE7756

POWER OFFSET CALIBRATION

on CF when the MSB in the Digital-to-Frequency register (24

bits) toggles, i.e., when the register accumulates 2²³. This means

the register is updated 2²³/CCCDh times (or 159.999 times). Since

the update rate is 4/CLKIN or 1.1175 µs, the time between

MSB toggles (CF pulses) is given as:

The ADE7756 also incorporates an Active Power Offset regis-

ter (APOS[11:0]). This is a signed, two’s complement, 12-bit

register that can be used to remove offsets in the active power

calculation—see Figure 30. An offset may exist in the power

calculation due to crosstalk between channels on the PCB or

in the IC itself. The offset calibration will allow the contents

of the Active Power register to be maintained at zero when no

power is being consumed.

159.999 × 1.1175 µs = 1.78799 × 10^–4s = 5592.86 Hz.

Equation 8 gives an expression for the output frequency at CF

with the CFDIV register = 0.

Average LPF2 Output × CLKIN

Sixteen LSBs (APOS = 010h) written to the Active Power Off-

set register are equivalent to 1 LSB in the Waveform Sample

register. Assuming the average value outputs from LPF2 to store

in the Waveform Register is CCCDh (52,429 in Decimal) when

inputs on Channels 1 and 2 are both at full scale. At –60 dB

down on Channel 1 (1/1000 of the full-scale input), the average

word value outputs from LPF2 is 52.429 (52,429/1,000). 1 LSB

in the Waveform register has a measurement error of 1/52.429 ×

100% = 1.9% of the average value. The Active Power Offset

register has a resolution equal to 1/16 LSB of the Waveform

register, hence the power offset correction resolution is 0.12%

(1.9%/16) at –60 dB.

CF(Hz) =

(8)

2²⁵

This output frequency is easily scaled by the Calibration Fre-

quency Division register (CFDIV[11:0]). This frequency scaling

register is a 12-bit register that scales the output frequency by 1

to 2¹². The output frequency is given in Equation 9.

Frequency (CFDIV = 0)

Frequency =

(9)

CFDIV +1

For example, if the output frequency is 5.59286 kHz while the

content of CFDIV is zero (000h), the output frequency can be

set to 5.4618 Hz by writing 3FFh Hex (1023 Decimal) to the

CFDIV register. The power-up default value in CFDIV is 3Fh.

ENERGY-TO-FREQUENCY CONVERSION

ADE7756 also provides energy-to-frequency conversion for

calibration purposes. After initial calibration at manufacture, the

manufacturer or end customer will often verify the energy meter

calibration. One convenient way to verify the meter calibration

is for the manufacturer to provide an output frequency that is

proportional to the energy or active power under steady load

conditions. This output frequency can provide a simple, single

wire, optically isolated interface to external calibration equip-

ment. Figure 32 illustrates the Energy-to-Frequency conversion

in the ADE7756.

The output frequency will have a slight ripple at a frequency equal

to twice the line frequency. This is due to imperfect filtering of

the instantaneous power signal to generate the Active Power

signal—see Active Power Calculation section. Equation 3 gives

an expression for the instantaneous power signal. This is

filtered by LPF2, which has a magnitude response given by

Equation 10.

1

|H( f )|=

(10)

1+ f /8.9 Hz

The Active Power signal (output of LPF2) can be rewritten as

APOS [11:0]

0

11

ACTIVE POWER

OFFSET

CALIBRATION

WAVEFORM [23:0]





VI

LPF2

0

23

p(t) =VI –

cos (4 × π × fl × t)









(11)

1+ 2 fl / 8.9 Hz

20

ENERGY-TO-FREQUENCY

23

ACTIVE POWER

SIGNAL – P

where fl is the line frequency (e.g., 60 Hz)

0

From Equation 6





MSB TRANSITION

VI

E(t) =VIt –

sin (4 × π × fl × t)





(12)

4 × π × fl 1+ 2 fl /8.9 Hz

(

)





CFDIV[11:0]

11

0

From Equation 12 it can be seen that there is a small ripple in

the energy calculation due to a sin(2 ωt) component. This is

shown graphically in Figure 33. The Active Energy calculation

is shown by the dashed straight line and is equal to V × I × t.

The sinusoidal ripple in the Active Energy calculation is also

shown. Since the average value of a sinusoid is zero, this ripple

will contribute nothing to the energy calculation over time. How-

ever, the ripple can be observed in the frequency output, especially

at higher output frequencies. The ripple will get larger as a

percentage of the frequency at larger loads and higher output

frequencies. The reason is simply that at higher output frequen-

cies the integration or averaging time in the energy-to-frequency

conversion process is shorter. As a consequence, some of the

sinusoidal ripple is observable in the frequency output. Choosing

a lower output frequency at CF for calibration can significantly

CF

Figure 32. Energy-to-Frequency Conversion

The energy-to-frequency conversion is accomplished by accumu-

lating the Active power signal in a 24-bit register. An output

pulse is generated when there is a zero to one transition on the

MSB (most significant bit) of the register. Under steady load con-

ditions the output frequency is proportional to the Active Power.

The output frequency at CF, with full-scale ac signals on Chan-

nel 1 and Channel 2 and CFDIV = 000h and APGAIN = 000h,

is approximately 5.593 kHz. This can be calculated as follows:

with the Active Power Gain register set to 000h, the average

value of the instantaneous power signal (output of LPF2) is

CCCDh or 52,429 decimal. An output frequency is generated

REV. 0

–23–

ADE7756

APOS [11:0]

reduce the ripple. Also, averaging the output frequency by using

a longer gate time for the counter will achieve the same results.

0

11

WAVEFORM [23:0]

LPF2

E(t)

0

23

FROM

MULTIPLIER

VIt

ACTIVE POWER

SIGNAL – P

AENERGY[39:0}

0

39

CCCDh

00h

LPF1

CHANNEL 2

ADC

CALIBRATION

CONTROL

ZERO CROSS

DETECT

VI

SIN(4 ꢅ ꢇ ꢅ f ꢅ t)

l

4 ꢅ ꢇ ꢅ f (1 + 2 ꢅ f /8.9Hz

l

SAGCYC[7:0]

t

Figure 34. Energy Calculation in Calibration Mode

Figure 33. Output Frequency Ripple

ENERGY CALIBRATION

CALIBRATING THE ENERGY METER

Calculating the Average Active Power

By using the on-chip zero-crossing detection on Channel 2 the

energy calibration can be greatly simplified and the time required

to calibrate the meter can be significantly reduced. To use the

zero-cross detection the ADE7756 is placed in calibration mode

by setting Bit 7 (CMODE) in the Mode register. In Calibration

Mode the ADE7756 accumulates the Active Power signal in the

Active Energy register for an integral number of half cycles, as

shown in Figure 34. The number of half-line cycles is specified

in the SAGCYC register. The ADE7756 can accumulate Active

Power for up to 255 half-cycles. Because the Active Power is

integrated on an integral number of line cycles, the sinusoidal

component is reduced to zero. This eliminates any ripple in the

energy calculation. Energy is calculated more accurately and in

a shorter time because integration period can be shortened. At

the end of an energy calibration cycle the SAG flag in the Inter-

rupt Status register is set; this will cause the SAG output to go

active low. If the SAG enable bit in the Interrupt Enable register

is enabled, the IRQ output will also go active low. Thus the IRQ

line can be used to signal the end of a calibration also. Another

calibration cycle will start as long as the CMODE bit in the

Mode register is set. Note that the result of the first calibration

is invalid and must be ignored. The result of all subsequent

calibration cycles is correct.

When calibrating the ADE7756, the first step is to calibrate

the frequency on CF to some required meter constant, e.g.,

3200 imp/kWh.

In order to determine the output frequency on CF, the average

value of the Active Power signal (output of LPF2) must first be

determined. One convenient way to do this is to use the calibra-

tion mode. When the CMODE (Bit 7) bit in the Mode register

is set to a Logic 1, energy is accumulated over an integer num-

ber of half-line cycles as described in the last section.

Since the line frequency is fixed at, say, 60 Hz, and the number

of half-cycles of integration is specified, the total integration

time is given as:

1

× number of half cycles

2 × 60 Hz

For 255 half-cycles this would give a total integration time of

2.125 seconds. This would mean the energy register was updated

2.125/1.1175 µs (4/CLKIN) times. The average output value of

LPF2 is given as:

Contents of AENERGY[39:0]at the end

Number of times AENERGY[39:0]was updated

Or equivalently, in terms of contents of various ADE7756 regis-

ters and CLKIN and line frequencies (fl):

From Equations 5 and 11,

AENERGY[39:0]× 8 × fl

SAGCYC[7:0]× CLKIN

where fl is the line frequency.

nT

^nTcos (2 ωt) dt









VI

Average word (LPF2) =

(16)

E(t) VIdt –

∫





(13)

1+ 2 fl / 8.9 Hz

0

where n is an integer and T is the line cycle period.

Since the sinusoidal component is integrated over an integer

number of line cycles, its value is always zero.

Calibrating the Frequency at CF

Once the average Active Power signal is calculated it can be used

to determine the frequency at CF before calibration. When the

frequency before calibration is known, the Calibration Frequency

Divider register (CFDIV) and the Active Power Gain register

(APGAIN) can be adjusted to produce the required frequency

on CF. In this example, a meter constant of 3200 imp/kWh is

chosen as an appropriate constant. This means that under a

steady load of 1 kW, the output frequency on CF would be,

Therefore:

E(t) = ^nTVIdt

∫

(14)

(15)

0

E(t) =VInt

3200 imp/kWh

60 min × 60 sec

3200

3600

Frequency (CF) =

=

= 0.8888 Hz

–24–

REV. 0

ADE7756

Assuming the meter is set up with a test current (basic current)

of 20 A and a line voltage of 220 V for calibration, the load is

calculated as 220 V × 20 A = 4.4 kW. Therefore the expected

output frequency on CF under this steady load condition would

be 4.4 × 0.8888 Hz = 3.9111 Hz.

CLKIN FREQUENCY

In this data sheet, the characteristics of the ADE7756 are shown

with CLKIN frequency equal to 3.579545 MHz. However, the

ADE7756 is designed to have the same accuracy at any CLKIN

frequency within the specified range. If the CLKIN frequency is

not 3.579545 MHz, various timing and filter characteristics will

need to be redefined with the new CLKIN frequency. For

example, the cut-off frequencies of all digital filters (LPF1,

LPF2, HPF1, etc.) will shift in proportion to the change in

CLKIN frequency according to the following equation:

Under these load conditions the transducers on Channel 1 and

Channel 2 should be selected such that the signal on the voltage

channel should see approximately half scale and the signal on

the current channel about 1/8 of full scale (assuming a maximum

current of 80A). The average value from LPF2 is calculated

as 3,276.81 decimal using the calibration mode as described

above. Then, using Equation 8 (Energy to Frequency Conver-

sion), the frequency under this load is calculated as:

CLKIN Frequency

3.579545 MHz

New Frequency = Original Frequency ×

(17)

The change of CLKIN frequency does not affect the timing

characteristics of the serial interface because the data transfer is

synchronized with serial clock signal (SCLK). But one needs to

observe the read/write timing of the serial data transfer-see

Timing Characteristics. Table III lists various timing changes

that are affected by CLKIN frequency.

3276.81× 3.579545 MHz

Frequency (CF) =

= 349.566 Hz

2²⁵

However, this is the frequency with the contents of the CFDIV

and APGAIN registers equal to 000h. The desired frequency

out is 3.9111 Hz. Therefore the CF frequency must be divided

by 349.566/3.9111 Hz or 89.378 decimal. This is achieved by

loading the CF Divide register with 88 (or 58h)—Note the CF

frequency is divided by the contents of CFDIV + 1.

APPLICATION INFORMATION

Application note AN-564 contains detail information on how

to design a ANSI Class 100 Watt-Hour meter based on the

ADE7756. It is available from the ADE7756 product home page

under the Application Note link. Figure 35 shows the block dia-

gram of the ADE7756 reference meter implemented in AN-564.

The fine adjustment of the output frequency can be made using

the Active Power Gain register. This register has a fine gain

adjustment of 0.0244%/LSB. With the CF Divide register con-

tents equal to 58h, the output frequency is given as 349.556 Hz/

89 = 3.9276 Hz. This setting has an error of 0.42%. This

error can be further reduced by writing –(0.21/0.0244) or –17 to

APGAIN[11:0] i.e., FEFh.

LOAD

16ꢅ2 LCD DISPLAY

Calibrating CF is made easy by using the Calibration mode on

the ADE7756. The only critical part of the setup is that the line

frequency be exactly known. If this is not possible, it could be

measured by using the ZX output of the ADE7756.

ADE7756

PIC16C62B

SPI BUS

EEPROM

Energy Meter Display

Besides the pulse output which is used to verify calibration, a

solid state energy meter will very often require some form of

display. The display should display the amount of energy con-

sumed in kWh (Kilowatt Hours). One convenient and simple

way to interface the ADE7756 to a display or energy register (e.g.,

MCU with nonvolatile memory) is to use CF. For example the

CF frequency could be calibrated to 1,000 imp/kWh. The MCU

would count pulses from CF. Every pulse would be equivalent

to 1 watt-hour. If more resolution is required the CF frequency

could be set to, say, 10,000 imp/kWh.

RS-232

N

L1

L2

CF

220V

Figure 35. Block Diagram of the ADE7756 Reference

Meter Described in AN-564

Table III. Frequency Dependencies of the

ADE7756 Parameters

CLKIN

If more flexibility is required when monitoring energy usage, the

Active Energy register (AENERGY) can be used to calculate

energy. A full description of this register can be found in the

Energy Calculation section. The AENERGY register gives the

user both sign and magnitude information regarding energy

consumption. On completion of the CF frequency output cali-

bration, i.e., after the Active Power Gain (APGAIN) register has

been adjusted, a second calibration sequence can be initiated.

The purpose of this second calibration routine is to determine a

kWh/LSB coefficient for the AENERGY register. Once the

coefficient has been calculated the MCU can determine the

energy consumption at any time by reading the AENERGY

contents and multiplying by the coefficient to calculate kWh.

Parameter

Dependency

Nyquist Frequency for CH 1 and 2 ADCs

PHCAL Resolution (Seconds per LSB)

Active Energy Register Update Rate (Hz)

Waveform Sampling Rate

(Number of Samples per Second)

WAVSEL 1, 0 = 0

CLKIN/8

16/CLKIN

CLKIN/4

0

1

0

1

CLKIN/128

CLKIN/256

CLKIN/512

CLKIN/1024

524,288/CLKIN

0

1

Maximum ZXTOUT Period

REV. 0

–25–

ADE7756

SUSPENDING THE ADE7756 FUNCTIONALITY

CS

The analog and the digital circuit can be suspended separately.

The analog portion of the ADE7756 can be suspended by set-

ting the ASUSPEND bit (Bit 4) of the Mode register to logic

high—see Mode Register section. In suspend mode, all wave-

form samples from the ADCs will be set to zeros. The digital

circuitry can be halted by holding the CLKIN input to 0 or 1.

The ADE7756 can be reactivated by restoring the CLKIN input

and setting the ASUSPEND bit to logic low.

SCLK

DIN

COMMUNICATIONS REGISTER WRITE

MULTIBYTE WRITE DATA

1

0 0

ADDRESS

Figure 37b. Writing Data to the ADE7756 via the Serial

Interface

A data transfer is complete when the LSB of the ADE7756

register being addressed (for a write or a read) is transferred to

or from the ADE7756.

SERIAL INTERFACE

All ADE7756 functionality is accessible via several on-chip

registers—see Figure 36. The contents of these registers can be

updated or read using the on-chip serial interface. After power-

on, or toggling the RESET pin low, on a falling edge on CS, the

ADE7756 is placed in Communications Mode. In Communications

Mode the ADE7756 expects a write to its Communications

register. The data written to the Communications register deter-

mines whether the next data transfer operation will be a read or

a write and also which register is accessed. Therefore all data trans-

fer operations with the ADE7756, whether a read or a write,

must begin with a write to the Communications register.

The Serial Interface of the ADE7756 is made up of four signals

SCLK, DIN, DOUT, and CS. The serial clock for a data trans-

fer is applied at the SCLK logic input. This logic input has a

Schmitt-trigger input structure, which allows slow rising (and

falling) clock edges to be used. All data transfer operations are

synchronized to the serial clock. Data is shifted into the ADE7756

at the DIN logic input on the falling edge of SCLK. Data is shifted

out of the ADE7756 at the DOUT logic output on a rising edge

of SCLK. The CS logic input is the chip select input. This input

is used when multiple devices share the serial bus. A falling edge

on CS also resets the serial interface and places the ADE7756 in

Communications Mode. The CS input should be driven low for

the entire data transfer operation. Bringing CS high during a data

transfer operation will abort the transfer and place the serial bus

in a high impedance state. The CS logic input may be tied low if

the ADE7756 is the only device on the serial bus. However,

with CS tied low all initiated data transfer operations must be

fully completed, i.e., the LSB of each register must be trans-

ferred as there is no other way of bringing the ADE7756 back

into Communications Mode without resetting the entire device,

i.e., using RESET.

DIN

COMMUNICATIONS REGISTER

IN

REGISTER #1

REGISTER #2

REGISTER #3

OUT

DOUT

IN

OUT

REGISTER

ADDRESS

DECODE

IN

OUT

IN

OUT

REGISTER #n–1

IN

OUT

Serial Write Operation

REGISTER #n

The serial write sequence takes place as follows. With the

ADE7756 in Communications Mode (i.e., the CS input logic

low), a write to the Communications register first takes place.

The MSB of this byte transfer is a 1, indicating that the data

transfer operation is a write. The LSBs of this byte contain the

address of the register to be written to. The ADE7756 starts

shifting in the register data on the next falling edge of SCLK.

All remaining bits of register data are shifted in on the falling

edge of subsequent SCLK pulses—see Figure 38.

Figure 36. Addressing ADE7756 Registers via the

Communications Register

The Communications register is an 8-bit-wide register. The

MSB determines whether the next data transfer operation is a

read or a write. The 5 LSBs contain the address of the register

to be accessed. See Communications Register section for a more

detailed description.

Figure 37a and 37b show the data transfer sequences for a read

and write operation respectively.

As explained earlier, the data write is initiated by a write to the

communications register followed by the data. During a data

write operation to the ADE7756, data is transferred to all on-

chip registers one byte at a time. After a byte is transferred into

the serial port, there is a finite time before it is transferred to

one of the ADE7756 on-chip registers. Although another byte

transfer to the serial port can start while the previous byte is

being transferred to an on-chip register, this second byte trans-

fer should not finish until at least 4 µs after the end of the previous

byte transfer. This functionality is expressed in the timing speci-

fication t₆—see Figure 38. If a write operation is aborted during

a byte transfer (CS brought high), that byte will not be written

to the destination register.

On completion of a data transfer (read or write) the ADE7756

once again enters Communications Mode.

CS

SCLK

COMMUNICATIONS REGISTER WRITE

DIN

0 0 0

ADDRESS

MULTIBYTE READ DATA

DOUT

Destination registers may be up to 2 bytes wide—see Register

Descriptions section. Hence the first byte shifted into the serial

port at DIN is transferred to the MSB (Most Significant Byte)

of the destination register. If the addressed register is 12 bits

Figure 37a. Data from the ADE7756 via the Serial

Interface

–26–

REV. 0

ADE7756

wide, for example, a 2-byte data transfer must take place. The

data is always assumed to be right justified, therefore, in this case,

the 4 MSBs of the first byte would be ignored and the 4 LSBs of

the first byte written to the ADE7756 would be the 4 MSBs of

the 12-bit word. Figure 39 illustrates this example.

All remaining bits of register data are shifted out on subsequent

SCLK rising edges. The serial interface also enters Communi-

cations Mode again as soon as the read has been completed. At

this point the DOUT logic output enters a high impedance state

on the falling edge of the last SCLK pulse. The read operation

may be aborted by bringing the CS logic input high before

the data transfer is complete. The DOUT output enters a high

impedance state on the rising edge of CS.

Serial Read Operation

During a data read operation from the ADE7756, data is shifted

out at the DOUT logic output on the rising edge of SCLK. As

was the case with the data write operation, a data read must be

preceded with a write to the Communications register.

When an ADE7756 register is addressed for a read operation,

the entire contents of that register are transferred to the serial

port. This allows the ADE7756 to modify its on-chip registers

without the risk of corrupting data during a multibyte transfer.

Note when a read operation follows a write operation, the read

command (i.e., write to communications register) should not

happen for at least 4 µs after the end of the write operation. If

the read command is sent within 4 µs of the write operation, the

last byte of the write operation may be lost. This is given as

timing specification t₉.

With the ADE7756 in Communications Mode (i.e., CS logic

low) an 8-bit write to the Communications register first takes

place. The MSB of this byte transfer is a 0, indicating that the

next data transfer operation is a read. The LSBs of this byte

contain the address of the register to be read. The ADE7756

starts shifting out of the register data on the next rising edge of

SCLK—see Figure 40. At this point the DOUT logic output

leaves its high impedance state and starts driving the data bus.

t₈

CS

t₂

t₆

t₁

t₃

t₇

SCLK

DIN

t₄

t₅

1

0

A4

A3

A2 A1

A0

DB7

DB0

DB7

DB0

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 38. Serial Interface Write Timing Diagram

SCLK

DIN

X

DB11 DB10 DB9 DB8

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LEAST SIGNIFICANT BYTE

MOST SIGNIFICANT BYTE

Figure 39. 12-Bit Serial Write Operation

CS

t₁

t₁₃

t₉

t₁₀

SCLK

DIN

0

A4

A3

A2 A1

A0

t₁₂

t₁₁

DOUT

DB0

DB7

DB0

DB7

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 40. Serial Interface Read Timing Diagram

REV. 0

–27–

ADE7756

Table IV. Register List

No. of

Bits

Address Name

R/W

Default Description

00h

01h

Not Used

WAVEFORM

No Operation.

R

24

40

0h

The Waveform register is a 24 bit read-only register. This register

contains the sampled waveform data from either Channel 1, Channel 2

or the Active Power signal. The data source is selected by data bits 14

and 13 in the Mode Register—see Channel 1 and 2 Sampling sections.

The Active Energy Register. Active Power is accumulated (Integrated)

over time in this 40-bit, read-only register. The energy register can hold a

minimum of 6 seconds of Active Energy information with full-scale

analog inputs before it overflows—see Energy Calculation section.

02h

AENERGY

R

03h

04h

RSTENERGY

STATUS

R

40

8

0h

Same as the Active Energy register except that the register is reset to

zero following a read operation

The Interrupt Status Register. This is an 8-bit read-only register. The

Status Register contains information regarding the source of ADE7756

interrupts—see Interrupts section.

05h

06h

RSTSTATUS

MODE

R

8

0h

Same as the Interrupt Status register except that the register contents

are reset to zero (all flags cleared) after a read operation.

The Mode Register. This is a 16-bit register through which most of the

ADE7756 functionality is accessed. Signal sample rates, filter enabling

and calibration modes are selected by writing to this register. The contents

may be read at any time—see Mode Register section.

R/W

16

000Ch

07h

CFDIV

R/W

12

3Fh

The Frequency Divider Register. This is a 12-bit read/write register.

The output frequency on the CF pin is adjusted by writing to this

register—see Energy to Frequency Conversion section.

08h

09h

0Ah

0Bh

CH1OS

CH2OS

GAIN

R/W

6

0h

Channel 1 Offset Adjust. Writing to this 6-bit register allows any off-

sets on Channel 1 to be removed—see Analog Inputs section.

Channel 2 Offset Adjust. Writing to this 6-bit register allows any off-

sets on Channel 2 to be removed—see Analog Inputs section.

PGA Gain Adjust. This 8-bit register is used to adjust the gain selec-

tion for the PGA in Channel 1 and Channel 2—Analog Inputs section.

Active Power Gain Adjust. This is a 12-bit register. The Active Power

calculation can be calibrated by writing to this register. The calibration

range is 50% of the nominal full scale active power. The resolution

of the gain adjust is 0.0244%/LSB—see Channel 1 ADC Gain

Adjust section.

6

8

APGAIN

12

0Ch

PHCAL

R/W

6

0h

Phase Calibration Register. The phase relationship between Channel 1

and Channel 2 can be adjusted by writing to this 6-bit register. The

adjustment range is approximately 3.1° at 60 Hz in 0.097° steps—see

Phase Compensation section.

0Dh

0Eh

APOS

R/W

12

8h

Active Power Offset Correction. This 12-bit register allows small off-

sets in the Active Power Calculation to be removed—see Active Power

Calculation section.

Zero-Cross Time Out. If no zero crossings are detected on Channel 2

within a time period specified by this 12-bit register, the interrupt

request line (IRQ) will be activated. The maximum time-out period is

0.15 second—see Zero Crossing Detection section.

ZXTOUT

FFFFh

0Fh

SAGCYC

R/W

8

FFh

Sag Line Cycle Register. This 8-bit register specifies the number of

consecutive half line cycles the signal on Channel 2 must be below

SAGLVL before the SAG output is activated—see Voltage Sag Detec-

tion section. It is also used during calibration mode to set the number

of line cycles Active power is accumulated for Energy calibration—see

Energy Calibration section.

–28–

REV. 0

ADE7756

Table IV. Register List (continued)

Default Description

No. of

Bits

Address Name

R/W

10H

11H

12H

IRQEN

SAGLVL

TEMP

R/W

8

0h

Interrupt Enable Register. ADE7756 interrupts may be deactivated at

any time by setting the corresponding bit in this 8-bit Enable register

Logic 0. The Status register will continue to register an interrupt event

even if disabled. However, the IRQ output will not be activated

—see Interrupts section.

Sag Voltage Level. An 8-bit write to this register determines at what

peak signal level on Channel 2 the SAG pin will become active. The

signal must remain low for the number of cycles specified in the SAGCYC

register before the SAG pin is activated—see Line Voltage Sag Detec-

tion section.

R/W

R

Temperature Register. This is an 8-bit register which contains the result

of the latest temperature conversion. A full description of this register’s

contents can be found in the Temperature Measurement section of this

data sheet.

REGISTER DESCRIPTIONS

All ADE7756 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications

register and then transferring the register data. A full description of the serial interface protocol is given in the Serial Interface section

of this data sheet.

Communications Register

The Communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7756 and the host

processor. All data transfer operations must begin with a write to the communications register. The data written to the communica-

tions register determines whether the next operation is a read or a write and which register is being accessed. Table V outlines the bit

designations for the Communications register.

Table V. Communications Register

DB7

DB6

0

DB5

0

DB4

A4

DB3

A3

DB2

A2

DB1

A1

DB0

A0

W/R

Bit

Location

Bit

Mnemonic

Description

0 to 4

A0 to A4

The five LSBs of the Communications register specify the register for the data transfer opera-

tion. Table IV lists the address of each ADE7756 on-chip register.

5 to 6

7

RESERVED

W/R

These bits are unused and should be set to zero.

When this bit is a Logic 1, the data transfer operation immediately following the write to the

Communications register will be interpreted as a write to the ADE7756. When this bit is a

Logic 0, the data transfer operation immediately following the write to the Communications

register will be interpreted as a read operation.

REV. 0

–29–

ADE7756

Mode Register (06H)

The ADE7756 functionality is configured by writing to the MODE register. Table VI summarizes the functionality of each bit in the

MODE register.

Table VI. Mode Register

Bit

Location

Bit

Mnemonic

Description

0

1

2

3

4

DISHPF

DISLPF2

DISCF

DISSAG

ASUSPEND

The HFP (High-Pass Filter) in Channel 1 is disabled when this bit is set.

The LPF (Low-Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.

The frequency output CF is disabled when this bit is set.

The line voltage Sag detection is disabled when this bit is set.

By setting this bit to Logic 1, both ADE7756’s A/D converters can be turned off. In normal

operation, this bit should be left at Logic 0. All digital functionality can be stopped by sus-

pending the clock signal at CLKIN pin.

5

6

TEMPSEL

SWRST

The temperature conversion starts when this bit is set to one. This bit is automatically reset to

zero when the temperature conversion is finished.

Software Chip Reset. A data transfer should not take place to the ADE7756 for at least 18 µs

after a software reset.

7

8

9

10

CMODE

DISCH1

DISCH2

SWAP

Setting this bit to a Logic 1 places the chip in calibration mode.

ADC 1 (Channel 1) inputs are internally shorted together.

ADC 2 (Channel 2) inputs are internally shorted together.

By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the

analog inputs V1P and V1N are connected to ADC 2.

12, 11

14, 13

15

DTRT1, 0

WAVSEL1, 0

TEST1

These bits are used to select the Waveform Register update rate.

DTRT 1

DTRT0

Update Rate

0

1

0

1

0

1

27.9 kSPS (CLKIN/128)

14 kSPS (CLKIN/256)

7 kSPS (CLKIN/512)

3.5 kSPS (CLKIN/1024)

These bits are used to select the source of the sampled data for the Waveform Register

WAVSEL1

WAVSEL0

Source

0

1

0

1

0

1

Active Power signal (output of LPF2)

RESERVED

Channel 1

Channel 2

Writing a Logic 1 to this bit position places the ADE7756 in test mode. This is intended for

factory testing only and should be left at zero.

*

MODE REGISTER

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

1

0

ADDR: 06H

TEST 1

DISHPF

(DISABLE HPF IN CHANNEL 1)

(TEST MODE SELECTION SHOULD BE SET TO 0)

WAVSEL

DISLPF2

(WAVE FORM SELECTION FOR SAMPLE MODE)

(DISABLE LPF2 AFTER MULTIPLIER)

00 = LPF2

01 = RESERVED

10 = CH1

DISCF

(DISABLE FREQUENCY OUTPUT CF)

11 = CH2

DISSAG

(DISABLE SAG OUTPUT)

DTRT

(WAVE FORM SAMPLES OUTPUT DATA RATE)

00 = 27.9kSPS (CLKIN/128)

ASUSPEND

(SUSPEND CH1 AND CH2 ADCs)

01 = 14.4kSPS (CLKIN/256)

TEMPSEL

(START TEMPERATURE SENSING)

10 = 7.2kSPS (CLKIN/512)

11 = 3.6kSPS (CLKIN/1024)

SWRST

(SOFTWARE CHIP RESET)

SWAP

(SWAP CH1 AND CH2 ADCs)

CMODE

(CALIBRATION MODE)

DISCH2

(SHORT THE ANALOG INPUTS ON CHANNEL 2)

DISCH1

(SHORT THE ANALOG INPUTS ON CHANNEL 1)

*

REGISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 41.

–30–

REV. 0

ADE7756

Interrupt Status Register (04H) / Reset Interrupt Status Register (05H)

The Status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the

ADE7756, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is Logic 1 in the Inter-

rupt Enable register, the IRQ logic output goes active low. When the MCU services the interrupt it must first carry out a read from

the Interrupt Status register to determine the source of the interrupt.

Table VII. Interrupt Status Register, Reset Interrupt Status Register and Interrupt Enable Register

Bit

Location

Interrupt

Flag

Description

0

1

AEHF

SAG

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active Energy register.

Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were detected.

In calibration mode this flag is also used to indicate the end of an integration over an integer number of

half line cycles—see Energy Calibration section.

3

4

5

7

WSMP

ZX

TEMP

AEOF

Indicates that new data is present in the Waveform register.

This status bit reflects the status of the ZX logic output—see Zero Crossing Detection section.

Indicates that a temperature conversion result is available in the Temperature register.

Indicates that the Active Energy register has overflowed.

*

INTERRUPT STATUS REGISTER

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ADDR: 04H / RESET: 05H

AEOF

AEHF

(ACTIVE ENERGY REGISTER OVERFLOW)

(ACTIVE ENERGY REGISTER HALF FULL)

RESERVED = 0

SAG

(LINE VOLTAGE SAG DETECT)

TEMP

ZX

RESERVED = 0

WSMP

(WAVEFORM SAMPLING)

*

REGISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 42. Interrupt Status Register

*

INTERRUPT ENABLE REGISTER

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ADDR: 10H

AEOF

AEHF

(ACTIVE ENERGY REGISTER OVERFLOW)

(ACTIVE ENERGY REGISTER HALF FULL)

RESERVED = 0

SAG

(LINE VOLTAGE SAG DETECT)

TEMP

ZX

RESERVED = 0

WSMP

(WAVEFORM SAMPLING)

*

REGISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 43. Interrupt Enable Register

REV. 0

–31–

ADE7756

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Plastic DIP

(N-20)

1.060 (26.90)

0.925 (23.50)

20

11

10

0.280 (7.11)

0.240 (6.10)

1

0.325 (8.25)

0.300 (7.62)

PIN 1

0.210 (5.33)

0.060 (1.52)

0.015 (0.38)

0.195 (4.95)

0.115 (2.93)

MAX

0.160 (4.06)

0.115 (2.93)

0.130

(3.30)

MIN

SEATING

PLANE

0.015 (0.381)

0.008 (0.204)

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

20-Lead Shrink Small Outline Package

(RS-20)

0.295 (7.50)

0.271 (6.90)

20

11

10

1

0.07 (1.78)

0.066 (1.67)

0.078 (1.98)

0.068 (1.73)

PIN 1

0.037 (0.94)

0.022 (0.559)

8ꢃ

0ꢃ

0.0256

(0.65)

BSC

0.008 (0.203)

0.002 (0.050)

SEATING 0.009 (0.229)

PLANE

0.005 (0.127)

–32–

REV. 0


型号：	ADE7756
厂家：	ADI
描述：	Active Energy Metering IC with Serial Interface 有功电能计量IC ，串行接口
文件：	总32页 (文件大小：346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADE7756 [ADI]

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