ADA4817-1ARDZ-R7 [ADI]
Low Noise, 1 GHz FastFET Op Amps; 低噪声， 1 GHz的FastFET运算放大器
| 型号： | ADA4817-1ARDZ-R7 |
| 厂家： | 
ADI |
| 描述： | Low Noise, 1 GHz FastFET Op Amps |
| 文件： | 总28页 (文件大小：543K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, 1 GHz
FastFET Op Amps
Data Sheet
ADA4817-1/ADA4817-2
FEATURES
CONNECTION DIAGRAMS
ADA4817-1
High speed
TOP VIEW
(Not to Scale)
−3 dB bandwidth (G = 1, RL = 100 Ω): 1050 MHz
Slew rate: 870 V/µs
0.1% settling time: 9 ns
Low input bias current: 2 pA
Low input capacitance
PD
FB
1
2
3
4
8
7
6
5
+V
S
OUT
NC
–IN
+IN
–V
S
Common-mode capacitance: 1.3 pF
Differential-mode capacitance: 0.1 pF
Low noise
NC = NO CONNECT
Figure 1. 8-Lead LFCSP (CP-8-2)
ADA4817-1
4 nV/√Hz @ 100 kHz
2.5 fA/√Hz @ 100 kHz
TOP VIEW
(Not to Scale)
Low distortion
FB
–IN
+IN
1
2
3
4
8
7
6
5
PD
+V
−90 dBc @ 10 MHz (G = 1, RL = 1 kΩ)
Offset voltage: 2 mV maximum
High output current: 40 mA
Supply current per amplifier: 19 mA
Power-down supply current per amplifier: 1.5 mA
S
OUT
NC
–V
S
NC = NO CONNECT
Figure 2. 8-Lead SOIC (RD-8-1)
ADA4817-2
APPLICATIONS
TOP VIEW
(Not to Scale)
Photodiode amplifiers
Data acquisition front ends
Instrumentation
Filters
ADC drivers
CCD output buffers
12 –V
11
–IN1 1
S1
2
3
4
+IN1
NC
NC
10
9
+IN2
–IN2
–V
S2
NC = NO CONNECT
Figure 3. 16-Lead LFCSP (CP-16-20)
GENERAL DESCRIPTION
With a wide supply voltage range from 5 V to 10 V and the
ability to operate on either single or dual supplies, the
ADA4817-1/ ADA4817-2 are designed to work in a variety of
applications including active filtering and ADC driving.
The ADA4817-1 (single) and ADA4817-2 (dual) FastFET™
amplifiers are unity-gain stable, ultrahigh speed voltage
feedback amplifiers with FET inputs. These amplifiers were
developed with the Analog Devices, Inc., proprietary eXtra Fast
Complementary Bipolar (XFCB) process, which allows the
amplifiers to achieve ultralow noise (4 nV/√Hz; 2.5 fA/√Hz)
as well as very high input impedances.
The ADA4817-1 is available in a 3 mm × 3 mm, 8-lead LFCSP and
8-lead SOIC, and the ADA4817-2 is available in a 4 mm × 4 mm,
16-lead LFCSP. These packages feature a low distortion pinout
that improves second harmonic distortion and simplifies circuit
board layout. They also feature an exposed paddle that provides a
low thermal resistance path to the printed circuit board (PCB).
This enables more efficient heat transfer and increases reliability.
These products are rated to work over the extended industrial
temperature range (−40°C to +105°C).
With 1.3 pF of input capacitance, low noise (4 nV/√Hz), low
offset voltage (2 mV maximum), and 1050 MHz −3 dB band-
width, the ADA4817-1/ADA4871-2 are ideal for data acquisition
front ends as well as wideband transimpedance applications,
such as photodiode preamps.
Rev. B
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ADA4817-1/ADA4817-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driving Capacitive Loads.......................................................... 15
Thermal Considerations............................................................ 15
Power-Down Operation ............................................................ 15
Capacitive Feedback................................................................... 16
Higher Frequency Attenuation................................................. 16
Layout, Grounding, and Bypassing Considerations .................. 17
Signal Routing............................................................................. 17
Power Supply Bypassing............................................................ 17
Grounding................................................................................... 17
Exposed Paddle........................................................................... 17
Leakage Currents........................................................................ 18
Input Capacitance ...................................................................... 18
Input-to-Input/Output Coupling............................................. 18
Applications Information .............................................................. 19
Low Distortion Pinout............................................................... 19
Wideband Photodiode Preamp................................................ 19
High Speed JFET Input Instrumentation Amplifier.............. 21
Active Low-Pass Filter (LPF) .................................................... 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Operation............................................................................. 3
5 V Operation ............................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Safe Power Dissipation ............................................. 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 13
Theory of Operation ...................................................................... 14
Closed-Loop Frequency Response........................................... 14
Noninverting Closed-Loop Frequency Response.................. 14
Inverting Closed-Loop Frequency Response ............................. 14
Wideband Operation ................................................................. 15
REVISION HISTORY
5/13—Rev. A to Rev. B
Changes to Figure 3.......................................................................... 1
Changes to Figure 7.......................................................................... 7
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 25
3/09—Rev. 0 to Rev. A
Added 8-Lead SOIC Package............................................Universal
Changes to Features Section and General Description Section . 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Figure 4.......................................................................... 5
Changes to Figure 9, Figure 11, and Figure 12 ............................. 8
Changes to Figure 21, Figure 22, and Figure 24 ......................... 10
Changes to Figure 33...................................................................... 12
Added Figure 34; Renumbered Sequentially .............................. 12
Changes to Thermal Considerations Section and Power-Down
Operation Section........................................................................... 15
Changes to Capacitive Feedback Section and Figure 46 ........... 16
Added Higher Frequency Attenuation Section, Figure 47,
Figure 48, and Figure 49; Renumbered Sequentially................. 16
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
11/08—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADA4817-1/ADA4817-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −V S = −5 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT = 0.1 V p-p
VOUT = 2 V p-p
1050
200
390
≥410
60
60
870
9
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
VOUT = 0.1 V p-p, G = 2
VOUT = 0.1 V p-p
VIN = 3.3 V p-p, G = 2
VOUT = 2 V p-p, RL = 100 Ω, G = 2
VOUT = 4 V step
Gain Bandwidth Product
Full Power Bandwidth
0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3)
VOUT = 2 V step, G = 2
f = 1 MHz, VOUT = 2 V p-p, RL = 1 kΩ
f = 10 MHz, VOUT = 2 V p-p, RL = 1 kΩ
f = 50 MHz, VOUT = 2 V p-p, RL = 1 kΩ
f = 100 kHz
−113/−117
−90/−94
−64/−66
4
dBc
dBc
dBc
nV/√Hz
fA/√Hz
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
f = 100 kHz
2.5
0.4
7
2
2
mV
µV/°C
pA
20
TMIN to TMAX
100
1
pA
pA
Input Bias Offset Current
Open-Loop Gain
62
65
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Common mode
Common mode
Differential mode
500
1.3
0.1
GΩ
pF
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection
−VS to +VS − 2.8
−90
VCM = 0.5 V
−77
dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
VIN = 2.5 V, G = 2
8
ns
V
−VS + 1.5 to
+VS − 1.5
−VS + 1.4 to
+VS − 1.3
RL = 1 kΩ
−VS + 1.1 to
+VS − 1.1
−VS + 1 to
+VS − 1
V
Linear Output Current
Short-Circuit Current
POWER-DOWN
1% output error
Sinking/sourcing
40
100/170
mA
mA
PD Pin Voltage
Enabled
>+VS − 1
<+VS − 3
0.3/1
V
Powered down
V
Turn-On/Turn-Off Time
Input Leakage Current
µs
µA
µA
PD = +VS
PD = −VS
0.3
3
34
61
POWER SUPPLY
Operating Range
5
10
21
3
V
Quiescent Current per Amplifier
Powered Down Quiescent Current
Positive Power Supply Rejection
Negative Power Supply Rejection
19
1.5
−72
−72
mA
mA
dB
dB
+VS = 4.5 V to 5.5 V, −VS = −5 V
+VS = 5 V, −VS = −4.5 V to −5.5 V
−67
−67
Rev. B | Page 3 of 28
ADA4817-1/ADA4817-2
Data Sheet
5 V OPERATION
TA = 25°C, +VS = 3 V, −V S = −2 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
VOUT = 0.1 V p-p
VOUT = 1 V p-p
VOUT = 0.1 V p- p, G = 2
VIN = 1 V p-p, G = 2
VOUT = 1 V p-p, G = 2
VOUT = 2 V step
500
160
280
95
32
320
11
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Full Power Bandwidth
0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3)
VOUT = 1 V step, G = 2
f = 1 MHz, VOUT = 1 V p-p, RL = 1 kΩ
f = 10 MHz, VOUT = 1 V p-p, RL = 1 kΩ
f = 50 MHz, VOUT = 1 V p-p, RL = 1 kΩ
f = 100 kHz
−87/−88
−68/−66
−57/−55
4
dBc
dBc
dBc
nV/√Hz
fA/√Hz
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
f = 100 kHz
2.5
0.5
7
2
2.3
20
mV
µV/°C
pA
TMIN to TMAX
100
1
pA
pA
Input Bias Offset Current
Open-Loop Gain
61
63
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Common mode
Common mode
Differential mode
500
1.3
0.1
GΩ
pF
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection
−VS to +VS − 2.9
−83
VCM = 0.25 V
−72
dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
VIN = 1.25 V, G = 2
RL = 100 Ω
13
ns
V
−VS + 1.3 to
+VS − 1.3
−VS + 1 to
+VS − 1.2
RL = 1 kΩ
−VS + 1 to
+VS − 1.1
−VS + 0.9 to
+VS − 1
V
Linear Output Current
Short-Circuit Current
POWER-DOWN
1% output error
Sinking/sourcing
20
40/130
mA
mA
PD Pin Voltage
Enabled
>+VS − 1
<+VS − 3
0.2/0.7
0.2
V
Powered down
V
Turn-On/Turn-Off Time
Input Leakage Current
µs
µA
µA
PD = +VS
PD = −VS
3
31
53
POWER SUPPLY
Operating Range
5
10
16
2.8
V
Quiescent Current per Amplifier
Powered Down Quiescent Current
Positive Power Supply Rejection
Negative Power Supply Rejection
14
1.5
−71
−69
mA
mA
dB
dB
+VS = 4.75 V to 5.25 V, −VS = 0 V
+VS = 5 V, −VS = −0.25 V to +0.25 V
−66
−63
Rev. B | Page 4 of 28
Data Sheet
ADA4817-1/ADA4817-2
ABSOLUTE MAXIMUM RATINGS
PD = Quiescent Power + (Total Drive Power – Load Power) (1)
Table 3.
2
Parameter
Rating
VS VOUT
VOUT
RL
PD =
(
VS × IS
)
+
×
–
(2)
Supply Voltage
10.6 V
2
RL
Power Dissipation
See Figure 4
−VS − 0.5 V to +VS + 0.5 V
±VS
−65°C to +125°C
−40°C to +105°C
Consider RMS output voltages. If RL is referenced to −VS, as
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
in single-supply operation, the total drive power is VS × IOUT. If
the rms signal levels are indeterminate, consider the worst-case
scenario, when VOUT = VS/4 for RL to midsupply.
2
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
(
VS/4
RL
)
PD =
(
VS × IS
)
+
(3)
In single-supply operation with RL referenced to −VS, the worst-
case situation is VOUT = VS/2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation, effectively reducing θJA.
More metal directly in contact with the package leads and
exposed paddle from metal traces, throughholes, ground,
and power planes also reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
LFCSP_VD (single 94°C/W), SOIC_N_EP (single 79°C/W)
and LFCSP_WQ (dual 64°C/W) package on a JEDEC standard
4-layer board. θJA values are approximations.
3.5
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board for the
surface-mount packages.
Table 4.
Package Type
3.0
θJA
94
79
64
θJC
29
29
14
Unit
°C/W
°C/W
°C/W
ADA4817-2, LFCSP
LFCSP_VD (ADA4817-1)
SOIC_N_EP (ADA4817-1)
LFCSP_WQ (ADA4817-2)
2.5
ADA4817-1, SOIC
2.0
1.5
ADA4817-1, LFCSP
MAXIMUM SAFE POWER DISSIPATION
1.0
0.5
0
The maximum safe power dissipation for the ADA4817-1/
ADA4817-2 are limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C (which is
the glass transition temperature), the properties of the plastic
change. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4817-x. Exceeding
a junction temperature of 175°C for an extended period can result
in changes in silicon devices, potentially causing degradation or
loss of functionality.
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Safe Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the ADA4817-1/ADA4817-2 drive at the output.
The quiescent power is the voltage between the supply pins (VS)
multiplied by the quiescent current (IS).
Rev. B | Page 5 of 28
ADA4817-1/ADA4817-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADA4817-1
TOP VIEW
(Not to Scale)
PD
FB
1
2
3
4
8
7
6
5
+V
S
OUT
NC
–IN
+IN
–V
S
NC = NO CONNECT
NOTES
1. EXPOSED PAD CAN BE CONNECTED
TO GROUND PLANE OR NEGATIVE
SUPPLY PLANE.
Figure 5. ADA4817-1 Pin Configuration (8-Lead LFCSP)
Table 5. ADA4817-1 Pin Function Descriptions (8-Lead LFCSP)
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
PD
Power-Down. Do not leave floating.
FB
Feedback Pin.
−IN
Inverting Input.
+IN
Noninverting Input.
−VS
Negative Supply.
NC
No Connect.
OUT
Output.
+VS
Positive Supply.
Exposed pad (EPAD)
Exposed Pad. Can be connected to GND, −VS plane, or left floating.
ADA4817-1
TOP VIEW
(Not to Scale)
FB
–IN
+IN
1
2
3
4
8
7
6
5
PD
+V
S
OUT
NC
–V
S
NC = NO CONNECT
NOTES
1. EXPOSED PAD CAN BE CONNECTED
TO GROUND PLANE OR NEGATIVE
SUPPLY PLANE.
Figure 6. ADA4817-1 Pin Configuration (8-Lead SOIC)
Table 6. ADA4817-1 Pin Function Descriptions (8-Lead SOIC)
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
FB
Feedback Pin.
−IN
Inverting Input.
+IN
Noninverting Input.
−VS
Negative Supply.
NC
No Connect.
OUT
Output.
+VS
PD
Positive Supply.
Power-Down. Do not leave floating.
Exposed pad (EPAD)
Exposed Pad. Can be connected to GND, −VS plane, or left floating.
Rev. B | Page 6 of 28
Data Sheet
ADA4817-1/ADA4817-2
ADA4817-2
TOP VIEW
(Not to Scale)
12 –V
11
–IN1
+IN1
NC
1
2
3
4
S1
NC
10
9
+IN2
–IN2
–V
S2
NC = NO CONNECT
NOTES
1. EXPOSED PAD CAN BE CONNECTED
TO THE GROUND PLANE OR NEGATIVE
SUPPLY PLANE.
Figure 7. ADA4817-2 Pin Configuration (16-Lead LFCSP)
Table 7. 16-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
−IN1
Inverting Input 1.
Noninverting Input 1.
No Connect.
2
+IN1
3, 11
4
NC
−VS2
Negative Supply 2.
Output 2.
5
OUT2
6
+VS2
Positive Supply 2.
Power-Down 2. Do not leave floating.
Feedback Pin 2.
7
PD2
8
FB2
9
−IN2
Inverting Input 2.
Noninverting Input 2.
Negative Supply 1.
Output 1.
10
12
13
14
15
16
+IN2
−VS1
OUT1
+VS1
Positive Supply 1.
Power-Down 1. Do not leave floating.
Feedback Pin 1.
PD1
FB1
Exposed pad (EPAD)
Exposed Pad. Can be connected to GND, −VS plane, or left floating.
Rev. B | Page 7 of 28
ADA4817-1/ADA4817-2
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, G = 1, (RF = 348 Ω for G > 1), RL = 100 Ω to ground, small signal VOUT = 100 mV p-p, large signal VOUT = 2 V p-p,
unless noted otherwise.
6
6
G = 1, DUAL
G = 2
G = 1, SINGLE
G = 2
3
3
G = 1, SINGLE
G = 1, DUAL
0
0
G = 5
G = 5
–3
–6
–9
–12
–3
–6
–9
–12
100k
1M
10M
100M
1G
10G
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. Small Signal Frequency Response for Various Gains (LFCSP)
Figure 11. Large Signal Frequency Response for Various Gains
6
6
3
V
= 10V, SOIC
S
V
= 10V, LFCSP
S
3
0
V
= 5V, LFCSP
S
V
= 10V
V
= 5V, SOIC
S
S
0
–3
–3
–6
–9
–12
V
= 5V
S
–6
–9
V
= 1V p-p
1M
OUT
–12
100k
100k
1M
10M
100M
1G
10G
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. Large Signal Frequency Response for Various Supplies
Figure 9. Small Signal Frequency Response for Various Supplies
9
9
C
= 6.6pF
L
R
= 274Ω
F
C
= 2.2pF
L
R = 348Ω
F
C
= 4.4pF
L
6
3
6
3
C
= 0pF
L
R
= 200Ω
F
0
0
–3
–6
–9
–3
–6
–9
G = 2
= 274Ω
G = 2
R
F
100k
1M
10M
100M
1G
10G
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Small Signal Frequency Response for Various RF
Figure 10. Small Signal Frequency Response for Various CL
Rev. B | Page 8 of 28
Data Sheet
ADA4817-1/ADA4817-2
0.5
6
3
0.4
G = 2, SS
G = 2, LS
0.3
0.2
0
0.1
G = 1, SS
–3
–6
–9
–12
0
G = 1, LS
–0.1
–0.2
–0.3
–0.4
T
T
T
T
T
T
= +25°C, SINGLE
A
A
A
A
A
A
= +25°C, DUAL
= –40°C, SINGLE
= –40°C, DUAL
= +105°C, SINGLE
= +105°C, DUAL
–0.5
100k
1M
10M
100M
1G
10G
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. 0.1 dB Flatness Frequency Response vs. Gain and Output Voltage
Figure 17. Small Signal Frequency Response vs. Temperature
–20
–40
–60
–20
–40
–60
HD2, V = 5V
S
HD2, R = 100Ω
L
HD3, V = 5V
S
–80
–100
–120
–140
–80
–100
–120
–140
HD2, R = 1kΩ
L
HD3, R = 100Ω
L
HD2, V = 10V
S
HD3, R = 1kΩ
HD3, V = 10V
L
S
100k
1M
10M
FREQUENCY (Hz)
100M
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 15. Distortion vs. Frequency for Various Loads, VOUT = 2 V p-p
Figure 18. Distortion vs. Frequency for Various Supplies, VOUT = 2 V p-p
–20
–40
–20
fC = 1MHz
–40
–60
–80
HD2, V = 5V
S
–60
–80
HD2, V = 10V
S
HD2, R = 100Ω
L
HD2, R = 1kΩ
L
–100
–120
–140
–100
–120
–140
HD3, V = 5V
S
HD3, V = 10V
S
HD3, R = 100Ω
L
HD3, R = 1kΩ
L
100k
1M
10M
FREQUENCY (Hz)
100M
0
1
2
3
4
5
6
OUTPUT VOLTAGE (V p-p)
Figure 16. Distortion vs. Frequency for Various Supplies, G = 2, VOUT = 2 V p-p
Figure 19. Distortion vs. Output Voltage for Various Loads
Rev. B | Page 9 of 28
ADA4817-1/ADA4817-2
Data Sheet
0.15
0.15
0.10
0.05
0
DUAL, C = 0.5pF
F
DUAL, C = 0.5pF
F
SINGLE, NO C
F
SINGLE, NO C
F
0.10
0.05
0
SINGLE
SINGLE
–0.05
–0.10
–0.15
–0.05
–0.10
–0.15
DUAL
DUAL
V
G = 2
= 5V
S
G = 2
TIME (5ns/DIV)
TIME (5ns/DIV)
Figure 20. Small Signal Transient Response
Figure 23. Small Signal Transient Response
1.5
1.0
0.075
0.050
0.025
0
0.5
0
–0.5
–1.0
–1.5
SINGLE,SOIC
DUAL, LFCSP
–0.025
–0.050
–0.075
R
R
V
= 0Ω
= 100Ω
= ±5V
F
L
S
DUAL, LFCSP
R
R
V
= 0Ω
= 100Ω
= ±5V
F
L
SINGLE, LFCSP
G = +1
SINGLE, LFCSP
S
G = +1
SINGLE, SOIC
TIME (5ns/DIV)
TIME (5ns/DIV)
Figure 21. Small Signal Transient Response vs. Package
Figure 24. Large Signal Transient Response
6
0.5
0.4
0.3
SETTLING TIME
2 × V
IN
4
2
0.2
0.1
0
0
–0.1
–0.2
–0.3
–2
–4
–6
V
OUT
–0.4
–0.5
G = 2
TIME (10ns/DIV)
TIME (5ns/DIV)
Figure 25. 0.1% Short-Term Settling Time
Figure 22. Output Overdrive Recovery
Rev. B | Page 10 of 28
Data Sheet
ADA4817-1/ADA4817-2
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.5
0.4
0.3
0.2
0.1
–PSRR
+PSRR
0
–0.1
–0.2
–0.3
–0.4
–0.5
–100
100k
1M
10M
FREQUENCY (Hz)
100M
1G
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 26. PSRR vs. Frequency
Figure 29. Offset Voltage vs. Temperature
1000
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
100
10
1
–100
100k
10
100
1k
10k
100k
1M
10M
100M
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. CMRR vs. Frequency
Figure 30. Input Voltage Noise
100
10
1
24
22
20
18
16
14
12
10
V
= ±5V
S
V
= +5V
S
0.1
0.01
100k
1M
10M
100M
1G
–40
–20
0
20
40
60
80
100
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 28. Output Impedance vs. Frequency
Figure 31. Quiescent Current vs. Temperature for Various Supply Voltages
Rev. B | Page 11 of 28
ADA4817-1/ADA4817-2
Data Sheet
1.6
N: 4197
V
= ±5V
R
= 100Ω
S
L
MEAN: –0.0248457
SD: 0.245658
800
700
600
500
400
300
200
100
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
–V + V
S
OUT
+V – V
OUT
S
+V – V
S
OUT
V
= +5V
S
–V + V
S
OUT
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–40
–20
0
20
40
60
80
100
V
(mV)
OS
TEMPERATURE (°C)
Figure 32. Output Saturation Voltage vs. Temperature
Figure 34. Input Offset Voltage Histogram
0
70
60
50
40
30
GAIN
–45
–90
PHASE
20
10
–135
–180
0
–10
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 33. Open-Loop Gain and Phase vs. Frequency
Rev. B | Page 12 of 28
Data Sheet
ADA4817-1/ADA4817-2
TEST CIRCUITS
The output feedback pins are used for ease of layout as shown in Figure 35 to Figure 40.
+V
S
+V
S
10µF
10µF
R
R
F
G
0.1µF
0.1µF
0.1µF
0.1µF
V
V
OUT
OUT
V
V
IN
IN
R
R
L
L
49.9Ω
10µF
49.9Ω
10µF
0.1µF
0.1µF
–V
–V
S
S
Figure 35. G = 1 Configuration
Figure 38. Noninverting Gain Configuration
+V
S
+V
S
10µF
AC
49.9Ω
0.1µF
V
OUT
V
OUT
R
L
R
L
49.9Ω
AC
10µF
0.1µF
–V
S
–V
S
Figure 36. Positive Power Supply Rejection
Figure 39. Negative Power Supply Rejection
+V
S
+V
S
10µF
10µF
R
R
F
G
1kΩ
0.1µF
0.1µF
0.1µF
0.1µF
1kΩ
1kΩ
V
V
V
OUT
IN
OUT
R
V
SNUB
IN
C
L
R
R
L
L
49.9Ω
10µF
53.6Ω
1kΩ
10µF
0.1µF
0.1µF
–V
–V
S
S
Figure 37. Capacitive Load Configuration
Figure 40. Common-Mode Rejection
Rev. B | Page 13 of 28
ADA4817-1/ADA4817-2
Data Sheet
THEORY OF OPERATION
The ADA4817-1/ADA4817-2 are voltage feedback operational
amplifiers that combine new architecture for FET input operational
amplifiers with the eXtra Fast Complementary Bipolar (XFCB)
process from Analog Devices, resulting in an outstanding
combination of speed and low noise. The innovative high speed
FET input stage handles common-mode signals from the negative
supply to within 2.7 V of the positive rail. This stage is combined
with an H-bridge to attain a 870 V/μs slew rate and low distortion,
in addition to 4 nV/√Hz input voltage noise. The amplifier
features a high speed output stage capable of driving heavy loads
sourcing and sinking up to 40 mA of linear current. Supply current
and offset current are laser trimmed for optimum performance.
These specifications make the ADA4817-1/ ADA4817-2 a great
choice for high speed instrumentation and high resolution data
acquisition systems. Its low noise, picoamp input current, precision
offset, and high speed make them superb preamps for fast photo-
diode applications.
Closed-loop −3 dB frequency
RG
RF + RG
f−3dB = fCROSSOVER
×
(6)
INVERTING CLOSED-LOOP FREQUENCY RESPONSE
Solving for the transfer function,
−2π× fCROSSOVER × RF
RF + RG S + 2π× fCROSSOVER × RG
VO
VI
=
(7)
(8)
(
)
VO
VI
RF
RG
At dc
= −
Solve for closed-loop −3 dB frequency by,
RG
RF + RG
(9)
f−3dB = fCROSSOVER
×
A = (2π × fCROSSOVER)/s
80
CLOSED-LOOP FREQUENCY RESPONSE
The ADA4817-1/ADA4817-2 are classic voltage feedback
amplifiers with an open-loop frequency response that can be
approximated as the integrator response shown in Figure 43. Basic
closed-loop frequency response for inverting and noninverting
configurations can be derived from the schematics shown in
Figure 41 and Figure 42.
60
40
20
0
R
F
fCROSSOVER = 410MHz
R
G
V
OUT
A
V
E
V
IN
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 43. Open-Loop Gain vs. Frequency and Basic Connections
Figure 41. Noninverting Configuration
R
F
The closed-loop bandwidth is inversely proportional to the noise
gain of the op amp circuit, (RF + RG)/RG. This simple model is
accurate for noise gains above 2. The actual bandwidth of circuits
with noise gains at or below 2 is higher than those predicted
with this model due to the influence of other poles in the
frequency response of the real op amp.
R
V
G
IN
V
OUT
V
A
E
Figure 42. Inverting Configuration
Figure 44 shows a voltage feedback amplifier’s dc errors. For
both inverting and noninverting configurations,
NONINVERTING CLOSED-LOOP FREQUENCY
RESPONSE
RG + RF
RG + RF
Solving for the transfer function,
VOUT
(
error
)
= Ib+ × RS
− Ib− × RF +VOS
RG
RG
2π × fCROSSOVER
(
RG + RF
)
VO
VI
=
(4)
(10)
(
RF + RG S + 2π × fCROSSOVER × RG
)
R
F
where fCROSSOVER is the frequency where the amplifier’s open-loop
gain equals 0 dB.
+V
OS
–
R
G
At dc,
I
I
V
OUT
A
b
–
R
S
VO RF + RG
VI
V
IN
=
(5)
RG
b+
Figure 44. Voltage Feedback Amplifier’s DC Errors
Rev. B | Page 14 of 28
Data Sheet
ADA4817-1/ADA4817-2
The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG
(though with the ADA4817-1/ADA4817-2 input currents in the
picoamp range, this is likely not a concern). To include common-
mode effects and power supply rejection effects, total VOS can be
modeled by
Note that such capacitance introduces significant peaking in the
frequency response. Larger capacitance values can be driven but
must use a snubbing resistor (RSNUB) at the output of the amplifier,
as shown in Figure 45. Adding a small series resistor, RSNUB, creates
a zero that cancels the pole introduced by the load capacitance.
Typical values for RSNUB can range from 10 Ω to 50 Ω. The value is
typically based on the circuit requirements. Figure 45 also shows
another way to reduce the effect of the pole created by the capacitive
load (CL) by placing a capacitor (CF) in the feedback loop parallel
to the feedback resistor Typical capacitor values can range from
0.5 pF to 2 pF. Figure 46 shows the effect of adding a feedback
capacitor to the frequency response.
ΔVS ΔVCM
PSR CMR
VOS =VOS
+
+
(11)
nom
where:
VOS
is the offset voltage specified at nominal conditions.
nom
ΔVS is the change in power supply from nominal conditions.
PSR is the power supply rejection.
ΔVCM is the change in common-mode voltage from nominal
conditions.
+V
S
10µF
CMR is the common-mode rejection.
C
F
F
WIDEBAND OPERATION
R
R
G
0.1µF
0.1µF
The ADA4817-1/ADA4817-2 provides excellent performance as
a high speed buffer. Figure 41 shows the circuit used for wideband
characterization for high gains. The impedance at the summing
junction (RF || RG) forms a pole in the loop response of the amp-
lifier with the amplifier’s input capacitance of 1.3 pF. This pole
can cause peaking and ringing if its frequency is too low. Feed-
back resistances of 100 Ω to 400 Ω are recommended because
they minimize the peaking and they do not degrade the
performance of the output stage. Peaking in the frequency
response can also be compensated for with a small feedback
capacitor (CF) in parallel with the feedback resistor, or a series
resistor in the noninverting input, as shown in Figure 45.
V
OUT
R
V
SNUB
IN
C
L
R
L
49.9Ω
10µF
0.1µF
–V
S
Figure 45. RSNUB or CF Used to Reduce Peaking
THERMAL CONSIDERATIONS
With 10 V power supplies and 19 mA quiescent current, the
ADA4817-1/ADA4817-2 dissipate 190 mW with no load. This
implies that in the LFCSP, whose thermal resistance is 94°C/W for
the ADA4817-1 and 64°C/W for the ADA4817-2, the junction
temperature is typically almost 25° higher than the ambient tem-
perature. The ADA4817-1/ADA4817-2 are designed to maintain a
constant bandwidth over temperature; therefore, an initial ramp up
of the current consumption during warm-up is expected. The VOS
temperature drift is below 8 µV/°C; therefore, it can change up to
0.3 mV due to warm-up effects for an ADA4817-1/ADA4817-2
in a LFCSP on 10 V. The input bias current increases by a factor
of 1.7 for every 10°C rise in temperature.
The distortion performance depends on a number of variables:
•
•
•
•
•
The closed-loop gain of the application
Whether it is inverting or noninverting
Amplifier loading
Signal frequency and amplitude
Board layout
The best performance is usually obtained in the G + 1
configuration with no feedback resistance, big output
load resistors, and small board parasitic capacitances.
Heavy loads increase power dissipation and raise the chip
junction temperature as described in the Absolute Maximum
Ratings section. Take care not to exceed the rated power
dissipation of the package.
DRIVING CAPACITIVE LOADS
In general, high speed amplifiers have a difficult time driving
capacitive loads. This is particularly true in low closed-loop
gains, where the phase margin is the lowest. The difficulty
arises because the load capacitance, CL, forms a pole with the
output resistance, RO, of the amplifier. The pole can be described
by the following equation:
POWER-DOWN OPERATION
The ADA4817-1/ADA4817-2 are equipped with separate power-
down pins ( ) for each amplifier. This allows the user the ability
PD
to reduce the quiescent supply current when an amplifier is
inactive from 19 mA to below 2 mA. The power-down threshold
levels are derived from the voltage applied to the +VS pin. In 5 V
supply application, the enable voltage is greater than +4 V, and in a
+3 V, −2 V supply application, the enable voltage is greater than
+2 V. However, the amplifier is powered down whenever the
1
fP
=
(12)
2πROCL
If this pole occurs too close to the unity-gain crossover point,
the phase margin degrades. This is due to the additional phase
loss associated with the pole.
voltage applied to
is 3 V below +VS. If the
PD
connect it to the positive supply to ensure proper start-up.
pin is not used,
PD
Rev. B | Page 15 of 28
ADA4817-1/ADA4817-2
Data Sheet
Table 8. Power-Down Voltage Control
Pin
5 V
+3 V, −2 V
PD
Figure 47 shows the higher frequency attenuation, which
reduces the peaking but also reduces the −3 dB bandwidth.
Not active
Active
>4 V
<2 V
>2 V
<0 V
6
R
= 75Ω
S
CAPACITIVE FEEDBACK
R
= 50Ω
S
3
0
Due to package variations and pin-to-pin parasitics between the
single and the dual models, the ADA4817-2 has a little more
peaking then the ADA4817-1, especially at a gain of 2. The best
way to tame the peaking is to place a feedback capacitor across
the feedback resistor. Figure 46 shows the small signal frequency
response of the ADA4817-2 at a gain of 2 vs. CF. At first, no CF
was used to show the peaking, but then two other values of
0.5 pF and 1 pF were used to show how to reduce the peaking or
even eliminate it. As shown in Figure 46, if the power consumption
is a factor in the system, then using a larger feedback capacitor
is acceptable as long as a feedback capacitor is used across it to
control the peaking. However, if power consumption is not an
issue, then a lower value feedback resistor, such as 200 Ω, would
not require any additional feedback capacitance to maintain
flatness and lower peaking.
R
= 0Ω
S
R
= 100Ω
S
–3
–6
–9
R
= 100Ω
= ±5V
= 0.1V p-p
L
S
V
V
OUT
G = 1
1M
10M
100M
1G
10G
FREQUENCY (Hz)
Figure 47. Small Signal Frequency Response for Various RS (SOIC)
As shown in Figure 47, the peaking dropped by almost 2 dB
when RS = 0 Ω to RS = 100 Ω, and in return, the −3 dB bandwidth
dropped from 1 GHz to 700 MHz. To maintain the −3 dB
bandwidth and to reduce peaking, an RLC circuit is recommended
instead of RS, as shown in Figure 48.
9
C
= 0.5pF
F
NO C
F
6
3
L
C
C
= 1pF
F
10nH
2pF
R
0
120Ω
Figure 48. RLC Circuit
–3
–6
–9
The R in parallel to the series LC forms a notch that can be
shaped to compensate for the peaking produced by the amplifier.
The result is a smooth 1 GHz −3 dB bandwidth, 250 MHz 0.1 dB
flatness, and less than 1 dB of peaking. This circuit should be
placed in the path of the noninverting input when the ADA4817-x
is used at a gain of 1. The RLC values may need tweaking
depending on the source impedance and the flatness and band-
width required. Figure 49 shows the frequency response after the
RLC circuit is in place.
R
G = 2
= 348Ω
F
V
V
R
= 10V
= 100mV p-p
S
OUT
= 100Ω
L
1M
10M
100M
FREQUENCY (Hz)
1G
10G
Figure 46. Small Signal Frequency Response vs. Feedback Capacitor
(ADA4817-2)
HIGHER FREQUENCY ATTENUATION
There is another package variation problem between the SOIC
and the LFCSP package. The SOIC package shows approximately
1 dB to 1.5 dB of additional peaking at a gain of 1. This is due to
the parasitic in the SOIC package, which is not recommended
for very high frequency parts that exceed 1 GHz. A good approach
to reducing the peaking is to place a resistor, RS, in series with
the noninverting input. This creates a first-order pole formed
by RS and CIN, the common-mode input capacitance.
6
NO RLC
3
0
RLC
–3
–6
R
= 100Ω
= 10V
= 100mV p-p
L
S
V
V
OUT
G = 1
–9
1M
10M
100M
1G
10G
FREQUENCY (Hz)
Figure 49. Frequency Response with RLC Circuit
Rev. B | Page 16 of 28
Data Sheet
ADA4817-1/ADA4817-2
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
Placement of the capacitor returns (grounds) is also important.
Returning the capacitors’ grounds close to the amplifier load is
critical for distortion performance. Keeping the capacitors distance
short but equal from the load is optimal for performance.
Laying out the PCB is usually the last step in the design process
and often proves to be one of the most critical. A brilliant design
can be rendered useless because of poor layout. Because the
ADA4817-1/ADA4817-2 can operate into the RF frequency
spectrum, high frequency board layout considerations must
be taken into account. The PCB layout, signal routing, power
supply bypassing, and grounding all must be addressed to
ensure optimal performance.
In some cases, bypassing between the two supplies can help
to improve PSRR and to maintain distortion performance in
crowded or difficult layouts. This is another option to improve
performance.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduces the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distortion
due to high frequency compression at the output. The use of
vias should be minimized in the direct path to the amplifier power
supply pins because vias can introduce parasitic inductance, which
can lead to instability. When required to use vias, choose multiple
large diameter vias because this lowers the equivalent parasitic
inductance.
SIGNAL ROUTING
The ADA4817-1/ADA4817-2 feature the new low distortion
pinout with a dedicated feedback pin that allows a compact
layout. The dedicated feedback pin reduces the distance from
the output to the inverting input, which greatly simplifies the
routing of the feedback network.
When laying out the ADA4817-1/ADA4817-2 as a unity-gain
amplifier, it is recommended that a short, but wide, trace be
placed between the dedicated feedback pins, and the inverting
input to the amplifier be used to minimize stray parasitic
inductance.
GROUNDING
To minimize parasitic inductances, use ground planes under
high frequency signal traces. However, remove the ground
plane from under the input and output pins to minimize the
formation of parasitic capacitors, which degrades phase margin.
Signals that are susceptible to noise pickup should be run on
the internal layers of the PCB, which can provide maximum
shielding.
The use of ground and power planes is encouraged as a method
of providing low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce stray
trace inductance and to provide a low thermal path for the
amplifier. Do not use ground and power planes under any of
the pins. The mounting pads and the ground or power planes
can form a parasitic capacitance at the input of the amplifier. Stray
capacitance on the inverting input and the feedback resistor form
a pole, which degrades the phase margin, leading to instability.
Excessive stray capacitance on the output also forms a pole,
which degrades phase margin.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the ADA4817-1/ADA4817-2
power supply pins need to be properly bypassed.
A parallel connection of capacitors from each of the power
supply pins to ground works best. Paralleling different values
and sizes of capacitors helps to ensure that the power supply
pins see a low ac impedance across a wide band of frequencies.
This is important for minimizing the coupling of noise into the
amplifier. Starting directly at the power supply pins, place the
smallest value and sized component on the same side of the
board as the amplifier, and as close as possible to the amplifier,
and connect it to the ground plane. Repeat this process for the
next largest value capacitor. It is recommended that a 0.1 µF
ceramic, 0508 case be used for the ADA4817-1/ADA4817-2.
EXPOSED PADDLE
The ADA4817-1/ADA4817-2 feature an exposed paddle, which
lowers the thermal resistance by 25% compared to a standard
SOIC plastic package. The exposed paddle of the ADA4817-1/
ADA4817-2 floats internally which provides the maximum
flexibility and ease of use. It can be connected to the ground plane
or to the negative power supply plane. In cases where thermal
heating is not an issue, the exposed pad can be left floating.
The use of thermal vias or heat pipes can also be incorporated
into the design of the mounting pad for the exposed paddle.
These additional vias help to lower the overall junction-to-
ambient temperature (θJA). Using a heavier weight copper on
the surface to which the exposed paddle of the amplifier is
soldered can greatly reduce the overall thermal resistance seen
by the ADA4817-1/ADA4817-2.
The 0508 offers low series inductance and excellent high
frequency performance. The 0.1 µF provides low impedance at
high frequencies. Place a 10 µF electrolytic capacitor in parallel
with the 0.1 µF. The 10 µF capacitor provides low ac impedance
at low frequencies. Smaller values of electrolytic capacitors can
be used depending on the circuit requirements. Additional
smaller value capacitors help to provide a low impedance path
for unwanted noise out to higher frequencies but are not always
necessary.
Rev. B | Page 17 of 28
ADA4817-1/ADA4817-2
Data Sheet
LEAKAGE CURRENTS
INPUT CAPACITANCE
Poor PCB layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the ADA4817-1/ADA4817-2. Any
voltage differential between the inputs and nearby runs sets
up leakage currents through the PCB insulator, for example, 1 V/
100 GΩ = 10 pA. Similarly, any contaminants, such as skin oils
on the board, can create significant leakage. To reduce leakage
significantly, put a guard ring (shield) around the inputs and
input leads that are driven to the same voltage potential as the
inputs. This way there is no voltage potential between the inputs
and surrounding area to set up any leakage currents. For the
guard ring to be completely effective, it must be driven by a
relatively low impedance source and should completely
surround the input leads on all sides (above and below)
while using a multilayer board.
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, in turn increasing the gain of the amplifier, causing
peaking of the frequency response or even oscillations if severe
enough. It is recommended that the external passive components
connected to the input pins be placed as close as possible to the
inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a small distance from the input pins on
all layers of the board.
INPUT-TO-INPUT/OUTPUT COUPLING
To minimize capacitive coupling between the inputs and outputs,
the output signal traces should not be parallel with the inputs.
In addition, the input traces should not be close to each other. A
minimum of 7 mils between the two inputs is recommended.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials,
such as Teflon® or ceramic, can be necessary in some instances.
Rev. B | Page 18 of 28
Data Sheet
ADA4817-1/ADA4817-2
APPLICATIONS INFORMATION
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the summing junction of the amplifier, including the
photodiode capacitance (CS) and the amplifier input capacitance.
RF and the total capacitance produce a pole in the amplifier’s
loop transmission that can result in peaking and instability.
Adding CF creates a zero in the loop transmission that compen-
sates for the effect of the pole and reduces the signal bandwidth.
It can be shown that the signal bandwidth obtained with a 45°
phase margin (f(45)) is defined by
LOW DISTORTION PINOUT
The ADA4817-1/ADA4817-2 feature a new low distortion
pinout from Analog Devices. The new pinout provides two
advantages over the traditional pinout. The first advantage is
improved second harmonic distortion performance, which is
accomplished by the physical separation of the noninverting
input pin and the negative power supply pin. The second
advantage is the simplification of the layout due to the dedicated
feedback pin and easy routing of the gain set resistor back to
the inverting input pin. This allows a compact layout, which
helps to minimize parasitics and increase stability.
fCR
f(45)
(14)
2 RF (CS CM CD )
The designer does not need to use the dedicated feedback pin to
provide feedback for the ADA4817-1/ADA4817-2. The output
pin of the ADA4817-1/ADA4817-2 can still be used to provide
feedback to the inverting input of the ADA4817-1/ADA4817-2.
where:
fCR is the amplifier crossover frequency.
RF is the feedback resistor.
CS is the source capacitance including the photodiode and the
board parasitic.
CM is the common-mode capacitance of the amplifier.
CD is the differential capacitance of the amplifier.
WIDEBAND PHOTODIODE PREAMP
The wide bandwidth and low noise of the ADA4817-1/
ADA4817-2 make it an ideal choice for transimpedance
amplifiers, such as those used for signal conditioning with
high speed photodiodes. Figure 50 shows an I/V converter
with an electrical model of a photodiode. The basic transfer
function is
The value of CF that produces f(45) can be shown to be
CS CM CD
2 RF fCR
CF
(15)
I
PHOTO RF
VOUT
(13)
The frequency response shows less peaking if bigger CF values
are used.
1 sCF RF
where:
IPHOTO is the output current of the photodiode.
The parallel combination of RF and CF sets the signal bandwidth.
The preamplifier output noise over frequency is shown in
Figure 51.
C
1
F
f1
f2
f3
=
=
=
2
R (C + C + C + C )
F F S M D
1
2
R C
F
F
R
F
fCR
(C + C + C + C )/C
F
F
S
M
D
11
C
C
I
R
= 10
Ω
R NOISE
F
M
PHOTO
SH
C
S
VEN (C + C + C + C )/C
F
f3
F
S
M
D
C
D
V
OUT
f2
M
f1
VEN
V
B
NOISE DUE TO AMPLIFIER
FREQUENCY (Hz)
Figure 50. Wideband Photodiode Preamp
Figure 51. Photodiode Voltage Noise Contributions
Rev. B | Page 19 of 28
ADA4817-1/ADA4817-2
Data Sheet
45
40
35
30
25
20
15
10
The loop transmission zero introduced by CF limits the
amplification. The noise gain bandwidth extends past the pre-
amp signal bandwidth and is eventually rolled off by the decreasing
loop gain of the amplifier. The current equivalent noise from the
inverting terminal is typically negligible for most applications.
The innovative architecture used in the ADA4817-1/ADA4817-2
makes balancing both inputs unnecessary, as opposed to traditional
FET input amplifiers. Therefore, minimizing the impedance
seen from the noninverting terminal to ground at all frequencies
is critical for optimal noise performance.
5
G = 63V/V
R
= 100Ω
L
S
OUT
0
Integrating the square of the output voltage noise spectral density
over frequency and then taking the square root allows users
to obtain the total rms output noise of the preamp. Table 9
summarizes approximations for the amplifier and feedback
and source resistances. Noise components for an example
preamp with RF = 50 kΩ, CS = 30 pF, and CF = 0.5 pF
(bandwidth of about 6.4 MHz) are also listed.
V
V
= 10V
= 6V p-p
–5
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 52. Photodiode Preamp Frequency Response
The pole in the loop transmission translates to a zero in the
noise gain of the amplifier, leading to an amplification of the
input voltage noise over frequency.
Table 9. RMS Noise Contributions of Photodiode Preamp
Contributor
Expression
RMS Noise with RF = 50 kΩ, CS = 30 pF, CF = 0.5 pF
RF
94 µV
4kT × RF × f2 ×1.57
VEN Amp
IEN Amp
777.5 µV
CS + CM + C D + CF
VEN ×
× f3 ×1.57
CF
0.4 µV
IEN ×RF × f2 ×1.57
783 µV (total)
Rev. B | Page 20 of 28
Data Sheet
ADA4817-1/ADA4817-2
Common-mode rejection of the in-amp is primarily determined by
the match of resistor ratios, R1:R2 to R3:R4. It can be estimated by
HIGH SPEED JFET INPUT INSTRUMENTATION
AMPLIFIER
VO
VCM
(
δ1− δ2
)
δ2
Figure 53 shows an example of a high speed instrumentation
amplifier with a high input impedance using the ADA4817-1/
ADA4817-2. The dc transfer function is
=
(17)
(
1+ δ1
)
The summing junction impedance for the preamps is equal
to RF || 0.5(RG). Keep this value relatively low to improve the
bandwidth response like in the previous example.
2RF
RG
(16)
VOUT
=
(
VN −VP
)
1+
For G = 1, it is recommended that the feedback resistors for the
two preamps be set to 0 Ω and the gain resistor be open. The
system bandwidth for G = 1 is 400 MHz. For gains higher than 2,
the bandwidth is set by the preamp, and it can be approximated by
In-amp−3 dB = (fCR × RG)/(2 × RF)
V
CC
0.1µF
10µF
R
S1
R2
350Ω
V
N
ADA4817-2
U1
V
CC
0.1µF
10µF
V
0.1µF
10µF
EE
R1
350Ω
R
= 500Ω
F
V
O
ADA4817-1
R
G
R3
350Ω
R
= 500Ω
F
0.1µF
10µF
V
CC
R4
350Ω
V
EE
0.1µF
10µF
ADA4817-2
U2
R
S2
0.1µF
10µF
V
P
V
EE
Figure 53. High Speed Instrumentation Amplifier
Rev. B | Page 21 of 28
ADA4817-1/ADA4817-2
Data Sheet
Resistor values are kept low for minimal noise contribution,
ACTIVE LOW-PASS FILTER (LPF)
offset voltage, and optimal frequency response. Due to the low
capacitance values used in the filter circuit, the PCB layout and
minimization of parasitics is critical. A few picofarads can detune
the corner frequency, fc, of the filter. The capacitor values shown
in Figure 55 actually incorporate some stray PCB capacitance.
Active filters are used in many applications such as antialiasing
filters and high frequency communication IF strips.
With a 410 MHz gain bandwidth product and high slew rate,
the ADA4817-1/ADA4817-2 is an ideal candidate for active
filters. Moreover, thanks to the low input bias current provided
by the FET stage, the ADA4817-1/ADA4817-2 eliminate any dc
errors. Figure 54 shows the frequency response of 90 MHz and
45 MHz LPFs. In addition to the bandwidth requirements, the slew
rate must be capable of supporting the full power bandwidth of the
filter. In this case, a 90 MHz bandwidth with a 2 V p-p output
swing requires at least 870 V/μs. This performance is achievable
at 90 MHz only because of the wide bandwidth and high slew
rate of the ADA4817-1/ADA4817-2.
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors and silver mica, are good choices for filter
elements.
15
12
9
6
3
0
–3
OUT2, f = 90MHz
OUT1, f = 90MHz
–6
The circuit shown in Figure 55 is a 4-pole, Sallen-Key, low-pass
filter (LPF). The filter comprises two identical cascaded Sallen-
Key LPF sections, each with a fixed gain of G = 2. The net gain
of the filter is equal to G = 4 or 12 dB. The actual gain shown in
Figure 54 is 12 dB. This does not take into account the output
voltage being divided in half by the series matching termination
resistor, RT, and the load resistor.
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
OUT1, f = 45MHz
OUT2, f = 45MHz
Setting the resistors equal to each other greatly simplifies the
design equations for the Sallen-Key filter. To achieve 90 MHz
the value of R should be set to 182 Ω. However, if the value of R
is doubled, the corner frequency is cut in half to 45 MHz. This
would be an easy way to tune the filter by simply multiplying
the value of R (182 Ω) by the ratio of 90 MHz and the new
corner frequency in megahertz. Figure 54 shows the output of
each stage of the filter and the two different filters corresponding
to R = 182 Ω and R = 365 Ω. It is not recommended to increase
the corner frequency beyond 90 MHz due to bandwidth and
slew rate limitations unless unity-gain stages are acceptable.
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 54. Low-Pass Filter Response
C1
3.9pF
C3
3.9pF
10µF
+5V
U1
10µF
+5V
U2
0.1µF
0.1µF
R
R
+IN1
R
R
R
T
R
C2
5.6pF
T
49.9Ω
10µF
49.9Ω
OUT2
OUT1
C4
5.6pF
10µF
0.1µF
0.1µF
–5V
–5V
R2
R1
348Ω
R4
348Ω
R3
348Ω
348Ω
Figure 55. 4-Pole Sallen-Key Low-Pass Filter (ADA4817-2)
Rev. B | Page 22 of 28
Data Sheet
ADA4817-1/ADA4817-2
1.2
0.8
0.15
0.10
0.05
0
90MHz
90MHz
45MHz
45MHz
0.4
0
–0.4
–0.8
–1.2
–0.05
–0.10
–0.15
TIME (5ns/DIV)
TIME (5ns/DIV)
Figure 57. Large Signal Transient Response (Low-Pass Filter)
Figure 56. Small Signal Transient Response (Low-Pass Filter)
Rev. B | Page 23 of 28
ADA4817-1/ADA4817-2
OUTLINE DIMENSIONS
Data Sheet
3.25
3.00 SQ
2.75
0.60 MAX
5
0.50
BSC
0.60 MAX
8
2.95
2.75 SQ
2.55
1.60
1.45
1.30
EXPOSED
PAD
TOP
VIEW
PIN 1
INDICATOR
(BOTTOM VIEW)
4
1
PIN 1
INDICATOR
0.50
0.40
0.30
1.89
1.74
1.59
12° MAX
0.70 MAX
0.65TYP
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
SECTION OF THIS DATA SHEET.
Figure 58. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2)
Dimensions shown in millimeters
5.00
4.90
4.80
2.29
0.356
5
6.20
6.00
5.80
8
4.00
3.90
3.80
2.29
0.457
4
1
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
BOTTOM VIEW
45°
1.27 BSC
3.81 REF
TOP VIEW
SECTION OF THIS DATA SHEET.
1.65
1.25
1.75
1.35
0.50
0.25
0.25
0.17
0.10 MAX
0.05 NOM
SEATING
PLANE
8°
0°
0.51
0.31
1.04 REF
COPLANARITY
0.10
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 59. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-1)
Dimensions shown in millimeters and (inches)
Rev. B | Page 24 of 28
Data Sheet
ADA4817-1/ADA4817-2
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
1
4
12
EXPOSED
PAD
2.40
2.35 SQ
2.30
9
5
8
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3.
Figure 60.16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad (CP-16-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4817-1ACPZ-R2
ADA4817-1ACPZ-RL
ADA4817-1ACPZ-R7
ADA4817-1ACP-EBZ
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
Evaluation Board for
8-Lead LFCSP
Package Option
CP-8-2
CP-8-2
Ordering Quantity
Branding
H1F
H1F
250
5,000
1,500
CP-8-2
H1F
ADA4817-1ARDZ
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
for8-Lead SOIC
RD-8-1
RD-8-1
RD-8-1
1
ADA4817-1ARDZ-RL
ADA4817-1ARDZ-R7
ADA4817-1ARD-EBZ
2,500
1,000
ADA4817-2ACPZ-R2
ADA4817-2ACPZ-RL
ADA4817-2ACPZ-R7
ADA4817-2ACP-EBZ
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
for16-Lead LFCSP
CP-16-20
CP-16-20
CP-16-20
250
5,000
1,500
1 Z = RoHS Compliant Part.
Rev. B | Page 25 of 28
ADA4817-1/ADA4817-2
NOTES
Data Sheet
Rev. B | Page 26 of 28
Data Sheet
NOTES
ADA4817-1/ADA4817-2
Rev. B | Page 27 of 28
ADA4817-1/ADA4817-2
NOTES
Data Sheet
©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07756-0-5/13(B)
Rev. B | Page 28 of 28
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