ADA4830 [ETC]
High Speed Difference Amplifier with Input Short to Battery Protection; 高速差动放大器，具有输入电池短路保护
| 型号： | ADA4830 |
| 厂家： | 
ETC |
| 描述： | High Speed Difference Amplifier with Input Short to Battery Protection |
| 文件： | 总16页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed Difference Amplifier with Input
Short to Battery Protection
Data Sheet
ADA4830-1
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ENA
+VS
STB
Input overvoltage (short to battery) protection of up to 18 V
Short to battery output flag for wire diagnostics
Wide input common-mode range with single 5 V supply
High performance video amplifier with 0.5 V/V gain
−3 dB bandwidth of 84 MHz
+VS
ADA4830-1
VREF
BUFFER
R/2
220 V/µs slew rate (2 V step)
Excellent video specifications
0.1 dB flatness to 20 MHz
R
R
INP
INN
VOUT
SNR of 73 dB to 15 MHz
R/2
Differential gain of 0.1%
Differential phase of 0.1°
GND
Wide supply range: 2.9 V to 5.5 V
Figure 1.
Power-down mode
Space saving 3 mm × 3 mm LFCSP package
Wide operating temperature range: −40°C to +125°C
APPLICATIONS
Automotive vision systems
Automotive infotainment
Surveillance systems
GENERAL DESCRIPTION
The ADA4830-1 is a monolithic high speed difference amplifier
that integrates input overvoltage (short to battery) protection of
up to 18 V with a wide input common-mode voltage range and
excellent ESD robustness. The ADA4830-1 is intended for use
as a receiver for differential or pseudo differential CVBS and
other high speed video signals in harsh, noisy environments
such as automotive infotainment and vision systems. The
ADA4830-1 combines the high speed and the precision that
allow accurate reproduction of CVBS video signals, yet rejects
unwanted common-mode error voltages.
series capacitors. The ADA4830-1 can withstand direct short to
battery voltages as high as 18 V on its input pins.
The ADA4830-1 is designed to operate at supply voltages as low
as 2.9 V and as high as 5.5 V, using only 6.8 mA of supply
current per channel. The device provides true single-supply
capability, allowing the input signal to extend 8.5 V below the
negative rail and to 8.5 V above ground on a single 5 V supply.
At the output, the amplifier can swing to within 250 mV of
either supply rail into a 150 Ω load.
The ADA4830-1 presents a gain of 0.5 V/V at its output. This is
designed to keep the video signal within the allowed range of
the video decoder, which is typically 1 V p-p or less.
The short to battery protection that is integrated into the
ADA4830-1 employs fast switching circuitry to clamp and hold
internal voltage nodes at a safe level when an input overvoltage
condition is detected. This protection allows the inputs of the
ADA4830-1 to be directly connected to a remote video source,
such as a rearview camera, without the need for large expensive
The ADA4830-1 is available in a 3 mm × 3 mm, 8-lead LFCSP
package and is specified for operation over the automotive
temperature range of −40°C to +125°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADA4830-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Overvoltage (Short to Battery) Protection.............................. 10
Short to Battery Output Flag .................................................... 10
ESD Protection ........................................................................... 10
Applications Information .............................................................. 11
Methods of Transmission.......................................................... 11
Voltage Reference (VREF Pin) ................................................. 11
Input Common-Mode Range ................................................... 11
Short to Battery Output Flag Pin ............................................. 12
Enable/Disable Modes (ENA Pin) ........................................... 12
PCB Layout ................................................................................. 12
Exposed Paddle (EPAD) Connection...................................... 12
Typical Applications Circuits........................................................ 13
Packaging and Ordering Information ......................................... 16
Outline Dimensions................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 4
Absolute Maximum Ratings ....................................................... 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Core Amplifier............................................................................ 10
REVISION HISTORY
10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
ADA4830-1
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, RL = 1 kΩ, VREF = 2.5 V (floating), VINCM = +VS/2, RSTB = 5 kΩ to +VS, unless otherwise specified.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
VOUT = 0.5 V p-p, RL = 150 Ω
VOUT = 0.1V p-p, RL = 1 kΩ
VOUT = 0.1V p-p, RL = 150 Ω
VOUT = 0.5 V p-p, RL = 150 Ω
VOUT = 2 V step
71
84
74
28
220
25
MHz
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate (tR/tF)
Settling Time to 0.1%
VOUT = 2 V step
NOISE/DISTORTION PERFORMANCE
Output Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Signal-to-Noise Ratio
f = 1 MHz
28
nV/√Hz
%
Degrees
dB
RL = 150 Ω, VIN = 1 V p-p
RL = 150 Ω, VIN = 1 V p-p
f = 100 kHz to 15 MHz, VOUT = 0.5 V p-p
0.1
0.1
73
DC PERFORMANCE
Nominal Gain
Output Bias Voltage
VIN to VOUT
0.49 0.50
2.45 2.50
0.51
2.55
V/V
V
INPUT CHARACTERISTICS
Input Resistance (Differential Mode)
Input Resistance (Common Mode)
Input Common-Mode Voltage Range
Common-Mode Rejection (CMR)
SHORT TO BATTERY CHARACTERISTICS
Input Current
Protected Input Voltage Range
Short to Battery Output Flag Trigger Level
VOLTAGE REFERENCE INPUT
Input Voltage Range
7
2
kΩ
kΩ
V
8.5
VIN = 5 V
45
65
dB
VIN = 18 V (short to battery)
Signals an input fault condition
4.1
10.3
mA
V
V
−9
9.8
+20
10.8
0.2 to 3.9
V
Input Resistance
Gain
20
1
kΩ
V/V
VREF to VOUT
LOGIC OUTPUT/INPUT CHARACTERISTICS
STB VOH
STB VOL
ENA VIH
ENA VIL
Input voltage ≤ 9.75 V (normal operation)
Input voltage ≥ 10.75 V (fault condition)
Voltage to enable device
5.0
V
mV
V
110
≥3.0
≤1.0
Voltage to disable device
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 150 Ω to GND
0.01 to
4.75
V
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
125
248/294
47
mA
mA
pF
Sourcing/sinking
Peaking ≤ 3 dB
Operating Range
Operation outside of this range results in performance
degradation
Enabled (ENA = 5 V), no load
Disabled (ENA = 0 V)
2.9
5.5
10
V
Quiescent Current per Amplifier
6.8
90
mA
µA
VIN = 18 V (short to battery)
+VS = 4.5 V to 5.5 V, VREF is forced to 2.5 V
5.3
53
mA
dB
Power Supply Rejection Ratio (PSRR)
OPERATING TEMPERATURE RANGE
−40
+125 °C
Rev. 0 | Page 3 of 16
ADA4830-1
Data Sheet
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, RL = 1 kΩ, VREF = 2.5 V (floating), VINCM = +VS/2, RSTB = 5 kΩ to +Vs, unless otherwise specified.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
VOUT = 0.5 V p-p, RL = 150 Ω
VOUT = 0.1V p-p, RL = 1 k Ω
VOUT = 0.1V p-p, RL = 150 Ω
VOUT = 0.5 V p-p, RL = 150 Ω
VOUT = 1 V step
73
89
76
25
220
25
MHz
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate (tR/tF)
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Output Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Signal-to-Noise Ratio
DC PERFORMANCE
VOUT = 1 V step
f = 1 MHz
28
nV/√Hz
%
Degrees
dB
RL = 150 Ω, VIN = 1 V p-p
RL = 150 Ω, VIN = 1 V p-p
f = 100 kHz to 15 MHz, VOUT = 0.5 V p-p
0.1
0.1
73
Nominal Gain
Output Bias Voltage
VIN to VOUT
0.49
1.60
0.50
1.65
0.51
1.70
V/V
V
INPUT CHARACTERISTICS
Input Resistance (Differential Mode)
Input Resistance (Common Mode)
Input Common-Mode Voltage Range
Common-Mode Rejection (CMR)
SHORT TO BATTERY CHARACTERISTICS
Input Current
Protected Input Voltage Range
Short to Battery Output Flag Trigger Level
VOLTAGE REFERENCE INPUT
Input Voltage Range
7
2
5.5
54
kΩ
kΩ
V
VIN = 3.3 V
43
dB
VIN = 18 V (short to battery)
Signals an input short to battery event
4.4
7.8
mA
V
V
−9
7.4
+20
8.2
0.2 to 2.2
V
Input Resistance
Gain
20
1
kΩ
V/V
VREF to VOUT
LOGIC OUTPUT/INPUT CHARACTERISTICS
STB VOH
STB VOL
ENA VIH
ENA VIL
Input voltage ≤ 7.25 V (normal operation)
Input voltage ≥ 8.25 V (fault condition)
Voltage to enable device
3.3
85
≥1.8
≤0.8
V
mV
V
Voltage to disable device
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
RL = 150 Ω to GND
0.01 to 3.08
50
85/180
47
V
mA
mA
pF
Sourcing/sinking
Peaking ≤ 4 dB
Operating Range
Operation outside of this range results in
performance degradation
Enabled (ENA = 3.3 V), no load
Disabled (ENA = 0 V)
2.9
5.5
8.0
V
Quiescent Current per Amplifier
5.5
60
mA
µA
VIN = 18 V (short to battery)
+VS = 3.0 V to 3.6 V, VREF forced to 1.65 V
4.3
42
mA
dB
Power Supply Rejection Ratio (PSRR)
OPERATING TEMPERATURE RANGE
−40
+125 °C
Rev. 0 | Page 4 of 16
Data Sheet
ADA4830-1
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
Table 3.
Parameter
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to load drive
depends on the particular application. The power due to load
drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Rating
Supply Voltage (+VS pin)
Input Voltage Positive Direction (INN, INP)
Input Voltage Negative Direction (INN, INP)
Reference Voltage (VREF pin)
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
6 V
22 V
−10 V
+VS + 0.3 V
See Figure 2
−65°C to +125°C
−40°C to +125°C
260°C
Airflow increases heat dissipation, effectively reducing θJA.
Figure 2 shows the maximum power dissipation in the package
vs. the ambient temperature for the 8-lead LFCSP (116°C/W) on
a JEDEC standard 4-layer board. θJA values are approximate.
1.8
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
THERMAL RESISTANCE
θJA is specified for the device soldered to a high thermal
conductivity, 4-layer (2s2p) circuit board, as described in
EIA/JESD 51-7.
Table 4.
Package Type
8-Lead LFCSP
0
10
20
30
40
50
60
70
80
90
100
θJA
Unit
AMBIENT TEMPERATURE (°C)
116
°C/W
Figure 2. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4830-1
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties.
Exceeding a junction temperature of 150°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
ESD CAUTION
Rev. 0 | Page 5 of 16
ADA4830-1
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VREF 1
INP 2
8
7
6
5
+VS
ENA
VOUT
STB
ADA4830-1
TOP VIEW
INN 3
(Not to Scale)
GND 4
NOTES
1. EXPOSED PAD ON BOTTOM SIDE
OF PACKAGE. NOT CONNECTED
ELECTRICALLY, BUT SHOULD BE
SOLDERED TO A METALIZED AREA
ON THE PCB TO MINIMIZE THERMAL
RESISTANCE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
VREF
Voltage Reference Input. Sets the output dc bias voltage. Internally biased to +Vs/2 when left floating. See the
Applications Information section.
2
3
4
5
INP
Positive Input.
Negative Input.
Power Supply Ground Pin.
INN
GND
STB
Short to Battery Indicator Pin. A logic low indicates an overvoltage condition (short to battery), whereas a logic
high indicates normal operation. An open-drain configuration requires external pull-up resistor.
6
7
8
VOUT
ENA
+VS
Video Amplifier Output.
Enable. Connect to +VS or float for normal operation. Connect to GND for device disable.
Positive Power Supply. Bypass this pin with a 0.1 µF capacitor to GND.
EPAD
Exposed Pad. The exposed pad is located on bottom side of package. The pad is not connected electrically but
should be soldered to a metalized area on the PCB to minimize thermal resistance.
Rev. 0 | Page 6 of 16
Data Sheet
ADA4830-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, RL = 1 kΩ, VREF = 2.5 V (floating), VINCM = +VS/2, RSTB = 5 kΩ to +VS unless otherwise specified.
3
0
3
0
R
= 1kΩ
LOAD
R
= 1kΩ
LOAD
R
= 150Ω
LOAD
R
= 150Ω
LOAD
–3
–6
–9
–12
–3
–6
–9
–12
+V = 5V
S
GAIN = 0.5V/V
–15
–18
–15
–18
V
= 200mV p-p
V
= 1V p-p
IN
IN
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 4. Small Signal Frequency Response vs. Load
Figure 7. Large Signal Frequency Response vs. Load
3
0
3
0
+V = 3.3V
S
+V = 3.3V
S
+V = 5V
S
–3
–6
–9
–12
–3
–6
–9
–12
+V = 5V
S
–15
–18
–15
–18
V
= 200mV p-p
V
= 1V p-p
IN
IN
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 5. Small Signal Frequency Response vs. Supply Voltage
Figure 8. Large Signal Frequency Response vs. Supply Voltage
3
0
3
0
–3
–6
–3
–45°C
–6
–45°C
–9
–9
+125°C
–12
–12
–15
–15
+25°C
+25°C
–18
–18
–21
–21
+125°C
V
R
= 1V p-p
IN
V
= 200mV p-p
= 150Ω
IN
LOAD
–24
–24
1
10
100
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Temperatures,
+VS = 5 V
Figure 9. Large Signal Frequency Response for Various Temperatures,
+VS = 3.3 V
Rev. 0 | Page 7 of 16
ADA4830-1
Data Sheet
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
7
6
V
= 200mV p-p
IN
f = 5MHz
5
4
3
C
C
= 68pF
= 47pF
L
+V = 3.0V
S
L
+V = 3.3V
+V = 5.0V
S
2
1
S
C
= 22pF
L
0
–1
C
= 10pF
L
V
R
= 1V p-p
–2
–3
C
= 0pF
IN
L
+V = 5.5V
S
= 150Ω
LOAD
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
0.1
1
10
FREQUENCY (MHz)
100
INPUT COMMON-MODE VOLTAGE (V)
Figure 10. Large Signal Frequency Response for Various Capacitor Loads
Figure 13. Small Signal CMR vs. VINCM and Supply Voltage
0
0.1
0
V
= 1V p-p
INP
ENA = 0V
–10
–20
–30
–40
–50
–60
–70
–0.1
–0.2
–0.3
–0.4
V
R
= 1V p-p
IN
= 150Ω
LOAD
–0.5
0.1
0.1
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 11. 0.1 dB Flatness
Figure 14. Disabled Response: Input to Output
–20
–30
–40
–50
–60
–70
–80
–90
6
3
+V = 5V
+V = 3.3V
+V = 5.0V
S
S
S
V
= 1V p-p
IN
LOAD
R
= 1kΩ
R
= 1kΩ
LOAD
LOAD
R
= 1kΩ
V
= +8V
INCM
0
+V = 5.0V
S
R
= 150Ω
LOAD
–3
–6
–9
V
= 0V
INCM
+V = 3.3V
S
V
= −8V
INCM
R
= 150Ω
LOAD
–12
–15
V
= 200mV p-p AT +V /2
S
REF
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 12. CM Frequency Response vs. Input Common-Mode Voltage
Figure 15. Small Signal Response: VREF to VOUT
Rev. 0 | Page 8 of 16
Data Sheet
ADA4830-1
2.9
40
30
+V = 3.3V
OUT
R
= 1kΩ
S
LOAD
V
= 1V p-p
R
= 1kΩ
LOAD
VREF PIN BYPASSED TO GND
THROUGH 4.7µF CAPACITOR
2.7
2.5
2.3
2.1
1.9
1.7
1.5
R
= 150Ω
LOAD
20
V
= 3.3V
DD
10
0
V
= 5V
DD
–10
–20
10
20
30
40
50
TIME (ns)
60
70
80
90
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
INPUT COMMON-MODE VOLTAGE (V)
Figure 16. Pulse Response at +VS = 3.3 V
Figure 19. Output Offset Voltage : VOUT − VREF
10
9
8
7
6
5
4
3
2
1
0
16
14
12
10
8
V
= 14V, 150ns PULSE
INP
+V = 5V
S
+V
INP
6
+V
STB
+V = 3.3V
S
4
2
0
V
V
= FLOATING
INP, INN
–2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
50
100
150
200
250
300
350
400
ENABLE VOLTAGE (V)
TIME (ns)
Figure 20. Supply Current vs. Enable Voltage
Figure 17. STB Flag Response
6
5
4
3
2
1
ENA
V
OUT
0
–1
0
100
200
300
400
500
600
TIME (ns)
Figure 18. Enable Pin Turn-on/Turn-off Time
Rev. 0 | Page 9 of 16
ADA4830-1
Data Sheet
THEORY OF OPERATION
CORE AMPLIFIER
SHORT TO BATTERY OUTPUT FLAG
At the core of the ADA4830-1 is a high speed, rail-to-rail op
amp that is built on a 0.35 μm CMOS process. Together with the
core amplifier, the ADA4830-1 combines four highly matched
on-chip resistors into a difference amplifier function. Common-
mode range extension at its inputs is achieved by employing a
resistive attenuator. The closed-loop differential to single-ended
gain of the video channel is internally fixed at 0.5 V/V (−6 dB)
to ensure compatibility with video decoders whose input range
is constrained to 1 V p-p or less. The transfer function of the
ADA4830-1 is
The short to battery output flag (STB pin) is functionally
independent of the short to battery protection. Its purpose is
to indicate an overvoltage condition on either input. Because
protection is provided passively, it is always available; the flag
merely indicates the presence or absence of a fault condition.
ESD PROTECTION
All pins on the ADA4830-1 are protected with internal ESD
protection structures connected to the power supply pins (+VS
and GND). These structures provide protection during the
handling and manufacturing process.
ꢀ
ꢅꢆꢇ
ꢈ ꢀ
ꢅꢆꢉ
ꢀꢁꢂꢃ
where:
ꢄ
ꢊ ꢀꢋꢌꢍ
The inputs (INN and INP) of the ADA4830-1 can be exposed
to dc voltages well above the supply voltage; therefore, conven-
tional ESD structure protection cannot be used.
2
V
V
OUT is the voltage at the output pin, VOUT.
IN+ and VIN− are the input voltages at Pin INP and Pin INN,
The ADA4830-1 employs Analog Devices, Inc., proprietary
ESD devices at the input pins (INN, INP) to allow for a wide
common-mode voltage range and ESD protection well beyond
the handling and manufacturing requirements.
respectively.
REF is the voltage at the VREF pin.
V
OVERVOLTAGE (SHORT TO BATTERY)
PROTECTION
Robust inputs guarantee that sensitive internal circuitry is not
subjected to extreme voltages or currents during a stressful
event. A short to battery condition usually consists of a voltage
on either input (or both inputs) that is significantly higher than
the power supply voltage of the amplifier. Duration may vary
from a short transient to a continuous fault.
The ADA4830-1 can withstand voltages of up to 18 V on the
inputs. Critical internal nodes are protected from exposure to
high voltages by circuitry that clamps the inputs at a safe level
and limits internal currents. This protection is available whether
the device is enabled or disabled, even when the supply voltage
is removed.
Rev. 0 | Page 10 of 16
Data Sheet
ADA4830-1
APPLICATIONS INFORMATION
METHODS OF TRANSMISSION
Fully Differential Mode
The differential inputs of the ADA4830-1 allow full balanced
transmission using any differential source. In this configuration,
the differential input termination is equal to twice the source
impedance of each output. For example, a source with 37.5 Ω
back termination resistors in each leg should be terminated
with a differential resistance of 75 Ω. An illustration of this
arrangement is shown in Figure 23.
Pseudo Differential Mode (Unbalanced Source
Termination)
The ADA4830-1 can be operated in a pseudo differential
configuration with an unbalanced input signal. This allows
the receiver to be driven by any single-ended source. Pseudo
differential mode uses a single conductor to carry an unbalanced
signal, and connects the negative input terminal to the ground
reference of the source.
DRIVER PCB
Use the positive wire or coaxial center conductor to connect the
source output to the positive input (INP) of the ADA4830-1.
Next, connect the negative wire or coaxial shield from the
negative input (INN) back to a ground reference on the source
printed circuit board (PCB). The input termination should
match the source impedance and be referenced to the remote
ground. An example of this configuration is shown in Figure 21.
POSITIVE WIRE
37.5Ω
37.5Ω
INP
75Ω
INN
+
DIFFERENTIAL
AMPLIFIER
ADA4830-1
−
NEGATIVE WIRE
Figure 23. Fully Differential Mode
VOLTAGE REFERENCE (VREF PIN)
DRIVER PCB
An internal reference level determines the output voltage when
the differential input voltage is zero. This is set by a resistor
divider connected between the supply rails. Built with a matched
pair of 40 kΩ resistors, the divider sets this voltage to +VS/2.
POSITIVE WIRE
75Ω
INP
75Ω
INN
+
SINGLE ENDED
AMPLIFIER
ADA4830-1
−
NEGATIVE WIRE
The voltage reference pin (VREF) normally floats at its default
value of +VS/2. However, it can be used to vary the output
reference level from this default value. A voltage applied to
VREF appears at the output with unity gain, within the
bandwidth limit of the internal reference buffer.
Figure 21. Pseudo Differential Mode
Pseudo Differential Mode (Balanced Source Impedance)
Pseudo differential signaling is typically implemented using
unbalanced source termination as shown in Figure 21. With this
arrangement, however, common-mode signals on the positive
and negative inputs receive different attenuation due to unbalanced
termination at the source. This effectively converts some of the
common-mode signal into differential mode signal, degrading
the overall common-mode rejection of the system. System
common-mode rejection can be improved by balancing the
output impedance of the driver as shown in Figure 22. Splitting
the source termination resistance evenly between the hot and
cold conductors results in matched attenuation of the common-
mode signals, ensuring maximum rejection.
Any noise on the +VS supply rail appears at the output with only
6 dB of attenuation (the divide-by-two provided by the reference
divider). Even when this pin is floating, it is recommended that
an external capacitor be connected from the reference node to
ground to provide further attenuation of noise on the power supply
line. A 4.7 µF capacitor combined with the internal 40 kΩ resistor
sets the low-pass corner at under 1 Hz and results in better than
40 dB of supply noise attenuation at 100 Hz.
INPUT COMMON-MODE RANGE
In a standard four resistor difference amplifier with 0.5 V/V
gain, the input common-mode (CM) range is three times the
CM range of the core amplifier. In the ADA4830-1, however,
the input CM has been extended to more than 17 V (with a 5 V
supply). The input CM range can be approximated by using the
following formulas:
DRIVER PCB
POSITIVE WIRE
37.5Ω
37.5Ω
INP
75Ω
INN
+
SINGLE ENDED
AMPLIFIER
ADA4830-1
−
NEGATIVE WIRE
Maximum CM voltage
5(+VS − 1.25) − 4VREF ≈ VINCM(MAX) ≤ 9.5 V
Figure 22. Pseudo Differential Mode with Balanced Source Impedance
Minimum CM voltage
−10 V ≤ VINCM(MIN) ≈ − (1 + 4VREF
)
Rev. 0 | Page 11 of 16
ADA4830-1
Data Sheet
Approximate minimum and maximum CM voltages are shown
in Table 6 for several common supply voltages.
the speed is determined by external capacitance and the
magnitude of the pull-up resistor. For the case of 10 pF of
external capacitance and a pull-up of 5 kΩ, the time constant
of the rising edge is approximately 50 ns.
Table 6.
+VS (V)
VREF (V)
1.51
0.97
1.671
1.15
1.81
1.34
2.51
2.22
VINCM(MIN) (V)
–7.0
–4.9
–7.6
–5.6
–8.2
–6.4
–10
–9.9
VINCM(MAX) (V)
Table 7. STB Pin Function
3.0
3.0
3.3
3.3
3.6
3.6
5.0
5.0
2.8
4.9
3.6
5.6
4.5
6.4
8.7
9.9
STB Pin Output
High (Logic 1)
Low (Logic 0)
Device State
Normal operation
STB fault condition
ENABLE/DISABLE MODES (ENA PIN)
The power-down, or enable/disable (ENA) pin, is internally
pulled up to +VS through a 250 kΩ resistor. When the voltage
on this pin is high, the amplifier is enabled; pulling ENA low
disables the channel. With no external connection, this pin
floats high, enabling the amplifier channel.
1 Floating (default condition).
15
VREF PIN FLOATING
Table 8. ENA Pin Function
10
ENA Pin Input
High (Logic 1)
Low (Logic 0)
Device State
Enabled
Disabled
V
INCM (MAX)
5
0
PCB LAYOUT
As with all high speed applications, attention to PCB layout is of
paramount importance. Adhere to standard high speed layout
practices in designs using the ADA4830-1. A solid ground plane
is recommended, and placing a 0.1 µF surface-mount, ceramic
power supply, decoupling capacitor as close as possible to the
supply pin is recommended.
–5
–10
V
INCM (MIN)
–15
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Connect the GND pin(s) to the ground plane with a trace that is
as short as possible. In cases where the ADA4830-1 drives trans-
mission lines, series terminate the outputs and use controlled
impedance traces of the shortest length possible to connect to
the signal I/O pins, which should not pass over any voids in the
ground plane.
Figure 24. Input Common-Mode Range vs. Supply Voltage
SHORT TO BATTERY OUTPUT FLAG PIN
The flag output (STB pin) is of an active low, open-drain logic
style. A low level on this output indicates that more than 11 V
has been detected on either the positive or the negative input.
Flags from multiple chips may be wire-or'ed to form a single
fault detection signal. The output is driven by a grounded source
NMOS device, capable of sinking approximately 10 mA while
pulling within 100 mV of ground. The output high level is set
with an external pull-up resistor connected to the supply voltage
of the logic family that is used to monitor the state of the flag.
EXPOSED PADDLE (EPAD) CONNECTION
The ADA4830-1 has an exposed thermal pad (EPAD) on the
bottom of the package. This pad is not electrically connected
to the die and can be left floating or connected to the ground
plane. Should heat dissipation be a concern, thermal resistance
can be minimized by soldering the EPAD to a metalized pad on
the PCB. Connect this pad to the ground plane with multiple
The speed with which the flag output responds primarily
depends, in the falling direction, on the external capacitance
attached to this node and the sink current that can be provided.
For example, if the load is 10 pF, and the external pull-up voltage is
3.3 V, the fall time is a few nanoseconds. In the rising direction,
vias. Note that the thermal resistance (θ ) of the device is
JA
specified with the EPAD soldered to the PCB.
Rev. 0 | Page 12 of 16
Data Sheet
ADA4830-1
TYPICAL APPLICATIONS CIRCUITS
+VS
STB FLAG
(2.9V TO 5.5V) (OUTPUT)
ENABLE
(INPUT)
4.7kΩ
+
2.2µF
0.1µF
ENA
+VS
STB
+VS
VREF
4.7µF
DRIVER PCB
POSITIVE WIRE
75Ω
INP
+
SINGLE ENDED
AMPLIFIER
TO VIDEO
DECODER
VOUT
0.1µF
75Ω
INN
−
NEGATIVE WIRE
ADA4830-1
GND
Figure 25. Typical Application with Pseudo Differential Input
STB FLAG
(OUTPUT)
+VS
(2.9V TO 5.5V)
ENABLE
(INPUT)
4.7kΩ
+
2.2µF
0.1µF
ENA
+VS
STB
+VS
VREF
4.7µF
DRIVER PCB
37.5Ω
37.5Ω
INP
+
TO VIDEO
DECODER
VOUT
0.1µF
DIFFERENTIAL
AMPLIFIER
75Ω
INN
−
ADA4830-1
GND
Figure 26. Typical Application with Fully Differential Input
Rev. 0 | Page 13 of 16
ADA4830-1
Data Sheet
STB FLAG
(OUTPUT)
+VS
(2.9V TO 5.5V)
ENABLE
(INPUT)
4.7kΩ
D
_1.8V
D
A
_1.8V
VDD
VDD
VDDIO
+
2.2µF
ENA
+VS
0.1µF
0.1µF
10nF 0.1µF
10nF 0.1µF
10nF
+VS
STB
P
_1.8V
VDD
D
_3.3V
VDD
VREF
4.7µF
D
_1.8V
VDD
A
_1.8V
0.1µF
10nF
VDD
+
INP
VOUT
P[0:7]
19
A
1
75Ω
INN
IN
IN
IN
0.1µF
23
24
25
A
A
2
3
−
16
15
10
9
P0
P0
P1
P2
P3
P4
P5
P6
P7
ADA4830-1
P1
P2
P3
P4
P5
P6
P7
YCrCb
8-BIT
656 DATA
RESET
RESET
GND
KEEP VREFN AND VREFP CAPACITORS AS CLOSE AS
POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE
OF THE PCB AS THE ADV7180.
8
7
6
21
5
VREFN
VREFP
0.1µF
20
0.1µF
LOCATE CLOSE TO, AND
ON THE SAME SIDE AS,
THE ADV7180
ADV7180
13
XTAL
11
32
4
LLC
INTRQ
SFL
LLC
47pF
28.63636MHz
1MΩ
INTRQ
SFL
12
26
XTAL1
31
1
47pF
VS/FIELD
HS
VS/FIELD
HS
D
VDDIO
4kΩ
P
_1.8V
VDD
ALSB
EXTERNAL
LOOP FILTER
2
ALSB TIED HI ≥ I C ADDRESS = 42h
ALSB TIED LOW ≥ I C ADDRESS = 40h
2
10nF
17
ELPF
82nF
28
27
SCLK
SDA
SCLK
1.69kΩ
SDATA
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
Figure 27. ADA4830-1 Driving an ADV7180 Video Decoder
Rev. 0 | Page 14 of 16
Data Sheet
ADA4830-1
STB FLAG
(OUTPUT)
+VS
(2.9V TO 5.5V)
ENABLE
(INPUT)
+VS
STB FLAG
ENABLE
(INPUT)
(2.7V TO 3.6V) (OUTPUT)
4.7kΩ
+
+
2.2µF
ENA
0.1µF
2.2µF
ENA
+VS
0.1µF
+VS
STB
+VS
STB
FROM
IMAGER
OR VIDEO
VREF
4.7µF
ENCODER
75Ω
TWISTED
PAIR
+IN
LPF
–OUT
+OUT
37.5Ω
37.5Ω
INP
−
+
R
TO VIDEO
T
DECODER
VOUT
75Ω
INN
0.1µF
+
−
+VS
–IN
ADA4830-1
LPF
GND
GND
Figure 28. Differential Video Filter Driver and ADA4830-1 Difference Amplifier
Rev. 0 | Page 15 of 16
ADA4830-1
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
EXPOSED
PAD
1.70
1.60
1.50
0.50
0.40
0.30
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TOJEDEC STANDARDS MO-229-WEED
Figure 29.8-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-8-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Branding Ordering Quantity
ADA4830-1BCPZ-R7
−40°C to +125°C
8-Lead Lead Frame Chip CP-8-11
Scale Package [LFCSP]
H30
1,500
ADA4830-1BCPZ-R2
−40°C to +125°C
8-Lead Lead Frame Chip CP-8-11
Scale Package [LFCSP]
H30
250
ADA4830-1BCP-EBZ
Evaluation Board
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10020-0-10/11(0)
www.analog.com/ADA4830-1
Rev. 0 | Page 16 of 16
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