AD9731BRS [ADI]
10-Bit, 170 MSPS D/A Converter; 10位， 170 MSPS D / A转换器
| 型号： | AD9731BRS |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 170 MSPS D/A Converter |
| 文件： | 总11页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 170 MSPS
D/A Converter
a
AD9731
FUNCTIONAL BLOCK DIAGRAM
FEATURES
170 MSPS Update Rate
TTL/High-Speed CMOS-Compatible Inputs
Wideband SFDR: 66 dB @ 2 MHz/50 dB @ 65 MHz
Pin-Compatible, Lower Cost Replacement for
Industry Standard AD9721 DAC
Low Power: 439 mW @ 170 MSPS
Fast Settling: 3.8 ns to 1/2 LSB
Internal Reference
ANALOG
RETURN
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DECODERS
AND
DRIVERS
TTL
DRIVE
LOGIC
IOUT
SWITCH
NETWORK
REGISTER
IOUT
Two Package Styles: 28-Lead SOIC and SSOP
REF IN
APPLICATIONS
CLOCK
CONTROL
AMP
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging
INTERNAL VOLTAGE
REFERENCE
AMP OUT
R
DIGITAL DIGITAL ANALOG
SET
5 MHz–65 MHz HFC Upstream Path
REF OUT
CONTROL
AMP IN
–V
+V
–V
S
S
S
GENERAL DESCRIPTION
Optimized for direct digital synthesis (DDS) waveform recon-
struction, the AD9731 provides 50 dB of wideband harmonic
suppression over a dc-to-65 MHz analog output bandwidth.
This signal bandwidth addresses the transmit spectrum in many
of the emerging digital communications applications where
signal purity is critical. Narrowband, the AD9731 provides an
SFDR of greater than 79 dB. This excellent wideband and
narrowband ac performance, coupled with a lower pricing struc-
ture, make the AD9731 the optimum high performance DAC
value.
The AD9731 is a 10-bit, 170 MSPS, bipolar D/A converter that
is optimized to provide high dynamic performance, yet offer
lower power dissipation and more economical pricing than
afforded by previous bipolar high performance DAC solutions.
The AD9731 was designed primarily for demanding communi-
cations systems applications where wideband spurious-free
dynamic range (SFDR) requirements are strenuous and could
previously only be met by using a high performance DAC such
as the industry-standard AD9721. The proliferation of digital
communications into basestation and high volume subscriber-
end markets has created a demand for excellent DAC perfor-
mance delivered at reduced levels of power dissipation and cost.
The AD9731 is the answer to that demand.
The AD9731 is packaged in 28-lead SOIC (same footprint
as the industry standard AD9721) and super space-saving
28-lead SSOP; both are specified to operate over the extended
industrial temperature range of –40°C to +85°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
5/27/99 8 PM
(+VS = +5 V, –VS = –5.2 V, CLOCK = 125 MHz, RSET = 1.96 k⍀ for 20.4 mA IOUT
REF = –1.25 V, unless otherwise noted.)
,
V
AD9731–SPECIFICATIONS
Parameter
Temp
Test Level
Min
Typ
10
Max
Units
Bits
RESOLUTION
THROUGHPUT RATE
+25°C
IV
165
170
MHz
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
0.25
0.35
0.6
1
1.5
1
LSB
LSB
LSB
LSB
Integral Nonlinearity
VI
0.7
1.5
INITIAL OFFSET ERROR
Zero-Scale Offset Error
+25°C
Full
+25°C
Full
I
VI
I
VI
V
35
40
2.5
2.5
0.04
70
100
5
µA
µA
% FS
% FS
µA/°C
Full-Scale Gain Error1
Offset Drift Coefficient
5
REFERENCE/CONTROL AMP
Internal Reference Voltage2
Internal Reference Voltage Drift
Internal Reference Output Current3
Amplifier Input Impedance
Amplifier Bandwidth
+25°C
Full
Full
+25°C
+25°C
I
–1.35
–50
–1.25
100
–1.15
+500
V
µV/°C
µA
kΩ
MHz
IV
VI
V
50
2.5
V
REFERENCE INPUT4
Reference Input Impedance
+25°C
+25°C
V
V
4.6
75
kΩ
MHz
Reference Multiplying Bandwidth5
OUTPUT PERFORMANCE
Output Current4, 6
Output Compliance
Output Resistance
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
V
IV
V
V
V
V
V
V
V
V
20
mA
V
Ω
pF
ns
ns
pVs
V/µs
ns
–1.5
+3
240
5
Output Capacitance
7
Voltage Settling Time to 1/2 LSB (tST
)
3.8
2.9
4.1
400
1
8
Propagation Delay (tPD
)
Glitch Impulse9
Output Slew Rate10
Output Rise Time10
Output Fall Time10
1
ns
DIGITAL INPUTS
Input Capacitance
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Full
Full
Full
+25°C
+25°C
+25°C
Full
+25°C
Full
IV
VI
VI
VI
VI
IV
IV
IV
IV
IV
IV
2
pF
V
V
2.0
0.8
50
100
2
2.5
1.0
1.0
8
µA
µA
ns
ns
ns
ns
ns
ns
30
1.2
1.5
0.1
0.1
Minimum Data Setup Time (tS)11
Minimum Data Hold Time (tH)12
Clock Pulsewidth Low (pwMIN
Clock Pulsewidth High (pwMAX
)
+25°C
+25°C
2
2
)
SFDR PERFORMANCE (Wideband) 13
2 MHz AOUT
10 MHz AOUT
20 MHz AOUT
40 MHz AOUT
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
V
V
V
V
V
V
66
62
61
55
50
47
dB
dB
dB
dB
dB
dB
65 MHz AOUT (Clock = 170 MHz)
70 MHz AOUT (Clock = 170 MHz)
–2–
REV. A
5/27/99 8 PM
AD9731
Parameter
Temp
Test Level
Min
Typ
Max
Units
SFDR PERFORMANCE (Narrowband)13
2 MHz; 2 MHz Span
25 MHz, 2 MHz Span
+25°C
+25°C
+25°C
V
V
V
79
61
73
dB
dB
dB
10 MHz, 5 MHz Span (Clock = 170 MHz)
INTERMODULATION DISTORTION14
F1 = 800 kHz, F2 = 900 kHz
+25°C
V
58
dB
POWER SUPPLY15
Digital –V Supply Current
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
I
VI
I
VI
I
VI
V
V
V
27
27
45
45
13
15
439
449
100
37
42
53
66
20
22
mA
mA
mA
mA
mA
mA
mW
mW
µA/V
Analog –V Supply Current
Digital +V Supply Current
Power Dissipation
PSRR
+25°C
NOTES
1Measured as an error in ratio of full-scale current to current through RSET (640 µA nominal); ratio is nominally 32. DAC load is virtual ground.
2Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification.
3Internal reference output current defines load conditions applied during Internal Reference Voltage test.
4Full-scale current variations among devices are higher when driving REFERENCE IN directly.
5Frequency at which a 3 dB change in output of DAC is observed; RL = 50 Ω; 100 mV modulation at midscale.
6Based on IFS = 32 (CONTROL AMP IN/RSET) when using internal control amplifier. DAC load is virtual ground.
7Measured as voltage settling at midscale transition to ±0.1%; RL = 50 Ω.
8Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
9Peak glitch impulse is measured as the largest area under a single positive or negative transient.
10Measured with RL = 50 Ω and DAC operating in latched mode.
11Data must remain stable for specified time prior to rising edge of CLOCK.
12Data must remain stable for specified time after rising edge of CLOCK.
13SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
The frequency span is dc-to-Nyquist unless otherwise noted.
14Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at sum and difference frequencies of the two tones.
15Supply voltages should remain stable within ±5% for nominal operation.
Specifications subject to change without notice.
pw
pw
MAX
MIN
CLOCK
DATA
tS
tH
CODE 1
DATA
CODE 2
DATA
CODE 3
DATA
CODE 4
DATA
CODE 2
CODE 4
ANALOG OUTPUT
CODE 1
CODE 3
GLITCH AREA =
1/2 HEIGHT
؋
WIDTH DETAIL OF SETTLING TIME
CLOCK
SPECIFIED
ERROR BAND
H
tPD
ANALOG OUTPUT
W
tST
Figure 1. Timing Diagrams
–3–
REV. A
AD9731
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Test Level Definition
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS to +VS
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to –4 V
Reference Input Voltage Range . . . . . . . . . . . . . . . . 0 V to –VS
Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Internal Reference Output Current . . . . . . . . . . . . . . . 500 µA
Lead Temperature (10 sec Soldering) . . . . . . . . . . . . .+300°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +165°C
Control Amplifier Output Current . . . . . . . . . . . . . ±2.5 mA
I
100% Production Tested.
II
The parameter is 100% production tested at
+25°C; sampled at temperature production.
III
IV
Sample Tested Only.
Parameter is guaranteed by design and character-
ization testing.
V
Parameter is a typical value only.
VI
All devices are 100% production tested at +25°C;
guaranteed by design and characterization testing
for industrial temperature range devices.
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options
Model
AD9731BR
AD9731BRS
AD9731-PCB
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
28-Lead Wide Body (SOIC)
28-Lead Shrink Small (SSOP)
PCB
R-28
RS-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9731 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD9731
PIN FUNCTION DESCRIPTION
Pin Description
Pin #
Pin Name
1
D9(MSB)
D8–D1
Most significant data bit of digital input word.
Eight bits of 10-bit digital input word.
2–9
10
D0(LSB)
CLOCK
NC
Least significant data bit of digital input word.
TTL-compatible edge-triggered latch enable signal for on-board registers.
No internal connection to this pin.
11
12, 13
14
DIGITAL +VS
+5 V supply voltage for digital circuitry.
Converter Ground.
15, 18, 28 GND
16
17
DIGITAL –VS
–5.2 V supply voltage for digital circuitry.
RSET
Connection for external reference set resistor; nominal 1.96 kΩ. Full-scale output current =
32 (Control Amp in V/RSET).
19
20
ANALOG RETURN
IOUT
Analog Return. This point and the reference side of the DAC load resistors should be con-
nected to the same potential (nominally ground).
Analog current output; full-scale current occurs with a digital word input of all “1s.” With
external load resistor, output voltage = IOUT (RLOADʈRINTERNAL). RINTERNAL is nominally
240 Ω.
21
IOUTB
Complementary analog current output; full-scale current occurs with a digital word input
of all “0s.”
22
23
ANALOG –VS
REF IN
Negative analog supply, nominally –5.2 V.
Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current
source network. Voltage changes (noise) at this point have a direct effect on the full-scale
output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/RSET
when using the internal amplifier. DAC load is virtual ground.
)
24
25
CONTROL AMP OUT Normally connected to REF IN (Pin 23). Output of internal control amplifier which pro-
vides a reference for the current switch network.
REF OUT
Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference, nomi-
nally –1.25 V.
26
27
CONTROL AMP IN
DIGITAL –VS
Normally connected to REF Out (Pin 25) if not connected to external reference.
Negative digital supply, nominally –5.2 V.
PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D9(MSB)
D8
GND
DIGITAL –V
S
3
D7
CONTROL AMP IN
REF OUT
4
D6
5
D5
CONTROL AMP OUT
REF IN
6
D4
AD9731
TOP VIEW
(Not to Scale)
7
D3
ANALOG –V
S
8
D2
I
OUTB
9
D1
I
OUT
10
11
12
13
14
D0(LSB)
CLOCK
NC
ANALOG RETURN
GND
R
SET
NC
DIGITAL –V
GND
S
DIGITAL +V
S
NC = NO CONNECT
REV. A
–5–
AD9731–Typical Performance Characteristics
60
55
80
75
70
50
45
40
65
60
55
50
20
18
16
14
12
10
8
6
4
2
10
20
30
40
A
50
60
70
80
I
– mA
– MHz
OUT
OUT
Figure 5. SFDR vs. IOUT (Clock =125 MHz/AOUT = 40 MHz)
Figure 2. Narrowband SFDR (Clock = 170 MHz) vs.
A
OUT Frequency
0.4
0.3
0.2
0.1
0
85
80
75
70
65
–0.1
–0.2
60
55
50
–0.3
–0.4
10
20
30
40
– MHz
50
60
A
OUT
Figure 6. Typical Differential Nonlinearity Performance
(DNL)
Figure 3. Narrowband SFDR (Clock = 125 MHz) vs.
AOUT Frequency
0.6
0.4
0.2
65
60
55
50
45
40
0
–0.2
–0.4
–0.6
10
20
30
40
50
– MHz
60
70
80
90
A
OUT
Figure 7. Typical Integral Nonlinearity Performance (INL)
Figure 4. Wideband SFDR (170 MHz Clock) vs. AOUT
–6–
REV. A
AD9731
1
1
–10
–20
–10
–20
ENCODE = 125MHz
= 2MHz
ENCODE = 125MHz
= 40MHz
A
A
OUT
OUT
SPAN = 62.5MHz
SPAN = 62.5MHz
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
1AP
1AP
1
1
–90
–90
–100
–100
0Hz
START
6.25MHz
62.5MHz
STOP
0Hz
START
6.25MHz
62.5MHz
STOP
Figure 8. Wideband SFDR 2 MHz AOUT; 125 MHz Clock
Figure 11. Wideband SFDR 40 MHz AOUT; 125 MHz Clock
1
–10
0
1
ENCODE = 125MHz
–20
A
= 10MHz
–10
OUT
SPAN = 62.5MHz
–30
–40
–50
–60
–70
–80
–20
–30
–40
–50
–60
–70
1AP
PRN
1AP
1
1
–90
–80
–90
–100
0Hz
START
6.25MHz
62.5MHz
STOP
0Hz
START
8.5MHz
85MHz
STOP
Figure 9. Wideband SFDR 10 MHz AOUT; 125 MHz Clock
Figure 12. Wideband SFDR 65 MHz AOUT; 170 MHz Clock
1
1
–10
–10
ENCODE = 125MHz
ENCODE = 170MHz
–20
A
= 20MHz
A
= 70MHz
–20
OUT
OUT
SPAN = 85MHz
SPAN = 62.5MHz
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
1AP
1AP
1
1
–90
–90
–100
–100
0Hz
START
6.25MHz
62.5MHz
STOP
0Hz
START
8.5MHz
85MHz
STOP
Figure 10. Wideband SFDR 20 MHz AOUT; 125 MHz Clock
Figure 13. Wideband SFDR 70 MHz AOUT; 170 MHz Clock
REV. A
–7–
AD9731
The on-board register is rising-edge triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data setup and hold times as shown in the
timing diagram. Although the AD9731 is designed to provide
isolation of the digital inputs to the analog output, some cou-
pling of digital transitions is inevitable. Digital feedthrough can
be minimized by forming a low-pass filter at the digital input by
using a resistor in series with the capacitance of each digital
input. This common high speed DAC application technique has
the effect of isolating digital input noise from the analog output.
1
–10
–20
ENCODE = 125MHz
A
1 = 800kHz
OUT
A
2 = 900kHz
OUT
–30
–40
–50
–60
SPAN = 2MHz
1AP
1
–70
–80
References
–90
The internal bandgap reference, control amplifier and reference
input are pinned out to provide maximum user flexibility in
configuring the reference circuitry for the AD9731. When using
the internal reference, REF OUT (Pin 25) should be connected
to CONTROL AMP IN (Pin 26). CONTROL AMP OUT (Pin
24) should be connected to REF IN (Pin 23). A 0.1 µF ceramic
capacitor connected from Pin 23 to Analog –VS (Pin 22) im-
proves settling time by decoupling switching noise from the
current sink baseline. A reference current cell provides feedback
to the control amplifier by sinking current through RSET (Pin 17).
–100
0Hz
START
200kHz
2MHz
STOP
Figure 14. Wideband Intermodulation Distortion
F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 2 MHz
1
–10
ENCODE = 125MHz
–20
Full-scale current is determined by CONTROL AMP IN and
A
A
1 = 800kHz
2 = 900kHz
OUT
RSET according to the following equation:
OUT
–30
–40
–50
–60
–70
–80
SPAN = 62.5MHz
1AP
PRN
I
OUT (FS) = 32(CONTROL AMP IN/RSET
)
The internal reference is nominally –1.25 V with a tolerance of
±8% and typical drift over temperature of 100 ppm/°C. If
greater accuracy or temperature stability is required, an external
reference can be used. The AD589 reference features 10 ppm/°C
drift over the 0°C to +70°C temperature range.
1
Two modes of multiplying operation are possible with the
AD9731. Signals with bandwidths up to 2.5 MHz and input
swings from –0.6 V to –1.2 V can be applied to the CONTROL
AMP IN pin as shown in Figure 16. Because the control ampli-
fier is internally compensated, the 0.1 µF capacitor discussed
above can be reduced to maximize the multiplying bandwidth.
However, it should be noted that output settling time, for
changes in the digital word, will be degraded.
–90
–100
0Hz
START
6.25MHz
62.5MHz
STOP
Figure 15. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 62.5 MHz
THEORY AND APPLICATIONS
The AD9731 high speed digital-to-analog converter utilizes
most significant bit decoding and segmentation techniques to
reduce glitch impulse and deliver high dynamic performance
on lower power consumption than previous bipolar DAC
technologies.
AD9731
R
SET
R
SET
CONTROL
AMP IN
The design is based on four main subsections: the decoder/
driver circuits, the edge-triggered data register, the switch net-
work and the control amplifier. An internal bandgap reference is
included to allow operation of the device with minimum exter-
nal support components.
–0.6 TO –1.2V
2.5MHz TYPICAL
R
T
CONTROL
AMP OUT
Digital Inputs/Timing
REFERENCE IN
The AD9731 has TTL/high speed CMOS-compatible single-
ended inputs for data inputs and clock. The switching threshold
is +1.5 V.
0.1F
ANALOG –V
S
In the decoder/driver section, the three MSBs are decoded to
seven “thermometer code” lines. An equalizing delay is included
for the seven least significant bits and the clock signals. This
delay minimizes data skew and data setup and hold times at the
register inputs.
Figure 16. Low Frequency Multiplying Circuit
–8–
REV. A
AD9731
The REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. The analog signal for this mode
of operation must have a signal swing in the range of –3.3 V to
–4.25 V. This can be implemented by capacitively coupling into
An operational amplifier can also be used to perform the I-to-V
conversion of the DAC output. Figure 18 shows an example of a
circuit that uses the AD9617, a high speed, current feedback
amplifier. The resistor values in Figure 18 provide a 4.096 V
swing, centered at ground, at the output of the AD9617 amplifier.
REFERENCE IN a signal with a dc bias of –3.3 V (IOUT
≈
22.5 mA) to –4.25 V (IOUT ≈ 3 mA), as shown in Figure 17, or
by dividing REFERENCE IN with a low impedance op amp
whose signal swing is limited to the stated range.
10k⍀
10k⍀
1/2
AD708
NOTE: When using an external reference, the external refer-
ence voltage must be applied prior to applying –VS.
1/2
AD708
I
FS
R1
200⍀
R2
100⍀
AD9731
R
FB
CONTROL
AMP IN
REF
OUT
R
FF
25⍀
400⍀
I
FS
APPROX
–3.8V
I
±2048V
V
OUT
R
L
25⍀
AD9617
OUT
AD9731
REFERENCE IN
–V
S
I
OUTB
–V
S
25⍀
Figure 17. Wideband Multiplying Circuit
Analog Output
The switch network provides complementary current outputs
OUT and IOUTB. The design of the AD9731 is based on statisti-
cal current source matching, which provides a 10-bit linearity
without trim. Current is steered to either IOUT or IOUTB in pro-
portion to the digital input word. The sum of the two currents is
always equal to the full-scale output current minus 1 LSB. The
current can be converted to a voltage by resistive loading as
shown in the block diagram. Both IOUT and IOUTB should be
equally loaded for best overall performance. The voltage that is
developed is the product of the output current and the value of
the load resistor.
Figure 18. I-to-V Conversion Using a Current Feedback
Amplifier
EVALUATION BOARD
I
The performance characteristics of the AD9731 make it ideally
suited for direct digital synthesis (DDS) and other waveform
synthesis applications. The AD9731 evaluation board provides a
platform for analyzing performance under optimum layout con-
ditions. The AD9731 also provides a reference for high speed
circuit board layout techniques.
REV. A
–9–
AD9731
Figure 19. AD9731-PCB Evaluation Board Schematic
–10–
REV. A
AD9731
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC Wide Body (SOIC)
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
28-Lead Shrink Small Outline (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
1
14
0.07 (1.79)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.066 (1.67)
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
REV. A
–11–
相关型号：
AD9731BRS-REEL
PARALLEL, WORD INPUT LOADING, 0.0038 us SETTLING TIME, 10-BIT DAC, PDSO28, MO-150AH, SSOP-28
ROCHESTER
AD9731BRS-REEL
IC PARALLEL, WORD INPUT LOADING, 0.0038 us SETTLING TIME, 10-BIT DAC, PDSO28, MO-150AH, SSOP-28, Digital to Analog Converter
ADI
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