AD9734-EB [ADI]
10-/12-/14-Bit, 1200 MSPS DACS; 10位/ 12位/ 14位， 1200 MSPS DACS
| 型号： | AD9734-EB |
| 厂家： | 
ADI |
| 描述： | 10-/12-/14-Bit, 1200 MSPS DACS |
| 文件： | 总72页 (文件大小：1077K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-/12-/14-Bit, 1200 MSPS DACS
AD9734/AD9735/AD9736
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Pin-compatible family
DACCLK– DACCLK+
RESET
IRQ
Excellent dynamic performance
S1S2S3
AD9736: SFDR = 82 dBc at fOUT = 30 MHz
AD9736: SFDR = 69 dBc at fOUT = 130 MHz
AD9736: IMD = 87 dBc at fOUT = 30 MHz
AD9736: IMD = 82 dBc at fOUT = 130 MHz
LVDS data interface with on-chip 100 Ω terminations
Built-in self test
SDIO
SDO
CSB
C1
C2
C3
CONTROLLER
SPI
C3
SCLK
DATACLK_OUT+
DATACLK_OUT–
CLOCK
DISTRIBUTION
S3
LVDS sampling integrity
IOUTA
IOUTB
14-, 12-,
2×
DATACLK_IN+
DATACLK_IN–
10-BIT DAC
CORE
LVDS-to-DAC data transfer integrity
Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz)
1.8/3.3 V dual-supply operation
Adjustable analog output
8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω)
On-chip 1.2 V reference
DB[13:0]+
DB[13:0]–
REFERENCE
CURRENT
BAND GAP
C2
S2
C1S1
VREF
I120
160-lead chip scale ball grid array (CSP_BGA) package
Figure 1.
APPLICATIONS
Broadband communications systems
Cellular infrastructure (digital predistortion)
Point-to-point wireless
CMTS/VOD
Instrumentation, automatic test equipment
Radar, avionics
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) features
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.
2. Double data rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
GENERAL DESCRIPTION
3. Direct pin programmability of basic functions or SPI port
access offers complete control of all AD973x family
functions.
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multicarrier generation up to their Nyquist
frequency. The AD9736 is the 14-bit member of the family,
while the AD9735 and the AD9734 are the 12-bit and 10-bit
members, respectively. They include a serial peripheral interface
(SPI) port that provides for programming of many internal
parameters and enables readback of status registers.
4. Manufactured on a CMOS process, the AD973x family
uses a proprietary switching technique that enhances
dynamic performance.
5. The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.
A reduced-specification LVDS interface is utilized to achieve
the high sample rate. The output current can be programmed
over a range of 8.66 mA to 31.66 mA. The AD973x family is
manufactured on a 0.18 μm CMOS process and operates from
1.8 V and 3.3 V supplies for a total power consumption of
380 mW in bypass mode. It is supplied in a 160-lead chip scale
ball grid array for reduced package parasitics.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD9734/AD9735/AD9736
TABLE OF CONTENTS
Features .............................................................................................. 1
Full Scale Current (FSC) Registers (Reg. 2, Reg. 3)............... 31
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 6
AC Specifications.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Location of Supply and Control Pins....................................... 16
Terminology .................................................................................... 17
Typical Performance Characteristics ........................................... 18
AD9736 Static Linearity, 10 mA Full Scale............................. 18
AD9736 Static Linearity, 20 mA Full Scale............................. 19
AD9736 Static Linearity, 30 mA Full Scale............................. 20
LVDS Controller (LVDS_CNT) Registers
(Reg. 4, Reg. 5, Reg. 6)............................................................... 31
SYNC Controller (SYNC_CNT) Registers
(Reg. 7, Reg. 8)............................................................................ 32
Cross Controller (CROS_CNT) Registers
(Reg. 10, Reg. 11)........................................................................ 32
Analog Control (ANA_CNT) Registers
(Reg. 14, Reg. 15)........................................................................ 33
Built-In Self Test Control (BIST_CNT) Registers
(Reg. 17, Reg. 18, Reg. 19, Reg. 20, Reg. 21)........................... 33
Controller Clock Predivider (CCLK_DIV) Reading
Register (Reg. 22) ....................................................................... 34
Theory of Operation ...................................................................... 35
Serial Peripheral Interface............................................................. 36
General Operation of the Serial Interface............................... 36
Short Instruction Mode (8-Bit Instruction) ........................... 36
Long Instruction Mode (16-Bit Instruction).......................... 36
Serial Interface Port Pin Descriptions ..................................... 36
SCLK—Serial Clock............................................................... 36
CSB—Chip Select................................................................... 37
SDIO—Serial Data I/O.......................................................... 37
SDO—Serial Data Out .......................................................... 37
MSB/LSB Transfers .................................................................... 37
Notes on Serial Port Operation ................................................ 37
Pin Mode Operation .................................................................. 38
RESET Operation....................................................................... 38
Programming Sequence ............................................................ 38
Interpolation Filter..................................................................... 39
Data Interface Controllers......................................................... 39
LVDS Sample Logic.................................................................... 40
LVDS Sample Logic Calibration............................................... 40
AD9735 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 21
AD9734 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 22
AD9736 Power Consumption, 20 mA Full Scale....................... 23
AD9736 Dynamic Performance, 20 mA Full Scale................ 24
AD9735, AD9734 Dynamic Performance, 20 mA
Full Scale...................................................................................... 27
AD973x WCDMA ACLR, 20 mA Full Scale .......................... 28
SPI Register Map............................................................................. 29
SPI Register Details ........................................................................ 30
Mode Register (Reg. 0) .............................................................. 30
Interrupt Request Register (IRQ) (Reg. 1).............................. 30
Operating the LVDS Controller in Manual Mode via the
SPI Port........................................................................................ 41
Rev. A | Page 2 of 72
AD9734/AD9735/AD9736
Operating the LVDS Controller in Surveillance and
Auto Mode ...................................................................................41
Mirror Roll-Off Frequency Control .........................................48
Headroom Bits.............................................................................48
Voltage Reference........................................................................48
Applications Information...............................................................50
Driving the DACCLK Input ......................................................50
DAC Output Distortion Sources...................................................51
DC-Coupled DAC Output.............................................................52
DAC Data Sources ..........................................................................53
Input Data Timing ..........................................................................54
Synchronization Timing.................................................................55
Power Supply Sequencing ..............................................................56
AD973X Evaluation Board Schematics ........................................57
AD973X Evaluation Board PCB Layout.......................................62
Outline Dimensions........................................................................69
Ordering Guide ...........................................................................69
SYNC Logic and Controller...........................................................42
SYNC Logic and Controller Operation....................................42
Operation in Manual Mode.......................................................42
Operation in Surveillance and Auto Modes............................42
FIFO Bypass.................................................................................42
Digital Built-In Self Test (BIST) ....................................................44
Overview ......................................................................................44
AD973x BIST Procedure............................................................45
AD973x Expected BIST Signatures ..........................................45
Generating Expected Signatures...............................................46
Cross Controller Registers .............................................................47
Analog Control Registers ...............................................................48
Band Gap Temperature Characteristic Trim Bits ...................48
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................6
Changes to Table 3 ............................................................................8
Inserted Table 5..................................................................................9
Replaced Pin Configuration and Function Descriptions
Section ..............................................................................................10
Changes to Figure 27 to Figure 38 ................................................21
Changes to Figure 40 ......................................................................23
Changes to Table 9 ..........................................................................29
Changes to Figure 103 ....................................................................56
Changes to Figure 105 ....................................................................58
Changes to Figure 107 ....................................................................60
Changes to Figure 108 ....................................................................61
Changes to Figure 115 ....................................................................68
Updated Outline Dimensions........................................................69
Changes to Ordering Guide...........................................................69
4/05—Revision 0: Initial Version
Rev. A | Page 3 of 72
AD9734/AD9735/AD9736
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted.
Table 1.
AD9736
Typ
AD9735
Typ
AD9734
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
RESOLUTION
14
12
10
Bits
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Offset Error
Gain Error (With Internal
Reference)
−5.6
−2.1
1.0
0.6
+5.6
+2.1
−1.5
−0.5
0.50
0.25
+1.5
+0.5
−0.5
−0.1
0.12
0.06
+0.5
+0.1
LSB
LSB
−0.01
0.005
1.0
+0.01
−0.01
0.005
1.0
+0.01
−0.01
0.005
1.0
+0.01
% FSR
% FSR
Gain Error (Without Internal
Reference)
1.0
1.0
1.0
% FSR
Full-Scale Output Current
Output Compliance Range
Output Resistance
Output Capacitance
TEMPERATURE DRIFT
Offset
8.66
−1.0
20.2
31.66
+1.0
8.66
−1.0
20.2
31.66
1.0
8.66
−1.0
20.2
31.66
+1.0
mA
V
MΩ
pF
10
1
10
1
10
1
0
80
40
0
80
40
0
80
40
ppm/°C
ppm/°C
ppm/°C
Gain
Reference Voltage1
REFERENCE
Internal Reference Voltage1
Output Resistance2
ANALOG SUPPLY VOLTAGES
AVDD33
1.14
1.2
5
1.26
1.14
1.2
5
1.26
1.14
1.2
5
1.26
V
kΩ
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
V
V
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
V
V
SUPPLY CURRENTS
1× Mode, 1.2 GSPS
IAVDD33
ICVDD18
IDVDD33
IDVDD18
25
47
10
122
380
25
47
10
122
380
25
47
10
122
380
mA
mA
mA
mA
mW
FIR Bypass (1×) Mode
2× Mode, 1.2 GSPS
IAVDD33
ICVDD18
IDVDD33
25
47
10
234
550
25
47
10
234
550
25
47
10
234
550
mA
mA
mA
mA
mW
IDVDD18
FIR 2× Interpolation Filter
Enabled
Rev. A | Page 4 of 72
AD9734/AD9735/AD9736
AD9736
Typ
AD9735
Typ
AD9734
Typ
Parameter
Static, No Clock
IAVDD33
Min
Max
Min
Max
Min
Max
Unit
25
8
10
2
25
8
10
2
25
8
10
2
mA
mA
mA
mA
mW
ICVDD18
IDVDD33
IDVDD18
FIR Bypass (1×) Mode
133
133
133
Sleep Mode, No Clock
IAVDD33
FIR Bypass (1×) Mode
Power-Down Mode3
IAVDD33
ICVDD18
IDVDD33
IDVDD18
FIR Bypass (1×) Mode
2.5
59
3.15
65
2.5
59
3.15
65
2.5
59
3.15
65
mA
mW
0.01
0.02
0.01
0.01
0.12
0.13
0.12
0.12
0.11
1.24
0.01
0.02
0.01
0.01
0.12
0.13
0.12
0.12
0.11
1.24
0.01
0.02
0.01
0.01
0.12
0.13
0.12
0.12
0.11
1.24
mA
mA
mA
mA
mW
1 Default band gap adjustment (Reg. 0x0E <2:0> = 0x0).
2 Use an external amplifier to drive any external load.
3 Typical wake-up time is 8 μs with recommended 1 nF capacitor on VREF pin.
Rev. A | Page 5 of 72
AD9734/AD9735/AD9736
DIGITAL SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
LVDS DATA INPUT
(DB[13:0]+, DB[13:0]−) DB+ = VIA, DB− = VIB
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate
825
−100
1575
+100
mV
mV
mV
Ω
MSPS
ps
20
80
1200
120
344
LVDS Minimum Data Valid Period (tMDE
)
LVDS CLOCK INPUT
(DATACLK_IN+, DATACLK_IN−) DATACLK_IN+ = VIA, DATACLK_IN− = VIB
Input Voltage Range, VIA or VIB
825
−100
1575
+100
mV
mV
mV
Ω
Input Differential Threshold,1 VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN
Maximum Clock Rate
20
80
600
120
MHz
LVDS CLOCK OUTPUT
(DATACLK_OUT+, DATACLK_ OUT−) DATACLK_OUT+ = Voa, DATACLK_OUT− = Vob 100 Ω Termination
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, Single-Ended, RO
RO Mismatch Between A and B, ΔRO
Change in |VOD| Between 0 and 1, |ΔVOD|
Change in VOS Between 0 and 1, ΔVOS
Output Current—Driver Shorted to Ground, ISA, ISB
Output Current—Drivers Shorted Together, ISAB
Power-Off Output Leakage, |IXA|, |IXB|
Maximum Clock Rate
1375
mV
mV
mV
mV
Ω
1025
150
1150
80
200
100
250
1250
120
10
%
25
mV
mV
mA
mA
mA
MHz
25
20
4
10
600
DAC CLOCK INPUT (CLK+, CLK−)
Input Voltage Range, CLK− or CLK+
Differential Peak-to-Peak Voltage
Common-Mode Voltage
0
800
1600
500
400
300
1200
800
400
mV
mV
MHz
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (fSCLK, 1/tSCLK
Minimum Pulse Width High, tPWH
Minimum Pulse Width Low, tPWL
)
20
MHz
ns
ns
20
20
Minimum SDIO and CSB to SCLK Setup, tDS
Minimum SCLK to SDIO Hold, tDH
10
5
ns
ns
Maximum SCLK to Valid SDIO and SDO, tDV
Minimum SCLK to Invalid SDIO and SDO, tDNV
20
5
ns
ns
Rev. A | Page 6 of 72
AD9734/AD9735/AD9736
Parameter
Min
Typ
Max
Unit
INPUT (SDI, SDIO, SCLK, CSB)
Voltage in High, VIH
Voltage in Low, VIL
Current in High, IIH
Current in Low, IIL
SDIO OUTPUT
2.0
3.3
0
V
V
μA
μA
0.8
+10
+10
−10
−10
Voltage out High, VOH
Voltage out Low, VOL
Current out High, IOH
Current out Low, IOL
2.4
0
3.6
0.4
V
V
mA
mA
4
4
1Refer to the Input Data Timing section for recommended LVDS differential drive levels.
Rev. A | Page 7 of 72
AD9734/AD9735/AD9736
AC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted.
Table 3.
AD9736
Typ
AD9735
Typ
AD9734
Typ
Parameter
Min
Max Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
Maximum Update Rate
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 800 MSPS
1200
1200
1200
MSPS
fOUT = 20 MHz
75
75
75
dBc
fDAC = 1200 MSPS
fOUT = 50 MHz
fOUT = 100 MHz
fOUT = 316 MHz
fOUT = 550 MHz
80
77
63
55
76
74
63
54
76
71
60
53
dBc
dBc
dBc
dBc
TWO-TONE INTERMODULATION
DISTORTION (IMD)
fDAC = 1200 MSPS
fOUT2 = fOUT + 1.25 MHz
fOUT = 40 MHz
fOUT = 50 MHz
fOUT = 100 MHz
88
85
84
70.5
65
84
84
81
67
60
83
83
79
66
60
dBc
dBc
dBc
dBc
dBc
fOUT = 316 MHz
fOUT = 550 MHz
NOISE SPECTRAL DENSITY (NSD)
Single Tone
fDAC = 1200 MSPS
fOUT = 50 MHz
−165
−164
−160.5
−158
−155
−154
−154
−155
−152
−149
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
−162
−161
−159.5
−157
−155
fOUT = 100 MHz
fOUT = 241MHz
fOUT = 316 MHz
fOUT = 550 MHz
Eight-Tone
fDAC = 1200 MSPS, 500 kHz Tone Spacing
fOUT = 50 MHz
fOUT = 100 MHz
fOUT = 241MHz
fOUT = 316 MHz
−158.5
−163.3
−166.5
−166
−165
−164
−162
−163
−163
−161.5
−162
−160
−154
−152
−150.5
−151
−150
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
fOUT = 550 MHz
Rev. A | Page 8 of 72
AD9734/AD9735/AD9736
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may effect
device reliability.
With
Respect to Min
Parameter
AVDD33
DVDD33
DVDD18
CVDD18
AVSS
AVSS
DVSS
CLK+, CLK−
PIN_MODE
DATACLK_IN,
Max
AVSS
DVSS
DVSS
CVSS
DVSS
CVSS
CVSS
CVSS
DVSS
DVSS
−0.3 V
+3.6 V
+3.6 V
+1.98 V
+1.98 V
+0.3 V
+0.3 V
+0.3 V
CVDD18 + 0.18 V
DVDD33 + 0.3 V
DVDD33 + 0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
1
θJA
Unit
DATACLK_OUT
160-Lead Ball, CSP_BGA
31.2
°C/W
LVDS Data Inputs
IOUTA, IOUTB
I120, VREF, IPTAT
IRQ, CSB, SCLK, SDO,
SDIO, RESET
DVSS
AVSS
AVSS
DVSS
−0.3 V
−1.0 V
−0.3 V
−0.3 V
DVDD33 + 0.3 V
AVDD33 + 0.3 V
AVDD33 + 0.3 V
DVDD33 + 0.3 V
1θJA measurement in still air.
JunctionTemperature
StorageTemperature
150°C
+150°C
−65°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Note that this device in its current form does not meet Analog Devices’ standard requirements for ESD as measured against the charged
device model (CDM). As such, special care should be used when handling this product, especially in a manufacturing environment. Analog
Devices will provide a more ESD-hardy product in the near future at which time this warning will be removed from this data sheet.
Rev. A | Page 9 of 72
AD9734/AD9735/AD9736
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
9 10 11 12 13 14
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DACCLK–
DACCLK+
G
H
J
DB13 (MSB)
DB12
K
L
DB11
DB0 (LSB)
M
N
P
Figure 2. AD9736 Digital LVDS Input, Clock I/O (Top View)
Table 6. AD9736 Pin Function Descriptions
Pin No.
Mnemonic
Description
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3
CVDD18
AVSS
1.8 V Clock Supply.
Analog Supply Ground.
A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,
B10, B11, C4, C5, C6, C9, C10, C11, D4, D5,
D6, D9, D10, D11
A7, B7, C7, D7
A8, B8, C8, D8
A12, A13, B12, B13, C12, C13, D12, D13
A14
B14
IOUTB
IOUTA
AVDD33
DNC
DAC Negative Output. 10 mA to 30 mA full-scale output current.
DAC Positive Output. 10 mA to 30 mA full-scale output current.
3.3 V Analog Supply.
Do Not Connect.
Nominal 1.2 V Reference. Tie to analog ground via 10 kΩ resistor to
generate a 120 μA reference current.
I120
C14
VREF
Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF
capacitor; output impedance is approximately 5 kΩ.
D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4
D14
CVSS
IPTAT
Clock Supply Ground.
Factory Test Pin. Output current, proportional to absolute
temperature, is approximately 10 μA at 25°C with a slope of
approximately 20 nA/°C.
E1, F1
DACCLK−/DACCLK+
AVSS
IRQ/UNSIGNED
Negative/Positive DAC Clock Input (DACCLK).
Analog Supply Ground Shield. Tie to AVSS at the DAC.
If PIN_MODE = 0, IRQ: Active low open-drain interrupt request
output, pull up to DVDD33 with 10 kΩ resistor.
E11, E12, F11, F12, G11, G12
E13
If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos
complement input data format, 1 = unsigned.
E14
F13
RESET/PD
CSB/2×
If PIN_MODE = 0, RESET: 1 resets the AD9736.
If PIN_MODE = 1, PD: 1 puts the AD9736 in the power-down state.
See the Serial Peripheral Interface section and the Pin Mode
Operation section for pin description.
F14
G13
G14
SDIO/FIFO
SCLK/FSC0
SDO/FSC1
See the Pin Mode Operation section for pin description.
See the Pin Mode Operation section for pin description.
See the Pin Mode Operation section for pin description.
1.8 V Digital Supply.
H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, DVDD18
J3, J4, J11, J12, J13, J14
Rev. A | Page 10 of 72
AD9734/AD9735/AD9736
Pin No.
Mnemonic
Description
K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6,
L9, L10, L11, L12, M3, M4, M5, M6, M9,
M10, M11, M12
DVSS
Digital Supply Ground.
K13, K14
DB<13>−/DB<13>+
PIN_MODE
Negative/Positive Data Input Bit 13 (MSB). Conforms to IEEE-1596
reduced range link.
0 = SPI Mode. SPI is enabled.
L1
1 = PIN Mode. SPI is disabled; direct pin control.
3.3 V Digital Supply.
Negative/Positive Data Input Bit 12. Conforms to IEEE-1596 reduced
range link.
L7, L8, M7, M8, N7, N8, P7, P8
L13, L14
DVDD33
DB<12>−/DB<12>+
M2, M1
M13, M14
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
N6, P6
DB<0>−/DB<0>+
DB<11>−/DB<11>+
DB<1>−/DB<1>+
DB<2>−/DB<2>+
DB<3>−/DB<3>+
DB<4>−/DB<4>+
DB<5>−/DB<5>+
Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
Negative/Positive Data Input Bit 11. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
DATACLK_OUT−/
DATACLK_OUT+
DATACLK_IN−/
DATACLK_IN+
N9, P9
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
DB<6>−/DB<6>+
Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced
range link.
DB<7>−/DB<7>+
DB<8>−/DB<8>+
DB<9>−/DB<9>+
DB<10>−/DB<10>+
Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced
range link.
Rev. A | Page 11 of 72
AD9734/AD9735/AD9736
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
DACCLK–
DACCLK+
G
H
J
DB11 (MSB)
DB10
K
L
DB9
NC M
N
P
Figure 3. AD9735 Digital LVDS Input, Clock I/O (Top View)
Table 7. AD9735 Pin Function Descriptions
Pin No.
Mnemonic
Description
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3
CVDD18
AVSS
1.8 V Clock Supply.
Analog Supply Ground.
A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,
B10, B11, C4, C5, C6, C9, C10, C11, D4, D5,
D6, D9, D10, D11
A7, B7, C7, D7
A8, B8, C8, D8
A12, A13, B12, B13, C12, C13, D12, D13
A14
B14
IOUTB
IOUTA
AVDD33
DNC
DAC Negative Output. 10 mA to 30 mA full-scale output current.
DAC Positive Output. 10 mA to 30 mA full-scale output current.
3.3 V Analog Supply.
Do Not Connect.
Nominal 1.2 V Reference. Tie to analog ground via 10 kΩ resistor to
generate a 120 μA reference current.
I120
C14
VREF
Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF
capacitor; output impedance approximately 5 kΩ.
D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4
D14
CVSS
IPTAT
Clock Supply Ground.
Factory Test Pin; Output current, proportional to absolute
temperature, is approximately 10 μA at 25°C with a slope of
approximately 20 nA/°C.
E1, F1
DACCLK−/DACCLK+
AVSS
IRQ/UNSIGNED
Negative/Positive DAC Clock Input (DACCLK).
Analog Supply Ground Shield. Tie to AVSS at the DAC.
If PIN_MODE = 0, IRQ: Active low open-drain interrupt request
output, pull up to DVDD33 with 10 kΩ resistor.
E11, E12, F11, F12, G11, G12
E13
If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos
complement input data format, 1 = unsigned.
E14
F13
RESET/PD
CSB/2×
If PIN_MODE = 0, RESET: 1 resets the AD9735.
If PIN_MODE = 1, PD: 1 puts the AD9735 in the power-down state.
See the Serial Peripheral Interface section and the Pin Mode
Operation section for pin description.
F14
G13
G14
SDIO/FIFO
SCLK/FSC0
SDO/FSC1
See the Pin Mode Operation section for pin description.
See the Pin Mode Operation section for pin description.
See the Pin Mode Operation section for pin description.
1.8 V Digital Supply.
H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, DVDD18
J3, J4, J11, J12, J13, J14
K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6,
L9, L10, L11, L12, M3, M4, M5, M6, M9,
M10, M11, M12
DVSS
Digital Supply Ground.
Rev. A | Page 12 of 72
AD9734/AD9735/AD9736
Pin No.
Mnemonic
Description
K13, K14
DB<11>−/DB<11>+
Negative/Positive Data Input Bit 11 (MSB). Conforms to IEEE-1596
reduced range link.
L1
PIN_MODE
0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI disabled; direct pin control.
3.3 V Digital Supply.
Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced
range link.
L7, L8, M7, M8, N7, N8, P7, P8
L13, L14
DVDD33
DB<10>−/DB<10>+
M1, M2
NC
No Connect.
M13, M14
DB<9>−/DB<9>+
Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced
range link.
N1, P1
N2, P2
NC
No Connect.
DB<0>−/DB<0>+
Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
N3, P3
N4, P4
N5, P5
N6, P6
DB<1>−/DB<1>+
DB<2>−/DB<2>+
DB<3>−/DB<3>+
Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
DATACLK_OUT−/
DATACLK_OUT+
DATACLK_IN−/
DATACLK_IN+
N9, P9
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
DB<4>−/DB<4>+
Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
DB<5>−/DB<5>+
DB<6>−/DB<6>+
DB<7>−/DB<7>+
DB<8>−/DB<8>+
Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
Rev. A | Page 13 of 72
AD9734/AD9735/AD9736
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
DACCLK–
DACCLK+
G
H
J
DB9 (MSB)
DB8
K
L
DB7
NC
M
N
P
Figure 4. AD9734 Digital LVDS Input, Clock I/O (Top View)
Table 8. AD9734 Pin Function Descriptions
Pin No.
Mnemonic
Description
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3
CVDD18
AVSS
1.8 V Clock Supply.
Analog Supply Ground.
A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,
B10, B11, C4, C5, C6, C9, C10, C11, D4, D5,
D6, D9, D10, D11
A7, B7, C7, D7
A8, B8, C8, D8
A12, A13, B12, B13, C12, C13, D12, D13
A14
B14
IOUTB
IOUTA
AVDD33
DNC
DAC Negative Output. 10 mA to 30 mA full-scale output current.
DAC Positive Output. 10 mA to 30 mA full-scale output current.
3.3 V Analog Supply.
Do Not Connect.
Nominal 1.2 V Reference. Tie to analog ground via 10 kΩ resistor to
generate a 120 μA reference current.
I120
C14
VREF
Band Gap Voltage Reference I/O. Tie to analog ground via 1 nF
capacitor; output impedance approximately 5 kΩ.
D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4
D14
CVSS
IPTAT
Clock Supply Ground.
Factory Test Pin. Output current, proportional to absolute
temperature, is approximately 10 μA at 25°C with a slope of
approximately 20 nA/°C.
E1, F1
DACCLK−/DACCLK+
AVSS
IRQ/UNSIGNED
Negative/Positive DAC Clock Input (DACCLK).
Analog Supply Ground Shield. Tie to AVSS at the DAC.
If PIN_MODE = 0, IRQ: Active low open-drain interrupt request
output, pull up to DVDD33 with 10 kΩ resistor.
E11, E12, F11, F12, G11, G12
E13
If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = twos
complement input data format, 1 = unsigned.
E14
F13
RESET/PD
CSB/2×
If PIN_MODE = 0, RESET: 1 resets the AD9734.
If PIN_MODE = 1, PD: 1 puts the AD9734 in the power-down state.
See the Serial Peripheral Interface section and the Pin Mode
Operation section for pin description.
F14
G13
G14
SDIO/FIFO
SCLK/FSC0
SDO/FSC1
See the Pin Mode Operation section for pin description.
See the Pin Mode Operation section for pin description.
See the Pin Mode Operation section for pin description.
1.8 V Digital Supply.
H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, DVDD18
J3, J4, J11, J12, J13, J14
K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6,
L9, L10, L11, L12, M3, M4, M5, M6, M9,
M10, M11, M12
DVSS
Digital Supply Ground.
Rev. A | Page 14 of 72
AD9734/AD9735/AD9736
Pin No.
Mnemonic
Description
K13, K14
DB<9>−/DB<9>+
Negative/Positive Data Input Bit 9 (MSB). Conforms to IEEE-1596
reduced range link.
L1
PIN_MODE
0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI is disabled; direct pin control.
3.3 V Digital Supply.
Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
L7, L8, M7, M8, N7, N8, P7, P8
L13, L14
DVDD33
DB<8>−/DB<8>+
M1, M2
NC
No Connect.
M13, M14
DB<7>−/DB<7>+
Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
N1, P1
N2, P2
N3, P3
N4, P4
NC
NC
NC
No Connect.
No Connect.
No Connect.
DB<0>−/DB<0>+
Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
N5, P5
N6, P6
DB<1>−/DB<1>+
Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
DATACLK_OUT−/
DATACLK_OUT+
DATACLK_IN−/
DATACLK_IN+
N9, P9
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
DB<2>−/DB<2>+
Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
DB<3>−/DB<3>+
DB<4>−/DB<4>+
DB<5>−/DB<5>+
DB<6>−/DB<6>+
Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
Rev. A | Page 15 of 72
AD9734/AD9735/AD9736
LOCATION OF SUPPLY AND CONTROL PINS
1
2
3
4
5
6
7
8
9
10 11 12 13 14
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
M
N
P
AVDD33, 3.3V, ANALOG SUPPLY
DVDD18, 1.8V DIGITAL SUPPLY
DVDD33, 3.3V DIGITAL SUPPLY
DVSS DIGITAL SUPPLY GROUND
AVSS, ANALOG SUPPLY GROUND
AVSS, ANALOG SUPPLY GROUND SHIELD
Figure 7. Digital Supply Pins (Top View)
Figure 5. Analog Supply Pins (Top View)
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
I120
VREF
IPTAT
PIN_MODE = 0,
SPI ENABLED
G
H
J
IRQ
RESET
SDIO
SDO
CSB
K
L
G
H
J
SCLK
M
N
P
PIN_MODE = 1,
SPI DISABLED
K
L
PIN_MODE
UNSIGNED
2×
PD
M
N
P
FIFO
FSC1
FSC0
CVDD18, 1.8V CLOCK SUPPLY
CVSS, CLOCK SUPPLY GROUND
Figure 8. Analog I/O and SPI Control Pins (Top View)
Figure 6. Clock Supply Pins (Top View)
Rev. A | Page 16 of 72
AD9734/AD9735/AD9736
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
The maximum deviation of the actual analog output from the
ideal output, determined by a straight line drawn from zero to
full scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (DNL)
Settling Time
The measure of the variation in analog value, normalized to full
scale, associated with a 1 LSB change in digital input code.
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Offset Error
The deviation of the output current from the ideal of zero. For
IOUTA, 0 mA output is expected when the inputs are all 0s. For
IOUTB, 0 mA output is expected when all inputs are set to 1s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal. It is expressed as
a percentage or in decibels (dB).
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
Temperature Drift
Specified as the maximum change from the ambient (25°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR) per
°C. For reference drift, the drift is reported in ppm per °C.
Rev. A | Page 17 of 72
AD9734/AD9735/AD9736
TYPICAL PERFORMANCE CHARACTERISTICS
AD9736 STATIC LINEARITY, 10 mA FULL SCALE
1.00
1.0
0.8
0.75
0.50
0.6
0.25
0.4
0
0.2
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
0
2048
2048
2048
4096
6144
8192 10240 12288 14336 16384
CODE
0
0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 9. AD9736 INL, −40°C, 10 mA FS
Figure 12. AD9736 DNL, −40°C, 10 mA FS
1.00
0.75
1.0
0.8
0.50
0.6
0.25
0.4
0
0.2
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
0
–0.2
–0.4
–0.6
–0.8
–1.0
4096
6144
8192 10240 12288 14336 16384
CODE
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 10. AD9736 INL, 25°C, 10 mA FS
Figure 13. AD9736 DNL, 25°C, 10 mA FS
1.00
0.75
1.0
0.8
0.50
0.6
0.25
0.4
0
0.2
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
0
–0.2
–0.4
–0.6
–0.8
–1.0
4096
6144
8192 10240 12288 14336 16384
CODE
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 11. AD9736 INL, 85°C, 10 mA FS
Figure 14. AD9736 DNL, 85°C, 10 mA FS
Rev. A | Page 18 of 72
AD9734/AD9735/AD9736
AD9736 STATIC LINEARITY, 20 mA FULL SCALE
1.0
0.6
0.5
0.8
0.6
0.4
0.4
0.3
0.2
0.2
0
0.1
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0
0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
0
0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 15. AD9736 INL, −40°C, 20 mA FS
Figure 18. AD9736 DNL, −40°C, 20 mA FS
1.0
0.8
0.6
0.5
0.6
0.4
0.4
0.3
0.2
0.2
0
0.1
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 16. AD9736 INL, 25°C, 20 mA FS
Figure 19. AD9736 DNL, 25°C, 20 mA FS
1.0
0.8
0.6
0.5
0.6
0.4
0.4
0.3
0.2
0.2
0
0.1
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 17. AD9736 INL, 85°C, 20 mA FS
Figure 20. AD9736 DNL, 85°C, 20 mA FS
Rev. A | Page 19 of 72
AD9734/AD9735/AD9736
AD9736 STATIC LINEARITY, 30 mA FULL SCALE
2.0
0.6
0.5
1.5
1.0
0.4
0.3
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.5
–1.0
–1.5
–2.0
0
0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
0
0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 21. AD9736 INL, −40°C, 30 mA FS
Figure 24. AD9736 DNL, −40°C, 30 mA FS
2.0
1.5
0.6
0.5
0.4
1.0
0.3
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.5
–1.0
–1.5
–2.0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 22. AD9736 INL, 25°C, 30 mA FS
Figure 25. AD9736 DNL, 25°C, 30 mA FS
2.0
1.5
1.0
0.5
0
1.0
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
0
–0.5
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 23. AD9736 INL, 85°C, 30 mA FS
Figure 26. AD9736 DNL, 85°C, 30 mA FS
Rev. A | Page 20 of 72
AD9734/AD9735/AD9736
AD9735 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE
0.4
0.100
0.050
0
0.3
0.2
–0.050
–0.100
–0.150
–0.200
–0.250
0.1
0
–0.1
–0.2
0
0
0
512
512
512
1024
1536
2048
2560
3072
3584
3584
3584
4096
4096
4096
0
0
0
512
1024
1536
2048
2560
3072
3584
3584
3584
4096
4096
4096
CODE
CODE
Figure 27. AD9735 INL, 25°C, 10 mA FS
Figure 30. AD9735 DNL, 25°C, 10 mA FS
0.15
0.10
0.05
0
0.100
0.075
0.050
0.025
0
–0.025
–0.050
–0.075
–0.100
–0.125
–0.05
–0.10
–0.15
–0.20
1024
1536
2048
2560
3072
512
1024
1536
2048
2560
3072
CODE
CODE
Figure 28. AD9735 INL, 25°C, 20 mA FS
Figure 31. AD9735 DNL, 25°C, 20 mA FS
0.2
0.1
0.050
0
–0.050
–1.000
–1.150
–0.200
–0.250
–0.300
–0.350
–0.400
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
1024
1536
2048
2560
3072
512
1024
1536
2048
2560
3072
CODE
CODE
Figure 29. AD9735 INL, 25°C, 30 mA FS
Figure 32. AD9735 DNL, 25°C, 30 mA FS
Rev. A | Page 21 of 72
AD9734/AD9735/AD9736
AD9734 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE
0.06
0.04
0.02
0
0.04
0.03
0.02
0.01
0
–0.02
–0.04
–0.06
–0.01
–0.02
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 36. AD9734 DNL, 25°C, 10 mA FS
Figure 33. AD9734 INL, 25°C, 10 mA FS
0.03
0.02
0.01
0
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.01
–0.02
–0.03
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 37. AD9734 DNL, 25°C, 20 mA FS
Figure 34. AD9734 INL, 25°C, 20 mA FS
0.01
0
0.06
0.04
0.02
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 38. AD9734 DNL, 25°C, 30 mA FS
Figure 35. AD9734 INL, 25°C, 30 mA FS
Rev. A | Page 22 of 72
AD9734/AD9735/AD9736
AD9736 POWER CONSUMPTION, 20 mA FULL SCALE
0.50
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.45
TOTAL
0.40
TOTAL
0.35
0.30
0.25
DVDD18
CVDD18
0.20
DVDD18
0.15
AVDD33
1000
0.10
0.05
0
DVDD33
AVDD33
CVDD18
DVDD33
1250
0
250
500
750
1500
0
250
500
750
1000
1250
1500
fDAC (MHz)
fDAC (MHz)
Figure 40. AD9736, 2× Interpolation Mode Power vs. fDAC at 25°C
Figure 39. AD9736 1× Mode Power vs. fDAC at 25°C
Rev. A | Page 23 of 72
AD9734/AD9735/AD9736
AD9736 DYNAMIC PERFORMANCE, 20 mA FULL SCALE
80
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
75
70
800MSPS
65
60
1.2GSPS
1GSPS
55
50
0
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
0
50 100 150 200 250 300 350 400 450 500 550
fOUT (MHz)
Figure 41. AD9736 SFDR vs. fOUT over fDAC at 25°C
Figure 44. AD9736 IMD vs. fOUT over 50 Parts, 25°C,1.2 GSPS
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
1GSPS
800MSPS
1.2GSPS
+85°C
–40°C
+25°C
0
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
0
100
200
300
400
500
600
fOUT (MHz)
Figure 42. AD9736 SFDR vs. fOUT over Temperature
Figure 45. AD9736 IMD vs. fOUT over fDAC at 25°C
90
85
80
75
70
65
60
55
50
78
76
74
72
70
68
66
64
62
60
58
56
54
52
–40°C
+85°C
+25°C
0
50 100 150 200 250 300 350 400 450 500 550
fOUT (MHz)
0
100
200
300
400
500
600
fOUT (MHz)
Figure 43. AD9736 SFDR vs. fOUT over 50 Parts, 25°C, 1.2 GSPS
Figure 46. AD9736 IMD vs. fOUT over Temperature, 1.2 GSPS
Rev. A | Page 24 of 72
AD9734/AD9735/AD9736
95
90
85
80
75
70
65
60
55
90
85
80
75
70
65
60
55
50
IMD
0dBFS
SFDR
–6dBFS
–12dBFS
0
10
100
0
100
200
300
400
500
600
fOUT (MHz)
fOUT (MHz)
Figure 50. AD9736 IMD vs. fOUT over AOUT, 25°C, 1.2 GSPS
Figure 47. AD9736 Low Frequency IMD and SFDR vs. fOUT, 25°C, 1.2 GSPS
90
90
85
80
75
70
65
60
55
50
THIRD-ORDER IMD
85
SFDR_2×
SFDR
80
75
70
65
60
55
50
SFDR_1×
0
50
100
150
200
250
300
350
0
50
100
150
200
250
300
350
fOUT (MHz)
fOUT (MHz)
Figure 51. AD9736 SFDR vs. fOUT, 25°C, 1.2 GSPS, 1× and 2× Interpolation
Figure 48. AD9736 IMD and SFDR vs. fOUT, 25°C, 1.2 GSPS, 2× Interpolation
90
80
75
THIRD-ORDER IMD_1×
85
80
70
65
60
55
50
45
40
–12dBFS
THIRD-ORDER IMD_2×
75
0dBFS
70
65
60
55
50
–6dBFS
0
50
100
150
200
250
300
350
0
100
200
300
fOUT (MHz)
400
500
600
fOUT (MHz)
Figure 49. AD9736 SFDR vs. fOUT over AOUT, 25°C, 1.2 GSPS
Figure 52. AD9736 IMD vs. fOUT, 25°C, 1.2 GSPS, 1× and 2× Interpolation
Rev. A | Page 25 of 72
AD9734/AD9735/AD9736
–150
–152
–154
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
–156
1GSPS
–158
–160
–162
–164
–166
–168
–170
1.2GSPS
+85°C
–40°C
+25°C
0
100
200
300
400
500
600
0
100
200
300
400
500
600
fOUT (MHz)
fOUT (MHz)
Figure 56. AD9736 8-Tone NSD vs. fOUT over Temperature, 1.2 GSPS
Figure 53. AD9736 1-Tone NSD vs. fOUT over fDAC, 25°C
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
–157
–158
–159
–160
–161
–162
–163
–164
–165
–166
+85°C
–40°C
+25°C
0
50 100 150 200 250 300 350 400 450 500 550
fOUT (MHz)
0
100
200
300
400
500
600
fOUT (MHz)
Figure 54. AD9736 1-Tone NSD vs. fOUT over Temperature, 1.2 GSPS
Figure 57. AD9736 1-Tone NSD vs. fOUT over 50 Parts, 1.2 GSPS, 25°C
–150
–152
–154
–156
–158
–160
–161
–162
–163
–164
–165
–166
–167
–162
1GSPS
–164
1.2GSPS
–166
–168
–170
0
100
200
300
400
500
600
0
50 100 150 200 250 300 350 400 450 500 550
fOUT (MHz)
fOUT (MHz)
Figure 55. AD9736 8-Tone NSD vs. fOUT over fDAC, 25°C
Figure 58. AD9736 8-Tone NSD vs. fOUT over 50 Parts, 1.2 GSPS, 25°C
Rev. A | Page 26 of 72
AD9734/AD9735/AD9736
AD9735, AD9734 DYNAMIC PERFORMANCE, 20 mA FULL SCALE
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
1GSPS
800MSPS
800MSPS
1.2GSPS
1GSPS
1.2GSPS
0
0
0
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
0
0
0
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
Figure 59. AD9735 SFDR vs. fOUT over fDAC, 1.2 GSPS
Figure 62. AD9734 IMD vs. fOUT over fDAC, 1.2 GSPS
80
75
70
65
60
55
50
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
1 TONE
800MSPS
1GSPS
8 TONES
1.2GSPS
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
Figure 60. AD9734 SFDR vs. fOUT over fDAC, 1.2 GSPS
Figure 63. AD9735 NSD vs. fOUT, 1.2 GSPS
90
85
80
75
70
65
60
55
50
–145
–147
–149
–151
–153
–155
–157
–159
–161
1GSPS
8 TONES
800MSPS
1 TONE
1.2GSPS
–163
–165
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
50 100 150 200 250 300 350 400 450 500 550 600
fOUT (MHz)
Figure 64. AD9734 NSD vs. fOUT, 1.2 GSPS
Figure 61. AD9735 IMD vs. fOUT over fDAC, 1.2 GSPS
Rev. A | Page 27 of 72
AD9734/AD9735/AD9736
AD973x WCDMA ACLR, 20 mA FULL SCALE
REF –22.75dBm
#AVG
LOG 10dB/
#ATTEN 6dB
PAVG
10
VBW 300kHz
SPAN 33.88MHz
SWEEP 109.9ms (601pts)
W1
S2
CENTER 134.83MHz
#RES BW 30kHz
LOWER
UPPER
RMS RESULTS
CARRIER POWER
–10.72dBm/
OFFSET FREQ
5.00MHz
REF BW
dBc
dBm
dBc
dBm
3.840MHz
3.840MHz
3.884MHz
–81.65
–82.06
–82.11
–92.37
–92.78
–92.83
–81.39
–82.43
–82.39
–92.11
–93.16
–93.11
10.0MHz
3.84000MHz
15.0MHz
Figure 65. AD9736 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS
REF –22.75dBm
#AVG
LOG 10dB/
#ATTEN 6dB
PAVG
VBW 300kHz
SPAN 33.88MHz
SWEEP 109.9ms (601pts)
10 S2
CENTER 134.83MHz
#RES BW 30kHz
LOWER
UPPER
RMS RESULTS
CARRIER POWER
–10.72dBm/
OFFSET FREQ
5.00MHz
REF BW
dBc
dBm
dBc
dBm
3.840MHz
3.840MHz
3.884MHz
–80.32
–81.13
–80.43
–91.10
–91.91
–91.21
–80.60
–80.75
–81.36
–91.38
–91.53
–92.13
10.0MHz
3.84000MHz
15.0MHz
Figure 66. AD9735 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS
REF –22.75dBm
#AVG
LOG 10dB/
#ATTEN 6dB
PAVG
VBW 300kHz
SPAN 33.88MHz
SWEEP 109.9ms (601pts)
10 S2
CENTER 134.83MHz
#RES BW 30kHz
LOWER
UPPER
RMS RESULTS
CARRIER POWER
–10.76dBm/
OFFSET FREQ
5.00MHz
REF BW
dBc
dBm
dBc
dBm
3.840MHz
3.840MHz
3.884MHz
–71.07
–70.55
–70.79
–81.83
–81.31
–81.56
–71.23
–71.42
–71.25
–81.99
–82.19
–82.01
10.0MHz
3.84000MHz
15.0MHz
Figure 67. AD9734 WCDMA Carrier at 134.83 MHz, fDAC = 491.52 MSPS
Rev. A | Page 28 of 72
AD9734/AD9735/AD9736
SPI REGISTER MAP
Write 0 to unspecified or reserved bit locations. Reading these bits returns unknown values.
Table 9. SPI Register Map
Reg. Addr.
Default Pin Mode
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Hex)
00
(Hex)
00
Dec.
0
Hex.
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
MODE
SDIO_DIR
LVDS
LSBFIRST
SYNC
RESET
CROSS
LONG_INS
RESERVED
2X MODE
IE_LVDS
FIFO MODE
IE_SYNC
DATAFRMT
IE_CROSS
FSC<9>
PD
1
IRQ
RESERVED
FSC<8>
FSC<0>
MHD<0>
CHECK
00
00
2
FSC_1
SLEEP
02
02
3
FSC_2
FSC<7>
MSD<3>
SD<3>
LSURV
FSC<6>
MSD<2>
SD<2>
FSC<5>
FSC<4>
FSC<3>
MHD<3>
LCHANGE
LFLT<1>
VALID
FSC<2>
MHD<2>
ERR_HI
FSC<1>
00
00
4
LVDS_CNT1
LVDS_CNT2
LVDS_CNT3
SYNC_CNT1
SYNC_CNT2
RESERVED
CROS_CNT1
CROS_CNT2
RESERVED
RESERVED
ANA_CNT1
ANA_CNT2
RESERVED
BIST_CNT
BIST<7:0>
BIST<15:8>
BIST<23:16>
BIST<31:24>
CCLK_DIV
MSD<1>
SD<1>
MSD<0>
SD<0>
MHD<1>
ERR_LO
00
00
5
00
00
6
LAUTO
LFLT<3>
FIFOSTAT1
SFLT<3>
LFLT<2>
FIFOSTAT0
SFLT<2>
LFLT<0>
SCHANGE
SFLT<0>
LTRH<1>
PHOF<1>
RESERVED
LTRH<0>
PHOF<0>
STRH<0>
00
00
7
FIFOSTAT3
SSURV
FIFOSTAT2
SAUTO
00
00
8
SFLT<1>
00
00
9
10
11
12
13
14
15
16
17
18
19
20
21
22
UPDEL<5>
DNDEL<5>
UPDEL<4>
DNDEL<4>
UPDEL<3>
DNDEL<3>
UPDEL<2>
DNDEL<2>
UPDEL<1>
DNDEL<1>
UPDEL<0>
DNDEL<0>
00
00
00
00
MSEL<1>
MSEL<0>
TRMBG<2>
HDRM<2>
TRMBG<1>
HDRM<1>
TRMBG<0>
HDRM<0>
C0
CA
C0
CA
HDRM<7>
HDRM<6>
HDRM<5>
SIG_READ
HDRM<4>
RESERVED
HDRM<3>
SEL<1>
SEL<0>
LVDS_EN
SYNC_EN
CLEAR
00
00
RESERVED
RESERVED
RESERVED
CCD<3>
CCD<2>
CCD<1>
CCD<0>
00
00
Rev. A | Page 29 of 72
AD9734/AD9735/AD9736
SPI REGISTER DETAILS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Reset value for write registers
in bold text.
MODE REGISTER (REG. 0)
ADDR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
MODE
SDIO_DIR
LSB/MSB
RESET
LONG_INS
2× MODE
FIFO MODE
DATAFRMT
PD
Table 10. Mode Register Bit Descriptions
Bit Name
Read/Write
Description
SDIO_DIR
WRITE
0, input only per SPI standard.
1, bidirectional per SPI standard.
LSB/MSB
WRITE
0, MSB first per SPI standard.
1, LSB first per SPI standard.
NOTE: Only change LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit
order errors.
RESET
WRITE
WRITE
0, execute software reset of SPI and controllers, reload default register values except Registers 0x00
and 0x04.
1, set software reset, write 0 on the next (or any following) cycle to release the reset.
LONG_INS
0, short (single-byte) instruction word.
1, long (two-byte) instruction word, not necessary since the maximum internal address is REG31
(0x1F).
2×_MODE
FIFO_MODE
DATAFRMT
PD
WRITE
WRITE
WRITE
WRITE
0, disable 2× interpolation filter.
1, enable 2× interpolation filter.
0, disable FIFO synchronization.
1, enable FIFO synchronization.
0, signed input DATA with midscale = 0x0000.
1, unsigned input DATA with midscale = 0x2000.
0, enable LVDS Receiver, DAC, and clock circuitry.
1, power down LVDS Receiver, DAC, and clock circuitry.
INTERRUPT REQUEST REGISTER (IRQ) (REG. 1)
ADDR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x01
IRQ
LVDS
SYNC
CROSS
RESERVED IE_LVDS
IE_SYNC
IE_CROSS
RESERVED
Table 11. Interrupt Register Bit Descriptions
Bit Name
Read/Write
Description
LVDS
WRITE
Don’t care.
READ
0, no active LVDS receiver interrupt.
1, interrupt in LVDS receiver occurred.
SYNC
WRITE
READ
Don’t care.
0, no active SYNC logic interrupt.
1, interrupt in SYNC logic occurred.
CROSS
WRITE
READ
Don’t care.
0, no active CROSS logic interrupt.
1, interrupt in CROSS logic occurred.
IE_LVDS
IE_SYNC
IE_CROSS
WRITE
WRITE
WRITE
0, reset LVDS receiver interrupt and disable future LVDS receiver interrupts.
1, enable LVDS receiver interrupt to activate IRQ pin.
0, reset SYNC logic interrupt and disable future SYNC logic interrupts.
1, enable SYNC logic interrupt to activate IRQ pin.
0, reset CROSS logic interrupt and disable future CROSS logic interrupts.
1, enable CROSS logic interrupt to activate IRQ pin.
Rev. A | Page 30 of 72
AD9734/AD9735/AD9736
FULL SCALE CURRENT (FSC) REGISTERS (REG. 2, REG. 3)
ADDR
Name
FSC_1
FSC_2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x02
SLEEP
FSC<7>
–
–
–
–
–
FSC<9>
FSC<1>
FSC<8>
FSC<0>
0x03
FSC<6>
FSC<5>
FSC<4>
FSC<3>
FSC<2>
Table 12. Full Scale Current Output Register Bit Descriptions
Bit Name
Read/Write
Description
SLEEP
WRITE
0, enable DAC output.
1, set DAC output current to 0 mA.
FSC<9:0>
WRITE
0x000, 10 mA full-scale output current.
0x200, 20 mA full-scale output current.
0x3FF, 30 mA full-scale output current.
LVDS CONTROLLER (LVDS_CNT) REGISTERS (REG. 4, REG. 5, REG. 6)
ADDR
0x04
0x05
0x06
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDS_CNT1
LVDS_CNT2
LVDS_CNT3
MSD<3>
SD<3>
LSURV
MSD<2>
SD<2>
LAUTO
MSD<1>
SD<1>
LFLT<3>
MSD<0>
SD<0>
LFLT<2>
MHD<3>
LCHANGE
LFLT<1>
MHD<2>
ERR_HI
LFLT<0>
MHD<1>
ERR_LO
LTRH<1>
MHD<0>
CHECK
LTRH<0>
Table 13. LVDS Controller Register Bit Descriptions
Bit Name
Read/Write Description
MSD<3:0>
WRITE
READ
0x0, set setup delay for the measurement system.
If ( LAUTO = 1), the latest measured value for the setup delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
MHD<3:0>
SD<3:0>
WRITE
READ
0x0, set hold delay for the measurement system.
If ( LAUTO = 1), the latest measured value for the hold delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
WRITE
READ
0x0, set sample delay.
If ( LAUTO = 1), the result of a measurement cycle is stored in this register.
If ( LAUTO = 0), readback of the last SPI write to this bit.
LCHANGE
READ
0, no change from previous measurement.
1, change in value from the previous measurement.
NOTE: The average filter and the threshold detection are not applied to this bit.
ERR_HI
ERR_LO
CHECK
READ
READ
READ
One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduced link specification.
One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link specification.
0, phase measurement—sampling in the previous or following DATA cycle.
1, phase measurement—sampling in the correct DATA cycle.
LSURV
LAUTO
WRITE
WRITE
0, the controller stops after completion of the current measurement cycle.
1, continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the
threshold value.
0, sample delay is not automatically updated.
1, continuously starts measurement cycles and updates the sample delay according to the measurement.
NOTE: LSURV (Reg. 6, Bit 7) must be set to 1 and the LVDS IRQ (Reg. 1, Bit 3) must be set to 0 for AUTO mode.
LFLT<3:0>
LTRH<2:0>
WRITE
WRITE
0x0, average filter length, Delay = Delay + Delta Delay/2^ LFLT <3:0>, values greater than 12 (0x0C) are
clipped to 12.
000, set auto update threshold values.
Rev. A | Page 31 of 72
AD9734/AD9735/AD9736
SYNC CONTROLLER (SYNC_CNT) REGISTERS (REG. 7, REG. 8)
ADDR Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x07
0x08
SYNC_CNT1
SYNC_CNT2
FIFOSTAT3
SSURV
FIFOSTAT2
SAUTO
FIFOSTAT1
SFLT<3>
FIFOSTAT0
SFLT<2>
VALID
SFLT<1>
SCHANGE
SFLT<0>
PHOF<1>
RESERVED
PHOF<0>
STRH<0>
Table 14. Sync Controller Register Bit Descriptions
Bit Name
Read/Write Description
FIFOSTAT<2:0> READ
Position of FIFO read counter ranges from 0 to 7.
FIFOSTAT<3>
READ
READ
READ
0, SYNC logic OK.
1, error in SYNC logic.
VALID
0, FIFOSTAT<3:0> is not valid yet.
1, FIFOSTAT<3:0> is valid after a reset.
SCHANGE
0, no change in FIFOSTAT<3:0>.
1, FIFOSTAT<3:0> has changed since the previous measurement cycle when SSURV = 1 (surveillance mode
active).
PHOF<1:0>
WRITE
READ
00, change the readout counter.
Current setting of the readout counter (PHOF<1:0>) in surveillance mode (SSURV = 1) after an interrupt.
Current calculated optimal readout counter value in AUTO mode (SAUTO = 1).
SSURV
SAUTO
WRITE
WRITE
0, the controller stops after completion of the current measurement cycle.
1, continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the
threshold value.
0, readout counter (PHOF<3:0>) is not automatically updated.
1, continuously starts measurement cycles and updates the readout counter according to the
measurement.
NOTE: SSURV (Reg. 8, Bit 7) must be set to 1 and the SYNC IRQ (Reg. 1, Bit 2) must be set to 0 for AUTO
mode.
SFLT<3:0>
STRH<0>
WRITE
WRITE
0x0, average filter length, FIFOSTAT = FIFOSTAT + Delta FIFOSTAT/2 ^ SFLT<3:0>; values greater than 12
(0x0C) are clipped to 12.
0, if FIFOSTAT<2:0> = 0 or 7, a sync interrupt is generated.
1, if FIFOSTAT<2:0> = 0, 1, 6 or 7, a sync interrupt is generated.
CROSS CONTROLLER (CROS_CNT) REGISTERS (REG. 10, REG. 11)
ADDR
0x0A
0x0B
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CROS_CNT1
CROS_CNT2
–
–
–
UPDEL<5> UPDEL<4> UPDEL<3> UPDEL<2>
DNDEL<5> DNDEL<4> DNDEL<3> DNDEL<2>
UPDEL<1>
UPDEL<0>
–
DNDEL<1> DNDEL<0>
Table 15. Cross Controller Register Description
Bit Name
Read/Write Description
UPDEL<5:0>
DNDEL<5:0>
WRITE
WRITE
0x00, move the differential output stage switching point up, set to 0 if DNDEL is non-zero.
0x00, move the differential output stage switching point down, set to 0 if UPDEL is non-zero.
Rev. A | Page 32 of 72
AD9734/AD9735/AD9736
ANALOG CONTROL (ANA_CNT) REGISTERS (REG. 14, REG. 15)
ADDR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0E
ANA_CNT1
ANA_CNT2
MSEL<1>
MSEL<0>
–
–
–
TRMBG<2> TRMBG<1> TRMBG<0>
0x0F
HDRM<7> HDRM<6>
HDRM<5> HDRM<4> HDRM<3> HDRM<2>
HDRM<1>
HDRM<0>
Table 16. Analog Control Register Bit Descriptions
Bit Name
Read/Write
Description
MSEL<1:0>
WRITE
00, mirror roll off frequency control = bypass.
01, mirror roll off frequency control = narrowest bandwidth.
10, mirror roll off frequency control = medium bandwidth.
11, mirror roll off frequency control = widest bandwidth.
NOTE: See the plot in the Analog Control Registers section.
TRMBG<2:0>
HDRM<7:0>
WRITE
WRITE
000, band gap temperature characteristic trim.
NOTE: See the plot in the Analog Control Registers section.
0xCA, output stack headroom control.
HDRM<7:4> set reference offset from AVDD33 (VCAS centering).
HDRM<3:0> set overdrive (current density) trim (temperature tracking).
Note: Set to 0xCA for optimum performance.
BUILT-IN SELF TEST CONTROL (BIST_CNT) REGISTERS (REG. 17, REG. 18, REG. 19, REG. 20, REG. 21)
ADDR Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x11
0x12
0x13
0x14
0x15
BIST_CNT
SEL<1>
BIST<7>
BIST<15>
SEL<0>
BIST<6>
BIST<14>
BIST<22>
BIST<30>
SIG_READ
BIST<5>
BIST<13>
BIST<21>
BIST<29>
–
–
LVDS_EN
BIST<2>
SYNC_EN
BIST<1>
BIST<9>
BIST<17>
BIST<25>
CLEAR
BIST<7:0>
BIST<4>
BIST<3>
BIST<0>
BIST<8>
BIST<16>
BIST<24>
BIST<15:8>
BIST<12>
BIST<20>
BIST<28>
BIST<11> BIST<10>
BIST<19> BIST<18>
BIST<27> BIST<26>
BIST<23:16> BIST<23>
BIST<31:24> BIST<31>
Table 17. BIST Control Register Bit Descriptions
Bit Name
Read/Write
Description
SEL<1:0>
WRITE
00, write result of the LVDS Phase 1 BIST to BIST<31:0>.
01, write result of the LVDS Phase 2 BIST to BIST<31:0>.
10, write result of the SYNC Phase 1 BIST to BIST<31:0>.
11, write result of the SYNC Phase 2 BIST to BIST<31:0>.
SIG_READ
LVDS_EN
SYNC_EN
CLEAR
WRITE
WRITE
WRITE
WRITE
READ
0, no action.
1, enable BIST signature readback.
0, no action.
1, enable LVDS BIST.
0, no action.
1, enable SYNC BIST.
0, no action.
1, clear all BIST registers.
BIST<31:0>
Results of the built-in self test.
Rev. A | Page 33 of 72
AD9734/AD9735/AD9736
CONTROLLER CLOCK PREDIVIDER (CCLK_DIV) READING REGISTER (REG. 22)
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x16
CCLK_DIV
RESERVED RESERVED RESERVED RESERVED CCD<3>
CCD<2>
CCD<1>
CCD<0>
Table 18. Controller Clock Predivider Register Bit Descriptions
Bit Name
Read/Write Description
CCD<3:0>
WRITE
0x0, controller clock = DACCLK/16.
0x1, controller clock = DACCLK/32.
0x2, controller clock = DACCLK/64 …
0xF, controller clock = DACCLK/524288.
NOTE: The 100 MHz to 1.2 GHz DACCLK must be divided to less than 10 MHz for correct operation. CCD<3:0>
must be programmed to divide the DACCLK so that this relationship is not violated. Controller clock =
DACCLK/(2 ^ ( CCD<3:0> + 4 )).
Rev. A | Page 34 of 72
AD9734/AD9735/AD9736
THEORY OF OPERATION
The AD9736, AD9735, and AD9734 are 14-bit, 12-bit, and
10-bit DACs that run at an update rate up to 1.2 GSPS. Input
data can be accepted up to the full 1.2 GSPS rate, or a 2×
interpolation filter can be enabled (2× mode) allowing full
speed operation with a 600 MSPS input data rate. The DATA
and DATACLK_IN inputs are parallel LVDS, meeting the IEEE
reduced swing LVDS specifications with the exception of input
hysteresis. The DATACLK_IN input runs at one-half the input
DATA rate in a double data rate (DDR) format. Each edge of
DATACLK_IN transfers DATA into the AD9736, as shown in
Figure 79.
The LVDS controller locates the data transitions and delays the
DATACLK_IN so that its transition is in the center of the valid
data window. The sync controller manages the FIFO that moves
data from the LVDS DATACLK_IN domain to the DACCLK
domain.
Both controllers can operate in manual mode under external
processor control, in surveillance mode where error conditions
generate external interrupts, or in automatic mode where errors
are automatically corrected.
The LVDS and sync controllers include moving average filtering
for noise immunity and variable thresholds to control activity.
Normally, the controllers are set to run in automatic mode,
making any necessary adjustments without dropping or dupli-
cating samples sent to the DAC. Both controllers require initial
calibration prior to entering automatic update mode.
The DACCLK−/DACCLK+ inputs (Pin E1 and Pin F1) directly
drive the DAC core to minimize clock jitter. The DACCLK
signal is also divided by 2 (1× and 2× mode), then output as the
DATACLK_OUT. The DATACLK_OUT signal clocks the data
source. The DAC expects DDR LVDS data (DB<13:0>) aligned
with the DDR input clock (DATACLK_IN) from a circuit simi-
lar to the one shown in Figure 96. Table 19 shows the clock
relationships.
The AD973x analog output changes 35 DACCLK cycles after
the input data changes in 1× mode with the FIFO disabled. The
FIFO adds up to eight additional cycles of delay. This delay is
read from the SPI port. Internal clock delay variation is less
than a single DACCLK cycle at 1.2 GHz (833 ps).
Table 19. AD973x Clock Relationship
MODE DACCLK DATACLK_OUT DATACLK_IN DATA
1×
2×
1.2 GHz
1.2 GHz
600 MHz
600 MHz
600 MHz
300 MHz
1.2 GSPS
600 MSPS
Stopping the AD973x DATACLK_IN while the DACCLK is still
running can lead to unpredictable output signals. This occurs
because the internal digital signal path is interleaved. The last
two samples clocked into the DAC continue to be clocked out
by DACCLK even after DATACLK_IN has stopped. The result-
ing output signal is at a frequency of one-half fDAC, and the
amplitude depends on the difference between the last two
samples.
Maintaining correct alignment of data and clock is a common
challenge with high speed DACs, complicated by changes in
temperature and other operating conditions. Using the
DATACLK_OUT signal to generate the data allows most of the
internal process, temperature, and voltage delay variation to be
cancelled. The AD973x further simplifies this high speed data
capture problem with two adaptive closed-loop timing
controllers.
Control of the AD973x functions is via the serially programmed
registers listed in Table 9. Optionally, a limited number of func-
tions can be directly set by external pins in pin mode.
One timing controller manages the LVDS data and data clock
alignment (LVDS controller), and the other manages the LVDS
data and DACCLK alignment (sync controller).
Rev. A | Page 35 of 72
AD9734/AD9735/AD9736
SERIAL PERIPHERAL INTERFACE
The AD973x serial port is a flexible, synchronous serial
communications port, allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer
formats, including both the Motorola SPI® and Intel® SSR
protocols. The interface allows read/write access to all registers
that configure the AD973x. Single- or multiple-byte transfers
are supported, as well as most significant bit first (MSB-first) or
least significant bit first (LSB-first) transfer formats. The
AD973x serial interface port can be configured as a single pin
I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO).
SHORT INSTRUCTION MODE (8-BIT INSTRUCTION)
The short instruction byte is shown in the following table:
MSB
I7
LSB
I0
I6
I5
I4
I3
I2
I1
R/W
N1
N0
A4
A3
A2
A1
A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation. N1, N0, Bit 6, and Bit 5 of the instruction byte
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in Table 20.
SDO (PIN G14)
A4, A3, A2, A1, A0, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte, determine which register is accessed during
the data transfer portion of the communications cycle. For
multibyte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD973x,
based on the LSBFIRST bit (Reg. 0, Bit 6).
SDIO (PIN F14)
AD973x
SPI PORT
SCLK (PIN G13)
CSB (PIN F13)
Figure 68. AD973x SPI Port
The AD973x can optionally be configured via external pins
rather than the serial interface. When the PIN_MODE input
(Pin L1) is high, the serial interface is disabled and its pins are
reassigned for direct control of the DAC. Specific functionality
is described in the Pin Mode Operation section.
Table 20. Byte Transfer Count
N1
N2
Description
0
0
1
1
0
1
0
1
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD973x. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD973x, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD973x serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD973x.
LONG INSTRUCTION MODE (16-BIT INSTRUCTION)
The long instruction bytes are shown in the following table:
MSB
I15
R/W
I7
LSB
I8
I14
N1
I6
I13
N0
I5
I12
A12
I4
I11
A11
I3
I10
A10
I2
I9
A9
I1
A8
I0
A7
A6
A5
A4
A3
A2
A1
A0
If LONG_INS = 1 (Reg. 0, Bit 4), the instruction byte is
extended to 2 bytes where the second byte provides an
additional 8 bits of address information. Address 0x00 to
Address 0x1F are equivalent in short and long instruction
The remaining SCLK edges are for Phase 2 of the communica-
tion cycle. Phase 2 is the actual data transfer between the
AD973x and the system controller. Phase 2 of the communica-
tion cycle is a transfer of 1, 2, 3, or 4 data bytes as determined
by the instruction byte. Using one multibyte transfer is the
preferred method. Single-byte data transfers are useful to
reduce CPU overhead when register access requires one byte
only. Registers change immediately upon writing to the last bit
of each transfer byte.
modes. The AD973x does not use any addresses greater than 31
(0x1F), so always set LONG_INS = 0.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD973x and to run the internal state machines. The maximum
frequency of SCLK is 20 MHz. All data input to the AD973x is
registered on the rising edge of SCLK. All data is driven out of
the AD973x on the rising edge of SCLK.
CSB (Chip Select) can be raised after each sequence of 8 bits
(except the last byte) to stall the bus. The serial transfer resumes
when CSB is lowered. Stalling on nonbyte boundaries resets
the SPI.
Rev. A | Page 36 of 72
AD9734/AD9735/AD9736
CSB—Chip Select
For multibyte transfers, writing to this register can occur during
the middle of the communication cycle. Care must be taken to
compensate for this new configuration for the remaining bytes
of the current communication cycle. The same considerations
apply to setting the software reset, RESET (Reg. 0, Bit 5). All
registers are set to their default values except Reg. 0 and Reg. 4,
which remain unchanged.
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
SDIO—Serial Data I/O
Use of only single-byte transfers when changing serial port
configurations or initiating a software reset is highly
recommended. In the event of unexpected programming
sequences, the AD973x SPI can become inaccessible. For
example, if user code inadvertently changes the LONG_INS bit
or the LSBFIRST bit, the following bits experience unexpected
results. The SPI can be returned to a known state by writing an
incomplete byte (1 to 7 bits) of all 0s followed by 3 bytes of
0x00. This returns to MSB-first short instructions
Data is always written into the AD973x on this pin. However,
this pin can be used as a bidirectional data line. The configu-
ration of this pin is controlled by SDIO_DIR at Reg. 0, Bit 7.
The default is Logic 0, which configures the SDIO pin as
unidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD973x operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
(Reg. 0 = 0x00), so the device can be reinitialized.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
MSB/LSB TRANSFERS
The AD973x serial port can support both MSB-first or LSB-first
data formats. This functionality is controlled by LSBFIRST at
Reg. 0, Bit 6. The default is MSB first (LSBFIRST = 0).
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5
D3 D2 D1 D0
0 0 0 0
N
N
N
Figure 69. Serial Register Interface Timing, MSB-First Write
When LSBFIRST = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least
significant bit. Multibyte data transfers in MSB-first format start
with an instruction byte that includes the register address of the
most significant data byte. Subsequent data bytes should follow
in order from high address to low address. In MSB-first mode,
the serial port internal byte address generator decrements for
each data byte of the multibyte communication cycle.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
R/W N1 N0 A4 A3 A2 A1 A0
D7
D6 D5
D3 D2 D1 D0
0 0 0 0
N
N
D6 D5
N
D3 D2 D1 D0
0 0 0 0
N
D7
When LSBFIRST = 1 (LSB first), the instruction and data bytes
must be written from least significant bit to most significant bit.
Multibyte data transfers in LSB-first format start with an
instruction byte that includes the register address of the least
significant data byte followed by multiple data bytes. The serial
port internal byte address generator increments for each byte of
the multibyte communication cycle.
Figure 70. Serial Register Interface Timing, MSB-First Read
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2
D4 D5 D6 D7
N N N N
0
0
0
The AD973x serial port controller data address decrements
from the data address written toward 0x00 for multibyte I/O
operations if the MSB-first mode is active. The serial port
controller address increments from the data address written
toward 0x1F for multibyte I/O operations if the LSB-first mode
is active.
Figure 71. Serial Register Interface Timing, LSB-First Write
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
NOTES ON SERIAL PORT OPERATION
A0 A1 A2 A3 A4 N0 N1 R/W
D0
D1 D2
0
D4 D5 D6 D7
N N N N
0
The AD973x serial port configuration is controlled by Reg. 0,
Bit 4, Bit 5, Bit 6, and Bit 7. Note that the configuration changes
immediately upon writing to the last bit of the register.
D1 D2
D4 D5 D6 D7
N N N N
0
0
D0
Figure 72. Serial Register Interface Timing, LSB-First Read
Rev. A | Page 37 of 72
AD9734/AD9735/AD9736
tDS
Table 22. PIN_MODE Input Functions
tSCLK
Mnemonic
Function
CSB
UNSIGNED
0, twos complement input data format
1, unsigned input data format
0, interpolation disabled
1, interpolation = 2× enabled
00, sleep mode
tPWH
tPWL
SCLK
SDIO
2×
tDS
tDH
INSTRUCTION BIT 7
FSC1, FSC0
INSTRUCTION BIT 6
01, 10 mA full-scale output current
10, 20 mA full-scale output current
11, 30 mA full-scale output current
0, chip enabled
Figure 73. Timing Diagram for SPI Register Write
CSB
PD
SCLK
1, chip in power-down state
0, input FIFO disabled
1, input FIFO enabled
FIFO
t
DNV
t
DV
I1
I0
D7
D6
D5
SDIO
Care must be taken when using PIN_MODE because only the
control bits shown in Table 22 can be changed. If the remaining
register default values are not suitable for the desired operation,
PIN_MODE cannot be used. If the FIFO is enabled, the
controller clock must be less than 10 MHz. This limits the DAC
clock to 160 MHz.
Figure 74. Timing Diagram for SPI Register Read
After the last instruction bit is written to the SDIO pin, the
driving signal must be set to a high impedance in time for the
bus to turn around. The serial output data from the AD973x is
enabled by the falling edge of SCLK. This causes the first output
data bit to be shorter than the remaining data bits, as shown in
Figure 74.
RESET OPERATION
The RESET pin forces all SPI register contents to their default
values (see Table 9), which places the DAC in a known state.
The software reset bit forces all SPI register contents, except
Reg. 0 and Reg. 4, to their default values.
To assure proper reading of data, read the SDIO or SDO pin
prior to changing the SCLK from low to high. Due to the more
complex multibyte protocol, multiple AD973x devices cannot
be daisy-chained on the SPI bus. Multiple DACs should be
controlled by independent CSB signals.
The internal reset signal is derived from a logical OR operation
on the RESET pin state and from the software reset state. This
internal reset signal drives all SPI registers to their default
values, except Reg. 0 and Reg. 4, which are unaffected. The data
registers are not affected by either reset.
PIN MODE OPERATION
When the PIN_MODE input (Pin L1) is set high, the SPI port is
disabled. The SPI port pins are remapped, as shown in Table 21.
The function of these pins is described in Table 22. The remain-
ing PIN_MODE register settings are shown in Table 9.
The software reset is asserted by writing 1 to Reg. 0, Bit 5. It
may be cleared on the next SPI write cycle or a later write cycle.
Table 21. SPI_MODE vs. PIN_MODE Inputs
PROGRAMMING SEQUENCE
Pin Number
PIN_MODE = 0
PIN_MODE = 1
The AD973x registers should be programmed in this order:
E13
F13
G13
E14
F14
G14
IRQ
CSB
SCLK
RESET
SDIO
UNSIGNED
2×
FSC0
PD
FIFO
FSC1
1.
2.
3.
4.
5.
6.
7.
Reset hardware.
Make changes to SPI port configuration, if necessary.
Input format, if unsigned.
Interpolation, if in 2× mode.
Calibrate and set the LVDS controller.
Enable the FIFO.
SDO
Calibrate and set the sync controller.
Step 1 through Step 4 are required, while Step 5 through Step 7
are optional. The LVDS controller can help assure proper data
reception in the DAC with changes in temperature and voltage.
The sync controller manages the FIFO to assure proper transfer
of the received data to the DAC core with changes in
temperature and voltage. The DAC is intended to operate with
both controllers active unless data and clock alignment is
managed externally.
Rev. A | Page 38 of 72
AD9734/AD9735/AD9736
0.10
0.08
0.06
0.04
0.02
0
INTERPOLATION FILTER
In 2× mode, the input data is interpolated by a factor of 2 so
that it aligns with the DAC update rate. The interpolation filter
is a hard-coded, 55-tap, symmetric FIR with a 0.001 dB pass-
band flatness and a stop-band attenuation of about 90 dB. The
transition band runs from 20% of fDAC to 30% of fDAC. The FIR
response is shown in Figure 75 where the frequency axis is
normalized to fDAC. Figure 76 shows the pass-band flatness and
Table 23 shows the 16-bit filter coefficients.
–0.02
–0.04
–0.06
–0.08
–0.10
Table 23. FIR Interpolation Filter Coefficients
Coefficient Number Coefficient Number Tap Weight
0
0.05
0.10
0.15
0.20
0.25
1
2
3
4
5
6
7
8
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
−7
0
+24
0
−62
0
+135
0
−263
0
+471
0
−793
0
+1273
0
−1976
0
+3012
0
−4603
0
FREQUENCY NORMALIZED TO fDAC
Figure 76. Interpolation Filter Pass-Band Flatness
DATA INTERFACE CONTROLLERS
Two internal controllers are utilized in the operation of the
AD973x. The first controller helps maintain optimum LVDS
data sampling; the second controller helps maintain optimum
synchronization between the DACCLK and the incoming data.
The LVDS controller is responsible for optimizing the sampling
of the data from the LVDS bus (DB13:0), while the sync
controller resolves timing problems between the DAC_CLK
(CLK+, CLK−) and the DATACLK. A block diagram of these
controllers is shown in Figure 77.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DATACLK
DATACLK_OUT
CLK
CONTROL
DATACLK_IN
DATA
LVDS
SYNC
CONTROLLER
SOURCE
CONTROLLER
i.e., FPGA
SYNC
LOGIC
LVDS
SAMPLE
LOGIC
+7321
0
−13270
0
+41505
+65535
DB<13:0>
FIFO
DAC
Figure 77. Data Controllers
The controllers are clocked with a divided-down version of the
DAC_CLK. The divide ratio is set utilizing the controller clock
predivider bits (CCD<3:0>) located at Reg. 22, Bits 3:0 to
generate the controller clock as follows:
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Controller Clock = DAC_CLK/(2(CCD<3:0> + 4))
Note that the controller clock cannot exceed 10 MHz for correct
operation. Until CCD<3:0> is properly programmed to meet
this requirement, the DAC output may not be stable. This
means the FIFO cannot be enabled in PIN_MODE unless the
DACCLK is less than 160 MHz.
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY NORMALIZED TO fDAC
Figure 75. Interpolation Filter Response
Rev. A | Page 39 of 72
AD9734/AD9735/AD9736
DBU
DBL
The LVDS and sync controllers are independently operated in
three modes via SPI port Reg. 6 and Reg. 8:
FF
FF
D1
D2
LVDS
RX
DB<13:0>
•
•
•
Manual mode
Surveillance mode
Auto mode
DATA SAMPLING
SIGNAL
DELAYED
CLOCK
SIGNAL
SD<3:0>
SAMPLE DELAY
In manual mode, all of the timing measurements and updates
are externally controlled via the SPI.
LVDS
RX
DATACLK_IN
MSD<3:0>
DELAY
FF
CHECK
In surveillance mode, each controller takes measurements and
calculates a new optimal value continuously. The result of the
measurement is passed through an averaging filter before
evaluating the results for increased noise immunity. The filtered
result is compared to a threshold value set via Reg. 6 and Reg. 8
of the SPI port. If the error is greater than the threshold, an
interrupt is triggered and the controller stops.
CLOCK
SAMPLING
SIGNAL
MSD<3:0>
DELAY
Figure 78. Internal LVDS Data Sampling Logic
CLK TO DB SKEW
DB13:0
SAMPLE
Reg. 1 of the SPI port controls the interrupts with Bit 3 and Bit 2
enabling the respective interrupts and Bit 7 and Bit 6 indicating
the respective controller interrupt. If an interrupt is enabled, it
also activates the AD973x IRQ pin. To clear an interrupt, the
interrupt enable bit of the respective controller must be set to 0
for at least 1 controller clock cycle (controller clock <10 MHz).
DELAY
DATACLK_IN
PROP DELAY
TO LATCH
DATA SAMPLING
SIGNAL (DSS)
PROP DELAY
TO LATCH
D1
D2
Auto mode is almost identical to surveillance mode. Instead
of triggering an interrupt and stopping the controller, the
controller automatically updates its settings to the newly
calculated optimal value and continues to run.
Figure 79. Internal LVDS Data Sampling Logic Timing
LVDS SAMPLE LOGIC CALIBRATION
The internal DSS delay must be calibrated to optimize the data
sample timing. Once calibrated, the AD973x generates an IRQ
or automatically corrects its timing if temperature or voltage
variations change the timing too much. This calibration is done
using the delayed clock sampling signal (CSS) to sample the
delayed clock signal (DCS). The LVDS sampling logic finds the
edges of the DATACLK_IN signal and, from this measurement,
the center of the valid data window is located.
LVDS SAMPLE LOGIC
A simplified diagram of the AD973x LVDS data sampling
engine is shown in Figure 78 and the timing diagram is shown
in Figure 79.
The incoming LVDS data is latched by the data sampling signal
(DSS), which is derived from DATACLK_IN. The LVDS
controller delays DATACLK_IN to create the data sampling
signal (DSS), which is adjusted to sample the LVDS data in the
center of the valid data window. The skew between the
DATACLK_IN and the LVDS data bits (DB<13:0>) must be
minimal for proper operation. Therefore, it is recommended
that the DATACLK_IN be generated in the same manner as the
LVDS data bits (DB<13:0>) with the same driver and data lines
(that is, it should just be another LVDS data bit running a
constant 01010101… sequence, as shown in Figure 96).
The internal delay line that derives the delayed DSS from
DATACLK_IN is controlled by SD3:0 (Reg. 5, Bits 7:4), while
the DCS is controlled by MSD3:0 (Reg. 4, Bits 7:4), and the CSS
is controlled by MHD3:0 (Reg. 4, Bits 3:0).
DATACLK_IN transitions must be time aligned with the LVDS
data (DB<13:0>) transitions. This allows the CSS, derived from
the DATACLK_IN, to find the valid data window of DB<13:0>
by locating the DATACLK_IN edges. The latching (rising) edge
of CSS is initially placed using Bits SD<3:0> and can then be
shifted to the left using MSD<3:0> and to the right using
MHD<3:0>. When CSS samples the DCS and the result is 1
(which can be read back via the check bit at Reg. 5, Bit 0), the
sampling occurs in the correct data cycle.
If the DATACLK_IN signal is stopped, the DACCLK continues
to generate an output signal based on the last two values
clocked into the registers that drive D1 and D2, as shown in
Figure 78. If these two registers are not equal, a large output at a
frequency of one-half fDAC can be generated at the DAC output.
Rev. A | Page 40 of 72
AD9734/AD9735/AD9736
To find the leading edge of the data cycle, increment the
measured setup delay until the check bit goes low. To find the
trailing edge, increment the measured hold delay (MHD) until
check goes low. Always set MHD = 0 when incrementing MSD
and vice versa.
SETUP TIME (tS
)
HOLD TIME (tH)
DB<13:0>
DATACLK_IN
SAMPLE DELAY SD<3:0>
CSS SAMPLE DCS
The incremental units of SD, MSD, and MHD are in units of real
time, not fractions of a clock cycle. The nominal step size is 80 ps.
MSD<3:0> = 0 1 2 3 4 5
CSS WITH
MHD<3:0> = 0
DSC DELAYED
= 0
BY MSD<3:0>
OPERATING THE LVDS CONTROLLER IN
MANUAL MODE VIA THE SPI PORT
CHECK = 1 1 1 1 1 0
CHECK = 1
The manual operation of the LVDS controller allows the user to
step through both the setup and hold delays to calculate the
optimal sampling delay (that is, the center of the data eye).
Figure 81. Hold Delay Measurement
OPERATING THE LVDS CONTROLLER IN
SURVEILLANCE AND AUTO MODE
With SD<3:0> and MHD<3:0> set to 0, increment the setup time
delay (MSD<3:0>, Reg. 4, Bits 7:4) until the check bit (Reg. 5,
Bit 0) goes low and record this value. This locates the leading
DATACLK_IN (and data) transition, as shown in Figure 80.
In surveillance mode, the controller searches for the edges of
the data eye in the same manner as in the manual mode of
operation and triggers an interrupt if the clock sampling signal
(CSS) has moved more than the threshold value set by
LTRH<1:0> (Reg. 6, Bits 1:0).
With SD<3:0> and MSD<3:0> set to 0, increment the hold time
delay (MHD<3:0>, Reg. 4, Bits 3:0) until the check bit (Reg. 5,
Bit 0) goes low and record this value. This locates the trailing
DATACLK_IN (and DB<13:0>) transition, as shown in Figure
81.
There is an internal filter that averages the setup and hold time
measurements to filter out noise and glitches on the clock lines.
Average Value = (MHD – MSD)/2
New Average = Average Value + (ꢀ Average/2 ^ LFLT<3:0>)
Once both DATACLK_IN edges are located, the sample delay
(SD<3:0>, Reg. 5, Bits 7:4) must be updated by
Sample Delay = (MHD − MSD)/2
If an accumulating error in the average value causes it to exceed
the threshold value (LTHR<1:0>), an interrupt is issued.
After updating SD<3:0>, verify that the sampling signal is in the
middle of the valid data window by adjusting both MHD and
MSD with the new sample delay until the check bit goes low.
The new MHD and MSD values should be equal to or within
one unit delay if SD<3:0> was set correctly.
The maximum allowable value for LFLT<3:0> is 12. If
LFLT<3:0> is too small, clock jitter and noise can cause erratic
behavior. In most cases, LFLT can be set to the maximum value.
In surveillance mode, the ideal sampling point should first be
found using manual mode and then applied to the sample delay
registers. Set the threshold and filter values depending on how
far the CSS signal is allowed to drift before an interrupt occurs.
Then, set the surveillance bit high (Reg. 6, Bit 7) and monitor
the interrupt signal either via the SPI port (Reg. 1, Bit 7) or the
IRQ pin.
MHD and MSD may not be equal to or within one unit delay if
the external clock jitter and noise exceeds the internal delay
resolution. Differences of 2, 3, or more are possible and can
require more filtering to provide stable operation.
The sample delay calibration should be performed prior to
enabling surveillance mode or auto mode.
In auto mode, follow the same steps to set up the sample delay,
threshold, and filter length. To run the controller in auto mode,
both the LAUTO (Reg. 6, Bit 6) and LSURV (Reg. 6, Bit 7) bits
need to be set to 1. In auto mode, the LVDS interrupt should be
set low (Reg. 1, Bit 3) to allow the sample delay to be automati-
cally updated if the threshold value is exceeded.
SETUP TIME (tS
)
DB<13:0>
DATACLK_IN
SAMPLE DELAY SD<3:0>
CSS SAMPLE DCS
CSS WITH
MHD<3:0> = 0
MSD<3:0> = 0 1 2 3 4 5
DSC DELAYED
BY MSD<3:0>
CHECK = 1
Figure 80. Setup Delay Measurement
Rev. A | Page 41 of 72
AD9734/AD9735/AD9736
SYNC LOGIC AND CONTROLLER
A FIFO structure is utilized to synchronize the data transfer
between the DACCLK and the DATACLK_IN clock domains.
The sync controller writes data from DB<13:0> into an 8-word
memory register based on a cyclic write counter clocked by the
DSS, which is a delayed version of DACCLK_IN. The data is
read out of the memory based on a second cyclic read counter
clocked by DACCLK. The 8-word FIFO shown in Figure 82
provides sufficient margin to maintain proper timing under
most conditions. The sync logic is designed to prevent the read
and write pointers from crossing. If the timing drifts far enough
to require an update of the phase offset (PHOF<1:0>), two
samples are duplicated or dropped. Figure 83 shows the timing
diagram for the sync logic.
OPERATION IN MANUAL MODE
To start operating the DAC in manual mode, allow DACCLK
and DATACLK_IN to stabilize, then enable FIFO mode (Reg. 0,
Bit 2). Read FIFOSTAT<2:0> (Reg. 7, Bits 6:4) to determine if
adjustment is needed. For example, if FIFOSTAT<2:0> = 6, the
timing is not yet critical, but it is not optimal.
To return to an optimal state (FIFOSTAT<2:0> = 4), the
PHOF<1:0> (Reg. 7, Bits 1:0) needs to be set to 1. Setting
PHOF<1:0> = 1 effectively increments the read pointer by 2.
This causes the write pointer value to be captured two clocks
later, decreasing FIFOSTAT<2:0> from 6 to 4.
OPERATION IN SURVEILLANCE AND AUTO MODES
M0
8 WORD
Once FIFOSTAT<2:0> is manually placed in an optimal state,
the AD973x sync logic can run in surveillance or auto mode. To
start, turn on surveillance mode by setting SSURV = 1 (Reg. 8,
Bit 7), then enable the sync interrupt (Reg. 1, Bit 2).
MEMORY
DAC<13:0>
DAC<13:0>
If STRH<0> = 0 (Reg. 8, Bit 0), an interrupt occurs if
FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (Reg. 8, Bit 0), an
interrupt occurs if FIFOSTAT<2:0> = 0, 1, 6, or 7. The interrupt
is read at Reg. 1, Bit 6 at the AD973x IRQ pin.
M7
ZD
FF
FIFOSTAT<2:0>
PHOF<1:0>
DACCLK
ADDER
WRITE
COUNTER
DSS
To enter auto mode, complete the preceding steps then set
SAUTO = 1 (Reg. 8, Bit 6). Next, set the sync interrupt = 0
(Reg. 1, Bit 2), to allow the phase offset (PHOF<1:0>) to be
automatically updated if FIFOSTAT<2:0> violates the threshold
value. The FIFOSTAT signal is filtered to improve noise
immunity and reduce unnecessary phase offset updates. The
filter operates with the following algorithm:
READ
COUNTER
Figure 82. Sync Logic Block Diagram
SYNC LOGIC AND CONTROLLER OPERATION
The relationship between the readout pointer and the write
pointer initially is unknown because the startup relationship
between DACCLK and DATACLK_IN is unknown. The sync
logic measures the relative phase between the two counters with
the zero detect block and the flip-flop in Figure 82. The relative
phase is returned in FIFOSTAT<2:0> (Reg. 7, Bits 6:4), and sync
logic errors are indicated by FIFOSTAT<3> (Reg. 7, Bit 7). If
FIFOSTAT<2:0> returns a value of 0 or 7, the memory is
sampling in a critical state (read and write pointers are close to
crossing).
FIFOSTAT = FIFOSTAT + ΔFIFOSTAT/2 ^ SFLT<3:0>
where:
0 ≤ SFLT<3:0> ≤ 12
Values greater than 12 are set to 12. If SFLT<3:0> is too small,
clock jitter and noise can cause erratic behavior. Normally, SFLT
can be set to the maximum value.
FIFO BYPASS
If the FIFOSTAT<2:0> returns a value of 3 or 4, the memory is
sampling at the optimal state (read and write pointers are
farthest apart). If FIFOSTAT<2:0> returns a critical value, the
pointer can be adjusted with the phase offset PHOF<1:0> (Reg.
7, Bits 1:0). Due to the architecture of the FIFO, the phase offset
can only adjust the read pointer in steps of 2.
When the FIFO_MODE bit (Reg. 1, Bit 2) is set to 0, the FIFO
is bypassed with a mux. When the FIFO is enabled, the pipeline
delay through the AD973x increases by the delta between the
FIFO read pointer and write pointer plus 4 more clock periods.
Rev. A | Page 42 of 72
AD9734/AD9735/AD9736
DACCLK
INTERNAL DELAY
EXTERNAL DELAY
DATACLK_OUT
DATACLK_IN
DATA_IN
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
SAMPLE_HOLD
SAMPLE_SETUP
SAMPLE_DELAY
DSS1
D1
O
Q
A
C
G
I
M
E
K
DSS2
D2
B
D
F
H
J
L
N
P
WRITE_PTR1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
SAFE ZONE
A
ERROR ZONE
I
M0
M1
M2
M3
B
J
C
DATA 'A' CAN BE
FIFOSTAT IS SET
EQUAL TO THE
WRITE POINTER
EACH TIME THE
READ POINTER
CHANGES FROM
7 TO 0.
D
SAFELY READ FROM
THE FIFO IN THE
SAFE ZONE. IN THE
ERROR ZONE, THE
POINTERS MAY
BRIEFLY OVERLAP
DUE TO CLOCK JITTER
OR NOISE.
M4
M5
M6
M7
E
F
G
H
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
READ_PTR1
FIFOSTAT
4
4
4
DAC_DATA
A
B
C
D
E
F
G
H
I
J
K
L
M
Figure 83. Sync Logic Timing Diagram
Rev. A | Page 43 of 72
AD9734/AD9735/AD9736
DIGITAL BUILT-IN SELF TEST (BIST)
OVERVIEW
The AD973x includes an internal signature generator that
processes incoming data to create unique signatures. These
signatures are read back from the SPI port, allowing verification
of correct data transfer into the AD973x. BIST vectors provided
on the AD973x-EB evaluation board CD check the full width
data input or individual bits for PCB debug, utilizing the
procedure in the AD973X BIST Procedure section. Alterna-
tively, any vector can be used provided the expected signature is
calculated in advance.
Placing the idle value on the data input also allows the BIST to
be set up while the DAC clock is running. The idle value should
be all 0s in unsigned mode (0x0000) and all 0s except for the
MSB in twos complement mode (0x2000).
The BIST consists of two stages; the first stage is after the LVDS
receiver and the second stage is after the FIFO. The first BIST
stage verifies correct sampling of the data from the LVDS bus
while the second BIST stage verifies correct synchronization
between the DAC_CLK domain and the DATACLK_IN
domain. The BIST vector is generated using 32-bit LFSR
signature logic. Because the internal architecture is a 2-bus
parallel system, there are two 32-bit LFSR signature logic blocks
on both the LVDS and SYNC blocks. Figure 84 shows where the
LVDS and SYNC phases are located.
The MATLAB® routine, in the Generating Expected Signatures
section, calculates the expected signature. BIST verifies correct
data transfer because not all errors are always evident on a
spectrum analyzer. There are four BIST signature generators
that can be read back using Reg. 18 to Reg. 21, based on the
setting of the BIST selection bits (Reg. 17, Bits 7:6), as shown in
Table 24. The BIST signature returned from the AD973x
depends on the digital input during the test. Because the filters
in the DAC have memory, it is important to put the correct idle
value on the DATA input to flush the memory prior to reading
the BIST signature.
Table 24. BIST Selection Bits
Bit
SEL<1>
SEL<0>
LVDS Phase 1
LVDS Phase 2
SYNC Phase 1
SYNC Phase 2
0
0
1
1
0
1
0
1
D1
DB<13:0>
LVDS
BIST
SYNC
BIST
LVDS
RX
FIFO
2x
DAC
PH1
PH1
(RISE)
(RISE)
DATACLK_IN
D2
LVDS
BIST
SYNC
BIST
SYNC LOGIC
PH2
PH2
(FALL)
(FALL)
SPI PORT
Figure 84. Block Diagram Showing LVDS and SYNC Phase 1 and SYNC Phase 2
Rev. A | Page 44 of 72
AD9734/AD9735/AD9736
AD973x BIST PROCEDURE
17. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18, as described in Step 14 ) for each of the four SEL
(Reg. 17, Bits 7:6) values, and verify that they match the
expected signatures shown in Table 25.
1.
2.
Set RESET pin = 1.
Set input DATA = 0x0000 for signed (0x2000 for
unsigned).
18. Flush the BIST circuitry. This must be done once before
valid data can be read. Loop back to Step 11 and rerun the
test to obtain the correct result.
3.
4.
5.
6.
7.
8.
9.
Enable DATACLK_IN if it is not already running.
Run for at least 16 DATACLK_IN cycles.
Set RESET pin = 0.
Each time BIST mode is entered, this flush needs to
be performed once. Multiple BIST runs can be performed
without reflushing, as long as the device remains in
BIST mode.
Run for at least 16 DATACLK_IN cycles.
Set RESET pin = 1.
Run for at least 16 DATACLK_IN cycles.
Set RESET pin = 0.
AD973x EXPECTED BIST SIGNATURES
The BIST vectors provided on the AD973x-EB CD are in signed
mode, so no programming is necessary for the part to pass the
BIST. The BIST vector is for 1×, no FIFO, and signed data.
10. Set desired operating mode (1× mode and signed data are
default values and expected for the supplied BIST vectors).
11. Set CLEAR (Reg. 17, Bit 0), SYNC_EN (Reg. 17, Bit 1),
and LVDS_EN (Reg. 17, Bit 2) high.
For testing all 14 input bits, use the vector all_bits_unsnew.txt
and verify against the signatures in Table 25.
12. Wait 50 DATACLK_IN cycles to allow 0s to propagate
through and clear sync signatures.
Table 25. Expected BIST Data Readback for All Bits
LVDS Phase 1 LVDS Phase 2 SYNC Phase 1 SYNC Phase 2
13. Set CLEAR low.
CF71487C
66DF5250
CF71487C
66DF5250
14. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18) for each of the four SEL (Reg. 17, Bits 7:6) values
and verify they are all 0x00.
For individual bit tests, use the vectors named bitn.txt (where n
is the desired bit number being tested) and compare them
against the values in Table 26.
LVDS Phase 1
Table 26. Expected BIST Data Readback for Individual Bits
a.
Reg. 17 set to 0x26 (SEL1 = 0, SEL0 = 0,
Bit
LVDS Rise
LVDS Fall
Expected
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
LVDS Phase 2
Vector
bit0.txt
bit1.txt
bit2.txt
bit3.txt
bit4.txt
bit5.txt
bit6.txt
bit7.txt
bit8.txt
bit9.txt
Number Expected
0
1
2
3
4
5
6
7
8
9
AABF0A00
2BBF0A00
29BE0A00
2DBC0A00
25B80A00
35B00A00
15A00A00
55800A00
D5C00A00
D5410A00
D5430B00
D5470900
D54F0D00
D55F0500
2A400500
6B400500
E9400500
ED410500
E5430500
F5470500
D54F0500
955F0500
157F0500
153E0500
15BC0500
15B80400
15B00600
15A00200
a.
Reg. 17 set to 0x66 (SEL1= 0, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 1
a. Reg. 17 set to 0xA6 (SEL1= 1, SEL0 = 0,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 2
a. Reg. 17 set to 0xE6 (SEL1= 1, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
bit10.txt 10
bit11.txt 11
bit12.txt 12
bit13.txt 13
15. Clock the BIST vector into the AD973x.
16. After the BIST vector is clocked into the part, hold DATA
= 0x0000 for signed (0x2000 for unsigned); otherwise, the
additional nonzero data changes the signature.
Note the following for Table 26:
•
•
The term rise refers to Phase 1 and fall refers to Phase 2.
Byte order is Decimal Register Address 21, Address 20,
Address 19, and Address 18.
•
SYNC phase should always equal LVDS phase in 1× mode.
Rev. A | Page 45 of 72
AD9734/AD9735/AD9736
To generate the expected BIST signatures, follow this procedure:
GENERATING EXPECTED SIGNATURES
The following MATLAB code duplicates the internal logic of
the AD973x. To use it, save this code in a file called bist.m.
1. Start MATLAB and type the following at the command
prompt:
t = round(randn(1,100) × 213/8+213) ;
[ b1 b2 ] = bist(t)
--- begin bist.m ---
function [ ret1 , ret2] = bist(vec)
ret1 = bist1(vec(1:2:length(vec)-1));
ret2 = bist1(vec(2:2:length(vec)));
function ret = bist1(v)
sum = zeros(1,32);
for i = 1 :length(v)
The first statement creates a random vector of 14-bit
words, with a length of 100.
if v(i) ~= 0
su(1) = ~xor(sum(32) ,bitget(v(i),1));
su(2) = ~xor(sum(1) ,bitget(v(i),2));
su(3) = ~xor(sum(2) ,bitget(v(i),3));
su(4) = ~xor(sum(3) ,bitget(v(i),4));
su(5) = ~xor(sum(4) ,bitget(v(i),5));
su(6) = ~xor(sum(5) ,bitget(v(i),6));
su(7) = ~xor(sum(6) ,bitget(v(i),7));
su(8) = ~xor(sum(7) ,bitget(v(i),8));
su(9) = ~xor(sum(8) ,bitget(v(i),9));
su(10) = ~xor(sum(9) ,bitget(v(i),10));
su(11) = ~xor(sum(10) ,bitget(v(i),11));
su(12) = ~xor(sum(11) ,bitget(v(i),12));
su(13) = ~xor(sum(12) ,bitget(v(i),13));
su(14) = ~xor(sum(13) ,bitget(v(i),14));
su(15) = sum(14); su(16) = sum(15);
su(17) = sum(16); su(18) = sum(17);
su(19) = sum(18); su(20) = sum(19);
su(21) = sum(20); su(22) = sum(21);
su(23) = sum(22); su(24) = sum(23);
su(25) = sum(24); su(26) = sum(25);
su(27) = sum(26); su(28) = sum(27);
su(29) = sum(28); su(30) = sum(29);
su(31) = sum(30); su(32) = sum(31);
sum = su;
2. Set t equal to any desired vector, or take this random vector
and input it to the AD973x.
3. Alter the command randn(1,100) to change the vector
length as desired.
4. Type b1 at the command line to see the calculated
signature for the LVDS BIST, Phase 1.
5. Type b2 to see the value for LVDS BIST, Phase 2.
The values returned for b1 and b2 each are 32-bit hex values.
They correspond to Reg. 18, Reg. 19, Reg. 20, and Reg. 21,
where b1 is the value read for SEL<1:0> = 0, 0 (see Table 17)
and b2 is the value read for SEL<1:0> = 0, 1.
When the DAC is in 1× mode, the signature at SYNC BIST,
Phase 1 should equal the signature at LVDS BIST, Phase 1. The
same is true for Phase 2.
end
end % for ret = dec2hex( 2.^[0:31]× sum',8);
--- end bist.m ---
Rev. A | Page 46 of 72
AD9734/AD9735/AD9736
CROSS CONTROLLER REGISTERS
The AD973x differential output stage is adjustable to equalize
the charge injection into the positive and negative outputs. This
adjustment impacts certain performance characteristics, such as
harmonic distortion or IMD. System performance can be en-
hanced by adjusting the cross controller.
Figure 85 shows the effect of UPDEL and DNDEL.
INCREMENT DNDEL TO MOVE
THE CROSSING TOWARD THE
IDEAL VALUE
IDEAL DIFFERENTIAL OUTPUT
CROSSING ALIGNMENT
If the system is calibrated after manufacture, adjust the cross
controller offsets to provide optimum performance. To start,
increment DNDEL<5:0> (Reg. 11, Bits 5:0) while observing
HD2 (second harmonic distortion) and/or IMD to find the
desired optimum. If DNDEL does not influence the perform-
ance, set it to 0 and increment UPDEL<5:0> (Reg. 10, Bits 5:0).
Based on system characterization, set one of these controls to
the maximum value to yield the best performance.
INCREMENT UPDEL TO MOVE
THE CROSSING TOWARD THE
IDEAL VALUE
Figure 85. Effect of UPDEL and DNDEL
Rev. A | Page 47 of 72
AD9734/AD9735/AD9736
ANALOG CONTROL REGISTERS
–110
–115
–120
–125
–130
–135
–140
The AD973x includes some registers for optimizing its analog
performance. These registers include temperature trim for the
band gap, noise reduction in the output current mirror, and
output current mirror headroom adjustments.
MSE
L3
BAND GAP TEMPERATURE CHARACTERISTIC
TRIM BITS
MSE
L1
Using TRMBG<2:0> (Reg. 14, Bits 2:0), the temperature
characteristic of the internal band gap can be trimmed to
minimize the drift over temperature, as shown in Figure 86.
MSE
L0
M
SE
L2
1.23
1
10
F (kHz)
100
000
1.22
Figure 87. 1/f Noise with Respect to MSEL Bits
001
010
1.21
HEADROOM BITS
011
HDRM<7:0> (Reg. 15, Bits 7:0) are for internal evaluation.
Changing the default reset values is not recommended.
100
1.2
101
110
VOLTAGE REFERENCE
1.19
The AD973x output current is set by a combination of digital
control bits and the I120 reference current, as shown in
Figure 88.
111
1.18
–50 –40 –30 –20
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
AD973x
Figure 86. Band Gap Temperature Characteristic for Various TRMBG Values
FSC<9:0>
V
BG
1.2V
DAC
The temperature changes are sensitive to process variations,
and Figure 86 may not be representative of all fabrication lots.
Optimum adjustment requires measurement of the device
operation at two temperatures and development of a trim
algorithm to program the correct TRMBG<2:0> values in
external nonvolatile memory.
V
REF
–
+
I120
CURRENT
SCALING
1nF
IFULL-SCALE
10kΩ
I120
AVSS
Figure 88. Voltage Reference Circuit
MIRROR ROLL-OFF FREQUENCY CONTROL
The reference current is obtained by forcing the band gap
voltage across an external 10 kΩ resistor from I120 (Pin B14) to
ground. The 1.2 V nominal band gap voltage (VREF) generates a
120 μA reference current in the 10 kΩ resistor. This current is
adjusted digitally by FSC<9:0> (Reg. 2, Reg. 3) to set the output
full-scale current IFS:
With MSEL <1:0> (Reg. 14, Bits 7:6), the user can adjust the
noise contribution of the internal current mirror to optimize
the 1/f noise. Figure 87 shows MSEL vs. the 1/f noise with
20 mA full-scale current into a 50 ꢁ resistor.
VREF
R
192
1024
⎛
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
IFS
=
× 72 +
× FSC < 9.0 >
⎜
⎝
⎠
Rev. A | Page 48 of 72
AD9734/AD9735/AD9736
Always connect a 10 kΩ resistor from the I120 pin to ground
and use the digital controls to vary the full-scale current. The
AD973x is not a multiplying DAC. Applying an analog signal to
I120 is not supported.
The full-scale output current range is approximately 10 mA to
30 mA for register values from 0x000 to 0x3FF. The default
value of 0x200 generates 20 mA full scale. The typical range is
shown in Figure 89.
35
30
25
20
15
10
5
VREF (Pin C14) must be bypassed to ground with a 1 nF
capacitor. The band gap voltage is present on this pin and can
be buffered for use in external circuitry. The typical output
impedance is near 5 kΩ. If desired, an external reference can be
used to overdrive the internal reference by connecting it to the
VREF pin.
IPTAT (Pin D14) is used for factory testing. Leave this pin
floating.
0
0
200
400
600
800
1000
DAC GAIN CODE
Figure 89. IFS vs. DAC Gain Code
Rev. A | Page 49 of 72
AD9734/AD9735/AD9736
APPLICATIONS INFORMATION
DRIVING THE DACCLK INPUT
0.1μF
50Ω
50Ω
The DACCLK input requires a low jitter differential drive
signal. It is a PMOS input differential pair powered from the
1.8 V supply, so it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 800 mV p-p about the 400 mV common-
mode voltage. While these input levels are not directly LVDS
compatible, DACCLK can be driven by an offset ac-coupled
LVDS signal, as shown in Figure 90.
TTL OR CMOS
CLK INPUT
CLK+
CLK–
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
= 400mV
CM
Figure 91. TTL or CMOS DACCLK Drive Circuit
0.1μF
A simple bias network for generating VCM is shown in
Figure 92. It is important to use CVDD18 and CVSS for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and may
degrade the DAC performance.
LVDS_P_IN
CLK+
50Ω
50Ω
V
= 400mV
CM
LVDS_N_IN
CLK–
0.1μF
V
= 400mV
CM
Figure 90. LVDS DACCLK Drive Circuit
CVDD
1.8V
1kΩ
If a clean sine clock is available, it can be transformer-coupled
to DACCLK, as shown in Figure 107. Use of a CMOS or TTL
clock can also be acceptable for lower sample rates. It is routed
through a CMOS to LVDS translator, then ac-coupled, as
described previously. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 91.
1nF
0.1µF
1nF
287Ω
CVSS
Figure 92. DACCLK VCM Generator Circuit
Rev. A | Page 50 of 72
AD9734/AD9735/AD9736
DAC OUTPUT DISTORTION SOURCES
The second harmonic is mostly due to an imbalance in the
output load. The dc transfer characteristic of the DAC is capable
of second harmonic distortion of at least −75 dBc. Output load
imbalance or digital data noise coupling onto DACCLK causes
additional second harmonic distortion.
This is the configuration implemented on the evaluation board
(Figure 107). The 20 Ω series resistors allow the DAC to drive a
less reactive load, which improves distortion. Further improvement
is realized by adding the Balun T3 to help provide an equal load
to both DAC outputs.
R19
20Ω
The DAC architecture inherently generates third harmonics, the
levels of which depend on the output frequency and amplitude
generated. If any output signal is rectified and coupled back
onto the DAC clock, it can generate additional third-harmonic
energy.
IOUTA
J2, 50Ω OUTPUT
T3
R8
1
3
5
4
6
5
1
3
50Ω
AVSS
T1
R6
50Ω
4
IOUTB
R17
20Ω
AVSS
Figure 93. IF Signal Output Circuit
The distortion components should be identical in amplitude
and phase at both AD973x outputs. Even though each single-
ended output includes a large amount of second-harmonic
energy, a careful differential-to-single-ended conversion can
remove most of it. Optimum performance at high intermediate
frequency (IF) output is obtained with the output circuit shown
in Figure 93.
Because T1 has a differential input, but a single-ended output,
Pin 4 of T1 has a higher capacitance to ground due to parasitics
to Pin 3. T1 Pin 6 has lower parasitic capacitance to ground
because it drives 50 Ω at Pin 1. This presents an unbalanced
load to the DAC output, so T3 is added to improve the load
balancing. Refer to Figure 107 for the transformer part numbers.
Rev. A | Page 51 of 72
AD9734/AD9735/AD9736
DC-COUPLED DAC OUTPUT
In some cases, it may be desirable to dc-couple the AD973x
output. The best method for doing this is shown in Figure 94.
This circuit can be used with voltage or current feedback
amplifiers. Because the DAC output current is driving a virtual
ground, this circuit may offer enhanced settling times. The
settling time is limited by the op amp rather than by the DAC.
This circuit is intended for use where the amplifiers can be
powered by a bipolar supply.
An alternate circuit is shown in Figure 95. It suffers from dc
offset at the output unless the DAC load resistors are small,
relative to the amplifier gain and feedback resistors.
0.5V p-p
0V TO –0.5V
IOUTA
2V p-p
1kΩ
2kΩ
2kΩ
25Ω
25Ω
0V TO –2V
DAC OUTPUT
20mA
FULL SCALE
AVSS
OUTPUT
1kΩ
IOUTB
AVSS
100Ω
2V p-p
0V TO –2V
IOUTA
Figure 95. Differential Op Amp Output Circuit
2V p-p
+1V TO –1V
500Ω
500Ω
100Ω
AVSS
100Ω
DAC
OUTPUT
20mA
OUTPUT
FULL SCALE
500Ω
500Ω
AVSS
IOUTB
100Ω
Figure 94. Op Amp I to V Conversion Output Circuit
Rev. A | Page 52 of 72
AD9734/AD9735/AD9736
DAC DATA SOURCES
The circuit shown in Figure 96 allows optimum data alignment
when running the AD973x at full speed. This circuit can be
easily implemented in the FPGA or ASIC used to drive the
digital input. It is important to use the DATACLK_OUT signal
because it helps to cancel some of the timing errors. In this
configuration, DATACLK_OUT generates the DDR LVDS
DATACLK_IN to drive the AD973x. The circuit aligns the
DATACLK_IN and the digital input data (DB<13:0>) as
required by the AD973x. The LVDS controller in the AD973x
uses DATACLK_IN to generate the internal DSS to capture the
incoming data in the center of the valid data window.
To operate in 2× mode, the circuit in Figure 96 must be
modified to include a divide-by-2 block in the path of
DATACLK_OUT. Without this additional divider, the data and
DATACLK_IN runs 2× too fast. DATACLK_OUT is always
DACCLK/2.
Contact FPGA vendors directly regarding the maximum output
data rates supported by their products.
DATA SOURCE
DATA SOURCE
DATACLK_OUT
FROM AD9736 (DDR)
DATACLK_OUT
FROM AD9736 (DDR)
÷2
D1
D2
D1
DATA1
DATA2
DATA1
DB(13:0) TO AD9736
MUX
MUX
DB(13:0) TO AD9736
MUX
MUX
DATA2
D2
LOGIC 1
LOGIC 0
DATACLK_IN
TO AD9736 (DDR)
LOGIC 0
LOGIC 1
DATACLK_IN
TO AD9736 (DDR)
Figure 96. Recommended FPGA/ASIC Configuration for Driving AD9736
Digital Inputs, 1× Mode
Figure 98. Recommended FPGA/ASIC Configuration for Driving AD9736
Digital Inputs, 2× Mode
DATACLK_OUT+
CLK_OUT+/2
DATACLK_OUT+
DATA1
A
C
B
E
DATA2
D
B
DATA1
A
C
B
E
D1
A
C
DATA2
B
D
D2
DB
D
D1
A
C
A
B
C
D
D2
DB
DATACLK_IN+
A
B
C
DATACLK_IN+
Figure 99. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 2× Mode
Figure 97. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 1× Mode
Rev. A | Page 53 of 72
AD9734/AD9735/AD9736
INPUT DATA TIMING
The AD973x is intended to operate with the LVDS and sync
controllers running to compensate for timing drift due to
voltage and temperature variations. In this mode, the key to
correct data capture is to present valid data for a minimum
amount of time. The AD973x minimum valid data time is
measured by increasing the input data rate to the point of
failure. The nominal supply voltages are used and the
temperature is set to the worst case of 85°C. The input
data is verified via the BIST signature registers, because the
DAC output does not run as fast as the input data logic. The
following example explains how the minimum data valid
period is calculated for the typical performance case.
The ability of the AD973x to capture incoming data is
dependent on the speed of the silicon, which varies from lot to
lot. The typical (or average) silicon speed operates with data
that is valid for 225 ps at 85°C. Statistically, the worst extreme
for slow silicon may require up to a 344 ps valid data period, as
specified in Table 2.
Table 27. Typical Minimum Data Valid Times
Differential Input BIST
Min Clock Typ Min Data
Voltage
400 mV
250 mV
Max fCLK
Period
465 ps
500 ps
Valid at Receiver
2.15 GHz
2.00 GHz
225 ps
260 ps
At 1.2 GHz, the typical 400 mV p-p minimum data valid period
of 225 ps leaves 608 ps for external factors. Under the same
conditions, the worst expected minimum data valid period of
344 ps leaves 489 ps for external data uncertainty.
These factors must be considered in determining the minimum
valid data window at the receiver input:
•
•
Data rise and fall times: 100 ps (rise + fall)
Internal clock jitter: 10 ps
The 100 mV LVDS VOD threshold test is a dc test to verify that
the input logic state changes. It does not indicate the operating
speed. The ability of the receiver to recover the data depends on
the input signal overdrive. With a 250 mV input, there is a
150 mV overdrive, and with a 400 mV signal, there is a 300 mV
overdrive. The relationship between overdrive level and timing
is very nonlinear. Higher levels of overdrive result in smaller
minimum valid data windows.
(DATACLK_OUT + DATACLK_IN)
Bit-to-bit skew: 50 ps
Bit-to-DATACLK_IN skew: 50 ps
Internal data sampling signal resolution: 80 ps
•
•
•
For nominal silicon, the BIST typically indicates failure at
2.15 GSPS or a DACCLK period of 465 ps. The valid data
window is calculated by subtracting all the other variables
from the total data period:
For typical silicon, decreasing the LVDS swing from 400 mV p-p
to 250 mV p-p requires the minimum data valid period to
increase by 15%. This is illustrated in Figure 100.
Minimum Data Valid Time = DACCLK Period − Data Rise −
Data Fall − Jitter − Bit-to-Bit Skew − Bit-to-DATACLK_IN Skew
− Data Sampling Signal Resolution
225ps
400mV
For the 400 mV p-p LVDS signal case:
Minimum Data Valid = 465 ps − 100 ps − 10 ps − 50 ps −
80 ps = 465 ps − 240 ps = 225 ps
260ps
250mV
For correct data capture, the input data must be valid for 225 ps.
Slower edges, more jitter, or more skew require an increase in
the clock period to maintain the minimum data valid period.
Table 27 shows the typical minimum data valid period (tMDE) for
400 mV p-p differential and 250 mV p-p differential LVDS swings.
Figure 100. Typical Minimum Valid Data Time (tMDE) vs. LVDS Swing
The minimum valid data window changes with temperature,
voltage, and process. The maximum value presented in the
specification table was determined from a 6σ distribution in the
worst-case conditions.
Rev. A | Page 54 of 72
AD9734/AD9735/AD9736
SYNCHRONIZATION TIMING
When more than one AD973x must be synchronized or when
a constant group delay must be maintained, the internal
controllers cannot be used. If the FIFO is enabled, the delay
between multiple AD973x devices is unknown. If the
DATACLK_OUT from multiple devices is used, there is an
uncertainty of two DACCLK periods because the initial phase
of DATACLK_OUT with respect to DACCLK cannot be
controlled. This means one DAC must be used to provide
DATACLK_OUT for all synchronized DACs and all timing
must be externally managed. The following timing information
allows system timing to be calculated so that multiple AD973xs
can be synchronized.
While correct DATA_IN vs. DATACLK_IN timing is critical,
the transition of the incoming data to the DACCLK domain is
equally critical. By referencing the incoming DATA and
DATACLK_IN timing to the DATACLK_OUT signal, some
timing uncertainty can be removed. The DATACLK_OUT
timing very closely tracks the timing of the DACCLK-
controlled registers. Any variation in the path delay affects both
paths in almost the same way. If DATACLK_OUT is not used,
the full DACCLK to DATACLK_OUT path variation reduces
the external timing margin. Figure 101 shows a simplified view
of the internal clocking scheme with the relevant delay paths.
The internal architecture is interleaved such that each phase has
twice as long to make the transition across the clock domains.
This results in an extremely narrow window where the
incoming data must be held stable.
DATACLK_OUT changes relative to the rising edge of
DACCLK+ and is delayed, as shown in Figure 101. Because
DACCLK is divided by 2 to create DATACLK_OUT, the phase
of DATACLK_OUT can be 0° or 180°. There is no way to
predict or control this relationship. It can be different after each
power cycle and is not affected by hardware or software resets.
Table 28 shows the timing parameters for Figure 101 and
Figure 102. These parameters were measured for a sample of
five devices from five silicon lots. Worst-case fast and slow skew
lots were included in addition to the nominal (or average) lot.
The typical −40°C to typical +85°C spread illustrates the
variability with temperature for a single lot. Adding in lot-to-lot
variation with the fast and slow lots indicates the worst-case
spread in timing.
DACCLK
t
DDCO
DATACLK_OUT
Figure 101. DACCLK to DATACLK_OUT Delay
The timing varies such that all of the parameters move in the
same direction. For example, if the DATACLK_IN to data setup
time is fast, the hold time is similarly fast. The DACCLK to
DATACLK_OUT delay and the DATACLK_OUT to data setup
and hold is also at the fast end of the range.
The incoming data is de-interleaved internally as shown in
Figure 78. In Figure 78, DBU (upper) and DBL (lower) represent
the de-interleaved data paths. Each edge of DATACLK_IN
latches an incoming sample in two alternating registers. The
DATACLK_IN to data setup and hold definitions are illustrated
in Figure 102. All the data input must be valid during the setup-
and-hold period. External skew effectively increases the setup
and hold times that the data source must meet.
Note that the polarities of setup-and-hold values in Table 28
conform to the standard convention of setup time occurring
prior to the latching edge and hold time occurring after the
latching edge, as shown in Figure 102.
DATACLK_IN
OR DATACLK_OUT
t
DSU
t
DH
DATA_IN
Figure 102. Standard Definitions for DATACLK_IN or DATACLK_OUT to
Data Setup and Hold, SD = 0
Table 28. AD973x Clock and Data Timing Parameters
Symbol and Definition
Fast −40°C
+1650
−100
+210
+1310
−1250
Typ −40°C
+1800
−120
+220
+1440
−1360
All +25°C
+1890
−150
+240
+1611
−1548
Typ +85°C
+2050
−170
+280
+1710
−1640
Slow +85°C
+2350
−220
+360
+1970
−1890
Unit
ps
ps
ps
ps
tDDCO − DACCLK to DATACLK_OUT Delay
tDCISU − DATACLK_IN to DATA Setup
tDCIH − DATACLK_IN to DATA Hold
tDISU − DATACLK_OUT to DATA Setup
tDIH − DATACLK_OUT to DATA Hold
ps
Rev. A | Page 55 of 72
AD9734/AD9735/AD9736
POWER SUPPLY SEQUENCING
The 1.8 V supplies should be enabled prior to enabling the 3.3 V supplies. Do not enable the 3.3 V supplies when the
1.8 V supplies are off.
DATACLK_IN DOMAIN
FF
DACCLK DOMAIN
D1
D2
D1A
FF
DAC_DATA
LVDS
RX
DAC
CORE
DAC_OUTPUT
DB<13:0>
D2A
FF
FF
DATA SAMPLING
SIGNAL
DAC SAMPLING
SIGNAL
SAMPLE DELAY
SD<3:0>
PATH A
PATH B
CLK
LVDS
RX
DACCLK
RX
÷
2
DATACLK_IN
COMMON SYSTEM CLOCK
LVDS
TX
DELAYS THROUGH PATH A AND B WILL TRACK,
THUS REDUCING TIMING UNCERTAINTY IN THE SYSTEM
DATACLK_OUT
Figure 103. Simplified Internal Clock Routing
Rev. A | Page 56 of 72
AD9734/AD9735/AD9736
AD973X EVALUATION BOARD SCHEMATICS
TP4
RED
33DIG
TB1
L6
FERRITE
1
VDD33
VSS
LC1210
+
C14
ACASE
10μF
6.3V
VSS
TB1
2
TP5
BLK
TP7
RED
L7
FERRITE
VDD18B
LC1210
+
C22
ACASE
10
μF
TP13
BLK
6.3V
VSS
L1, L3, L4, L5, L6, AND L7
TP6
RED
FERRITE BEAD CORE:
18DIG
TB1
L5 FERRITE
LC1210
PANASONIC EXC–CL3225U1
DIGIKEY PN: P9811CT–ND
3
VDD18A
+
C18
10
6.3V
μ
F
ACASE
VSS
TB1
4
VSS
TP14
BLK
JP1
VSS
VSSA
TP1
RED
UNDER DUT
33ANA
L1
FERRITE
TB2
1
VDDA33
VSSA
LC1210
+
C1
10μF
ACASE
6.3V
VSSA
TB2
2
TP3
BLK
POWER INPUT FILTERS
TP9
RED
18ANA
L3
FERRITE
LC1210
TB2
3
VDDC
VSSA
+
C10
10μF
ACASE
6.3V
VSSA
L4
FERRITE
TB2
4
LC1210
TP11
BLK
Figure 104. Power Supply Input for AD973x Evaluation Board, Rev. F
Rev. A | Page 57 of 72
AD9734/AD9735/AD9736
RC1206
Figure 105. Circuitry Local to AD973x, Evaluation Board, Rev. F
Rev. A | Page 58 of 72
AD9734/AD9735/AD9736
/ 0 D – G 0 2 4 – 2 N 6 C 8 F F
J A C K
0 5 G
S 4
8 4 G
9
7
7
5
5
3
3
1
1
9
9
7
7
5
5
3
3
1
1
9
9
7
7
5
5
3
3
1
1
9
9
7
7
5
5
3
3
1
1
G 4
8
S 4
G 4
S 4
G 4
S 4
G 4
S 4
G 4
S 3
G 3
S 3
G 3
S 3
G 3
S 3
G 3
S 3
G 3
S 2
G 2
S 2
G 2
S 2
G 2
S 2
G 2
S 2
G 2
S 1
G 1
S 1
G 1
S 1
G 1
S 1
G 1
S 1
G 1
6
S 4
6 4 G
4
S 4
4 4 G
2
S 4
2 4 G
0
S 4
0 4 G
8
S 3
8 3 G
6
S 3
6 3 G
4
S 3
4 3 G
2
S 3
2 3 G
0
S 3
0 3 G
8
S 2
8 2 G
6
S 2
6 2 G
4
S 2
4 2 G
2
S 2
2 2 G
0
S 2
0 2 G
8
S 1
8 1 G
6
S 1
6 1 G
4
S 1
4 1 G
2
S 1
2 1 G
0
0
S 1
S 9
G 1
S 8
G 8
S 6
G 6
S 4
G 4
S 2
G 2
G 9
S 7
G 7
S 5
G 5
S 3
G 3
S 1
G 1
A J C K
Figure 106. High Speed Digital I/O Connector, AD973x Evaluation Board, Rev. F
Rev. A | Page 59 of 72
AD9734/AD9735/AD9736
R C 0 6 0 3
R C 0 6 0 3
C C 0 6 0 3 C C 0 6 0 3
R C 0 6 0 3
R C 0 6 0 3
R C 0 6 0 3
R C 0 6 0 3
Figure 107. Clock Input and Analog Output, AD973x Evaluation Board, Rev. F
Rev. A | Page 60 of 72
AD9734/AD9735/AD9736
R C 0 6 0 3
R C 0 6 0 3
Figure 108. SPI Port Interface, AD973x Evaluation Board, Rev. F
Rev. A | Page 61 of 72
AD9734/AD9735/AD9736
AD973X EVALUATION BOARD PCB LAYOUT
Figure 109. CB Layout Top Placement, AD973x Evaluation Board, Rev. F
Rev. A | Page 62 of 72
AD9734/AD9735/AD9736
Figure 110. PCB Layout Layer 1, AD973x Evaluation Board, Rev. F
Rev. A | Page 63 of 72
AD9734/AD9735/AD9736
Figure 111. PCB Layout Layer 2, AD973x Evaluation Board, Rev. F
Rev. A | Page 64 of 72
AD9734/AD9735/AD9736
Figure 112. PCB Layout Layer 3, AD973x Evaluation Board, Rev. F
Rev. A | Page 65 of 72
AD9734/AD9735/AD9736
Figure 113. PCB Layout Layer 4, AD973x Evaluation Board, Rev. F
Rev. A | Page 66 of 72
AD9734/AD9735/AD9736
Figure 114. PCB Layout Bottom Placement, AD973x Evaluation Board, Rev. F
Rev. A | Page 67 of 72
AD9734/AD9735/AD9736
Figure 115. PCB Fabrication Detail, AD973x Evaluation Board, Rev. F
Rev. A | Page 68 of 72
AD9734/AD9735/AD9736
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
12.10
12.00 SQ
11.90
13 11
14 12 10
9
7
5
3
1
8
6
4
2
A
B
C
D
E
F
G
H
J
BALL A1
INDICATOR
10.40
BSC SQ
TOP VIEW
BOTTOM
VIEW
K
L
M
N
P
0.80
REF
0.80 BSC
DETAIL A
1.40 MAX
DETAIL A
1.00 MAX
0.85 MIN
0.43 MAX
0.25 MIN
0.12 MAX
COPLANARITY
0.55
0.50
SEATING
PLANE
0.45
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-205-AE.
Figure 116. 160-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-160-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
BC-160-1
AD9734BBC
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
160-Lead Chip Scale Package Ball Grid Array (CSP_BGA)
Evaluation Board
AD9734BBCRL
AD9734BBCZ1
AD9734BBCZRL1
AD9735BBC
AD9735BBCZ1
AD9735BBCRL
AD9735BBCZRL1
AD9736BBC
AD9736BBCRL
AD9736BBCZ1
AD9736BBCZRL1
AD9734-EB
AD9735-EB
Evaluation Board
AD9736-EB
Evaluation Board
1 Z = Pb-free part.
Rev. A | Page 69 of 72
AD9734/AD9735/AD9736
NOTES
Rev. A | Page 70 of 72
AD9734/AD9735/AD9736
NOTES
Rev. A | Page 71 of 72
AD9734/AD9735/AD9736
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04862-0-9/06(A)
Rev. A | Page 72 of 72
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