AD9732BRS [ADI]
10-Bit, 200 MSPS D/A Converter; 10位， 200 MSPS D / A转换器
| 型号： | AD9732BRS |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 200 MSPS D/A Converter |
| 文件： | 总11页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 200 MSPS
D/A Converter
a
AD9732
FEATURES
200 MSPS Throughput Rate
3.3 V PECL Digital Input
FUNCTIONAL BLOCK DIAGRAM
ANALOG
RETURN
65 dB SFDR @ 2 MHz AOUT, 200 MSPS/54 dB @ 40 MHz
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
A
OUT, 200 MSPS
Low Power: 305 mW
Fast Settling: 5 ns to 1/2 LSB
Low Glitch Energy: 6 pVs
Internal Reference
I
TTL
DRIVE
LOGIC
OUT
I
28-Lead SSOP Packaging
OUT
APPLICATIONS
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging
REF
IN
CLOCK
CONTROL
AMP
INTERNAL
VOLTAGE
REFERENCE
CONTROL
AMP OUT
AD9732
R
GENERAL DESCRIPTION
DIGITAL
+V
SET
S
The AD9732 is a 10-bit, 200 MSPS, bipolar D/A converter that
is optimized to provide high dynamic performance, yet offers
lower power dissipation and a more economical price than pre-
vious high speed DAC solutions. The AD9732 was primarily
designed for demanding communications systems applications
where maximum spurious-free dynamic range (SFDR) is required
at high throughput rates. The proliferation of digital communi-
cations into base station and high volume subscriber-end mar-
kets has created a demand for high performance bipolar DACs
delivered at CMOS associated levels of power dissipation and
cost. The AD9732 is the answer to that demand.
REF
CONTROL
AMP IN
OUT
spectrum in many of the emerging digital communications ap-
plications where signal purity is critical. Narrowband (±1 MHz
window), the AD9732 provides an SFDR of greater than 75 dB.
This level of wideband and narrowband ac performance, coupled
with its 200 MSPS throughput rate, enables the AD9732 to
present outstanding value in the high speed DAC function.
The AD9732 is packaged in a 28-lead SSOP and is specified to
operate over the extended industrial temperature range of –40°C
to +85°C. Digital inputs and clock are positive-ECL compatible.
Optimized for direct digital synthesis (DDS) and digital modu-
lator waveform reconstruction, the AD9732 provides >50 dB of
wideband harmonic suppression over the dc to 80 MHz analog
output bandwidth. This signal bandwidth addresses the transmit
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD9732–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS(+VS = +5 V, ENCODE = 125 MSPS, RSET = 1.95 k⍀ (for 20 mA IOUT) unless otherwise noted)
Test
Level
AD9732BRS
Typ
Parameter
Temp
Min
Max
Units
MHz
Bits
THROUGHPUT RATE
RESOLUTION
+25°C
IV
165
200
10
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
0.25
0.36
0.6
1
1
1.5
1.5
LSB
LSB
LSB
LSB
Integral Nonlinearity
VI
0.7
INITIAL OFFSET ERROR
Zero-Scale Offset Error
+25°C
Full
+25°C
Full
I
VI
I
VI
V
35
40
2.5
2.5
0.04
70
100
5
µA
µA
% FS
% FS
µA/°C
Full-Scale Gain Error1
5
Offset Drift Coefficient
REFERENCE/CONTROL AMP
Internal Reference Voltage2
Internal Reference Voltage Drift
Internal Reference Output Current3
Amplifier Input Impedance
Amplifier Bandwidth
+25°C
Full
Full
+25°C
+25°C
I
3.65
–50
3.75
150
3.85
V
µV/°C
µA
kΩ
MHz
IV
VI
I
+500
50
2.5
I
REFERENCE INPUT4
Reference Input Impedance
+25°C
+25°C
V
V
4.6
75
kΩ
MHz
Reference Multiplying Bandwidth5
OUTPUT PERFORMANCE
Output Current4, 6
Output Compliance
Output Resistance
Full
Full
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
V
IV
V
V
V
V
V
V
V
V
20
mA
V
Ω
pF
ns
ns
pVs
V/µs
ns
2
5.75
240
5
4.75
2.7
5.9
450
1
Output Capacitance
7
Voltage Settling Time to 1/2 LSB (tST
)
8
Propagation Delay (tPD
)
Glitch Impulse9
Output Slew Rate10
Output Rise Time10
Output Fall Time10
1
ns
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Full
Full
+25°C
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
VI
VI
I
I
V
IV
IV
IV
IV
IV
IV
2.4
–1
V
V
1.6
10
1
1.7
0.01
2
0.7
1
0.7
1
µA
µA
pF
ns
ns
ns
ns
ns
ns
Input Capacitance
Minimum Data Setup Time (tS)11
1.5
1.5
1.5
1.5
Minimum Data Hold Time (tH)12
Clock Pulsewidth Low (pwMIN
Clock Pulsewidth High (pwMAX
)
2
2
)
POWER SUPPLY13
Digital +V Supply Current
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
I
VI
I
VI
V
V
V
15
10
10
10
25
20
35
40
30
30
mA
mA
mA
mA
mW
mW
µA/V
Analog +V Supply Current
Power Dissipation14
305
350
200
Power Supply Rejection Ratio (PSRR)
–2–
REV. A
AD9732
Test
Level
AD9732BRS
Typ
Parameter
Temp
Min
Max
Units
SFDR PERFORMANCE (Wideband)15
2 MHz AOUT
10 MHz AOUT
20 MHz AOUT
40 MHz AOUT
2 MHz AOUT (Clock = 165 MHz)
10 MHz AOUT (Clock = 165 MHz)
20 MHz AOUT (Clock = 165 MHz)
40 MHz AOUT (Clock = 165 MHz)
65 MHz AOUT (Clock = 165 MHz)
65 MHz AOUT (Clock = 200 MHz)
80 MHz AOUT (Clock = 200 MHz)
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
V
V
V
V
V
V
V
V
V
V
V
66
63
57
52
63
62
56
51
48
45
43
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
SFDR PERFORMANCE (Narrowband)15
2 MHz; 2 MHz Span
25 MHz; 2 MHz Span
+25°C
+25°C
+25°C
V
V
V
77
65
70
dB
dB
dB
10 MHz; 5 MHz Span (Clock = 200 MHz)
INTERMODULATION DISTORTION16
F1 = 800 kHz, F2 = 900 kHz to Nyquist
F1 = 800 kHz, F2 = 900 kHz, Narrowband
(2 MHz)
+25°C
+25°C
V
V
69
61
dB
dB
NOTES
1Measured as an error in ratio of full-scale current to current through RSET (640 µA nominal); ratio is nominally 32. DAC load is virtual ground.
2Internal reference voltage is tested under load conditions specified in Internal Reference Output Current specification.
3Internal reference output current defines load conditions applied during Internal Reference Voltage test.
4Full-scale current variations among devices are higher when driving REFERENCE IN directly.
5Frequency at which a 3 dB change in output of DAC is observed; RL = 50 Ω; 100 mV modulation at midscale.
6Based on IFS = 32 ([CONTROL AMP IN – (+VS)]/RSET) when using internal control amplifier. DAC load is virtual ground.
7Measured as voltage settling at midscale transition to 0.1%; RL = 50 Ω.
8Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
9Peak glitch impulse is measured as the largest area under a single positive or negative transient.
10Measured with RL = 50 Ω and DAC operating in latched mode.
11Data must remain stable for a specified time prior to rising edge of CLOCK.
12Data must remain stable for a specified time after rising edge of CLOCK.
13Supply voltages should remain stable with ±5% for nominal operation.
14Power dissipation calculation includes current through a 50 Ω load.
15SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
The frequency span dc to Nyquist unless otherwise noted.
16Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at sum and difference frequencies of the two tones.
Specifications subject to change without notice.
IV Parameter is guaranteed by design and characterization
testing.
EXPLANATION OF TEST LEVELS
Test Level
I
100% production tested.
V
Parameter is a typical value only.
II 100% production tested at +25°C and sample tested at
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range.
specified temperatures.
III Sample tested only.
ORDERING GUIDE
Package
Temperature
Range
Package
Option
Model
Description
AD9732BRS
AD9732/PCB
–40°C to +85°C
+25°C
28-Lead Small Outline (SSOP)
Evaluation Board
RS-28
REV. A
–3–
AD9732
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+VS
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to +VS
Reference Input Voltage Range . . . . . . . . . . . . . . . 0 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . 500 µA
Control Amplifier Output Current . . . . . . . . . . . . . . ±2.5 mA
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Lead Temperature (10 sec) Soldering . . . . . . . . . . . . +300°C
D9 (MSB)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
DIGITAL +V
GND
S
D8
D7
3
CONTROL AMP IN
REF OUT
4
D6
5
D5
CONTROL AMP OUT
REF IN
6
D4
AD9732
TOP VIEW
(Not to Scale)
7
D3
GND
8
D2
I
OUTB
OUT
D1
9
I
10
11
12
13
14
D0 (LSB)
CLOCK
NC
ANALOG RETURN
ANALOG +V
S
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
R
SET
NC
GND
15 DIGITAL +V
DIGITAL +V
S
S
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Function
Pin Number
Name
1
2–9
D9 (MSB)
D8–D1
Most significant data bit of digital input word.
Eight bits of 10-bit digital input word.
10
11
D0 (LSB)
CLOCK
NC
DIGITAL +VS
GND
Least significant data bit of digital input word.
TTL-compatible edge-triggered latch enable signal for on-board registers.
No internal connection to this pin. Recommend tie to ground.
+5 V supply voltage for digital circuitry.
Converter Ground.
+5 V supply voltage for analog circuitry.
12, 13
14, 15, 28
16, 22, 27
18
ANALOG +VS
RSET
17
Connection for external reference set resistor; nominal 1.96 kΩ. Full-scale output
current = 32 [Control Amp + VS] (Reset).
19
20
ANALOG RETURN
IOUT
Analog Return. This point and the reference side of the DAC load resistors should be
connected to the same potential (Analog +VS).
Analog current output; full-scale current occurs with a digital word input of all “1s”
with external load resistor, output voltage = IOUT (RLOADʈRINTERNAL). RINTERNAL is
nominally 240 Ω.
21
23
IOUTB
Complementary analog current output; full-scale current occurs with a digital word
input of all “0s.”
Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current
source network. Voltage changes (noise) at this point have a direct effect on the full-
scale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/
RSET) when using internal amplifier. DAC load is virtual ground.
REF IN
24
25
26
CONTROL AMP OUT
REF OUT
Normally connected to REF IN (Pin 23). Output of internal control amplifier, which
provides a reference for the current switch network.
Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference,
nominally 3.75 V.
CONTROL AMP IN
Normally connected to REF OUT (Pin 25) if not connected to external reference.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9732 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD9732
pwMIN
pwMAX
CLOCK
tS
tH
CODE 1
DATA
CODE 2
DATA
CODE 3
DATA
CODE 4
DATA
DATA
CODE 2
ANALOG OUTPUT
CODE 4
CODE 1
CODE 3
a.
DETAIL OF SETTLING TIME
GLITCH AREA = 1/2 HEIGHT
؋
WIDTH H
CLOCK
SPECIFIED
ERROR BAND
tPD
W
ANALOG OUTPUT
tST
b.
c.
Figure 1. Timing Diagrams
REV. A
–5–
AD9732
75
70
65
60
55
50
45
40
35
55
50
45
40
30
0
10
20
30
40
A
50
60
70
80
90
100
20
18
16
14
12
10
8
6
4
2
– MHz
OUT
I
– mA
OUT
Figure 2. Narrowband SFDR (Clock = 200 MHz) vs. AOUT
Frequency
Figure 5. SFDR vs. IOUT
90
80
70
60
50
56
54
52
50
48
46
44
42
40
40
30
5
10
15
20
25
30
35
40
45
50
55
60
5
25
45
65
85 105 125 145 165 185 205
CLOCK – MHz
A
– MHz
OUT
Figure 3. Narrowband SFDR (Clock = 125 MHz) vs. AOUT
Frequency
Figure 6. SFDR vs. Clock for fCLK/AOUT = 3.125
65
60
0.4
0.3
0.2
0.1
0
55
50
45
40
35
30
–0.1
–0.2
–0.3
–0.4
10
20
30
40
50
– MHz
60
70
80
90
A
OUT
Figure 4. Wideband SFDR (200 MHz Clock) vs. AOUT
Figure 7. Typical Differential Nonlinearity Performance
(DNL)
–6–
REV. A
AD9732
0.6
0.4
0.2
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
ENCODE = 125MHz
= 20MHz
SPAN = 62.5MHz
SFDR = 57dB
A
OUT
0
–0.2
–0.4
–0.6
1
START 0Hz
6.25MHz/
STOP 62.5MHz
Figure 8. Typical Integral Nonlinearity Performance (INL)
Figure 11. Wideband SFDR 20 MHz AOUT; 125 MHz Clock
0
0
1
1
ENCODE = 125MHz
ENCODE = 125MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
A
= 2MHz
A
= 40MHz
–10
OUT
OUT
SPAN = 62.5MHz
SFDR = 66dB
SPAN = 62.5MHz
–20 SFDR = 52dB
–30
–40
–50
1
–60
1
–70
–80
–90
–100
START 0Hz
6.25MHz/
STOP 62.5MHz
START 0Hz
6.25MHz/
STOP 62.5MHz
Figure 9. Wideband SFDR 2 MHz AOUT; 125 MHz Clock
Figure 12. Wideband SFDR 40 MHz AOUT; 125 MHz Clock
0
0
1
1
ENCODE = 125MHz
ENCODE = 200MHz
A
= 10MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
A
= 40MHz
OUT
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
OUT
SPAN = 62.5MHz
SFDR = 63dB
SPAN = 100MHz
SFDR = 54dB
1
1
START 0Hz
6.25MHz/
STOP 62.5MHz
START 0Hz
10MHz/
STOP 100MHz
Figure 10. Wideband SFDR 10 MHz AOUT; 125 MHz Clock
Figure 13. Wideband SFDR 40 MHz AOUT; 200 MHz Clock
REV. A
–7–
AD9732
1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
ENCODE = 200MHz
= 65MHz
SPAN = 200MHz
SFDR = 45dB
ENCODE = 125MHz
A
OUT
A
1 = 800kHz
OUT
A
2 = 900kHz
OUT
SPAN = 2MHz
IMD = 61dB
1
1
START 0Hz
10MHz/
STOP 100MHz
START 0Hz
200MHz/
STOP 2MHz
Figure 14. Wideband SFDR 65 MHz AOUT; 200 MHz Clock
Figure 16. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 2 MHz
1
0
0
1
ENCODE = 125MHz
ENCODE = 200MHz
A
1 = 800kHz
2 = 900kHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
A
= 80MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
OUT
OUT
A
SPAN = 100MHz
SFDR = 43dB
OUT
SPAN = 62.5MHz
IMD = 69dB
1
1
START 0Hz
6.25MHz/
STOP 62.5MHz
START 0Hz
10MHz/
STOP 100MHz
Figure 15. Wideband SFDR 80 MHz AOUT; 200 MHz Clock
Figure 17. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 62.5 MHz
–8–
REV. A
AD9732
However, it should be noted that output settling time, for
changes in the digital word, will be degraded.
APPLICATION NOTES
THEORY OF OPERATION
The AD9732 high speed digital-to-analog converter utilizes most
significant bit decoding and segmentation techniques to reduce
glitch impulse and deliver high dynamic performance on lower
power consumption than previous bipolar DAC technologies.
+V
S
R
SET
R
SET
AD9732
The design is based on four main subsections: the decode/driver
circuits, the edge-triggered data register, the switch network and
the control amplifier. An internal bandgap reference is included
to allow operation of the device with minimum external support
components.
3.8V TO 4.4V
2.5MHz TYPICAL
CONTROL
AMP IN
R
T
CONTROL
AMP OUT
REFERENCE IN
Digital Inputs/Timing
The AD9732 has PECL high speed single-ended inputs for data
inputs and clock. The switching threshold is +2.0 V.
0.1F
In the decode/driver section, the three MSBs are decoded to
seven “thermometer code” lines. An equalizing delay is included
for the seven least significant bits and the clock signals. This
delay minimizes data skew and data setup-and-hold times at the
register inputs.
Figure 18. Lower Frequency Multiplying Circuit
The REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. The analog signal for this
mode of operation must have a signal swing in the range of
0.95 V to 1.9 V. This can be implemented by capacitively cou-
pling into REFERENCE IN a signal with a dc bias of 1.9 V (IOUT
= 22.5 mA) to 0.95 V (IOUT = 3 mA), as shown in Figure 19, or
by dividing REFERENCE IN with a low impedance op amp
whose signal swing is limited to the stated range.
The on-board register is rising-edge triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data setup-and-hold times as shown in the
timing diagram. Although the AD9732 is designed to provide
isolation of the digital inputs to the analog output, some cou-
pling of digital transitions is inevitable. Digital feedthrough can
be minimized by forming a low-pass filter at the digital input by
using a resistor in series with the capacitance of each digital
input. This common high speed DAC application technique has
the effect of isolating digital input noise from the analog output.
AD9732
APPROX
+V
S
1.4V
REFERENCE IN
References
The internal bandgap reference, control amplifier and reference
input are pinned out to provide maximum user flexibility in
configuring the reference circuitry for the AD9732. When using
the internal reference, REF OUT (Pin 25) should be connected
to CONTROL AMP IN (Pin 26). CONTROL AMP OUT (Pin
24) should be connected to REF IN (Pin 23). A 0.1 µF ceramic
capacitor connected from Pin 23 to GND improves settling time
by decoupling switching noise from the current sink baseline. A
reference current cell provides feedback to the control amplifier
by sinking current through RSET (Pin 17).
Figure 19. Wideband Multiplying Circuit
Analog Output
The switch network provides complementary current outputs
IOUT and IOUTB. The design of the AD9732 is based on statisti-
cal current source matching, which provides a 10-bit linearity
without trim. Current is steered to either IOUT or IOUTB in pro-
portion to the digital input word. The sum of the two currents is
always equal to the full-scale output current. The current can be
converted to a voltage by resistive loading as shown in Figure
20. Both IOUT and IOUTB should be equally loaded for best over-
all performance. The voltage that is developed is the product of
the output current and the value of the load resistor.
Full-scale current is determined by CONTROL AMP IN and
R
SET according to the following equation:
I
OUT(FS) = 32 ([CONTROL AMP IN – (+VS)]/RSET
)
The internal reference is nominally –1.25 V (referenced to
Analog +VS), with a tolerance of ±8% and typical drift over
temperature of 150 ppm/°C. If greater accuracy or temperature
stability is required, an external reference can be used. The
AD589 reference features 10 ppm/°C drift over the 0°C to
+70°C temperature range.
EVALUATION BOARD
The performance characteristics of the AD9732 make it ideally
suited for direct digital synthesis (DDS) and other waveform
synthesis applications. The AD9732 evaluation board provides a
platform for analyzing performance under optimum layout con-
ditions. The AD9732 also provides a reference for high speed
circuit board layout techniques.
Two modes of multiplying operation are possible with the
AD9732. Signals with bandwidths up to 2.5 MHz and input
swings from 3.8 V to 4.4 V can be applied to the CONTROL
AMP IN pin as shown in Figure 18. Because the control ampli-
fier is internally compensated, the 0.1 µF capacitor discussed
above can be reduced to maximize the multiplying bandwidth.
REV. A
–9–
AD9732
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 20. Evaluation Board
–10–
REV. A
AD9732
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.03 (0.762)
8؇
0؇
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
REV. A
–11–
相关型号：
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