AD9059BRS [ADI]
Dual 8-Bit, 60 MSPS A/D Converter; 双路，8位， 60 MSPS A / D转换器
| 型号： | AD9059BRS |
| 厂家： | 
ADI |
| 描述： | Dual 8-Bit, 60 MSPS A/D Converter |
| 文件： | 总12页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Dual 8-Bit, 60 MSPS A/D Converter
AD9059
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Dual 8-Bit ADCs on a Single Chip
Low Pow er: 400 m W Typical
On-Chip +2.5 V Reference and T/ Hs
1 V p-p Analog Input Range
Single +5 V Supply Operation
+5 V or +3 V Logic Interface
120 MHz Analog Bandw idth
Pow er-Dow n Mode: < 12 m W
V
PWRDN
V
D
DD
AD9059
8
AINA
VREF
D7A–D0A
T/H
ADC
A
ENCODE
+2.5V
APPLICATIONS
8
AINB
T/H
ADC
D7B–D0B
Digital Com m unications (QAM Dem odulators)
RGB & YC/ Com posite Video Processing
Digital Data Storage Read Channels
Medical Im aging
B
GND
Digital Instrum entation
P RO D UCT D ESCRIP TIO N
P IN CO NFIGURATIO N
T he AD9059 is a dual 8-bit monolithic analog-to-digital con-
verter optimized for low cost, low power, small size, and ease of
use. With a 60 MSPS encode rate capability and full-power
analog bandwidth of 120 MHz typical, the component is ideal
for applications requiring multiple ADCs with excellent dy-
namic performance.
1
2
28
27
26
25
AINA
VREF
AINB
GND
3
PWRDN
ENCODE
4
V
D
V
D
5
24 GND
GND
T o minimize system cost and power dissipation, the AD9059
includes an internal +2.5 V reference and dual track-and-hold
circuits. T he ADC requires only a +5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.
AD9059
TOP VIEW
(Not to Scale)
V
6
23
22
21
20
19
18
17
16
V
DD
DD
D7A (MSB)
D6A
7
D7B (MSB)
D6B
8
D5A
9
D5B
D4A
10
11
12
13
14
D4B
T he AD9059’s single encode input is T T L/CMOS compatible
and simultaneously controls both internal ADC channels. T he
parallel 8-bit digital outputs can be operated from +5 V or +3 V
supplies. A power-down function may be exercised to bring to-
tal consumption to < 12 mW when ADC data is not required
for lengthy periods of time. In power-down mode the digital
outputs are driven to a high impedance state.
D3A
D3B
D2A
D2B
D1A
D1B
D0A (LSB)
15 D0B (LSB)
Fabricated on an advanced BiCMOS process, the AD9059
is available in a space saving 28-lead surface mount plastic
package (28 SSOP) and is specified over the industrial
(–40°C to +85°C) temperature range.
Customers desiring single channel digitization may consider the
AD9057, a single 8-bit, 60 MSPS monolithic based on the
AD9059 ADC core. T he AD9057 is available in a 20-lead sur-
face mount plastic package (20 SSOP) and is specified over the
industrial temperature range.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD9059–SPECIFICATIONS
(V = +5 V, V = +3 V; external reference; ENCODE = 60 MSPS unless otherwise noted)
D
DD
ELECTRICAL CHARACTERISTICS
AD 9059BRS
Typ
P aram eter
Tem p
Test Level
Min
Max
Units
RESOLUT ION
8
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
Full
+25°C
Full
I
VI
I
VI
VI
I
VI
V
0.75
0.75
2.0
2.5
2.0
2.5
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Gain Error1
GUARANT EED
–6
–8
–2.5
+6
+8
% FS
% FS
ppm/°C
Gain T empco1
Full
±70
ANALOG INPUT
Input Voltage Range (Centered at +2.5 V)
Input Offset Voltage
+25°C
+25°C
Full
+25°C
+25°C
+25°C
+25°C
V
I
VI
V
V
I
1.0
0
V p-p
mV
mV
kΩ
pF
µA
–15
–25
+15
+25
Input Resistance
Input Capacitance
Input Bias Current
Analog Bandwidth
150
2
6
16
V
120
MHz
CHANNEL MAT CHING (A to B)
Gain Delta
Input Offset Voltage Delta
+25°C
+25°C
V
V
±1
±4
% FS
mV
BANDGAP REFERENCE
Output Voltage
T emperature Coefficient
Full
Full
VI
V
2.4
60
2.5
±10
2.6
V
ppm/°C
SWIT CHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Full
Full
+25°C
+25°C
Full
VI
IV
V
V
IV
IV
MSPS
MSPS
ns
ps, rms
ns
5
2.7
5
6.6
9.5
Aperture Uncertainty (Jitter)
Output Valid T ime (tV)2
4.0
2
Output Propagation Delay (tPD
)
Full
14.2
ns
DYNAMIC PERFORMANCE3
T ransient Response
Overvoltage Recovery T ime
+25°C
+25°C
V
V
9
9
ns
ns
Signal-to-Noise Ratio (SINAD) (with Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
+25°C
+25°C
I
V
40
44.5
43.5
dB
dB
Effective Number of Bits
fIN = 10.3 MHz
fIN = 76 MHz
Signal-to-Noise Ratio (SNR) (Without Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
+25°C
+25°C
I
V
6.35
42
7.1
6.9
Bits
Bits
+25°C
+25°C
I
V
46
45
dB
dB
2nd Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
3rd Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
T wo-T one Intermodulation Distortion (IMD)
Channel Crosstalk Rejection
Differential Phase
+25°C
+25°C
I
V
–50
–46
–62
–54
dBc
dBc
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
–60
–54
–52
–50
0.8
dBc
dBc
dBc
dBc
Degrees
%
V
V
V
V
V
Differential Gain
1.0
–2–
REV. 0
AD9059
AD 9059BRS
Typ
P aram eter
Tem p
Test Level
Min
Max
Units
DIGIT AL INPUT S
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulse Width High (tEH
Encode Pulse Width Low (tEL
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
2.0
V
V
0.8
±1
±1
µA
µA
pF
ns
ns
4.5
)
IV
IV
6.7
6.7
166
166
)
DIGIT AL OUT PUT S
Logic “1” Voltage (VDD = +3 V)
Logic “1” Voltage (VDD = +5 V)
Logic “0” Voltage (VDD = +3 V or +5 V)
Output Coding
Full
Full
Full
VI
IV
VI
2.95
4.95
V
V
V
0.05
Offset Binary Code
POWER SUPPLY
VD Supply Current (VD = +5 V)
VDD Supply Current (VDD = +3 V)4
Power Dissipation5, 6
Power-Down Dissipation
Power Supply Rejection Ratio (PSRR)
Full
Full
Full
Full
+25°C
VI
VI
VI
VI
I
72
13
400
6
92
15
505
12
mA
mA
mW
mW
mV/V
15
NOT ES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. T he digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ±40 µA.
3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4Digital supply current based on VDD = +3 V output drive with <10 pF loading under dynamic test conditions.
5Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (VD = +5 V ± 5%, VDD = +3 V ± 5%).
6T ypical thermal impedance for the RS style (SSOP) 28-pin package: θJC = 39°C/W, θCA = 70°C/W, θJA = 109°C/W.
Specifications subject to change without notice.
EXP LANATIO N O F TEST LEVELS
Test Level
ABSO LUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating T emperature . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
I
–
–
100% production tested.
II
100% production tested at +25°C and sample tested at
specified temperatures.
III
IV
–
–
Sample tested only.
Parameter is guaranteed by design and characteriza-
tion testing.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
V
VI
–
–
Parameter is a typical value only.
100% production tested at +25°C; guaranteed by
design and characterization testing for industrial tem-
perature range.
O RD ERING GUID E
Model
Tem perature Range
P ackage O ption
AD9059BRS
AD9059/PCB
–40°C to +85°C
+25°C
RS-28
Evaluation Board
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9059 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD9059
P IN D ESCRIP TIO NS
Function
N
N + 3
N + 5
P in No.
1, 28
2
Nam e
AIN
N + 1
N + 2
AINA, AINB Analog Inputs for ADC A and B.
N + 4
tA
VREF
Internal Voltage Reference (+2.5 V
T ypical); Bypass with 0.1 µF to
Ground or Overdrive with External
Voltage Reference.
tEH tEL
ENCODE
tV
3
PWRDN
Power-Down Function Select;
Logic HIGH for Power-Down
Mode (Digital Outputs Go to High-
Impedance State).
DIGITAL
OUTPUTS
N – 3
N – 2
N – 1
N
N + 1
N + 2
tPD
MAX
MIN
TYP
2.7ns
4, 25
VD
Analog +5 V Power Supply.
Ground.
tA
APERTURE DELAY
PULSE WIDTH HIGH
PULSE WIDTH LOW
OUTPUT VALID TIME
OUTPUT PROP DELAY
5, 24, 27
6, 23
GND
VDD
6.7ns
6.7ns
4.0ns
tEH
tEL
tV
166ns
166ns
Digital Output Power Supply.
Nominally +3 V to +5 V.
6.6ns
9.5ns
tPD
14.2ns
7–14
22–15
26
D7A–D0A
D7B–D0B
ENCODE
Digital Outputs of ADCA.
Digital Outputs of ADCB.
Figure 1. Tim ing Diagram
Encode Clock for ADCs A and B
(ADCs Sample Simultaneously On
the Rising Edge of ENCODE).
P IN CO NFIGURATIO N
1
2
28
27
26
25
AINA
VREF
AINB
GND
Table I. D igital Coding (VREF = +2.5 V)
3
PWRDN
ENCODE
Analog Input
Voltage Level
D igital O utput
4
V
D
V
D
5
24 GND
GND
3.0 V
Positive Full Scale
Midscale + 1/2 LSB
Midscale – 1/2 LSB
Negative Full Scale
1111 1111
1000 0000
0111 1111
0000 0000
AD9059
TOP VIEW
(Not to Scale)
V
6
23
22
21
20
19
18
17
16
V
2.502 V
2.498 V
2.0 V
DD
DD
D7A (MSB)
D6A
7
D7B (MSB)
D6B
8
D5A
9
D5B
D4A
10
11
12
13
14
D4B
D3A
D3B
D2A
D2B
D1A
D1B
D0A (LSB)
15 D0B (LSB)
REV. 0
–4–
AD9059
–30
–35
–40
–45
–50
–55
0
ENCODE = 60MSPS
ANALOG IN = 10.3MHz, –0.5dBFS
SINAD = 43.9dB
ENOB = 7.0 BITS
SNR = 45.1dB
ENCODE = 60MSPS
AIN = –0.5dBFS
–10
–20
–30
–40
–50
2ND HARMONIC
–60
–70
–80
–60
–65
–70
3RD HARMONIC
–90
0
20
40
60
80
100
120
140
160
0
30
FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
Figure 2. FFT Spectral Plot 60 MSPS, 10.3 MHz
Figure 5. Harm onic Distortion vs. AIN Frequency
0
0
ENCODE = 60MSPS
F1 IN = 9.5MHz @ –7.0dBFS
F2 IN = 9.9MHz @ –7.0dBFS
2F1 - F2 = –52.0dBc
ENCODE = 60MSPS
–10
–10
ANALOG IN = 76MHz, –0.5dBFS
SINAD = 43.0dB
–20
–20
ENOB = 6.85 BITS
2F2 - F1 = –53.0dBc
SNR = 44.1dB
–30
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
0
10
20
30
0
30
FREQUENCY – MHz
FREQUENCY – MHz
Figure 3. Spectral Plot 60 MSPS, 76 MHz
Figure 6. Two-Tone IMD
46
54
48
42
36
30
24
18
12
6
SNR
AIN = 10.3MHz, –0.5dBFS
SNR
44
42
SINAD
SINAD
40
38
ENCODE = 60MSPS
AIN = –0.5dBFS
36
34
32
30
0
20
40
60
80
100
120
140
160
5
10
20
30
40
50
60
70
80
90
ANALOG INPUT FREQUENCY – MHz
ENCODE RATE – MSPS
Figure 4. SINAD/SNR vs. AIN Frequency
Figure 7. SINAD/SNR vs. Encode Rate
REV. 0
–5–
AD9059
12
600
550
500
450
400
350
300
250
AIN = 10.3MHz, –0.5dBFS
11
10
V
= +3V
DD
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
V
= +5V
DD
V
= +5V
DD
V
= +3V
50
DD
5
10
20
30
40
60
70
80
90
–45
0
25
TEMPERATURE – °C
70
90
ENCODE RATE – MSPS
Figure 8. Power Dissipation vs. Encode Rate
Figure 11. tPD vs. Tem perature/Supply (+3 V/+5 V)
46
45.5
SNR
45.5
45
SNR
45.0
44.5
44.5
44
SINAD
44.0
43.5
43
SINAD
43.5
43.0
42.5
42
ENCODE = 60MSPS
AIN = 10.3MHz, –0.5dBFS
ENCODE = 60MSPS
AIN = 10.3MHz, –0.5dBFS
42.5
41.5
42.0
41.5
41
40.5
5.8
6.7
7.5
8.35
9.2
10
10.9
–45
0
25
TEMPERATURE –
70
90
ENCODE HIGH PULSE WIDTH – ns
°
C
Figure 9. SINAD/SNR vs. Tem perature
Figure 12. SINAD/SNR vs. Encode Pulse Width
0
0
–1
–0.2
–2
–3
–4
–5
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–6
ENCODE = 60MSPS
–7
AIN = –0..5dBFS
–8
–9
–10
–45
0
25
70
90
1
100
ANALOG FREQUENCY – MHz
200
2
5
10
500
20
50
TEMPERATURE – °C
Figure 10. ADC Gain vs. Tem perature (With External
+2.5 V Reference)
Figure 13. ADC Frequency Response
REV. 0
–6–
AD9059
TH EO RY O F O P ERATIO N
applied to the VREF pin to overdrive the internal voltage refer-
ence for gain adjustment of up to ±10% (the VREF pin is inter-
nally tied directly to the ADC circuitry). ADC gain and offset
will vary simultaneously with external reference adjustment with
a 1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference
varies ADC gain by 2% and ADC offset by 50 mV).
T he AD9059 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology
to provide dual high performance 8-bit ADCs in a single low
cost monolithic device. T he design architecture ensures low
power, high speed, and 8-bit accuracy.
T he AD9059 provides two linked ADC channels that are
clocked from a single ENCODE input (refer to block diagram).
T he two ADC channels simultaneously sample the analog in-
puts (AINA and AINB) and provide non-interleaved parallel
digital outputs (D0A–D7A and D0B–D7B). T he voltage refer-
ence (VREF) is internally connected to both ADCs so channel
gains and offsets will track if external reference control is
desired.
T heoretical input voltage range versus reference input voltage
may be calculated from the following equations:
VRANGE (p-p) = VREF/2.5
VMIDSCALE = VREF
VTOP-OF-RANGE = VREF + VRANGE/2
VBOTTOM-OF-RANGE = VREF – VRANGE/2
T he external reference should have a 1 mA minimum sink/
source current capability to ensure complete overdrive of the
internal voltage reference.
T he analog input signal is buffered at the input of each ADC
channel and applied to a high speed track-and-hold. T he T /H
circuit holds the analog input value during the conversion pro-
cess (beginning with the rising edge of the ENCODE com-
mand). T he T /H’s output signal passes through the gray code
and flash conversion stages to generate coarse and fine digital
representations of the held analog input level. Decode logic
combines the multistage data and aligns the 8-bit word for
strobed outputs on the rising edge of the ENCODE command.
T he MagAmp/Flash architecture of the AD9059 results in three
pipeline delays for the output data.
D igital Logic (+5 V/+3 V System s)
T he digital inputs and outputs of the AD9059 can easily be
configured to interface directly with +3 V or +5 V logic systems.
T he encode and power-down (PWRDN) inputs are CMOS
stages with T T L thresholds of 1.5 V, making the inputs compat-
ible with T T L, +5 V CMOS, and +3 V CMOS logic families.
As with all high speed data converters, the encode signal should
be clean and jitter free to prevent degradation of ADC dynamic
performance.
USING TH E AD 9059
T he AD9059’s digital outputs will also interface directly with
+5 V or +3 V CMOS logic systems. T he voltage supply pins
(VDD) for these CMOS stages are isolated from the analog VD
voltage supply. By varying the voltage on these supply pins the
digital output HIGH levels will change for +5 V or +3 V sys-
tems. T he VDD pins are internally connected on the AD9059
die. Care should be taken to isolate the VDD supply voltages
from the +5 V analog supply to minimize noise coupling into
the ADCs.
Analog Inputs
T he AD9059 provides independent single-ended high imped-
ance (150 kΩ) analog inputs for the dual ADCs. Each input
requires a dc bias current of 6 µA (typical) centered near +2.5 V
(±10%). T he dc bias may be provided by the user or may be
derived from the ADC’s internal voltage reference. Figure 14
shows a low cost dc bias implementation allowing the user to
capacitively couple ac signals directly into the ADC without ad-
ditional active circuitry. For best dynamic performance the
VREF pin should be decoupled to ground with a 0.1 µF capaci-
tor (to minimize modulation of the reference voltage), and the
bias resistor should approximately 1 kΩ.
T he AD9059 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic HIGH). A 200 ns (minimum) power-down time should
be provided before a high impedance characteristic is required.
A 200 ns power-up period should be provided to ensure accu-
rate ADC output data after reactivation (valid output data is
available three clock cycles after the 200 ns delay).
Figure 15 shows typical connections for high performance dc bi-
asing using the ADC’s internal voltage reference. All compo-
nents may be powered from a single +5 V supply (example
analog input signals are referenced to ground).
Tim ing
Voltage Refer ence
T he AD9059 is guaranteed to operate with conversion rates
from 5 MSPS to 60 MSPS. At 60 MSPS the ADC is designed
to operate with an encode duty cycle of 50%, but performance
is insensitive to moderate variations. Pulse width variations of
up to ±10% (allowing the encode signal to meet the minimum/
maximum HIGH/LOW specifications) will cause no degrada-
tion in ADC performance (refer to Figure 1 Timing Diagram).
A stable and accurate +2.5 V voltage reference is built into the
AD9059 (VREF). T he reference output is used to set the ADC
gain/offset and can provide dc bias for the analog input signals.
T he internal reference is tied to the ADC circuitry through a
800 Ω internal impedance and is capable of providing 300 µA
external drive current (for dc biasing the analog input or other
user circuitry).
Due to the linked ENCODE architecture of the ADCs, the
AD9059 cannot be operated in a two-channel ping-pong mode.
Some applications may require greater accuracy, improved tem-
perature performance, or gain adjustments which cannot be ob-
tained using the internal reference. An external voltage may be
REV. 0
–7–
AD9059
1kΩ
P ower D issipation
+5V
T he power dissipation of the AD9059 is specified to reflect a
typical application setup under the following conditions: en-
code is 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, VD
is +5 V, VDD is +3 V, and digital outputs are loaded with 7 pF
typical (10 pF maximum). T he actual dissipation will vary as
these conditions are modified in user applications. Figure 8
shows typical power consumption for the AD9059 versus ADC
encode frequency and VDD supply voltage.
+5V
1kΩ
AD8041
VIN
A
1
3
AINA
10kΩ
V
REF
10kΩ
+5V
0.1µF
AD9059
AD8041
+5V
28
1kΩ
AINB
VIN
B
(–0.5V TO +0.5V)
1kΩ
0.1µF
VIN
1
3
AINA
A
(1V p-p)
1kΩ
1kΩ
Figure 15. DC Coupled AD9059 (VIN Inverted)
AD9059
EXTERNAL V
V
AD9059
REF
REF
(OPTIONAL)
0.1µF
0.1µF
ADC
ADC
BPF
BPF
90°
IF IN
28
VIN
B
AINB
(1V p-p)
VCO
VCO
Figure 14. Capacitively Coupled AD9059
Figure 16. I and Q Digital Receiver
A power-down function allows users to reduce power dissipa-
tion when ADC data is not required. A T T L/CMOS HIGH
signal (PWRDN) shuts down portions of the dual ADC and
brings total power dissipation to less than 10 mW. The internal
bandgap voltage reference remains active during power-down
mode to minimize ADC reactivation time. If the power-down
function is not desired, Pin 3 should be tied to ground. Both
ADC channels are controlled simultaneously by the PWRDN
pin; they cannot be shut down or turned on independently.
T he high sampling rate and analog bandwidth of the AD9059
are ideal for computer RGB video digitizer applications. With a
full-power analog bandwidth of 2× the maximum sampling rate,
the ADC provides sufficient pixel-to-pixel transient settling
time to ensure accurate 60 MSPS video digitization. Figure 17
shows a typical RGB video digitizer implementation for the
AD9059.
AD9059
Applications
8
ADC
ADC
RED
T he wide analog bandwidth of the AD9059 makes it attractive
for a variety of high performance receiver and encoder applica-
tions. Figure 16 shows the dual ADC in a typical low cost I & Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. T he excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (refer
to Figure 3, Spectral Plot). IF sampling eliminates or simplifies
analog mixer and filter stages to reduce total system cost and
power.
8
GREEN
H-SYNC
BLUE
PIXEL CLOCK
PLL
8
ADC
ADC
AD9059
Figure 17. RGB Video Encoder
REV. 0
–8–
AD9059
+V
DD
+3V TO +5V
+V
+V
+V
D
D
D
3kΩ
800Ω
500Ω
ENCODE
PWRDN
AIN
D0–D7
V
V
REF
REF
2.5kΩ
+2.5V
Digital Inputs
Digital Outputs
Voltage Reference
Analog Inputs
Figure 18. Equivalent Circuits
Evaluation Boar d
Analog input signals to the board should be 1 V p-p into 50 Ω
for full-scale ADC drive. For ac coupled operation, connect E7
to E8 (analog input A to C12 feedthrough capacitor), E13 to
E15 (C12 to R15 termination resistor for channel A), E4 to E6
(analog input B to C11 feedthrough capacitor), and E10 to E12
(C11 to R14 termination resistor for channel B) using the board
jumper connectors.
T he AD9059/PCB evaluation board provides an easy-to-use
analog/digital interface for the dual 8-bit, 60 MSPS ADC. T he
board includes typical hardware configurations for a variety of
high speed digitization evaluations. On-board components in-
clude the AD9059 (in the 28-pin SSOP package), optional ana-
log input buffer amplifiers, digital output latches, board timing
drivers, and configurable jumpers for ac coupling, dc coupling,
and power-down function testing. T he board is configured at
shipment for dc coupling using the AD9059’s internal reference.
T he on-board reference voltage may be used to drive the ADC
or an external reference may be applied. T he standard configu-
ration employs the internal voltage reference without any exter-
nal connection requirements. An external voltage reference may
be applied at board connector input REF to overdrive the lim-
ited current output of the AD9059’s internal voltage reference.
T he external voltage reference should be +2.5 V typical.
For dc coupled analog input applications, amplifiers U3 and U4
are configured to operate as unity gain inverters with adjustable
offset for the analog input signals. For full-scale ADC drive
each analog input signal should be 1 V p-p into 50 Ω referenced
to ground. Each amplifier offsets its analog signal by +VREF
(+2.5 V typical) to center the voltage for proper ADC input
drive. For dc coupled operation, connect E7 to E9 (analog in-
put A to R11), E14 to E13 (amplifier output to analog input A
of AD9059), E4 to E5 (analog input B to R10), and E11 to E10
(amplifier output to analog input B of AD9059) using the board
jumper connectors.
T he power-down function of the AD9059 can be exercised
through a board jumper connection. Connect E2 to E1 (+5 V
to PWRDN) for power-down mode operation. For normal op-
eration, connect E3 to E1 (ground to PWRDN).
T he encode signal source should be T T L/CMOS compatible
and capable of driving a 50 Ω termination. T he digital outputs
of the AD9059 are buffered through latches on the evaluation
board (U5 and U6) and are available for the user at connector
Pins 30–37 and Pins 22–29. Latch timing is derived from the
ADC ENCODE clock and a digital clocking signal is provided
for the board user at connector Pins 2 and 21.
For ac coupled analog input applications, amplifiers U3 and U4
are removed from the analog signal paths. T he analog signals
are coupled through capacitors C11 and C12, each terminated
to the VREF voltage through separate 1 kΩ resistors (providing
bias current for the AD9059 analog inputs, AINA and AINB).
REV. 0
–9–
AD9059
J9, V
DD
ANALOG IN–A
BNC
U4
C12
0.1µF
AD8041Q
E8
E9
J5
C9
0.1µF
C16
10µF
8
7
6
5
1
2
3
4
E7
NC
DIS
P2
C37DRPF
R5
10Ω
U1
AD9059RS
+5V
+V
S
E14
E15
R13
50Ω
R11
1kΩ
E13
1
1
2
28
AINA
AINB
–V
NC
S
2
3
27
26
25
24
23
22
21
20
19
18
17
16
15
REF
GND
3
R7
1kΩ
R15
1kΩ
PWRDN
ENC
U5
74ACQ574
4
4
+5V
V
D
V
D
+5V
5
5
GND
GND
C10
0.1µF
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
6
C17
10µF
R8
10kΩ
6
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
8D
7D
6D
5D
4D
3D
2D
1D
CK
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
V
V
DD
DD
7
7
C8
0.1µF
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B
8
8
R9
10kΩ
J1, REF
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
10
11
12
13
14
E2
E3
+5V
E1
PWRDN
E12
E11
R14
1kΩ
OE
11
1
R8
1kΩ
E10
U6
74ACQ574
R4
10Ω
U3
AD8041Q
9
12
13
14
15
16
17
18
19
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
8D
7D
6D
5D
4D
3D
2D
1D
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
ANALOG IN–B
BNC
8
7
6
5
4
3
2
R10
1kΩ
8
7
6
5
1
2
3
4
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
NC
DIS
E5
E6
J4
+V
+5V
S
E4
C11
0.1µF
R12
50Ω
–V
NC
S
U7
74AC00
CK
OE
30
31
32
33
34
35
36
37
BNC
J10
1
11
1
3
2
J11, V
ENCODE
D
C6
0.1µF
C7
0.1µF
C14
0.1µF
U7
74AC00
R15
50Ω
+5V
4
5
C3
0.1µF
C4
0.1µF
C5
0.1µF
C13
0.1µF
C15
10µF
6
U7
74AC00
DECOUPLING CAPS
12
13
11
J12, GND
Figure 19. AD9059 Dual Evaluation Board Schem atic
REV. 0
–10–
AD9059
Figure 20. Evaluation Board Layout (Top)
Figure 21. Evaluation Board Layout (Bottom )
REV. 0
–11–
AD9059
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead SSO P
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.03 (0.762)
8°
0°
0.015 (0.38)
0.010 (0.25)
0.0256
(0.65)
BSC
0.008 (0.203)
0.002 (0.050)
0.022 (0.558)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
REV. 0
–12–
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