AD9060KZ [ADI]
10-Bit 75 MSPS A/D Converter; 10位75 MSPS A / D转换器
| 型号： | AD9060KZ |
| 厂家： | 
ADI |
| 描述： | 10-Bit 75 MSPS A/D Converter |
| 文件： | 总12页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit 75 MSPS
A/D Converter
a
AD9060
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Monolithic 10-Bit/ 75 MSPS Converter
ECL Outputs
LSBS
MSB
INVERT
INVERT
61 59
Bipolar (؎1.75 V) Analog Input
57 dB SNR @ 2.3 MHz Input
Low (45 pF) Input Capacitance
MIL-STD-883 Com pliant Versions Available
8
9
ANALOG IN
OVERFLOW
+VREF
12
11
+VSENSE
APPLICATIONS
Digital Oscilloscopes
Medical Im aging
Professional Video
Radar Warning/ Guidance System s
Infrared System s
R/2
R
512
C
O
M
P
A
R
A
T
385
384
R/2
R/2
7
3/4REF
1/2REF
1/4REF
51 OVERFLOW
R
R
50
49
48
D9 (MSB)
GENERAL D ESCRIP TIO N
D
E
C
O
D
E
D8
D7
T he AD9060 A/D converter is a 10-bit monolithic converter ca-
pable of word rates of 75 MSPS and above. Innovative architec-
ture using 512 input comparators instead of the traditional 1024
required by other flash converters reduces input capacitance and
improves linearity.
L
A
T
257
256
OVERFLOW
1024
OVERFLOW
D6
47
46
23
R/2
R/2
1
D5
D4
O
R
L
O
G
I
C
H
10
R
R
D3
D2
22
21
Inputs and outputs are ECL-compatible, which makes the
AD9060 the recommended choice for systems with conversion
rates >30 MSPS to minimize system noise. An overflow bit is
L
C
20 D1
D0 (LSB)
129
128
A
T
19
R/2
R/2
63
provided to indicate analog input signals greater than +VSENSE
.
Voltage sense lines are provided to ensure accurate driving of
the ±VREF voltages applied to the units. Quarter-point taps on
the resistor ladder help optimize the integral linearity of the
unit.
C
H
E
S
R
R
2
1
Either 68-pin ceramic leaded (gull wing) packages or ceramic
R
LCCs are available and specifically designed for low thermal im-
pedances. T wo performance grades for temperatures of both
0°C to +70°C and –55°C to +125°C ranges are offered to allow
the user to select the linearity best suited for each application.
Dynamic performance is fully characterized and production
tested at +25°C. MIL-ST D-883 units are available.
R/2
–VSENSE
–VREF
57
56
ENCODE 14
13
ENCODE
GROUND
–VS
+VS
T he AD9060 A/D converter is available in versions compliant
with MIL-ST D-883. Refer to the Analog Devices Military Prod-
ucts Databook or current AD9060/883B data sheet for detailed
specifications.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD9060–SPECIFICATIONS
ABSO LUTE MAXIMUM RATINGS1
3/4REF, 1/2REF, 1/4REF Current . . . . . . . . . . . . . . . . . . ±10 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating T emperature
AD9060JE/KE/JZ/KZ . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction T emperature2 . . . . . . . . . . . . . . . +175°C
Lead Soldering T emp (10 sec) . . . . . . . . . . . . . . . . . . +300°C
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +2 V
+VREF, –VREF, 3/4REF, 1/2REF, 1/4REF . . . . . . . . . –2 V to +2 V
+VREF to –VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
ENCODE, ENCODE . . . . . . . . . . . . . . . . . . . . . . . 0 V to –VS
SENSE = ؎1.75 V; ENCODE = 60 MSPS
ELECTRICAL CHARACTERISTICS (+V = +5 V; –V = –5.2 V; ؎V
unless otherwise noted)3
S
S
Test
AD 9060JE/JZ
Typ
AD 9060KE/KZ
Typ
P aram eter (Conditions)
Tem p
Level
Min
Max
Min
Max
Units
RESOLUT ION
10
10
Bits
DC ACCURACY3
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
VI
VI
1.0
1.25
1.5
2.0
0.75
1.0
1.0
1.25
1.5
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
1.25
2.5
2.0
Full
Guaranteed
ANALOG INPUT
Input Bias Current4
+25°C
Full
+25°C
+25°C
+25°C
I
VI
I
V
V
0.4
1.0
2.0
0.4
1.0
2.0
mA
mA
kΩ
pF
MHz
Input Resistance
Input Capacitance4
Analog Bandwidth
2.0
7.0
45
175
2.0
7.0
45
175
REFERENCE INPUT
Reference Ladder Resistance
+25°C
Full
Full
I
VI
V
22
14
37
0.1
45
45
50
56
66
22
14
37
0.1
45
45
50
56
66
Ω
Ω
Ω/°C
Ladder T empco
Reference Ladder Offset
T op of Ladder
+25°C
Full
+25°C
Full
I
VI
I
VI
V
90
90
90
90
90
90
90
90
mV
mV
mV
mV
Bottom of Ladder
Offset Drift Coefficient
Full
µV/°C
SWIT CHING PERFORMANCE
Conversion Rate
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
75
2
75
2
MSPS
ns
ps, rms
ns
ns
ns
Aperture Delay (tA)
V
V
I
I
I
1
5
4
1
1
1.5
1
5
4
1
1
1.5
Aperture Uncertainty (Jitter)
5
Output Delay (tOD
Output Rise T ime
Output Fall T ime
)
9
3
3
3
9
3
3
3
Output T ime Slew5
I
ns
DYNAMIC PERFORMANCE
T ransient Response
Overvoltage Recovery T ime
Effective Number of Bits (ENOB)
fIN = 2.3 MHz
+25°C
+25°C
V
V
10
10
10
10
ns
ns
+25°C
+25°C
+25°C
I
IV
IV
8.7
8.0
7.0
9.1
8.6
7.4
8.7
8.0
7.0
9.1
8.6
7.4
Bits
Bits
Bits
fIN = 10.3 MHz
fIN = 29.3 MHz
Signal-to-Noise Ratio6
fIN = 2.3 MHz
+25°C
+25°C
+25°C
I
I
I
54
51
44
56
54
47
54
51
44
56
54
47
dB
dB
dB
fIN = 10.3 MHz
fIN = 29.3 MHz
–2–
REV. A
AD9060
Test
Level
AD 9060JE/JZ
Typ
AD 9060KE/KZ
Typ
P aram eter (Conditions)
Tem p
Min
Max
Min
Max
Units
DYNAMIC PERFORMANCE
(CONT INUED)
Signal-to-Noise Ratio6
(Without Harmonics)
fIN = 2.3 MHz
+25°C
+25°C
+25°C
I
I
I
54
51
46
56
55
48
54
51
46
58
55
48
dB
dB
dB
fIN = 10.3 MHz
fIN = 29.3 MHz
Harmonic Distortion
fIN = 2.3 MHz
fIN = 10.3 MHz
+25°C
+25°C
+25°C
I
I
I
61
55
47
65
58
50
61
55
47
65
58
50
dBc
dBc
dBc
fIN = 29.3 MHz
T wo-T one Intermodulation
Distortion Rejection7
Differential Phase
Differential Gain
+25°C
+25°C
+25°C
V
V
V
70
0.5
1
70
0.5
1
dBc
Degree
%
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Pulse Width (High)
Pulse Width (Low)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
–1.1
–1.1
V
V
–1.5
300
300
–1.5
300
300
150
150
5
150
150
5
µA
µA
pF
ns
ns
I
I
6
6
6
6
DIGIT AL OUT PUT S
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
–1.1
–1.1
V
V
–1.5
–1.5
POWER SUPPLY
+VS Supply Current
+25°C
Full
+25°C
Full
+25°C
Full
VI
VI
VI
VI
VI
VI
420
150
2.8
500
500
180
190
3.3
420
150
2.8
500
500
180
190
3.3
mA
mA
mA
mA
W
–VS Supply Current
Power Dissipation
3.5
3.5
W
Power Supply Rejection
Ratio (PSRR)8
Full
VI
6
10
6
10
mV/V
NOT ES
1Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2T ypical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θJC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W
(air flow = 500 LFM). 68-pin ceramic LCC: θJC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM).
33/4REF, 1/2REF and 1/4REF reference ladder taps are driven from dc sources at +0.875 V, 0 V and –0.875 V, respectively. Outputs terminated through 100 Ω to –2.0 V;
CL < 4 pF. Accuracy of the overflow comparator is not tested and not included in linearity specifications.
4Measured with ANALOG IN = +VSENSE
5Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D 0–D9. Output skew
measured as worst-case difference in output delay among D 0–D9.
6RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.
7Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change m +VS or –VS.
Specifications subject to change without notice.
REV. A
–3–
AD9060
EXP LANATIO N O F TEST LEVELS
Test Level
I
– 100% production tested.
II – 100% production tested at +25°C and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V
– Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes
for commercial/industrial devices.
O RD ERING GUID E
D IE LAYO UT AND MECH ANICAL INFO RMATIO N
Die Dimensions . . . . . . . . . . . . . . . . 206 × 140 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Tem perature
Range
P ackage
O ptions1
D evice
AD9060JZ
AD9060JE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
0°C to +70°C
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
AD9060KZ
AD9060KE
AD9060SZ2
AD9060SE2
AD9060T Z2
AD9060T E2
AD9060/PCB
E-68A
Evaluation Board
NOT ES
1E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
2For specifications, refer to Analog Devices Military Products Databook.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9060 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–4–
AD9060
61
60
9
NC
SENSE
10
NC
+V
LSBs INVERT
NC
+V
REF
–V
–V
ENCODE
ENCODE
SENSE
REF
+V
–V
S
NC
–V
GND
GND
S
S
AD9060
TOP VIEW
(Not to scale)
GND
GND
(LSB) D
OVERFLOW
0
D
1
D
D
D
D
D
(MSB)
9
8
7
6
5
D
2
D
3
D
4
NC
GND
NC
GND
NC
26
27
44
43
AD9060 Pin Designations
AD 9060 P IN D ESCRIP TIO NS
Function
P in No.
Nam e
1
1/2REF
–VS
Midpoint of internal reference ladder.
2, 16, 28, 29, 35,
41, 42, 54, 64
Negative supply voltage; nominally –5.2 V ± 5%.
3, 6, 15, 30, 33, 34,
37, 40, 65, 68
+VS
Positive supply voltage; nominally +5 V ± 5%.
4, 5, 17, 18, 25, 27,
31, 32, 36, 38, 39, 43,
45, 52, 53, 66, 67
GROUND
All ground pins should be connected together and to low-
impedance ground plane.
7
3/4REF
T hree-quarter point of internal reference ladder.
8, 9
11
ANALOG IN
+VSENSE
Analog input; nominally between ±1.75 V.
Voltage sense line to most positive point on internal resistor
ladder. Normally +1.75 V.
12
+VREF
Voltage force connection for top of internal reference ladder.
Normally driven to provide +1.75 V at +VSENSE
.
13
ENCODE
ENCODE
D0–D9
Differential ECL convert signal that starts digitizing process.
ECL-compatible convert command used to begin digitizing process.
ECL-compatible digital output data.
14
19–23, 46–50
51
56
OVERFLOW
–VREF
ECL-compatible output indicating ANALOG IN > +VSENSE
Voltage force connection for bottom of internal reference
.
ladder. Normally driven to provide –1.75 V at –VSENSE
.
57
59
61
63
–VSENSE
Voltage sense line to most negative point on internal
resistor ladder. Normally –1.75 V.
LSBs INVERT
MSB INVERT
1/4REF
Normally grounded. When connected to +VS, lower order
bits (D0–D8) are inverted. Not ECL-compatible.
Normally grounded. When connected to +VS, most
significant bit (MSB; D9) is inverted. Not ECL-compatible.
One-quarter point of internal reference ladder.
REV. A
–5–
AD9060
MIL-STD -883 Com pliance Infor m ation
+
5.0V
T he AD9060 devices are classified within Microcircuits Group
57, T echnology Group D (bipolar A/D converters) and are con-
structed in accordance with MIL-ST D-883. T he AD9060 is
electrostatic sensitive and falls within electrostatic sensitivity
classification Class 1. Percent Defective Allowance (PDA) is
computed based on Subgroup 1 of the specified Group A test
list. Quality Assurance (QA) screening is in accordance with Al-
ternate Method A of Method 5005.
0.1 µF
510 Ω
3,6,15,30,33,34,
37,40,55,65,68
100 Ω
8
9
19
23
D
D
– D
– D
AD1
0
5
4
9
+V
S
ANALOG IN
510 Ω
510 Ω
AD2
AD3
14
13
12
ENCODE
ENCODE
46
51
510 Ω
AD9060
T he following apply: Burn-In per 1015; Life T est per 1005;
Electrical T esting per 5004. (Note: Group A electrical testing
assumes T A = T C = T J.) MIL-ST D-883-compliant devices are
marked with “C” to indicate compliance.
+2V
+V
REF
4,5,17,
18,25,27,
31,32,36,
38,39,43,
–2V
56
–V
REF
GROUND
LSB INVERT
MSB
510 Ω 59
–V
S
45,52,53,66,67
61
INVERT
2,16,28,29,35,
41,42,54,64
STATIC:
AD1 = –2V; AD 2 = ECL HIGH
AD3 = ECL LOW
0.1µF
DYNAMIC:
AD1 = ±2V TRIANGLE WAVE
AD2,AD3 = ECL PULSE TRAIN
–5.2V
AD9060 Burn-ln Connections
AP P LICATIO NS
TH EO RY O F O P ERATIO N
Many of the specifications used to describe analog/digital con-
verters have evolved from system performance requirements in
these applications. Different systems emphasize particular speci-
fications, depending on how the part is used. T he following ap-
plications highlight some of the specifications and features that
make the AD9060 attractive in these systems.
Refer to the AD9060 block diagram. As shown, the AD9060
uses a modified “flash,” or parallel, A/D architecture. T he ana-
log input range is determined by an external voltage reference
(+VREF and –VREF), nominally ±1.75 V. An internal resistor
ladder divides this reference into 512 steps, each representing
two quantization levels. T aps along the resistor ladder (1/4REF
1/2REF and 3/4REF) are provided to optimize linearity. Rated
,
Wideband Receiver s
performance is achieved by driving these points at 1/4, 1/2 and
3/4, respectively, of the voltage reference range.
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence and
spectral analysis all place stringent ac performance requirements
on analog-to-digital converters (ADCs). Frequency domain
characterization of the AD9060 provides signal-to-noise ratio
(SNR) and harmonic distortion data to simplify selection of the
ADC.
T he A/D conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. T he value of the least signifi-
cant bit (LSB) is determined by a unique interpolation scheme
between adjacent comparators. T he decoding logic processes
the comparator outputs and provides a 10-bit code to the out-
put stage of the converter.
Receiver sensitivity is limited by the Signal-to-Noise Ratio (SNR)
of the system. T he SNR for an ADC is measured in the fre-
quency domain and calculated with a Fast Fourier T ransform
(FFT ). T he SNR equals the ratio of the fundamental compo-
nent of the signal (rms amplitude) to the rms value of the
“noise.” T he noise is the sum of all other spectral components,
including harmonic distortion but excluding dc.
Flash architecture has an advantage over other A/D architec-
tures because conversion occurs in one step. T his means the
performance of the converter is limited primarily by the speed
and matching of the individual comparators. In the AD9060, an
innovative interpolation scheme takes advantage of flash archi-
tecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the result
of imperfections in the device transfer function (nonlinearities,
delay mismatch, varying input impedance, etc.). In the ADC,
these spurious signals appear as Harmonic Distortion. Harmonic
Distortion is also measured with an FFT and is specified as the
ratio of the fundamental component of the signal (rms ampli-
tude) to the rms value of the worst case harmonic (usually the
2nd or 3rd).
T hese advantages occur because of using only half the normal
number of input comparator cells to accomplish the conversion.
In addition, a proprietary decoding scheme minimizes error
codes. Input control pins allow the user to select from among
Binary, Inverted Binary, T wos Complement and Inverted T wos
Complement coding (see AD9060 T ruth T able).
REV. A
–6–
AD9060
Im aging
Two-Tone Intermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, third-
order IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is charac-
terized with two, equal amplitude, pure input frequencies. T he
IMD equals the ratio of the power of either of the two input sig-
nals to the power of the strongest third order IMD signal. Un-
like mixers and amplifiers, the IMD does not always behave as it
does in linear devices (reduced input levels do not result in pre-
dictable reductions in IMD).
Visible and infrared imaging systems each require similar char-
acteristics from ADCs. T he signal input (from a CCD camera
or multiplexer) is a time division multiplexed signal consisting
of a series of pulses whose amplitude varies in direct proportion
to the intensity of the radiation detected at the sensor. T hese
varying levels are then digitized by applying encode commands
at the correct times, as shown below.
+F
S
Performance graphs provide typical harmonic and SNR data for
the AD9060 for increasing analog input frequencies. In choosing
an A/D converter, always look at the dynamic range for the ana-
log input frequency of interest. T he AD9060 specifications pro-
vide guaranteed minimum limits at three analog test frequencies.
A
AD9060
IN
–F
S
ENCODE
Aperture Delay is the delay between the rising edge of the EN-
CODE command and the instant at which the analog input is
sampled. Many systems require simultaneous sampling of more
than one analog input signal with multiple ADCs. In these situ-
ations timing is critical, and the absolute value of the aperture
delay is not as critical as the matching between devices.
Im aging Application Using AD9060
T he actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. T he low frequency test for
SNR or ENOB is a good measure of the noise of the AD9060.
At this frequency, the static errors in the ADC determine the
useful dynamic range of the ADC.
Aperture Uncertainty, or jitter, is the sample-to-sample variation
in aperture delay. T his is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture un-
certainty is one of the factors that degrades dynamic perfor-
mance as the analog input frequency is increased.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not im-
portant. T he Transient Response and Overvoltage Recovery Time
specifications ensure that the ADC can track full-scale changes
in the analog input sufficiently fast to capture a valid sample.
D igitizing O scilloscopes
Oscilloscopes provide amplitude information about an observed
waveform with respect to time. Digitizing oscilloscopes must ac-
curately sample this signal without distorting the information to
be displayed.
Transient Response is the time required for the AD9060 to
achieve full accuracy when a step function is applied. Overvolt-
age Recovery Time is the time required for the AD9060 to re-
cover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
One figure of merit for the ADC in these applications is Effective
Number of Bits (ENOBs). ENOB is calculated with a sine wave
curve fit and equals:
P r ofessional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also re-
quires high resolution ADCs for studio quality measurement
and frame storage.
ENOB = N – LOG2 [Error (measured)/Error (ideal)]
N is the resolution (number of bits) of the ADC. T he measured
error is the actual rms error calculated from the converter out-
puts with a pure sine wave input.
T he Analog Bandwidth of the converter is the analog input fre-
quency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. T he analog band-
width is a good indicator of a converter’s slewing capabilities.
T he AD9060 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and ana-
log bandwidth are suitable for digitizing both composite and
RGB video sources.
T he Maximum Conversion Rate is defined as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.
REV. A
–7–
AD9060
USING TH E AD 9060
Voltage Refer ences
T he select resistors (RS) shown in the schematic (each pair can
be a potentiometer) are chosen to adjust the quarter-point
voltage references but are not necessary if R1–R4 match
within 0.05%.
T he AD9060 requires the user to provide two voltage references:
+VREF and –VREF. T hese two voltages are applied across an inter-
nal resistor ladder (nominally 37 Ω) and set the analog input
voltage range of the converter. T he voltage references should be
driven from a stable, low impedance source. In addition to these
two references, three evenly spaced taps on the resistor ladder
(1/4REF, 1/2REF, 3/4REF) are available. Providing a reference to
these quarter points on the resistor ladder will improve the inte-
gral linearity of the converter and improve ac performance. (AC
and dc specifications are tested while driving the quarter points
at the indicated levels.) T he figure below is not intended to show
the transfer characteristic of the ADC but illustrates how the lin-
earity of the device is affected by reference voltages applied to
the ladder.
10.0
62
56
9.0
8.0
7.0
50
44
6.0
5.0
38
32
1111111111
(NOT TO SCALE)
TAPS
DRIVEN
0.4 0.6
0.8
1.0
±V
1.2
1.4
1.6
1.8 2.0
– Volts
SENSE
1100000000
1000000000
AD9060 SNR and ENOB vs. Reference Voltage
TAPS
FLOATING
An alternative approach for defining the quarter-point references
of the resistor ladder to evaluate the integral linearity error of an
individual device and adjust the voltage at the quarter-points to
minimize this error. T his may improve the low frequency ac
performance of the converter.
IDEAL
LINEARITY
0100000000
Performance of the AD9060 has been optimized with an analog
input voltage of ±1.75 V (as measured at ±VSENSE). If the ana-
log input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, performance of the
0000000000
–V
+V
1/4
1/2
3/4
REF
SENSE
SENSE
REF
REF
V
IN
Effect of Reference Taps on Linearity
converter is a function of ±VSENSE
.
Resistance between the reference connections and the taps of the
first and last comparators causes offset errors. T hese errors,
called “top and bottom of the ladder offsets,” can be nulled by
using the voltage sense lines, +VSENSE and –VSENSE, to adjust the
reference voltages. Current through the sense lines should be
limited to less than 100 µA. Excessive current drawn through the
voltage sense lines will affect the accuracy of the sense line
voltage.
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values and
may cause permanent damage to the AD9060. T he design of
the reference circuit should limit the voltage available to the
references.
Analog Input Signal
T he signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
T his connection has a typical input resistance of 7 kΩ and input
capacitance of 45 pF. T he input capacitance is nearly constant
over the analog input voltage range as shown in the graph, which
illustrates that characteristic.
T he next page shows a reference circuit that nulls out the offset
errors using two op amps, and provides appropriate voltage refer-
ences to the quarter-point taps. Feedback from the sense lines
causes the op amps to compensate for the offset errors. T he two
transistors limit the amount of current drawn directly from the
op amps; resistors at the base connections stabilize their opera-
tion. T he 10 kΩ resistors (R1–R4) between the voltage sense
lines form an external resistor ladder; the quarter point voltages
are taken off this external ladder and buffered by an op amp. T he
actual values of resistors R1–R4 are not critical, but they should
T he analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide band-
width, monolithic operational amplifier with excellent ac and dc
performance. T he input capacitance should be isolated by a
small series resistor (24 Ω for the AD9617) to improve the ac
performance of the amplifier (see AD9060/PCB Evaluation
Board Block Diagram).
match well and be large enough (
≥10 kΩ) to limit the amount of
current drawn from the voltage sense lines.
REV. A
–8–
AD9060
+5V
+VSENSE
ANALOG INPUT
150Ω
1/2
AD708
*
+VREF
12
11
0.1µF
+1.75V
+VSENSE
R/2
R1
10kΩ
3/4REF
1/2REF
1/4REF
R
RS
+0.875V
R/2
R/2
1/2
3/4REF
7
RS
AD708
0.1µF
0.1µF
0.1µF
R2
10kΩ
R
R
+2.5V
RS
RS
+1.75V
356Ω
0V
R/2
AD580
1/2
150Ω
1/2REF
1
AD708
R/2
R
R3
10kΩ
R
–0.875V
R/2
R/2
R
1/2
63
1/4REF
AD708
R4
10kΩ
–VSENSE
AD9060 Equivalent Analog Input
R
R
20kΩ
R/2
GROUND
–VSENSE
57
56
20kΩ
–1.75V
*
–VREF
150Ω
1/2
*
0.1µF
= WIRING
RESISTANCE = < 5Ω
AD708
DIGITAL BITS
AND OVERFLOW
AD9060
–5V
AD9060 Equivalent Digital Outputs
AD9060 Reference Circuit
GROUND
14
13
ENCODE
ENCODE
–V
–V
S
S
AD9060 Encode and Encode
Equivalent Circuits
REV. A
–9–
AD9060
N
ANALOG
INPUT
N + 1
ta
ENCODE
ENCODE
N
N + 1
tOD
DATA
OUTPUT
DATA FOR N + 1
DATA FOR N
ta – Aperture Delay
tOD – Output Delay
AD9060 Tim ing Diagram
Tim ing
cluded in the data sheet limits. Performance of the overflow in-
dicator is dependent on circuit layout and slew rate of the en-
code signal. T he operation of this function does not affect the
other data bits (D0–D9). It is not recommended for applications
requiring a critical measure of analog input voltage.
In the AD9060, the rising edge of the ENCODE signal triggers
the A/D conversion by latching the comparators. (See the
AD9060 T iming Diagram.) T hese ENCODE and ENCODE
signals are ECL compatible and should be driven differentially.
Jitter on the ENCODE signal will raise the noise floor of the
converter. Differential signals, with fast clean edges, will reduce
the jitter in the signal and allow optimum ac performance. In
applications with a fixed, high frequency encode rate, converter
performance is also improved (jitter reduced) by using a crystal
oscillator as the system clock.
Layout and P ower Supplies
Proper layout of high speed circuits is always critical but is par-
ticularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. T he analog input volt-
age and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
T he AD9060 units are designed to operate with a 50% duty
cycle encode signal; adjustment of the duty cycle may improve
the dynamic performance of individual devices. Since the EN-
CODE and ENCODE signals are differential, the logic levels are
not critical. Users should remember, however, that reduced logic
levels will reduce the slew rate of the edges and effectively in-
crease the jitter of the signal. ECL terminations for the EN-
CODE and ENCODE signals should be as close as possible to
the AD9060 package to avoid reflections.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch. T er-
minations for ECL signals should be as close as possible to the
receiving gate.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane on the component
side of the board will reduce noise on the circuit ground. Power
supplies should be capacitively coupled to the ground plane to
reduce noise in the circuit. Multilayer boards allow designers to
lay out signal traces, without interrupting the ground plane, and
provide low impedance power planes.
In systems where only single-ended signals are available, the use
of a high speed comparator (such as the AD96685) is recom-
mended to convert to differential signals. An alternative is to
connect +1.3 V (ECL midpoint) to ENCODE and drive the
ENCODE connection single ended. In such applications, clean,
fast edges are necessary to minimize jitter in the signal.
Output data of the AD9060, D0–D9 and OVERFLOW are also
ECL compatible and should be terminated through 100 Ω to
–2 V (or an equivalent load).
It is especially important to maintain the continuity of the
ground plane under and around the AD9060. In systems with
dedicated digital and analog grounds, all grounds of the
AD9060 should be connected to the analog ground plane.
D ata For m at
T he format of the output data (D0–D9) is controlled by the MSB
INVERT and LSBs INVERT pins. T hese inputs are dc control
inputs and should be connected to GROUND or +VS. T he
AD9060 T ruth T able gives information to choose from among
Binary, Inverted Binary, T wos Complement and Inverted T wos
Complement coding.
T he power supplies (+VS and –VS) of the AD9060 should be
isolated from the supplies used for external devices; this further
reduces the amount of noise coupled into the A/D converter.
Sockets limit the dynamic performance and should be used only
for prototypes or evaluation—PCK Elastomerics Part No. CCS6855
is recommended for the LCC package. (T el. 215-672-0787)
T he OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at +VSENSE. T he accuracy of the
overflow transition voltage and output delay are not tested or in-
An evaluation board is available to aid designers and provide a
suggested layout.
REV. A
–10–
AD9060
30
35
40
45
50
55
10.0
9.0
62
56
ENCODE RATE = 60MSPS
8.0
7.0
6.0
50
44
38
+125°C
–55°C
+25°C
–55°C & +125°C
5.0
4.0
32
26
20
60
65
70
+25°C
1
2
4
6
8 10
20
40 60 100
200
1
2
4
6
8
10
20
40 60
100
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
AD9060 Harm onics vs. Input Frequency
AD9060 SNR and ENOB vs. Input Frequency
70
60
10.0
9.0
62
56
ANALOG INPUT = 2.3MHz
48
47
50
40
30
8.0
RESISTANCE
50
7.0
6.0
5.0
4.0
44
38
CAPACITANCE
46
45
44
20
10
32
26
20
–1.8
–1.2
–0.6
0
+0.6
+1.2
+1.8
10
20
40
60
80
100
ANALOG INPUT (AIN ) – Volts
CONVERSION RATE – MSPS
Input Capacitance/Resistance vs. Input Voltage
AD9060 SNR and ENOB vs. Conversion Rate
O ffset Binary
Twos Com plem ent
Step
Range
True
Inverted
True
Inverted
0 = –1.75 V
FS = +1.75 V
MSB INV = “ 0”
LSBs INV = “ 0”
MSB INV = “ 1”
LSBs INV = “ 1”
MSB INV = “ 1”
LSBs INV = “ 0”
MSB INV = “ 0”
LSBs INV = “ 1”
1024
> + 1.7500
(1)1111111111
(l)0000000000
(1)0111111111
(1)1000000000
1023
+ 1.7466
1111111111
0000000000
0111111111
1000000000
1022
+ 1.7432
1111111110
0000000001
0111111110
1000000001
.
.
.
.
.
.
.
.
.
.
.
.
.
.
+0.0034
0.000
–0.0034
.
.
.
.
.
512
511
510
.
1000000000
0111111111
0111111110
.
0111111111
1000000000
1000000001
.
0000000000
1111111111
1111111110
.
1111111111
0000000000
0000000001
.
.
.
.
.
.
.
.
.
.
.
.
.
02
01
00
– 1.7432
– 1.7466
< – 1.7466
0000000010
0000000001
0000000000
1111111101
1111111110
1111111111
1000000010
1000000001
1000000000
0111111101
0111111110
0111111111
T he overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered dc controls.
AD9060 Truth Table
REV. A
–11–
AD9060
DAC
OUT
–5V
+5V
I
AD9712 DAC OUT
TO ERROR
WAVEFORM
CIRCUIT
50Ω
D
DUT
ANALOG
INPUT
–V
S
+5V
+V
S
GND MSB INVERT
LSBs INVERT
BUFFERED
ANALOG
INPUT
400Ω
J2
200Ω
D
D
D
D
D
D
D
D
D
D
D
(LSB) D
0
24Ω
U5
AD9617
ANALOG
INPUT
D
D
1
50Ω
OUTPUT
DATA
CONNECTOR
2
3
4
D
D
Q
ECL
LATCHES
AD9060
DUT
D
D
TO ERROR
WAVEFORM
CIRCUIT
5
6
+V
DATA
READY
REF
D
D
7
+V
SENSE
8
3/4
REF
(MSB) D
9
CLK
REFERENCE
CIRCUIT
1/2
OVERFLOW
REF
1/4
REF
–V
SENSE
ENCODE
ENCODE
–V
REF
DIFFERENTIAL
ECL CLOCK
TIMING
CIRCUIT
AD9060/PCB Evaluation Board Block Diagram
AD 9060/P CB EVALUATIO N BO ARD
T he AD9060/PCB Evaluation Board is available from the fac-
tory and is shown here in block diagram form. T he board in-
cludes a reference circuit that allows the user to adjust both
references and the quarter-point voltages. T he AD9617 is in-
cluded as the drive amplifier, and the user can configure the
gain from –1 to –15.
Onboard reconstruction of the digital data is provided through
the AD9712, a 12-bit monolithic DAC. T he analog and recon-
structed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9060 and the effects of the
quarter-point voltages. T he digital data and an adjustable Data
Ready signal are available via a 37-pin edge connector.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Leaded Cer am ic Chip Car r ier
Suffix Z
Leadless Chip Car r ier (LCC)
Suffix E
REV. A
–12–
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