AD9057PCB [ADI]
8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter; 8位40 MSPS / 60 MSPS / 80 MSPS A / D转换器
| 型号： | AD9057PCB |
| 厂家： | 
ADI |
| 描述： | 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| 文件： | 总12页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit
a
40 MSPS/60 MSPS/80 MSPS A/D Converter
AD9057
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
8-Bit, Low Pow er ADC: 200 m W Typical
120 MHz Analog Bandw idth
V
PWRDN
V
DD
D
On-Chip +2.5 V Reference and T/ H
1 V p-p Analog Input Range
Single +5 V Supply Operation
+5 V or +3 V Logic Interface
Pow er-Dow n Mode: < 10 m W
Three Perform ance Grades (40 MSPS, 60 MSPS, 80 MSPS)
AD9057
8
AIN
D7–D0
T/H
ADC
1kΩ
BIAS OUT
VREF IN
VREF OUT
+2.5V
GND
APPLICATIONS
Digital Com m unications (QAM Dem odulators)
RGB & YC/ Com posite Video Processing
Digital Data Storage Read Channels
Medical Im aging
ENCODE
Digital Instrum entation
P RO D UCT D ESCRIP TIO N
Customers desiring multichannel digitization may consider the
AD9059, a dual 8-bit, 60 MSPS monolithic based on the
AD9057 ADC core. T he AD9059 is available in a 28-lead sur-
face mount plastic package (28 SSOP) and is specified over the
industrial temperature range.
T he AD9057 is an 8-bit monolithic analog-to-digital converter
optimized for low cost, low power, small size, and ease of use.
With a 40 MSPS, 60 MSPS or 80 MSPS encode rates capabil-
ity and full-power analog bandwidth of 120 MHz, the compo-
nent is ideal for applications requiring excellent dynamic
performance.
P IN CO NFIGURATIO N
T o minimize system cost and power dissipation, the AD9057
includes an internal +2.5 V reference and a track-and-hold
circuit. T he user must provide only a +5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.
20
D0 (LSB)
PWRDN
1
2
19 D1
18 D2
17 D3
VREF OUT
3
VREF IN
GND
4
AD9057
T he AD9057’s encode input is T T L/CMOS compatible and the
8-bit digital outputs can be operated from +5 V or +3 V supplies.
A power-down function may be exercised to bring total con-
sumption to < 10 mW. In power-down mode the digital outputs
are driven to a high impedance state.
V
D
5
TOP VIEW 16
(Not to Scale)
15
GND
BIAS OUT
AIN
6
V
DD
14 D4
13
7
V
D
8
D5
12 D6
D7 (MSB)
9
GND
Fabricated on an advanced BiCMOS process, the AD9057 is
available in a space saving 20-lead surface mount plastic pack-
age (20 SSOP) and is specified over the industrial (–40°C to
+85°C) temperature range.
10
11
ENCODE
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(V = +5 V, V = +3 V; external reference)
AD9057–SPECIFICATIONS
D
DD
Test
AD 9057BRS-40
AD 9057BRS-60
AD 9057BRS-80
P aram eter
Tem p
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
RESOLUT ION
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
Full
+25°C
Full
I
VI
I
VI
VI
I
VI
V
0.75
0.75
1.9
2.0
1.9
2.0
0.75
0.75
1.9
2.0
1.9
2.0
0.75
0.75
1.9
2.0
1.9
2.0
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Gain Error1
GUARANT EED
GUARANT EED
GUARANT EED
–6
–8
–2.5
+6
+8
–6
–8
–2.5
+6
+8
–6
–8
–2.5
+6
+8
% FS
% FS
ppm/°C
Gain T empco1
Full
±70
±70
±70
ANALOG INPUT
Input Voltage Range
(Centered at +2.5 V)
Input Offset Voltage
+25°C
+25°C
Full
+25°C
+25°C
+25°C
Full
V
I
VI
V
V
I
1.0
±0
1.0
±0
1.0
±0
V p-p
mV
mV
kΩ
pF
µA
–15
–25
+15
+25
–15
–25
+15
+25
–15
–25
+15
+25
Input Resistance
Input Capacitance
Input Bias Current
150
2
6
150
2
6
150
2
6
16
25
16
25
16
25
VI
V
µA
MHz
Analog Bandwidth
+25°C
120
120
120
BANDGAP REFERENCE
Output Voltage
T emperature Coefficient
Full
Full
VI
V
2.4
40
2.5
±10
2.6
2.4
60
2.5
±10
2.6
2.4
80
2.5
±10
2.6
V
ppm/°C
SWIT CHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Full
Full
+25°C
+25°C
Full
VI
IV
V
V
IV
IV
MSPS
MSPS
ns
ps, rms
ns
5
5
5
2.7
5
6.6
11.5
2.7
5
6.6
9.5
2.7
5
6.6
8.0
Aperture Uncertainty (Jitter)
Output Valid T ime (tV)2
4.0
4.0
4.0
2
Output Propagation Delay (tPD
)
Full
18.0
14.2
11.3
ns
DYNAMIC PERFORMANCE3
T ransient Response
Overvoltage Recovery T ime
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
+25°C
+25°C
V
V
9
9
9
9
9
9
ns
ns
fIN = 10.3 MHz
fIN = 76 MHz
Effective Number of Bits
fIN = 10.3 MHz
fIN = 76 MHz
+25°C
+25°C
I
V
42
45.5
44.0
42
45
43.5
41.5
6.6
45
43.5
dB
dB
+25°C
+25°C
I
V
6.7
7.2
7.0
6.7
7.2
6.9
7.2
6.9
Bits
Bits
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
2nd Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
3rd Harmonic Distortion
fIN = 10.3 MHz
+25°C
+25°C
I
V
43
46.5
45.5
43
46
45
42.5
–50
–46
46
45
dB
dB
+25°C
+25°C
I
V
–50
–46
–62
–54
–50
–46
–62
–54
–62
–54
dBc
dBc
+25°C
+25°C
I
V
–60
–54
–60
–54
–60
–54
dBc
dBc
fIN = 76 MHz
T wo T one Intermodulation
Distortion (IMD)
Differential Phase
+25°C
+25°C
+25°C
V
V
V
–52
0.8
1.0
–52
0.8
1.0
–52
0.8
1.0
dBc
Degrees
%
Differential Gain
DIGIT AL INPUT S
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
2.0
2.0
2.0
V
V
0.8
±1
±1
0.8
±1
±1
0.8
±1
±1
µA
µA
pF
ns
ns
4.5
4.5
4.5
Encode Pulse Width High (tEH
Encode Pulse Width Low (tEL
)
IV
IV
9.0
9.0
166
166
6.7
6.7
166
166
5.5
5.5
166
166
)
–2–
REV. B
AD9057
Test
AD 9057BRS-40
AD 9057BRS-60
AD 9057BRS-80
P aram eter
Tem p Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
DIGIT AL OUT PUT S
Logic “1” Voltage (VDD = +3 V)
Logic “1” Voltage (VDD = +5 V)
Logic “0” Voltage
Full
Full
Full
VI
IV
VI
2.95
4.95
V
V
V
0.05
Output Coding
Offset Binary Code
POWER SUPPLY
VD Supply Current (VD = +5 V)
Full
VI
VI
VI
VI
36
4.0
192
6
48
38
5.5
205
6
48
40
7.4
220
6
51
mA
mA
mW
mW
VDD Supply Current (VDD = +3 V)4 Full
6.5
260
10
6.5
260
10
8.8
281
10
Power Dissipation5, 6
Power-Down Dissipation
Power Supply Rejection Ratio
(PSRR)
Full
Full
+25°C
I
15
15
15
mV/V
NOT ES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. T he digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ±40 µA.
3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4Digital supply current based on VDD = +3 V output drive with <10 pF loading under dynamic test conditions.
5Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (V D = +5 V ± 5%, VDD = +3 V ± 5%).
6T ypical thermal impedance for the RS style (SSOP) 20-pin package: θJC = 46°C/W, θCA = 80°C/W, θJA = 126°C/W.
Specifications subject to change without notice.
EXP LANATIO N O F TEST LEVELS
Test Level
D escription
I
100% Production T ested
II
100% Production T ested at +25°C and Sample
T ested at Specified T emperatures
III
IV
Sample T ested Only
Parameter is Guaranteed by Design and Char-
acterization T esting
V
Parameter is a T ypical Value Only
VI
100% Production T ested at +25°C; Guaran-
teed by Design and Characterization T esting
for Industrial T emperature Range
N
N + 5
N + 3
AIN
N + 1
N + 4
N + 2
tA
tEH
tEL
ENCODE
tV
DIGITAL
OUTPUTS
N – 3
N – 2
N – 1
N
N + 1
N + 2
tPD
MIN TYP
2.7 ns
MAX
t
APERTURE DELAY
PULSE WIDTH HIGH
PULSE WIDTH LOW
OUTPUT VALID TIME
OUTPUT PROP DELAY
A
t
166 ns
166 ns
EH
t
EL
t
6.6 ns
9.5 ns
V
4.0 ns
t
PD
Figure 1. Tim ing Diagram
–3–
REV. B
AD9057
ABSO LUTE MAXIMUM RATINGS
P IN D ESCRIP TIO NS
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
VREF Input . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating T emperature . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction T emperature . . . . . . . . . . . . . . . . +175°C
Maximum Case T emperature . . . . . . . . . . . . . . . . . . +150°C
P in No.
Nam e
Function
1
PWRDN
Power-Down Function Select;
Logic HIGH for Power-Down
Mode (Digital Outputs Go to
High Impedance State).
2
3
VREF OUT
VREF IN
Internal Reference Output
(+2.5 V typ); Bypass with
0.1 µF to Ground.
Reference Input for ADC (+2.5
V typ, ±10%).
O RD ERING GUID E
Tem perature
4, 9, 16
5, 8
GND
Ground (Analog/Digital).
Analog +5 V Power Supply.
Model
Range
P ackage O ption*
VD
AD9057BRS–40, –60, –80 –40°C to +85°C RS-20
6
BIAS OUT
Bias Pin for AC Coupling
AD9057/PCB +25°C Evaluation Board
(1 kΩ to REF IN).
7
AIN
Analog Input for ADC.
*RS = Shrink Small Outline (SSOP).
10
ENCODE
Encode Clock for ADC (ADC
Samples on Rising Edge of
ENCODE).
Table I. D igital Coding (VREF = +2.5 V)
11–14, 17–20 D7–D4, D3–D0
15 VDD
Digital Outputs of ADC.
Digital Output Power Supply.
Nominally +3 V to +5 V.
Analog Input
Voltage Level
D igital O utput
3.0 V
Positive Full Scale
Midscale +1/2 LSB
Midscale –1/2 LSB
Negative Full Scale
1111 1111
1000 0000
0111 1111
0000 0000
2.502 V
2.498 V
2.0
P IN CO NFIGURATIO N
20
D0 (LSB)
PWRDN
1
2
19 D1
18 D2
17 D3
VREF OUT
3
VREF IN
GND
4
AD9057
V
D
5
TOP VIEW 16
(Not to Scale)
15
GND
BIAS OUT
AIN
6
V
DD
14 D4
13
7
V
D
8
D5
12 D6
9
GND
10
D7 (MSB)
11
ENCODE
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9057 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–4–
Typical Performance Characteristics–AD9057
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–30
ENCODE = 60MSPS
ANALOG IN = 10.3MHz, –0.5dBFS
SINAD = 46.1dB
ENOB = 7.36 BITS
SNR = 46.5dB
ENCODE = 60MSPS
–35
AIN = –0.5dBFS
–40
–45
ND
2
HARMONIC
–50
–55
–60
RD
3
HARMONIC
–65
–70
0
30
0
20
40
60
80
100
120
140
160
FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
Figure 2. Spectral Plot 60 MSPS, 10.3 MHz
Figure 5. Harm onic Distortion vs. AIN Frequency
0
0
ENCODE = 60MSPS
ENCODE = 60MSPS
F1 IN = 9.5MHz @ –7.0dBFS
F2 IN = 9.9MHz @ –7.0dBFS
2F1 - F2 = –52.0dBc
ANALOG IN = 76MHz, –0.5dBFS
SINAD = 44.9dB
ENOB = 7.16 BITS
SNR = 45.2dB
–10
–10
–20
–20
2F2 - F1 = –53.0dBc
–30
–30
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
0
30
0
10
20
30
FREQUENCY – MHz
FREQUENCY – MHz
Figure 3. Spectral Plot 60 MSPS, 76 MHz
Figure 6. Two-Tone Interm odulation Distortion
54
48
SNR
SNR
46
44
42
40
38
36
34
48
42
SINAD
SINAD
36
30
ENCODE = 60MSPS
AIN = –0.5dBFS
AIN = 10.3MHz, –0.5dBFS
24
18
12
0
32
30
5
10
20
30
40
50
60
70
80
90
0
20
40
60
80
100
120
140
160
ENCODE RATE – MSPS
ANALOG INPUT FREQUENCY – MHz
Figure 4. SINAD/SNR vs. AIN Frequency
Figure 7. SINAD/SNR vs. Encode Rate
REV. B
–5–
AD9057–Typical Performance Characteristics
350
12
11
10
300
V
= +3V
DD
V
= +5V
DD
250
200
150
100
50
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
V
= +3V
DD
V
= +5V
DD
AIN = 10.3MHz, –0.5dBFS
0
5
10
20
30
40
50
60
70
80
90
–45
0
25
TEMPERATURE –
70
90
ENCODE RATE – MSPS
°
C
Figure 8. Power Dissipation vs. Encode Rate
Figure 11. tPD vs. Tem perature/Supply (VDD = +3 V/+5 V)
46.5
46.5
46
46.0
SNR
45.5
45.0
SNR
45.5
SINAD
45
44.5
44
44.5
44.0
43.5
43.0
42.5
42.0
41.5
ENCODE = 60MSPS
AIN = 10.3MHz, –0.5dBFS
SINAD
43.5
ENCODE = 60MSPS
AIN = 10.3MHz, –05dBFS
43
42.5
5.8
–45
0
25
70
90
6.7
7.5
8.35
9.2
10
10.9
TEMPERATURE – °C
ENCODE HIGH PULSE WIDTH – ns
Figure 9. SINAD/SNR vs. Tem perature
Figure 12. SINAD/SNR vs. Encode Pulse Width
0
0
–1
–2
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–3
ENCODE = 60MSPS
AIN = –0.5dBFS
–4
–5
–6
–7
–8
–9
–10
1
2
5
10
20
50
100
200
500
–45
0
25
70
90
ANALOG FREQUENCY – MHz
TEMPERATURE – °C
Figure 13. ADC Frequency Response
Figure 10. ADC Gain vs. Tem perature (with External
+2.5 V Reference)
REV. B
–6–
AD9057
+5V
TH EO RY O F O P ERATIO N
T he AD9057 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology to
provide a high performance, low cost ADC. T he design archi-
tecture ensures low power, high speed, and 8-bit accuracy. A
single-ended T T L/CMOS compatible ENCODE input controls
ADC timing for sampling the analog input pin and strobing the
digital outputs (D7–D0). An internal voltage reference (VREF
OUT ) may be used to control ADC gain and offset or an exter-
nal reference may be applied.
2
3
7
REF OUT
AD9057
REF IN
10kΩ
10kΩ
0.1µF
+5V
AD8041
AIN
1kΩ
VIN
(–0.5V TO +0.5V)
T he analog input signal is buffered at the input of the ADC and
applied to a high speed track-and-hold. T he T /H circuit holds
the analog input value during the conversion process (beginning
with the rising edge of the ENCODE command). T he T /H’s
output signal passes through the gray code and flash conversion
stages to generate coarse and fine digital representations of the
held analog input level. Decode logic combines the multistage
data and aligns the 8-bit word for strobed outputs on the rising
edge of the ENCODE command. T he MagAmp/Flash architec-
ture of the AD9057 results in three pipeline delays for the out-
put data.
1kΩ
Figure 15. DC Coupled AD9057 (Inverted VIN)
Voltage Refer ence
A stable and accurate +2.5 V voltage reference is built into the
AD9057 (VREF OUT ). T he reference output may be used to
set the ADC gain/offset by connecting VREF OUT to VREF IN.
T he internal reference is capable of providing 300 µA of drive
current (for dc biasing the analog input or other user circuitry).
Some applications may require greater accuracy, improved
temperature performance, or gain adjustments which cannot be
obtained using the internal reference. An external voltage may
be applied to the VREF IN with VREF OUT disconnected for
gain adjustment of up to ±10% (the VREF IN pin is internally
tied directly to the ADC circuitry). ADC gain and offset will
vary simultaneously with external reference adjustment with a
1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference
varies ADC gain by 2% and ADC input range center offset by
50 mV). T heoretical input voltage range versus reference input
voltage may be calculated from the following equations:
USING TH E AD 9057
Analog Inputs
T he AD9057 provides a single-ended analog input impedance of
150 kΩ. T he input requires a dc bias current of 6 µA (typical)
centered near +2.5 V (±10%). T he dc bias may be provided by
the user or may be derived from the ADC’s internal voltage
reference. Figure 14 shows a low cost dc bias implementation
allowing the user to capacitively couple ac signals directly into
the ADC without additional active circuitry. For best dynamic
performance, the VREF OUT pin should be decoupled to
ground with a 0.1 µF capacitor (to minimize modulation of
the reference voltage) and the bias resistor should be approxi-
mately 1 kΩ. A 1 kΩ bias resistor (±20%) is included within
the AD9057 and may be used to reduce application board size
and complexity.
VRANGE (p-p)
VMIDSCALE
= VREF IN/2.5
= VREF IN
VTOP-OF-RANGE
= VREF IN + VRANGE/2
VBOTTOM-OF-RANGE = VREF IN – VRANGE/2
D igital Logic (+5 V/+3 V System s)
+5V
T he digital inputs and outputs of the AD9057 can easily be
configured to interface directly with +3 V or +5 V logic systems.
T he ENCODE and power-down (PWRDN) inputs are CMOS
stages with T T L thresholds of 1.5 V, making the inputs compat-
ible with T T L, +5 V CMOS, and +3 V CMOS logic families.
As with all high speed data converters, the encode signal should
be clean and jitter free to prevent degradation of ADC dynamic
performance.
2
3
6
7
REF OUT
REF IN
1kΩ
0.1µF
BIAS OUT
0.1µF
AIN
VIN
(1V p-p)
AD9057
T he AD9057’s digital outputs will also interface directly with
+5 V or +3 V CMOS logic systems. T he voltage supply pin
(VDD) for these CMOS stages is isolated from the analog VD
voltage supply. By varying the voltage on this supply pin the
digital output HIGH level will change for +5 V or +3 V systems.
Optimum SNR is obtained running the outputs at +3 V. Care
should be taken to isolate the VDD supply voltage from the +5 V
analog supply to minimize digital noise coupling into the ADC.
Figure 14. Capacitively Coupled AD9057
Figure 15 shows typical connections for high performance dc
biasing using the ADC’s internal voltage reference. All compo-
nents may be powered from a single +5 V supply (in the example
analog input signals are referenced to ground).
REV. B
–7–
AD9057
full-power analog bandwidth of 2× the maximum sampling
rate, the ADC provides sufficient pixel to pixel transient set-
tling time to ensure accurate 60 MSPS video digitization. Fig-
ure 17 shows a typical RGB video digitizer implementation for
the AD9057.
T he AD9057 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic HIGH). A 200 ns (minimum) power-down time should be
provided before a high impedance characteristic is required at
the outputs. A 200 ns power-up period should be provided to
ensure accurate ADC output data after reactivation (valid output
data is available three clock cycles after the 200 ns delay).
8
AD9057
AD9057
AD9057
RED
Tim ing
T he AD9057 is guaranteed to operate with conversion rates
from 5 MSPS to 80 MSPS depending on grade. T he ADC is
designed to operate with an encode duty cycle of 50%, but per-
formance is insensitive to moderate variations. Pulse width varia-
tions of up to ±10% (allowing the encode signal to meet the
minimum/maximum HIGH/LOW specifications) will cause no
degradation in ADC performance (see Figure 1 timing diagram).
8
8
GREEN
BLUE
PIXEL CLOCK
PLL
H-SYNC
P ower D issipation
T he power dissipation of the AD9057 is specified to reflect a
typical application setup under the following conditions: analog
input is –0.5 dBFS at 10.3 MHz, VD is +5 V, VDD is +3 V, and
digital outputs are loaded with 7 pF typical (10 pF maximum).
T he actual dissipation will vary as these conditions are modified
in user applications. Figure 8 shows typical power consumption
for the AD9057 versus ADC encode frequency and VDD supply
voltage.
Figure 17. RGB Video Encoder
Evaluation Boar d
T he AD9057/PCB evaluation board provides an easy to use
analog/digital interface for the 8-bit, 60 MSPS ADC. T he
board includes typical hardware configurations for a variety of
high speed digitization evaluations. On board components
include the AD9057 (in the 20-pin SSOP package), an optional
analog input buffer amplifier, a digital output latch, board
timing drivers, an analog reconstruction digital-to-analog con-
verter, and configurable jumpers for ac coupling, dc coupling,
and power-down function testing. T he board is configured at
shipment for dc coupling using the AD9057’s internal voltage
reference.
A power-down function allows users to reduce power dissipation
when ADC data is not required. A T T L/CMOS HIGH signal
(PWRDN) shuts down portions of the ADC and brings total
power dissipation to less than 10 mW. T he internal bandgap
voltage reference remains active during power-down mode to
minimize ADC reactivation time. If the power-down function is
not desired, Pin 1 should be tied to ground.
For dc coupled analog input applications, amplifier U2 is con-
figured to operate as a unity gain inverter with adjustable offset
for the analog input signal. For full-scale ADC drive the analog
input signal should be 1 V p-p into 50 Ω (R1) referenced to
ground (0 V). T he amplifier offsets the analog signal by
+VREF (+2.5 V typical) to center the voltage for proper ADC
input drive. For dc coupled operation, connect E1 to E2 (ana-
log input to R2) and E11 to E12 (amplifier output to analog
input of AD9057) using the board jumper connectors. DC
offset of the analog input signal can be modified by adjusting
potentiometer R10.
AP P LICATIO NS
T he wide analog bandwidth of the AD9057 makes it attractive
for a variety of high performance receiver and encoder applica-
tions. Figure 16 shows two ADCs in a typical low cost I & Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. T he excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (refer
to Figure 3 spectral plot). IF sampling eliminates or simplifies
analog mixer and filter stages to reduce total system cost and
power.
For ac coupled analog input applications, amplifier U2 is
removed from the analog signal path. T he analog signal is
coupled into the input of the AD9057 through capacitor C2.
T he ADC pulls analog input bias current from the VREF IN
voltage through the 1 kΩ resistor internal to the AD9057
(BIAS OUT ). T he analog input signal to the board should be
1 V p-p into 50 Ω (R1) for full-scale ADC drive. For ac
coupled operation, connect E1 to E3 (analog input A to C2
feedthrough capacitor) and E10 to E12 (C2 to the analog input
and internal bias resistor) using the board jumper connectors.
AD9057
AD9057
BPF
BPF
IF IN
90°
VCO
VCO
T he onboard reference voltage may be used to drive the ADC
or an external reference may be applied. T o use the internal
voltage reference, connect E6 to E5 (VREF OUT to VREF
IN). T o apply an external voltage reference, connect E4 to E5
(external reference from the REF banana jack to VREF IN).
T he external voltage reference should be +2.5 V ± 10%.
Figure 16. I & Q Digital Receiver
T he high sampling rate and analog bandwidth of the AD9057
are ideal for computer RGB video digitizer applications. With a
REV. B
–8–
AD9057
T he power-down function of the AD9057 can be exercised
through a board jumper connection. Connect E7 to E9 (+5 V to
PWRDN) for power-down operation. For normal operation,
connect E8 to E9 (ground to PWRDN).
oscilloscope or spectrum analyzer. T he DAC converts the
ADC’s digital outputs to an analog signal for examination at
the DAC OUT connector. T he DAC is clocked at the ADC
ENCODE frequency. T he AD9760 is a 10-bit/100 MSPS single
+5 V supply DAC. T he reconstruction signal facilitates quick
system troubleshooting or confirmation of ADC functionality
without requiring external digital memory, timing, or display
interfaces. T he DAC can be used for limited dynamic testing,
but customers should note that test results will be based on the
combined performance of the ADC and DAC (the best ADC
performance will be recognized by evaluating the digital outputs
of the ADC directly).
T he encode signal source should be T T L/CMOS compatible
and capable of driving a 50 Ω termination (R7). T he digital
outputs of the AD9057 are buffered through latches on the
evaluation board (U3) and are available for the user at connec-
tor Pins 30–37. Latch timing is derived from the ADC EN-
CODE clock and a digital clocking signal is provided for the
board user at connector Pins 2 and 21.
An onboard reconstruction digital-to-analog converter is
available for quick evaluations of ADC performance using an
+V
D
+V
D
ENCODE
PWRDN
500Ω
V
AIN
REFIN
Analog Input
Digital Inputs
+V , +3V TO +5V
DD
+V
D
1kΩ
V
BIAS OUT
REFIN
D0–D7
Bias Output
Digital Outputs
+V
D
+V
D
3kΩ
V
REFIN
V
REFOUT
2.5kΩ
V
Output
V
Input
REF
REF
Figure 18. Equivalent Circuits
REV. B
–9–
AD9057
E7
E9
+5V
PWRDN
E8
J6, REF
GND
C17
0.1µF
ANALOG IN
C37DRPF
P2
U2
AD8041Q
E4
E5
E6
1
2
3
4
5
1
2
3
4
5
20
19
18
17
16
R2
1kΩ
1
2
3
4
8
7
6
5
DIS
+V
PWRDN
REF OUT
REF IN
GND
NC
(LSB) D0
D1
D0
U3
74ACQ574
E2
E1
E3
R5
2kΩ
BNC
J1
D1
S
D2
D2
9
8
7
6
5
12
13
14
15
16
D7
D6
D5
D4
D3
D2
D1
D0
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
C1
0.1µF
R10
500Ω
NC
GND
+5V
–V
D3
D3
S
V
D
GND
GND
6
7
6
7
15
14
13
12
11
R3
1kΩ
BIAS OUT
AIN
V
V
DD
DD
R1
50Ω
R4
2kΩ
D4
D5
D4
D5
D6
D7
8
8
R6
10Ω
V
D
+5V
4
3
2
17
18
19
9
9
E11
GND
GND
ENC
D6
10
11
12
10
E12
E10
(MSB) D7
CK
OE
13
14
15
16
17
18
19
11
1
C2
0.1µF
20
21
22
23
24
25
26
U4
74AC00
BNC
J3
DAC
AD9760AR
1
2
3
28
ENCODE
+5V
C18
CLK
27
R7
50Ω
U4
74AC00
+5V
+5V
DVDD
(MSB)
DB9
1
24
0.1µF
DA7
2
AVDD
4
5
27
28
29
6
11
8
DA6
3
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
23
19
COMP2
COMP1
DA5
4
C19
0.1µF
U4
74AC00
DA4
5
30
31
32
33
34
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA3
18
12
13
6
FSADJ
DA2
7
17
16
DA1
8
R9
2kΩ
REFIO
DA0
9
U4
74AC00
REFLO
GND
10
35
36
37
15
9
GND
DB0
SLEEP
10
C13
(LSB)
0.1µF
IOUT
A
B
BNC
J2
22
21
ANALOG
PWRDN
RECONSTRUCT
DAC OUT
V
J7, V
DD
DD
R8
50Ω
R11
50Ω
+
C10
0.1µF
C11
10µF
J4, GND
J5, +5V
C7
0.1µF
C8
0.1µF
C14
0.1µF
+
C3
0.1µF
C4
0.1µF
C5
0.1µF
C9
0.1µF
C12
10µF
DECOUPLING CAPS
Figure 19. Evaluation Board Schem atic
REV. B
–10–
AD9057
Figure 20. Evaluation Board Layout
REV. B
–11–
AD9057
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-Lead SSO P
(RS-20)
0.295 (7.50)
0.271 (6.90)
20
11
1
10
0.07 (1.78)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.037 (0.94)
8°
0°
0.0256
(0.65)
BSC
0.022 (0.559)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
REV. B
–12–
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