AD9058 [ADI]
Dual 8-Bit 50 MSPS A/D Converter; 双路，8位50 MSPS A / D转换器
| 型号： | AD9058 |
| 厂家： | 
ADI |
| 描述： | Dual 8-Bit 50 MSPS A/D Converter |
| 文件： | 总8页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 8-Bit 50 MSPS
A/D Converter
a
AD9058
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Two Matched ADCs on Single Chip
50 MSPS Conversion Speed
On-Board Voltage Reference
Low Power (<1W)
Low Input Capacitance (10 pF)
65 V Power Supplies
AD9058
+V
REF
8-BIT
ANALOG-
TO-
DIGITAL
CONVERTER
ENCODE
8
A
Flexible Input Range
A
IN
APPLICATIONS
–V
REF
Quadrature Demodulation for Communications
Digital Oscilloscopes
Electronic Warfare
+2 V
REF
Radar
+V
REF
8-BIT
ANALOG-
TO-
8
ENCODE
B
DIGITAL
CONVERTER
GENERAL DESCRIPTION
A
IN
The AD9058 combines two independent high performance
8-bit analog-to-digital converters (ADCs) on a single mono-
lithic IC. Combined with an optional onboard voltage refer-
ence, the AD9058 provides a cost effective alternative for
systems requiring two or more ADCs.
–V
REF
QUADRATURE RECEIVER
Dynamic performance (SNR, ENOB) is optimized to provide
up to 50 MSPS conversion rates. The unique architecture
results in low input capacitance while maintaining high per-
formance and low power (<0.5 watt/channel). Digital inputs
and outputs are TTL compatible.
8
8
G
Q
AD9058
RF
LO
90°
Performance has been optimized for an analog input of 2 V
p-p ( 1 V; 0 V to +2 V). Using the onboard +2 V voltage
reference, the AD9058 can be set up for unipolar positive
operation (0 V to +2 V). This internal voltage reference can
drive both ADCs.
G
I
Commercial (0°C to +70°C) and military (–55°C to +125°C)
temperature range parts are available. Parts are supplied in
hermetic 48-lead DIP and 44-lead “J” lead packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD9058–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1
–VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.5
Operating Temperature Range
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . .–1.5 V to +2.5 V
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to –6 V2
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . .53 mA
+VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5 V
AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Junction Temperature3
AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
[؎VS = ؎5 V; VREF = +2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to +2 V; –VREF
=
GROUND, unless otherwise noted.]2 All specifications apply to either of the two ADCs
ELECTRICAL CHARACTERISTICS
Test
AD9058JD/JJ
AD9058KD/KJ
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
8
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
VI
VI
0.25
0.5
0.65
0.8
1.3
1.4
0.25
0.5
0.5
0.7
1.0
1.25
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Full
GUARANTEED
GUARANTEED
ANALOG INPUT
Input Bias Current
+25°C
Full
+25°C
+25°C
+25°C
I
VI
I
IV
V
75
170
340
75
170
340
µA
µA
Input Resistance
Input Capacitance
Analog Bandwidth
12
28
10
175
12
28
10
175
kΩ
pF
MHz
15
15
REFERENCE INPUT
Reference Ladder Resistance
+25°C
Full
Full
+25°C
Full
+25°C
Full
Full
I
120
80
170
220
270
120
80
170
220
270
Ω
VI
V
I
VI
I
VI
V
Ω
Ladder Tempco
Reference Ladder Offset
(Top)
Reference Ladder Offset
(Bottom)
0.45
8
0.45
8
Ω/°C
mV
mV
mV
mV
µV/°C
16
24
23
33
16
24
23
33
8
8
Offset Drift Coefficient
50
50
INTERNAL VOLTAGE REFERENCE
Reference Voltage
+25°C
Full
Full
I
VI
V
1.95
1.90
2.0
150
10
2.20
2.25
1.95
1.90
2.0
150
10
2.20
2.25
V
V
µV/°C
Temperature Coefficient
Power Supply Rejection
Ratio (PSRR)
+25°C
I
25
25
mV/V
SWITCHING PERFORMANCE
Maximum Conversion Rate4
Aperture Delay (tA)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
Output Delay (Valid) (tV)4
+25°C
+25°C
+25°C
+25°C
+25°C
Full
+25°C
Full
+25°C
I
50
0.8
0.2
10
8
16
12
–16
1
50
0.1
60
0.8
0.2
10
8
16
12
–16
1
MSPS
ns
ns
ps, rms
ns
ps/°C
ns
ps/°C
ns
IV
IV
V
I
V
I
0.1
1.5
0 5
1.5
0.5
5
Output Delay (tV) Tempco
4
Propagation Delay (tPD
)
19
Propagation Delay (tPD) Tempco
Output Time Skew
V
V
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Pulsewidth (High)
Pulsewidth (Low)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
I
I
2
2
V
V
µA
µA
pF
ns
ns
0.8
600
1000
0.8
600
1000
5
8
8
5
8
8
–2–
REV. B
AD9058
Test
Level Min
AD9058JD/JJ
AD9058KD/KJ
Parameter (Conditions)
Temp
Typ
Max Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Transient Response
+25°C
+25°C
V
V
2
2
2
2
ns
ns
Overvoltage Recovery Time
Effective Number of Bits (ENOB)5
Analog Input @ 2.3 MHz
@ 10.3 MHz
+25°C
+25°C
I
I
7.7
7.4
7.2
7.1
7.7
7.4
Bits
Bits
Signal-to-Noise Ratio5
Analog Input @ 2.3 MHz
@ 10.3 MHz
+25°C
+25°C
I
I
48
46
45
44
48
46
dB
dB
Signal-to-Noise Ratio5 (Without Harmonics)
Analog Input @ 2.3 MHz
@ 10.3 MHz
+25°C
+25°C
I
I
48
47
46
45
48
47
dB
dB
2nd Harmonic Distortion
Analog Input @ 2.3 MHz
@ 10.3 MHz
+25°C
+25°C
I
I
58
58
48
48
58
58
dBc
dBc
3rd Harmonic Distortion
Analog Input @ 2.3 MHz
@ 10.3 MHz
+25°C
+25°C
+25°C
I
I
IV
58
58
60
50
50
48
58
58
60
dBc
dBc
dBc
Crosstalk Rejection6
DIGITAL OUTPUTS
Logic “1” Voltage (IOH = 2 mA)
Logic “0” Voltage (IOL = 2 mA)
Full
Full
VI
VI
2.4
2.4
V
V
0.4
0.4
POWER SUPPLY7
+VS Supply Current
–VS Supply Current
Power Dissipation
Full
Full
Full
VI
VI
VI
127
27
770
154
38
960
127
27
770
154
38
960
mA
mA
mW
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2For applications in which +VS may be applied before –VS, or +VS current is not limited to 500 mA, a reverse biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”
3Typical thermal impedances: 44-lead hermetic J-Leaded ceramic package: θJA = 86.4°C/W; θJC = 24.9°C/W; 48-lead hermetic DIP θJA = 40°C/W;
θ
JC = 12°C/W.
4To achieve guaranteed conversion rate, connect each data output to ground through
a 2 k Ω pull-down resistor.
5SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.
6Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.
7Applies to both A/Ss and includes internal ladder dissipation.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
ORDERING GUIDE
Temperature
Package
Option1
I
– 100% production tested.
Model
Range
Description
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
AD9058JJ
0°C to +70°C
44-Lead J-Leaded
Ceramic2
J-44
J-44
J-44
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
AD9058KJ
0°C to +70°C
44-Lead J-Leaded
Ceramic, AC Tested
AD9058TJ/8833 –55°C to +125°C 44-Lead J-Leaded
V
– Parameter is a typical value only.
Ceramic, AC Tested
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
AD9058JD
AD9058KD
0°C to +70°C
0°C to +70°C
48-Lead Ceramic DIP D-48
48-Lead Ceramic
DIP, AC Tested
D-48
AD9058TD/8833 –55°C to +125°C 48-Lead Ceramic
D-48
DIP, AC Tested
NOTES
1D = Hermetic Ceramic DIP Package; J = Leaded Ceramic Package.
2Hermetically sealed ceramic package; footprint equivalent to PLCC.
3For specifications, refer to Analog Devices Military Products Databook.
–3–
REV. B
AD9058
PIN DESCRIPTIONS
Function
J-Lead
Pin Number
ADC-A ADC-B
Ceramic DIP
Pin Number
Name
ADC-A
ADC-B
3
4
5
6
7
8
9
43
42
41
40
39
38
37
36
35
34–29
28
27
26
25
24
+VREF
GROUND
+VS
AIN
–VS
–VREF
+VS
ENCODE
D7 (MSB)
D6–D1
D0 (LSB)
GROUND
–VS
Top of internal voltage reference ladder.
Analog ground return.
Positive 5 V analog supply voltage.
Analog input voltage.
14
15
16
17
19
20
22
23
11
10
9
8
6
5
3
2
48
47–42
41
1, 4, 40
39
38
Negative 5 V supply voltage.
Bottom of internal voltage reference ladder.
Positive 5 V digital supply voltage.
TTL compatible convert command.
Most significant bit of TTL digital output.
TTL compatible digital output bits.
Least significant bit of TTL digital output.
Digital ground return.
Negative 5 V supply voltage.
Analog ground return.
Positive 5 V analog supply voltage.
10
11
12–17
18
19
20
21
22
25
26–31
32
21, 24, 33
34
35
GROUND
+VS
36
37
COMMON PINS
1
COMMON PINS
12
COMP
+VINT
Connection for external (0.1 µF)
compensation capacitor.
Internal +2 V reference; can drive
+VREF for both ADCs.
2
13
GROUND
ENCODE
1
48
D
(MSB)
7
D
D
D
D
6
5
4
3
+V
S
6
40
GROUND
39
–V
7
–V
REF
–V
S
S
–V
S
D
D
2
1
–V
–V
REF
REF
NC
A
D
(LSB)
0
IN
+V
+V
S
S
+V
S
GROUND
ENCODE
(MSB)
ENCODE
–V
GROUND
S
D
(MSB)
D
7
+V
7
GROUND
REF
AD9058
TOP VIEW
+V
S
COMP
D
6
D
D
D
6
5
4
+V
S
+V
INT
D
5
(Not to Scale)
+V
GROUND
REF
D
4
–V
GROUND
S
+V
S
GROUND
D
3
D
D
3
A
D
(LSB)
IN
0
D
2
2
D
D
D
D
NC
1
2
3
4
GROUND
D
1
D
1
–V
S
–V
29
REF
17
GROUND
18
28
+V
S
D
D
5
6
ENCODE
GROUND
24
D
(MSB)
7
25
NC = NO CONNECT
NC = NO CONNECT
AD9058JD/KD Pinouts
AD9058JJ/KJ Pinouts
+V
S
+5.0V
+V
D –D *
–V
REF
S
0
7
+V
A
**
INT
IN
13kΩ
ENCODE**
+V
+V
REF
+5V
–5.2V
S
S
COMP AD9058
GROUND
ENCODE
0.1F
–V
DIGITAL BITS
* INDICATES EACH PIN IS CONNECTED THROUGH 2 k⍀
** INDICATES EACH PIN IS CONNECTED THROUGH 100 ⍀
AD9058 Equivalent Encode Circuit
AD9058 Burn-In Connections
AD9058 Equivalent Digital Outputs
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
AD9058
THEORY OF OPERATION
ANALOG IN
128
127
The AD9058 contains two separate 8-bit analog-to-digital con-
verters (ADCs) on a single silicon die. The two devices can be
operated independently with separate analog inputs, voltage
references and clocks.
+V
REF
256
8
8
In a traditional flash converter, 256 input comparators are required
to make the parallel conversion for 8-bit resolution. This is in
marked contrast to the scheme used in the AD9058, as shown
in Figure 1.
2
1
Unlike traditional “flash,” or parallel, converters, each of the two
ADCs in the AD9058 utilizes a patented interpolating archi-
tecture to reduce circuit complexity, die size and input capacitance.
These advantages accrue because, compared to a conventional
flash design, only half the normal number of input comparator
cells is required to accomplish the conversion.
–V
REF
Figure 1. AD9058 Comparator Block Diagram
The onboard voltage reference, +VINT, is a bandgap reference
which has sufficient drive capability for both reference ladders.
It provides a +2 V reference that can drive both ADCs in the
AD9058 for unipolar positive operation (0 V to +2 V).
In this unit, each of the two independent ADCs uses only 128
(27) comparators to make the conversion. The conversion for
the seven most significant bits (MSBs) is performed by the 128
comparators. The value of the least significant bit (LSB) is
determined by interpolation between adjacent comparators in
the decoding register. A proprietary decoding scheme processes
the comparator outputs and provides an 8-bit code to the output
register of each ADC; the scheme also minimizes error codes.
USING THE AD9058
Refer to Figure 2. Using the internal voltage reference con-
nected to both ADCs as shown reduces the number of external
components required to create a complete data acquisition sys-
tem. The input ranges of the ADCs are positive unipolar in this
configuration, ranging from 0 V to +2 V. Bipolar input signals
are buffered, amplified and offset into the proper input range of
the ADC using a good low distortion amplifier such as the
AD9617 or AD9618.
Analog input range is established by the voltages applied at the
voltage reference inputs (+VREF and –VREF). The AD9058 can
operate from 0 V to +2 V using the internal voltage reference,
or anywhere between –1 V and +2 V using external references.
Input range is limited to 2 V p-p when using external references.
The internal resistor ladder divides the applied voltage reference
into 128 steps, with each step representing two 8-bit quantiza-
tion levels.
1k
ENCODE
74HCT04
10pF
50
10
36
ENCODE
A
ENCODE
B
5, 9, 22,
8
+V
+5V
–V
S
REF A
24, 37, 41
400
38
–V
REF B
18
D
(LSB)
200
0A
ANALOG
IN A
17
16
15
14
13
12
11
–
5
6
0.5 V
A
AD9617
+
IN A
8
800
+
2
3
+V
INT
–
2V
AD707
20k
20k
0.1µF
D
(MSB)
(LSB)
+2V
7A
0.1µF
–
+V
REF A
CLOCK
28
29
30
31
32
33
34
35
D
0B
43
1
+V
REF B
800
400
8
COMP
0.1µF
200
ANALOG
IN B
–
5
40
0.5 V
A
AD9617
+
D
(MSB)
IN B
7B
CLOCK
7, 20,
–V
–
5V
S
AD9058
26, 39
(J-LEAD)
1N4001
(SEE TEXT)
0.1µF
4,19, 21
25, 27, 42
Figure 2. AD9058 Using Internal +2 V Voltage Reference
–5–
REV. B
AD9058
+5V
1
3
AD580
2
1k
74ACT04
ENCODE
10pF
50k
10k
10k
+5V
10
36
+
150
2N3904
10
ENCODE
A
1/2
AD708
ENCODE
B
0.1µF
–
5, 9, 22,
24, 37, 41
+V
+5V
0.1µF
3
S
+V
REF A
20k
400
0.1µF
5
43
+1V
+V
A
REF B
50
ANALOG
IN A
0.125 V
RZ1
–
18
D
(LSB)
0A
1V
6
17
16
15
14
13
12
11
AD9618
IN A
+
8
20k
150
10
8
–V
REF A
D
(MSB)
(LSB)
–
7A
1/2
AD708
0.1µF
CLOCK
38
RZ2
2N3906
5V
–V
+
REF B
28
29
30
31
32
33
34
35
–1V
D
0B
–
400
8
50
ANALOG
IN B
–
5k
1 V
0.125 V
AD9618
A
IN B
40
1
+
D
(MSB)
7B
COMP
CLOCK
0.1µF
7, 20,
–V
AD9058
(J-LEAD)
S
–5V
1N4001
RZ1, RZ2 = 2,000Ω SIP (8/PKG)
26, 39
(SEE TEXT)
0.1µF
4,19, 21
25, 27, 42
Figure 3. AD9058 Using External Voltage References
The AD9058 offers considerable flexibility in selecting the ana-
log input ranges of the ADCs; the two independent ADCs can
even have different input ranges if required. In Figure 3 above,
the AD9058 is shown configured for 1 V operation.
logic family devices have short set-up and hold times and are the
recommended choices for speeds of 40 MSPS or more.
Layout
To insure optimum performance, a single low-impedance ground
plane is recommended. Analog and digital grounds should be
connected together and to the ground plane at the AD9058 de-
vice. Analog and digital power supplies should be bypassed to
ground through 0.1 µF ceramic capacitors as close to the unit as
possible.
The Reference Ladder Offset shown in the specifications table re-
fers to the error between the voltage applied to the +VREF (top)
or –VREF (bottom) of the reference ladder and the voltage re-
quired at the analog input to achieve a 1111 1111 or 0000 0000
transition. This indicates the amount of adjustment range which
must be designed into the reference circuit for the AD9058.
An evaluation board (ADI part #AD9058/PCB) is available to
aid designers and provide a suggested layout. The use of sockets
may limit the dynamic performance of the part and is not rec-
ommended except for prototype or evaluation purposes.
The diode shown between ground and –VS is normally reverse
biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow
+VS to be applied before –VS; or the +VS supply is not current
limited. If the negative supply is allowed to float (the +5 V sup-
ply is powered up before the –5 V supply), substantial +5 V
supply current will attempt to flow through the substrate (VS
supply contact) to ground. If this current is not limited to <500
mA, the part may be destroyed. The diode prevents this poten-
tially destructive condition from occurring.
For prototyping or evaluation, surface mount sockets are available
from Methode (part #213-0320602) for evaluating AD9058 sur-
face mount packages. To evaluate the AD9058 in through-hole
PCB designs, use the AD9058JD/KD with individual pin sockets
(AMP part #6-330808-0). Alternatively, surface mount AD9058
units can be mounted in a through-hole socket (Circuit Assembly
Corporation, Irvine California part #CA-44SPC-T).
Timing
AD9058 APPLICATIONS
Refer to the AD9058 Timing Diagram. The AD9058 provides
latched data outputs with no pipeline delay. To conserve power,
the data outputs have relatively slow rise and fall times. When
designing system timing, it is important to observe (1) set-up
and hold times; and (2) the intervals when data is changing.
Combining two ADCs in a single package is an attractive alter-
native in a variety of systems when cost, reliability and space are
important considerations. Different systems emphasize particu-
lar specifications, depending on how the part is used.
In high density digital radio communications, a pair of high
speed ADCs are used to digitize the in-phase (I) and quadrature
(Q) components of a modulated signal. The signal presented to
each ADC in this type of system consists of message-dependent
amplitudes varying at the symbol rate, which is equal to the
sample rates of the converters.
Figure 3 shows 2 kΩ pull-down resistors on each of the D0–D7
output data bits. When operating at conversion rates higher than
40 MSPS, these resistors help equalize rise and fall times and
ease latching the output data into external latches. The 74ACT
–6–
REV. B
AD9058
N
ANALOG INPUT
ENCODE
tA
N + 1
N + 2
tA= APERTURE TIME
= DATA DELAY OF
PRECEDING ENCODE
tV
tV
tPD = OUTPUT PROPAGATION DELAY
VALID DATA
FOR N – 1
VALID DATA
FOR N
VALID DATA
FOR N + 1
D
– D
7
0
tPD
DATA
CHANGING
Figure 4. AD9058 Timing Diagram
Figure 5 below shows what the analog input to the AD9058 would
look like when observed relative to the sample clock. Signal-
to-noise ratio (SNR), transient response, and sample rate are all
critical specifications in digitizing this “eye pattern.”
is actual rms error calculated from the converter’s outputs with
a pure sine wave applied as the input.
Maximum conversion rate is defined as the encode (sample) rate
at which SNR of the lowest frequency analog test signal drops
no more than 3 dB below the guaranteed limit.
ANALOG
INPUT
60
+125°C
+25°C
55
–55°C
SAMPLE
CLOCK
50
45
40
Figure 5. AD9058 I and Q Input Signals
Receiver sensitivity is limited by the SNR of the system. For the
ADC, SNR is measured in the frequency domain and calculated
with a Fast Fourier Transform (FFT). The signal-to-noise ratio
equals the ratio of the fundamental component of the signal
(rms amplitude) to the rms level of the noise. Noise is the sum
of all other spectral components, including harmonic distortion,
but excluding dc.
35
30
0.1
1
10
100
INPUT FREQUENCY – MHz
Although the signal being sampled does not have a significant
slew rate at the instant it is encoded, dynamic performance of
the ADC and the system is still critical. Transient response is the
time required for the AD9058 to achieve full accuracy when a
step function input is applied. Overvoltage recovery time is the in-
terval required for the AD9058 to recover to full accuracy after
an overdriven analog input signal is reduced to its input range.
Figure 6. Harmonic Distortion vs. Analog Input Frequency
55
+25°C AND +125°C
50
45
8.0
7.2
6.4
5.5
Time domain performance of the ADC is also extremely impor-
tant in digital oscilloscopes. When a track (sample)-and-hold is
used ahead of the ADC, its operation becomes similar to that
described above for receivers.
40
35
30
–55°C
The dynamic response to high-frequency inputs can be described
by the effective number of bits (ENOB). The effective number of bits
is calculated with a sine wave curve fit and is expressed as:
ENOB = N – LOG2 [Error (measured)/Error (ideal)]
0.1
1
10
100
where N is the resolution (number of bits) and measured error
INPUT FREQUENCY – MHz
Figure 7. AD9058 Dynamic Performance vs. Analog Input
Frequency
–7–
REV. B
AD9058
MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . 106 × 108 × 15 ( 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
Bond Wire . . . . . . . . . . . . 1–1.3 mil, Gold; Gold Ball Bonding
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead J-Leaded Ceramic (J-44) Package
48-Lead Hermetic Ceramic DIP (D-48) Package
0.690 0.012 SQ.
(17.5 0.305)
0.650 0.008 SQ.
(16.51 0.203)
PIN 1
6
40
48
1
25
24
7
39
0.225 MAX
(5.72 MAX)
2.400 0.024
0.060 (1.52)
0.050 TYP
(1.27)
(60.96 0.609)
0.015 (0.38)
0.020 TYP
(0.508)
0.70 MAX
(1.77 MAX)
0.023 (0.58)
0.014 (0.36)
0.110 (2,79)
0.090 (2.29)
0.150
(3.81)
MIN
29
17
0.62 (15.75)
0.59 (12.95)
18
28
0.500 0.008
(12.70 0.203)
0.135 (3.42)
MAX
0.015 (0.38)
0.008 (0.20)
0.017 (0.432)
TYP
0.037 0.012
(0.940 0.305)
0.63 (16.00)
0.52 (13.21)
0.630 0.020
(16.0 0.058)
–8–
REV. B
相关型号：
AD9058CHIPS
IC DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, UUC42, 0.106 X 0.108 INCH, 0.015 INCH HEIGHT, DIE-42, Analog to Digital Converter
ADI
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