AD9058AJJ-REEL [ADI]
Dual 8-Bit 50 MSPS A/D Converter; 双路，8位50 MSPS A / D转换器
| 型号： | AD9058AJJ-REEL |
| 厂家： | 
ADI |
| 描述： | Dual 8-Bit 50 MSPS A/D Converter |
| 文件： | 总11页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 8-Bit 50 MSPS
A/D Converter
a
AD9058
FUNCTIONAL BLOCK DIAGRAM
FEATURES
2 Matched ADCs on Single Chip
50 MSPS Conversion Speed
On-Board Voltage Reference
Low Power (<1 W)
AD9058
+V
REF
Low Input Capacitance (10 pF)
65 V Power Supplies
Flexible Input Range
ENCODE
8-BIT
8
ANALOG-
TO-DIGITAL
CONVERTER
A
A
IN
APPLICATIONS
–V
REF
Quadrature Demodulation for Communications
Digital Oscilloscopes
Electronic Warfare
2V
REF
Radar
+V
REF
ENCODE
8
8-BIT
ANALOG-
TO-DIGITAL
CONVERTER
B
GENERAL DESCRIPTION
A
IN
The AD9058 combines two independent, high performance,
8-bit analog-to-digital converters (ADCs) on a single monolithic
IC. Combined with an optional on-board voltage reference,
the AD9058 provides a cost-effective alternative for systems
requiring two or more ADCs.
–V
REF
Dynamic performance (SNR, ENOB) is optimized to provide
up to 50 MSPS conversion rates. The unique architecture
results in low input capacitance while maintaining high per-
formance and low power (<0.5 W/channel). Digital inputs
and outputs are TTL compatible.
QUADRATURE RECEIVER
G
8
8
Q
Performance has been optimized for an analog input of 2 V p-p
( 1 V; 0 V to 2 V). Using the on-board 2 V voltage reference,
the AD9058 can be set up for unipolar positive operation
(0 V to 2 V). This internal voltage reference can drive
both ADCs.
AD9058
RF
LO
90؇
I
G
Commercial (0°C to 70°C) and military (–55°C to +125°C)
temperature range parts are available. Parts are supplied in
hermetic 48-lead DIP and 44-lead “J” lead packages.
E
REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
781/461-3113
www.analog.com
Analog Devices, Inc. All rights reserved.
2012
Fax:
©
AD9058–SPECIFICATIONS
[؎VS = ؎5 V; VREF = 2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to 2 V; –VREF
=
GROUND, unless otherwise noted.]1 All specifications apply to either of the two ADCs.
ELECTRICAL CHARACTERISTICS
Test
AD9058AJD/AJJ
AD9058AKD/AKJ
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
I
VI
I
VI
VI
0.25
0.5
0.65
0.8
1.3
1.4
0.25
0.5
0.5
0.7
1.0
1.25
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Full
Guaranteed
75
Guaranteed
75
ANALOG INPUT
Input Bias Current
25°C
Full
25°C
25°C
25°C
I
VI
I
IV
V
170
340
170
340
μA
μA
Input Resistance
Input Capacitance
Analog Bandwidth
12
28
10
175
12
28
10
175
kΩ
15
15
pF
MHz
REFERENCE INPUT
Reference Ladder Resistance
25°C
Full
Full
25°C
Full
25°C
Full
Full
I
120
80
170
220
270
120
80
170
220
270
Ω
VI
V
I
VI
I
VI
V
Ω
Ladder Tempco
Reference Ladder Offset
(Top)
Reference Ladder Offset
(Bottom)
0.45
8
0.45
8
Ω/°C
mV
mV
mV
mV
μV/°C
16
24
23
33
16
24
23
33
8
8
Offset Drift Coefficient
50
50
INTERNAL VOLTAGE REFERENCE
Reference Voltage
25°C
Full
Full
I
VI
V
1.95
1.90
2.0
150
10
2.20
2.25
1.95
1.90
2.0
150
10
2.20
2.25
V
V
μV/°C
Temperature Coefficient
Power Supply Rejection
Ratio (PSRR)
25°C
I
25
25
mV/V
SWITCHING PERFORMANCE
Maximum Conversion Rate2
Aperture Delay (tA)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
Output Delay (Valid) (tV)2
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
I
50
0.8
0.2
10
8
16
12
–16
1
50
0.1
60
0.8
0.2
10
8
16
12
–16
1
MSPS
ns
ns
ps, rms
ns
ps/°C
ns
ps/°C
ns
IV
IV
V
I
V
I
0.1
1.5
0 5
1.5
0.5
5
Output Delay (tV) Tempco
2
Propagation Delay (tPD
)
19
Propagation Delay (tPD) Tempco
Output Time Skew
V
V
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Pulsewidth (High)
Pulsewidth (Low)
Full
Full
Full
Full
25°C
25°C
25°C
VI
VI
VI
VI
V
I
I
2
2
V
V
μA
μA
pF
ns
ns
0.8
600
1000
0.8
600
1000
5
8
8
5
8
8
–2–
E
REV.
AD9058
Test
Level Min
AD9058AJD/AJJ
AD9058AKD/AKJ
Parameter
Temp
Typ
Max Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Transient Response
25°C
25°C
V
V
2
2
2
2
ns
ns
Overvoltage Recovery Time
Effective Number of Bits (ENOB)3
Analog Input @ 2.3 MHz
@ 10.3 MHz
25°C
25°C
I
I
7.7
7.4
7.2
7.1
7.7
7.4
Bits
Bits
Signal-to-Noise Ratio3
Analog Input @ 2.3 MHz
@ 10.3 MHz
25°C
25°C
I
I
48
46
45
44
48
46
dB
dB
Signal-to-Noise Ratio3 (Without Harmonics)
Analog Input @ 2.3 MHz
@ 10.3 MHz
25°C
25°C
I
I
48
47
46
45
48
47
dB
dB
Second Harmonic Distortion
Analog Input @ 2.3 MHz
@ 10.3 MHz
25°C
25°C
I
I
58
58
48
48
58
58
dBc
dBc
Third Harmonic Distortion
Analog Input @ 2.3 MHz
@ 10.3 MHz
25°C
25°C
25°C
I
I
IV
58
58
60
50
50
48
58
58
60
dBc
dBc
dBc
Crosstalk Rejection4
DIGITAL OUTPUTS
Logic “1” Voltage (IOH = 2 mA)
Logic “0” Voltage (IOL = 2 mA)
Full
Full
VI
VI
2.4
2.4
V
V
0.4
0.4
POWER SUPPLY5
+VS Supply Current
–VS Supply Current
Power Dissipation
Full
Full
Full
VI
VI
VI
127
27
770
154
38
960
127
27
770
154
38
960
mA
mA
mW
NOTES
1For applications in which +VS may be applied before –VS, or +VS current is not limited to 500 mA, a reverse-biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”
2To achieve guaranteed conversion rate, connect each data output to ground through a 2 kΩ pull-down resistor.
3SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.
4Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.
5Applies to both A/Ss and includes internal ladder dissipation.
Specifications subject to change without notice.
E
–3–
REV.
AD9058
ABSOLUTE MAXIMUM RATINGS1
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +2.5 V
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to –6 V2
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . 53 mA
+VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 V
–VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V
Operating Temperature Range
AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . 0°C to 70°C
Maximum Junction Temperature3
AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2For applications in which +VS may be applied before –VS, or +VS current is
not limited to 500 mA, a reverse-biased clamping diode should be inserted
between ground and –VS to prevent destructive latch up. See section entitled
“Using the AD9058.”
3Typical thermal impedances: 44-lead hermetic J-leaded ceramic package: θJA = 86.4°C/W;
θ
JC = 24.9°C/W; 48-lead hermetic: DIP θJA = 40°C/W; θJC = 12°C/W.
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C, and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
+V
S
5V
+V
D –D *
–V
A
S
0
7
REF
**
13k⍀
+V
IN
INT
ENCODE**
+V
REF
+5V
–5.2V
+V
S
COMP
AD9058
DIGITAL BITS
ENCODE
0.1F
–V
S
GROUND
* INDICATES EACH PIN IS CONNECTEDTHROUGH 2k⍀
** INDICATES EACH PIN IS CONNECTEDTHROUGH 100⍀
Equivalent Encode Circuit
–4–
Burn-In Connections
Equivalent Digital Outputs
E
REV.
AD9058
PIN CONFIGURATIONS
GROUND
ENCODE
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
D
D
D
D
D
D
D
D
(MSB)
7
6
5
4
3
2
1
0
+V
S
GROUND
–V
REF
6
40
–V
S
NC
7
39
–V
–V
A
(LSB)
S
IN
S
+V
S
40 GROUND
39 –V
–V
–V
REF
REF
GROUND 10
+V 11
COMP 12
+V
S
S
+V
S
38 GROUND
REF
ENCODE
ENCODE
(MSB)
AD9058
TOP VIEW
(Not to Scale)
37 +V
36 +V
S
S
D
D
(MSB)
7
7
AD9058
+V
13
14
INT
D
6
D
D
6
TOPVIEW
(Not to Scale)
+V
35 GROUND
34 –V
REF
D
5
5
GROUND 15
S
D
4
D
D
D
4
3
2
+V
16
17
33 GROUND
S
D
3
A
32
31
30
29
28
27
26
25
D
D
D
D
D
D
D
D
(LSB)
IN
0
1
2
3
4
5
6
7
D
2
NC 18
GROUND
D
1
D
1
19
20
–V
S
17
29
–V
REF
28
18
GROUND 21
+V 22
S
ENCODE 23
GROUND 24
(MSB)
NC = NO CONNECT
NC = NO CONNECT
AD9058AJJ/AKJ Pinouts
AD9058AJD/AKD Pinouts
PIN FUNCTION DESCRIPTIONS
Function
J-Lead
Pin Number
Ceramic DIP
Pin Number
ADC-A
ADC-B
Mnemonic
ADC-A
ADC-B
3
4
5
6
7
8
9
43
42
41
40
39
38
37
36
35
34–29
28
27
26
25
24
+VREF
GROUND
+VS
AIN
–VS
Top of Internal Voltage Reference Ladder
Analog Ground Return
Positive 5 V Analog Supply Voltage
Analog Input Voltage
14
15
16
17
19
20
22
23
11
10
9
8
6
5
3
2
48
47–42
41
1, 4, 40
39
38
Negative 5 V Supply Voltage
–VREF
+VS
Bottom of Internal Voltage Reference Ladder
Positive 5 V Digital Supply Voltage
TTL Compatible Convert Command
Most Significant Bit of TTL Digital Output
TTL Compatible Digital Output Bits
Least Significant Bit of TTL Digital Output
Digital Ground Return
Negative 5 V Supply Voltage
Analog Ground Return
Positive 5 V Analog Supply Voltage
10
11
12–17
18
19
20
21
22
ENCODE
D7 (MSB)
D6–D1
D0 (LSB)
GROUND
–VS
25
26–31
32
21, 24, 33
34
35
GROUND
+VS
36
37
COMMON PINS
1
COMMON PINS
12
COMP
+VINT
Connection for External (0.1 μF)
Compensation Capacitor
Internal 2 V Reference; Can Drive
+VREF for Both ADCs
2
13
E
–5–
REV.
AD9058
THEORY OF OPERATION
ANALOG IN
128
127
The AD9058 contains two separate 8-bit analog-to-digital con-
verters (ADCs) on a single silicon die. The two devices can be
operated independently with separate analog inputs, voltage
references, and clocks.
+V
REF
In a traditional flash converter, 256 input comparators are required
to make the parallel conversion for 8-bit resolution. This is in
marked contrast to the scheme used in the AD9058, as shown
in Figure 1.
256
8
8
2
1
Unlike traditional “flash,” or parallel, converters, each of the two
ADCs in the AD9058 utilizes a patented interpolating archi-
tecture to reduce circuit complexity, die size, and input capacitance.
These advantages accrue because, compared to a conventional
flash design, only half the normal number of input comparator
cells is required to accomplish the conversion.
–V
REF
Figure 1. Comparator Block Diagram
In this unit, each of the two independent ADCs uses only 128 (27)
comparators to make the conversion. The conversion for the
seven most significant bits (MSBs) is performed by the 128
comparators. The value of the least significant bit (LSB) is
determined by interpolation between adjacent comparators in
the decoding register. A proprietary decoding scheme processes
the comparator outputs and provides an 8-bit code to the output
register of each ADC; the scheme also minimizes error codes.
Analog input range is established by the voltages applied at the
voltage reference inputs (+VREF and –VREF). The AD9058 can
operate from 0 V to 2 V using the internal voltage reference,
or anywhere between –1 V and +2 V using external references.
Input range is limited to 2 V p-p when using external references.
The internal resistor ladder divides the applied voltage reference
into 128 steps, with each step representing two 8-bit quanti-
zation levels.
1k⍀
ENCODE
74HCT04
10pF
50⍀
10
36
ENCODE
A
ENCODE
B
5, 9, 22,
24, 37, 41
8
–V
+V
S
REF A
+5V
400⍀
38
–V
REF B
18
17
16
15
14
13
12
11
D
(LSB)
0A
200⍀
ANALOG
IN A ؎0.5V
5⍀
6
A
AD9617
IN A
8
800⍀
2
3
+V
INT
–2V
AD707
D
(MSB)
(LSB)
7A
+2V
20k⍀
0.1F
0.1F
+V
REF A
CLOCK
20k⍀
28
29
30
31
32
33
34
35
D
0B
43
1
+V
REF B
800⍀
400⍀
8
COMP
0.1F
200⍀
ANALOG
IN B ؎0.5V
5⍀
40
A
D
(MSB)
AD9617
IN B
7B
7, 20,
CLOCK
26, 39
–5V
1N4001
AD9058
(J-LEAD)
–V
S
(SEETEXT)
0.1F
4, 19, 21,
25, 27, 42
Figure 2. AD9058 Using Internal 2 V Voltage Reference
–6–
E
REV.
AD9058
1k⍀
ENCODE
74ACT04
+5V
1
10pF
50k⍀
3
AD580
2
10
36
10k⍀
10k⍀
ENCODE
A
ENCODE
B
+5V
2N3904
150⍀
5, 9, 22,
24, 37, 41
1/2
AD708
+V
S
+5V
10⍀
0.1F
0.1F
3
+V
REF A
RZ1
20k⍀
18
17
16
15
14
13
12
11
0.1F
D
(LSB)
43
400⍀
0A
+V
REF B
ANALOG
50⍀
IN A
5⍀
؎1V
؎0.125V
8
AD9618
A
IN A
6
20k⍀
150⍀
D
(MSB)
(LSB)
7A
10k⍀
2N3906
–5V
8
CLOCK
–V
–V
REF A
1/2
AD708
RZ2
28
29
30
31
32
33
34
35
0.1F
D
0B
38
REF B
–1V
400⍀
8
ANALOG
IN B
؎0.125V
50⍀
5k⍀
؎1V
A
AD9618
IN B
40
D
(MSB)
7B
COMP
7, 20,
26, 39
1
CLOCK
0.1F
–5V
1N4001
AD9058
(J-LEAD)
–V
S
(SEETEXT)
0.1F
4, 19, 21,
25, 27, 42
Figure 3. AD9058 Using External Voltage References
limited. If the negative supply is allowed to float (the +5 V supply
is powered up before the –5 V supply), substantial +5 V supply
current will attempt to flow through the substrate (VS supply con-
tact) to ground. If this current is not limited to <500 mA, the part
may be destroyed. The diode prevents this potentially destructive
condition from occurring.
The on-board voltage reference, +VINT, is a band gap reference
that has sufficient drive capability for both reference ladders.
It provides a 2 V reference that can drive both ADCs in the
AD9058 for unipolar positive operation (0 V to 2 V).
USING THE AD9058
Refer to Figure 2. Using the internal voltage reference con-
nected to both ADCs as shown reduces the number of external
components required to create a complete data acquisition
system. The input ranges of the ADCs are positive unipolar
in this configuration, ranging from 0 V to 2 V. Bipolar input
signals are buffered, amplified, and offset into the proper input
range of the ADC using a good low distortion amplifier such
as the AD9617 or AD9618.
Timing
Refer to the AD9058 Timing Diagram, Figure 4. The AD9058
provides latched data outputs with no pipeline delay. To conserve
power, the data outputs have relatively slow rise and fall times.
When designing system timing, it is important to observe (1) setup
and hold times; and (2) the intervals when data is changing.
Figure 3 shows 2 kΩ pull-down resistors on each of the D0–D7
output data bits. When operating at conversion rates higher than
40 MSPS, these resistors help equalize rise and fall times and
ease latching the output data into external latches. The 74ACT
logic family devices have short setup and hold times and are the
recommended choices for speeds of 40 MSPS or more.
The AD9058 offers considerable flexibility in selecting the analog
input ranges of the ADCs; the two independent ADCs can even
have different input ranges if required. In Figure 3, the AD9058
is shown configured for 1 V operation.
The “Reference Ladder Offset” shown in the specifications table
refers to the error between the voltage applied to the +VREF (top)
or –VREF (bottom) of the reference ladder and the voltage required
at the analog input to achieve a 1111 1111 or 0000 0000 transi-
tion. This indicates the amount of adjustment range that must be
designed into the reference circuit for the AD9058.
Layout
To ensure optimum performance, a single low impedance ground
plane is recommended. Analog and digital grounds should be con-
nected together and to the ground plane at the AD9058 device.
Analog and digital power supplies should be bypassed to ground
through 0.1 μF ceramic capacitors as close to the unit as possible.
The diode shown between ground and –VS is normally reverse-
biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow
+VS to be applied before –VS; or the +VS supply is not current
For prototyping or evaluation, surface-mount sockets are available
from Methode Electronics, Inc. (Part No. 213-0320602) for
evaluating AD9058 surface-mount packages. To evaluate the
E
–7–
REV.
AD9058
AD9058 in through-hole PCB designs, use the AD9058AJD/AKD
with individual pin sockets (AMP Part No. 6-330808-0). Alterna-
tively, surface-mount AD9058 units can be mounted in a
through-hole socket (Circuit Assembly Corporation, Irvine, Cali-
fornia Part No. CA-44SPC-T).
the time required for the AD9058 to achieve full accuracy when
a step function input is applied. Overvoltage recovery time is the
interval required for the AD9058 to recover to full accuracy after an
overdriven analog input signal is reduced to its input range.
Time domain performance of the ADC is also extremely important
in digital oscilloscopes. When a track-/sample-and-hold is used
ahead of the ADC, its operation becomes similar to that described
above for receivers.
AD9058 APPLICATIONS
Combining two ADCs in a single package is an attractive alterna-
tive in a variety of systems when cost, reliability, and space are
important considerations. Different systems emphasize particular
specifications, depending on how the part is used.
The dynamic response to high frequency inputs can be described by
the effective number of bits (ENOB). The effective number of
bits is calculated with a sine wave curve fit and is expressed as:
In high density digital radio communications, a pair of high
speed ADCs are used to digitize the in-phase (I) and quadrature
(Q) components of a modulated signal. The signal presented to
each ADC in this type of system consists of message-dependent
amplitudes varying at the symbol rate, which is equal to the
sample rates of the converters.
ENOB = N − LOG2 Error measured Error ideal
(
)
(
)
]
[
where N is the resolution (number of bits) and measured error is
actual rms error calculated from the converter’s outputs with
a pure sine wave applied as the input.
Maximum conversion rate is defined as the encode (sample)
rate at which SNR of the lowest frequency analog test signal
drops no more than 3 dB below the guaranteed limit.
N
ANALOG
INPUT
N+1
tA
N+2
60
+125 C
ENCODE
D –D
55
50
45
40
35
30
+25 C
tV
–55 C
VALID DATA
FOR N–1
VALID DATA
FOR N
VALID DATA
FOR N+1
0
7
tPD
DATA
CHANGING
tA = APERTURETIME
tV = DATA DELAY OF PRECEDING ENCODE
tPD = OUTPUT PROPAGATION DELAY
Figure 4. Timing Diagram
Figure 5 shows what the analog input to the AD9058 would
look like when observed relative to the sample clock. Signal-to-
noise ratio (SNR), transient response, and sample rate are all
critical specifications in digitizing this “eye pattern.”
0.1
1
10
100
INPUT FREQUENCY – MHz
Figure 6. Harmonic Distortion vs. Analog Input Frequency
ANALOG
INPUT
55
50
45
40
35
30
8.0
7.2
SAMPLE
CLOCK
+25 C AND +125 C
Figure 5. I and Q Input Signals
Receiver sensitivity is limited by the SNR of the system. For the
ADC, SNR is measured in the frequency domain and calculated
with a Fast Fourier Transform (FFT). The signal-to-noise ratio
equals the ratio of the fundamental component of the signal
(rms amplitude) to the rms level of the noise. Noise is the sum
of all other spectral components, including harmonic distortion,
but excluding dc.
6.4
5.5
–55 C
0.1
1
10
100
INPUT FREQUENCY – MHz
Although the signal being sampled does not have a significant
slew rate at the instant it is encoded, dynamic performance of
the ADC and the system is still critical. Transient response is
Figure 7. Dynamic Performance vs. Analog Input
Frequency
–8–
E
REV.
AD9058
MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . 106 mils × 108 mils × 15 ( 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils
Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
Bond Wire . . . . . . . . . 1 mil–1.3 mil, Gold; Gold Ball Bonding
A
D
(LSB)
IN
0
+V
GROUND
S
–V
S
GROUND
+V
GROUND
REF
+V
S
COMP
+VINT
+V
S
+V
GROUND
REF
–V
S
GROUND
+V
S
GROUND
A
D (LSB)
0
IN
E
–9–
REV.
AD9058
OUTLINE DIMENSIONS
0.078 (1.98)
0.040 (1.02)
REF
0.020 (0.51)
REF
45°
0.662 (16.82)
0.628 (15.95)
0.054 (1.37)
SQ
45°
0.025 (0.64)
MIN
3 PLACES
39
29
40
28
0.032 (0.81)
0.020 (0.51)
PIN 1 INDEX
0.065 (1.65)
0.050
(1.27)
BSC
0.650 (16.51)
0.610 (15.49)
PIN 1
0.500 (12.70)
0.492 (12.50)
BOTTOM VIEW
TOP VIEW
0.023 (0.58)
0.013 (0.33)
6
18
7
17
0.700 (17.78)
0.680 (17.27)
SQ
0.135 (3.43)
0.100 (2.54)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
44-Lead Ceramic Leaded Chip Carrier — J-Formed Leads [JLCC]
(J-44)
Dimensions shown in inches and (millimeters)
0.098 (2.49)
MAX
0.005 (0.13)
MIN
48
25
0.620 (15.75)
0.590 (14.99)
PIN 1
1
24
0.630 (16.00)
0.520 (13.21)
0.225 (5.72)
MAX
2.424 (63.57) MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
0.110 (2.79)
0.090 (2.29)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
48-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-48)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
AD9058AJJ
AD9058AJJ-REEL
AD9058AKJ
AD9058ATJ/883B
AD9058AJD
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
–55°C to +125°C
0°C to 70°C
Package Description
44-Lead JLCC
44-Lead JLCC
44-Lead JLCC
44-Lead JLCC
48-Lead SBDIP
48-Lead SBDIP
48-Lead SBDIP
Package Option2
J-44
J-44
J-44
J-44
D-48
D-48
D-48
AD9058AKD
AD9058ATD/883B
0°C to 70°C
–55°C to +125°C
1 For AD9058ATJ/883B and AD9058ATD/883B specifications, refer to Analog Devices Military Products Databook.
2 D = Hermetic ceramic DIP package; J = leaded ceramic package.
Rev. E | Page 10
AD9058
REVISION HISTORY
9/12—Rev. D to Rev. E
Changes to Mechanical Information Figure ................................. 9
Changes to Outline Dimensions................................................... 10
Changes to Ordering Guide .......................................................... 10
5/03—Rev. C to Rev. D
Changes to Ordering Guide ............................................................ 4
Changes to Outline Dimensions................................................... 10
6/01—Rev. B to Rev. C
Edits to ELECTRICAL CHARACTERISTICS headings............. 2
Edits to ABSOLUTE MAXIMUM RATINGS .............................. 4
Edits to ORDERING GUIDE.......................................................... 4
Edits to Pinout captions................................................................... 5
Edits to Layout section..................................................................... 7
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00562-0-9/12(E)
Rev. E | Page 11
相关型号：
AD9058CHIPS
IC DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, UUC42, 0.106 X 0.108 INCH, 0.015 INCH HEIGHT, DIE-42, Analog to Digital Converter
ADI
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