AD8598ARU-REEL [ADI]
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| 型号： | AD8598ARU-REEL |
| 厂家： | 
ADI |
| 描述： | 暂无描述 比较器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 7 ns
a
Single Supply Comparator
AD8598
FEATURES
PIN CONFIGURATIONS
7 ns Propagation Delay
Single Supply Operation: +3 V to +10 V
Low Power
Symmetrical Layout
Latch Function
N-16, RU-16 and R-16A
1
2
3
4
5
6
7
8
16 QB
QA
15
QA
GND
LEA
NC
QB
14
13
12
11
10
9
GND
LEB
NC
TSSOP Packages
AD8598
TOP VIEW
APPLICATIONS
Clock Recovery and Clock Distribution
High Speed Data
Line Receivers
Phase Detectors
(Not to Scale)
V–
V+
IN B–
IN B+
IN A–
IN A+
NC = NO CONNECT
Digital Communications
I and Q Detection
High Speed Sampling
Upgrade for MAX912
Satellite Receivers
PCMCIA Cards
Wireless Data Links
Battery Operated Instrumentation
GENERAL DESCRIPTION
The AD8598 is a dual 7 ns comparator with digital latches.
Separate supplies enable the input stage to be operated from
+5 V to as high as ±5 V.
Ultrafast 7 ns propagation delay makes the AD8598 a good
choice for timing circuits and line receivers. Propagation delays
for rising and falling signals are closely matched and track over
temperature. This matched delay makes the AD8598 a good
choice for clock recovery, since the duty cycle of the output will
match the duty cycle of the input.
The AD8598 has the same pinout as the DIP version of the
AD9698. For a single comparator like the AD8598, please refer
to the AD8561 data sheet.
The AD8598 is specified over the industrial (–40°C to +85°C)
temperature range. The AD8598 is available in both the 16-lead
plastic DIP, 16-lead TSSOP or narrow R-16A surface mount
packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
AD8598–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V+ = +5.0 V, V– = VGND = 0 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
VOS
2.3
7
8
mV
mV
µV/°C
µA
µA
µA
–40°C ≤ TA ≤ +85°C
Offset Voltage Drift
Input Bias Current
∆VOS/∆T
IB
IB
IOS
4
–3
–3.5
VCM = 0 V
–40°C ≤ TA ≤ +85°C
VCM = 0 V
–6
–7
Input Offset Current
±4
Input Common-Mode Voltage Range VCM
0.0
65
+3.0
V
dB
V/V
pF
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Capacitance
CMRR
AVO
CIN
0 V ≤ VCM ≤ +3.0 V
RL = 10 kΩ
85
+3,000
3.0
LATCH ENABLE INPUT
Logic “1” Voltage Threshold
Logic “0” Voltage Threshold
Logic “1” Current
Logic “0” Current
Latch Enable
VIH
VIL
IIH
IIL
+2.0
+1.65
+1.60 +0.8
–0.3
–2
V
V
µA
µA
VLH = +3.0 V
VLL = +0.3 V
–1.0
–4
Pulsewidth
Setup Time
Hold Time
tPW(E)
tS
tH
6
1
1.2
ns
ns
ns
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “1” Voltage
Logic “0” Voltage
VOH
VOH
VOL
IOH = –50 µA, ∆VIN > 250 mV
IOH = –3.2 mA, ∆VIN > 250 mV
IOL = 3.2 mA, ∆VIN > 250 mV
+3.5
+2.4
V
V
V
+3.5
+0.25 +0.4
DYNAMIC PERFORMANCE
Propagation Delay
tP
tP
200 mV Step with 100 mV Overdrive
–40°C ≤ TA ≤ +85°C
100 mV Step with 5 mV Overdrive
6.75
8
8
9.8
13
ns
ns
ns
Propagation Delay
Differential Propagation Delay
(Rising Propagation Delay vs.
Falling Propagation Delay)
Rise Time
∆tP
100 mV Step with 100 mV Overdrive1
20% to 80%
80% to 20%
0.5
3.8
1.5
2.0
ns
ns
ns
Fall Time
POWER SUPPLY
Power Supply Rejection Ratio
Positive Supply Current (V+ Pin)
PSRR
I+
+4.5 V ≤ V+ ≤ +5.5 V
–40°C ≤ TA ≤ +85°C
50
65
9.0
dB
12.0
15.0
6.6
7.6
9.0
mA
mA
mA
mA
mA
mA
Ground Supply Current (GND Pins) IGND
Analog Supply Current (V– Pin) I–
VO = 0 V, RL =
–40°C ≤ TA ≤ +85°C
∞
4.4
4.6
–40°C ≤ TA ≤ +85°C
11.0
NOTES
1Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. A
AD8598
(@ V+ = +5.0 V, VGND = 0 V, V– = –5 V, TA = +25؇C unless otherwise noted)
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
VOS
1
7
8
mV
mV
µV/°C
µA
µA
µA
–40°C ≤ TA ≤ +85°C
Offset Voltage Drift
Input Bias Current
∆VOS/∆T
IB
IB
IOS
4
–3
–2.5
VCM = 0 V
–40°C ≤ TA ≤ +85°C
VCM = 0 V
–6
–7
Input Offset Current
±4
Input Common-Mode Voltage Range VCM
–5.0
65
+3.0
V
dB
V/V
pF
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Capacitance
CMRR
AVO
CIN
–5.0 V ≤ VCM ≤ +3.0 V
RL = 10 kΩ
85
+3,000
3.0
LATCH ENABLE INPUT
Logic “1” Voltage Threshold
Logic “0” Voltage Threshold
Logic “1” Current
Logic “0” Current
Latch Enable
VIH
VIL
IIH
IIL
+2.0
+1.65
+1.60 +0.8
–0.5
–2
V
V
µA
µA
VLH = +3.0 V
VLL = +0.3 V
–1
–4
Pulsewidth
Setup Time
Hold Time
tPW(E)
tS
tH
6
1.0
1.2
ns
ns
ns
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
VOH
VOL
IOH = –3.2 mA
IOL = 3.2 mA
+2.6
+3.5
+0.2
V
V
+0.3
DYNAMIC PERFORMANCE
Propagation Delay
tP
tP
200 mV Step with 100 mV Overdrive
–40°C ≤ TA ≤ +85°C
100 mV Step with 5 mV Overdrive
6.5
8
7
9.8
13
ns
ns
ns
Propagation Delay
Differential Propagation Delay
(Rising Propagation Delay vs.
Falling Propagation Delay)
Rise Time
∆tP
100 mV Step with 100 mV Overdrive1
20% to 80%
80% to 20%
0.5
3.8
1.5
1
2
ns
ns
ns
ns
Fall Time
Dispersion
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
PSRR
I+
±4.5 V ≤ VCC and VEE ≤ ±5.5 V
55
70
dB
VO = 0 V, RL =
∞
Positive Supply Current (V+ Pin)
9.4
4.4
4.8
13.0
15.0
6.6
7.6
9.0
mA
mA
mA
mA
mA
mA
–40°C ≤ TA ≤ +85°C
VO = 0 V, RL =
Ground Supply Current (GND Pins) IGND
Analog Supply Current (V– Pin) I–
∞
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
11.0
NOTES
1Guaranteed by design.
Specifications subject to change without notice.
REV. A
–3–
AD8598–SPECIFICATIONS
(@ V+ = +3.0 V, V– = VGND = 0 V, TA = +25؇C unless otherwise noted)
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
Input Bias Current
VOS
IB
IB
7
mV
µA
µA
V
VCM = 0 V
–40°C ≤ TA ≤ +85°C
–6
–7
0
–3.0
–4
Input Common-Mode Voltage Range VCM
Common-Mode Rejection Ratio
+1.5
+0.3
CMRR
+0.1 V ≤ VCM ≤ +1.5 V
50
dB
OUTPUT CHARACTERISTICS
Output High Voltage1
Output Low Voltage
VOH
VOL
IOH = –3.2 mA, VIN > 250 mV
IOL = +3.2 mA, VIN > 250 mV
+1.2
V
V
POWER SUPPLY
Power Supply Rejection Ratio
Supply Currents
PSRR
I+
+2.7 V ≤ VCC, VEE ≤ +6 V
40
dB
VO = 0 V, RL =
∞
Positive Supply Current (V+ Pin)
8.0
3.2
4.8
9.0
11.0
5.0
6.0
6.6
7.6
mA
mA
mA
mA
mA
mA
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
Ground Supply Current (GND Pins) IGND
Analog Supply Current (V– Pin)
I–
DYNAMIC PERFORMANCE
Propagation Delay
tP
100 mV Step with 20 mV Overdrive2
8.5
9.8
ns
NOTES
1Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for +3 V operation.
2Guaranteed by design.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Package Type
2
Units
JA
JC
Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . +14 V
16-Lead Plastic DIP
16-Lead SOIC
16-Lead TSSOP
103
158
240
43
43
43
°C/W
°C/W
°C/W
Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Positive Supply–Digital Positive Supply . . . . . –600 mV
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±8 V
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
NOTES
1The analog input voltage is equal to ±7 V or the analog supply voltage, whichever
is less.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for P-DIP and θJA is specified for device soldered in circuit board for SOIC and
TSSOP packages.
N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . .+300°C
ORDERING GUIDE
Package
Temperature
Range
Package
Options
Model
Descriptions
AD8598AN
AD8598ARU
AD8598AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
16-Lead Plastic DIP
16-Lead Thin Shrink Small Outline (TSSOP)
16-Lead Narrow Body IC
N-16
RU-16
R-16A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8598 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD8598
Typical Performance Characteristics (V+ = +5 V, V– = 0 V, TA = +25؇C unless otherwise noted)
5
4
3
2
1
0
20
15
10
5
500
400
300
200
100
0
+125؇C
V
= +5V, SINGLE SUPPLY
S
V
= +5V, SINGLE SUPPLY
S
STEP SIZE = 100mV
CAPACITANCE LOAD = 10pF
؊40؇C
T
= +25؇C
A
+25؇C
0
؊2.5 ؊2.0 ؊1.5 ؊1.0 ؊0.5
0
0.5 1.0 1.5
10
20
30
40
50
0
؊5 ؊4 ؊3 ؊2 ؊1
0
1
2
3
4
5
DIFFERENTIAL INPUT VOLTAGE – mV
OVERDRIVE – mV
INPUT VOLTAGE – mV
Figure 1. Output Voltage vs. Differen-
tial Input Voltage
Figure 2. Typical Distribution of Input
Offset Voltage
Figure 3. Propagation Delay vs.
Overdrive
20
40
20
V
= +5V, SINGLE SUPPLY
S
V
= +5V, SINGLE SUPPLY
S
T
= +25؇C
A
STEP SIZE = 100mV
OVERDRIVE LOAD = 5mV
OVERDRIVE = 10mV
CAPACITANCE LOAD = 10pF
SINGLE SUPPLY
STEP SIZE = 100mV
OVERDRIVE = 5mV
T
= +25؇C
A
15
10
5
30
20
10
0
15
10
5
CAPACITANCE LOAD = 10pF
STEP SIZE = 800mV
400mV
tPD
؊
FALLING EDGE
200mV
tPD
+
FALLING EDGE
100mV
0
0
10
20
30
40
50
0
0.5
1
1.5
2
0
4.5
4.75
5
5.25
5.5
LOAD CAPACITANCE – pF
SUPPLY VOLTAGE – Volts
SOURCE RESISTANCE – k⍀
Figure 4. Propagation Delay vs. Load
Capacitance
Figure 5. Propagation Delay vs.
Source Resistance
Figure 6. Propagation Delay vs. Posi-
tive Supply Voltage
20
20
4
3
+25؇C
V
= +5V, SINGLE SUPPLY
S
STEP SIZE = 100mV
OVERDRIVE = 5mV,
LOAD CAPACITANCE = 10pF
15
15
10
5
؊40؇C
+125؇C
10
2
1
0
HOLD TIME
SETUP TIME
5
0
V = +5V
S
STEP SIZE = 100mV
OVERDRIVE = 5mV
LOAD CAPACITANCE = 10pF
0
1
2
3
4
5
0
–50 –25
0
25
50
75
100 125
–50
–25
0
25
50
75
100 125
TEMPERATURE – ؇C
COMMON-MODE VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 9. Latch Setup-and-Hold Time
vs. Temperature
Figure 8. Propagation Delay vs. VCM
Figure 7. Propagation Delay vs.
Temperature
REV. A
–5–
AD8598
5.0
4.4
3.8
3.2
2.6
2.0
0.5
0
؊4.0
0.4
0.3
T
= +125؇C
A
V+ = +5V, V؊ = 0V
؊8.0
T = +25؇C
A
T
= ؊40؇C
T
= +25؇C
A
A
V+ = +5V, V؊ = ؊5V
0.2
0.1
0
؊12.0
؊16.0
؊20.0
T
= +125؇C
A
T
= ؊40؇C
A
–75 –50 –25
0
25 50 75 100 125 150
0
3
6
9
12
15
0
3
6
9
12
15
SINK CURRENT – mA
SOURCE CURRENT – mA
TEMPERATURE – ؇C
Figure 11. Output High Voltage, VOH
vs. Source Current
Figure 12. Analog Supply Current vs.
Temperature for ±5 V Supplies
Figure 10. Output Low Voltage, VOL
vs. Sink Current
0
؊1
؊2
؊3
؊4
؊5
0
80
70
60
50
؊4.0
T
= ؊40؇C
A
؊8.0
؊12.0
؊16.0
؊20.0
T
= +25؇C
A
40
+125؇C
+25؇C
30
T
= +125؇C
A
20
–40؇C
10
0
؊7.5
؊5
؊2.5
0
2.5
5
2
4
6
8
10
12
1
10
100
INPUT COMMON-MODE VOLTAGE – Volts
SUPPLY VOLTAGE – Volts
FREQUENCY – MHz
Figure 15. Input Bias Current vs. Input
Common-Mode Voltage for ±5 V
Supplies
Figure 13. Analog Supply Current vs.
Supply Voltage
Figure 14. Positive Supply Current
vs. Input Frequency
0
؊1.0
؊2.0
؊3.0
؊4.0
؊5.0
؊75 ؊50 ؊25
0
25 50 75 100 125 150
TEMPERATURE – ؇C
Figure 16. Input Bias Current vs.
Temperature
–6–
REV. A
AD8598
Note that signals much greater than +3.0 V will result in increased
input currents and may cause the device to operate more slowly.
APPLICATIONS
Optimizing High Speed Performance
As with any high speed comparator or amplifier, proper design
and layout techniques should be used to ensure optimal perfor-
mance from the AD8598. The performance limits of high speed
circuitry can easily be a result of stray capacitance, improper
ground impedance or other layout issues.
The input bias current of the AD8598 is the same magnitude
(–3 µA typical) as the MAX912 (+3 µA typical), and the cur-
rent flows out of the AD8598 and into MAX912. If relatively
low value resistors and/or low impedance sources are used on
the inputs, the voltage shift due to bias current should be small.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
AD8598. Source resistance in combination with equivalent
input capacitance could cause a lagged response at the input,
thus delaying the output. The input capacitance of the AD8598,
in combination with stray capacitance from an input pin to
ground could result in several picofarads of equivalent capaci-
tance. A combination of 3 kΩ source resistance and 5 pF of
input capacitance yields a time constant of 15 ns, which is
slower than the 5 ns capability of the AD8598. Source imped-
ances should be less than 1 kΩ for the best performance.
The AD8598 (6.75 ns typical) is faster than the MAX912
(10 ns typical). While this is beneficial to many systems, timing
may need to be adjusted to take advantage of the higher speed.
The AD8598 has slightly more output voltage swing when the
output is lightly loaded.
The AD8598 uses less current (typically 10 mA) than the MAX912
(typically 12 mA).
Increasing Output Swing
Although not required for normal operation, the output voltage
swing of the AD8598 can be increased by connecting a 5 kΩ
resistor from the output of the device to the V+ power supply.
This configuration can be useful in low voltage power supply
applications where maximizing output voltage swing is impor-
tant. Adding a 5 kΩ pull-up resistor to the device’s output will
not adversely affect the specifications of the AD8598.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors will reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible from the
power supply pins to ground. These capacitors act as a charge
reservoir for the device during high frequency switching.
Output Loading Considerations
The AD8598 output can deliver up to 40 mA of output current
without any significant increase in propagation delay. The
output of the device should not be connected to more than
twenty (20) TTL input logic gates, nor drive a load resistance
less than 100 Ω.
A ground plane is recommended for proper high speed perfor-
mance. This can be created by using a continuous conductive
plane over the surface of the circuit board, only allowing breaks in
the plane for necessary current paths. The ground plane provides
a low inductance ground, eliminating any potential differences at
different ground points throughout the circuit board caused from
“ground bounce.” A proper ground plane also minimizes the
effects of stray capacitance on the circuit board.
To ensure the best performance from the AD8598 it is impor-
tant to minimize capacitive loading of the output of the device.
Capacitive loads greater than 50 pF will cause ringing on the
output waveform and will reduce the operating bandwidth of
the comparator.
Replacing the MAX912
Setup and Hold Times for Latching the Output
The AD8598 is pin compatible with the MAX912 comparator.
While it is easy to replace the MAX912 with the higher perfor-
mance AD8598, please note that there are differences, and it is
useful to check these to ensure proper operation.
The latch inputs can be used to retain data at the outputs of the
AD8598. When the voltage at the latch input goes high, the
output of the device will remain constant regardless of the input
voltages. The setup time for the latch is 2 ns–3 ns and the hold
time is 3 ns. This means that to ensure data retention at the
output, the input signal must be valid at least 5 ns before the
latch pin goes high and must remain valid at least 3 ns after the
latch pin goes high. Once the latch input voltage goes low, new
output data will appear in approximately 8 ns.
There are five major differences between the AD8598 and the
MAX912; input voltage range, input bias currents, speed, out-
put swing and power consumption.
When operated on a +5 V single supply, the MAX912 has an
input voltage range from –0.2 V to +3.5 V. The AD8598 has an
input range from 0 V to +3.0 V. Signals above +3.0 V may
result in slower response times (see Figure 8). If both signals
exceed +3.0 V, the signals may be shifted or attenuated to bring
them into range, keeping in mind the note about source resis-
tance in Optimizing High Speed Performance. If only one of the
signals exceeds +3.0 V only slightly, and the other signal is
always well within the 0 V to +3 V range, the comparator may
operate without changes to the circuit.
A logic high for the latch input is a minimum of +2.0 V and a
logic low is a maximum of +0.8 V. This makes the latch input
easily interface with TTL or CMOS logic gates. The latch
circuitry in the AD8598 has no built-in hysteresis.
Input Stage and Bias Currents
The AD8598 uses a PNP differential input stage that enables
the input common-mode range to extend all the way from the
negative supply rail to within +2.2 V of the positive supply rail.
The input common-mode voltage can be found as the average
of the voltage at the two inputs of the device. To ensure the
fastest response time, care should be taken not to allow the
input common-mode voltage to exceed either of these voltages.
Example: A comparator compares a fast moving signal to a fixed
+2.5 V reference. Since the comparator only needs to operate
when the signal is near +2.5 V, both signals will be within the
input range (near +2.5 V and well under +3.0 V) when the
comparator needs to change output.
REV. A
–7–
AD8598
The input signal is directly connected to the noninverting input
of the comparator. The output is fed back to the inverting input
through R1 and R2. The ratio of R1 to R1 + R2 establishes the
width of the hysteresis window with VREF setting the center of
the window, or the average switching voltage. The Q output will
switch high when the input voltage is greater than VHI and will
not switch low again until the input voltage is less than VLO as
given in Equation 1:
The input bias current for the AD8598 is 3 µA. As with any
PNP differential input stage, this bias current will go to zero on
an input that is high and will double on an input that is low.
Care should be taken in choosing resistor values to be con-
nected to the inputs as large resistors could cause significant
voltage drops due to the input bias current.
The input capacitance for the AD8598 is typically 3 pF. This is
measured by inserting a 5 kΩ source resistance to the input and
measuring the change in propagation delay.
R1
VHI = V –1–V
+VREF
Using Hysteresis
(
)
R1+ R2
+
REF
Hysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is not desir-
able for the output to toggle between states when the input
signal is near the switching threshold. Figure 17 shows a
method for configuring the AD8598 with hysteresis.
(1)
R1
R1+ R2
VLO =VREF 1–
where V+ is the positive supply voltage.
The capacitor, CF, can also be added to introduce a pole into the
feedback network. This has the effect of increasing the amount of
hysteresis at high frequencies. This can be useful when comparing
a relatively slow signal in a high frequency noise environment. At
COMPARATOR
SIGNAL
R1
R2
V
REF
1
frequencies greater than fP =
, the hysteresis window
C
F
2π CF R2
approaches VHI = V+ – 1 V and VLO = 0 V. At frequencies less
than fP the threshold voltages remain as in Equation 1.
Figure 17. Configuring the AD8598 with Hysteresis
–8–
REV. A
AD8598
SPICE Model
* AD8598 SPICE Macro-Model Typical Values
* 4/98, Ver. 1.0
* TAM / ADSC
*
* Node assignments
*
non-inverting input
*
*
*
*
*
*
*
*
|
|
|
|
|
|
|
|
1
inverting input
|
|
|
|
|
|
|
2
positive supply
|
|
|
|
|
|
99
negative supply
|
Latch
|
|
DGND
|
|
|
Q
|
|
|
|
|
|
QNOT
|
|
|
.SUBCKT AD8598
50
80
51
45
65
*
* INPUT STAGE
*
*
Q1
Q2
4
6
3 5 PIX
2 5 PIX
IBIAS 99 5 800E-6
RC1
RC2
CL1
CIN
4 50 1E3
6 50 1E3
4
1
6 1E-12
2 3E-12
VCM1 99 7 1
D1
EOS
*
5
3
7 DX
1 POLY(1) (31,98) 1E-3 1
* Reference Voltage
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
RREF 98 0 100E3
*
* CMRR=80dB, ZERO AT 1kHz
*
ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
RCM1 30 31 10E3
RCM2 31 98 1
CCM1 30 31 15.9E-9
*
* Latch Section
*
RX 80 51 100E3
E1 10 98 (4,6) 1
S1 10 11 (80,51) SLATCH1
R2 11 12 1
C3 12 98 10E-12
E2 13 98 (12,98) 1
R3 12 13 500
*
* Power Supply Section
*
REV. A
–9–
AD8598
GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4
GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3
RSY 52 51 10
*
* Gain Stage Av=250 fp=100MHz
*
G2 98 20 (12,98) 0.25
R1 20 98 1000
C1 20 98 10E-13
D2 20 21 DX
D3 22 20 DX
V1 99 21 DC 0.8
V2 22 50 DC 0.8
*
* Q Output
*
Q3 99 41 46 NOX
Q4 47 42 50 NOX
RB1 43 41 200
RB2 40 42 5E3
CB1 99 41 10E-12
CB2 42 50 5E-12
RO1 46 45 2E3
RO2 47 45 500
EO1 98 43 POLY(1) (20,98) 0 1
EO2 40 98 POLY(1) (20,98) 0 1
*
* Q NOT Output
*
Q5 99 61 66 NOX
Q6 67 62 50 NOX
RB3 63 61 200
RB4 60 62 5E3
CB3 99 61 10E-12
CB4 62 50 5E-12
RO3 66 65 2E3
RO4 67 65 500
EO3 63 98 POLY(1) (20,98) 0 1
EO4 98 60 POLY(1) (20,98) 0 1
*
* MODELS
*
.MODEL PIX PNP(BF=100,IS=1E-16)
.MODEL NOX NPN(BF=100,VAF=130,IS=1E-14)
.MODEL DX D(IS=1E-16)
.MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500,VOFF=2.1,VON=1.4)
.ENDS AD8598
–10–
REV. A
AD8598
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
1
9
0.280 (7.11)
0.240 (6.10)
8
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.100
(2.54)
BSC
0.070 (1.77) SEATING
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
PLANE
16-Lead Thin Shrink Small Outline
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
8
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
16-Lead Narrow Body IC
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
9
16
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
8
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
؋
45؇ 0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. A
–11–
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