AD8597ARZ [ADI]
Single and Dual, Ultralow Distortion, Ultralow Noise Op Amps; 单路和双路，超低失真，超低噪声运算放大器
| 型号： | AD8597ARZ |
| 厂家： | 
ADI |
| 描述： | Single and Dual, Ultralow Distortion, Ultralow Noise Op Amps |
| 文件： | 总20页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single and Dual, Ultralow
Distortion, Ultralow Noise Op Amps
AD8597/AD8599
PIN CONFIGURATIONS
FEATURES
Low noise: 1.1 nV/√Hz at 1 kHz
Low distortion: −120 dB THD @ 1 kHz
Input noise, 0.1 Hz to 10 Hz: <76 nV p-p
Slew rate: 14 V/μs
NC
–IN
+IN
V–
1
2
3
4
8
7
6
5
NC
V+
AD8597
OUT
NC
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Wide bandwidth: 10 MHz
Supply current: 4.8 mA/amp typical
Low offset voltage: 10 μV typical
CMRR: 120 dB
Figure 1. AD8597 8-Lead SOIC (R-8)
Unity-gain stable
1ꢀ V operation
PIN 1
INDICATOR
NC
–IN
+IN
V–
1
2
3
4
8
7
6
5
NC
V+
AD8597
TOP VIEW
OUT
NC
APPLICATIONS
Professional audio preamplifiers
ATE/precision testers
Imaging systems
Medical/physiological measurements
Precision detectors/instruments
Precision data conversion
NOTES
1. NC = NO CONNECT.
2. PIN 4 AND THE EXPOSED PAD MUST BE
CONNECTED TO V–.
Figure 2. AD8597 8-Lead LFCSP (CP-8-2)
OUT A
–IN A
+IN A
–V
1
2
3
4
8
7
6
5
+V
AD8599
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
Figure 3. AD8599 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The AD8597/AD8599 are very low noise, low distortion opera-
tional amplifiers ideal for use as preamplifiers. The low noise of
1.1 nV/√Hz and low harmonic distortion of −120 dB (or better)
at audio bandwidths give the AD8597/AD8599 the wide dynamic
range necessary for preamplifiers in audio, medical, and instru-
mentation applications. The excellent slew rate of 14 V/μs and
10 MHz gain bandwidth make them highly suitable for medical
applications. The low distortion and fast settling time make
them ideal for buffering of high resolution data converters.
The AD8597 is available in 8-lead SOIC and LFCSP packages,
while the AD8599 is available in an 8-lead SOIC package. They
are both specified over a −40°C to +125°C temperature range.
The AD8597 and AD8599 are members of a growing series of
low noise op amps offered by Analog Devices, Inc., (see
Table 1).
Table 1. Low Noise Op Amps
Voltage Noise
0.9 nV
1.1 nV
1.8 nV
2.8 nV
3.2 nV
3.8 nV
Single
Dual
AD797
AD8597
AD8599
AD8675
AD8676
OP27
AD8671
AD8672
AD8674
Quad
ADA4004-4
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.
AD8597/AD8599
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Functional Operation..................................................................... 15
Input Voltage Range................................................................... 15
Output Phase Reversal............................................................... 15
Noise and Source Impedance Considerations ........................... 15
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Power Sequencing ........................................................................ 5
REVISION HISTORY
10/08—Rev.A to Rev. B
4/07—Rev. 0 to Rev. A
Added AD8597 ...................................................................Universal
Added LFCSP_VD .............................................................Universal
Added Table 1.................................................................................... 1
Changes to Specifications Section.................................................. 3
Changes to Absolute Maximum Ratings Section......................... 5
Changes to Typical Performance Characteristics Section........... 6
Added Figure 12 and Figure 15....................................................... 7
Added Figure 18 and Figure 19....................................................... 8
Added Figure 30 and Figure 33..................................................... 10
Added Figure 34 to Figure 38........................................................ 11
Added Figure 42 and Figure 45..................................................... 12
Added Figure 52, Figure 55, Figure 57......................................... 14
Added Functional Operation Section.......................................... 15
Added Figure 58.............................................................................. 15
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 17
Updated Layout .................................................................................5
Changes to Figure 45 Caption ...................................................... 12
Added Figure 48 ............................................................................. 12
Changes to Figure 51 Caption ...................................................... 13
2/07—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8597/AD8599
SPECIFICATIONS
VSY = 5 V, VCM = 0 V, VO = 0 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
15
120
180
μV
μV
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
0.8
40
2.2
μV/°C
nA
nA
nA
nA
V
dB
dB
dB
dB
210
340
250
340
+2.0
Input Offset Current
IOS
65
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
−2.0
120
105
105
100
−2.0 V ≤ VCM ≤ +2.0 V
−40°C ≤ TA ≤ +125°C
RL ≥ 600 Ω, VO = −11 V to +11 V
−40°C ≤ TA ≤ +125°C
135
110
Large Signal Voltage Gain
AVO
Input Capacitance
Differential Capacitance
Common-Mode Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
CDIFF
CCM
15.4
5.5
pF
pF
VOH
RL = 600 Ω
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ
−40°C ≤ TA ≤ +125°C
RL = 600 Ω
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ
3.5
3.3
3.7
3.5
3.7
V
V
V
V
V
V
V
V
3.8
Output Voltage Low
VOL
−3.6
−3.7
−3.4
−3.3
−3.5
−3.4
−40°C ≤ TA ≤ +125°C
Output Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
52
5
mA
Ω
At 1 MHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY
=
18 V to 4.5 V
120
118
140
4.8
dB
dB
mA
mA
−40°C ≤ TA ≤ +125°C
Supply Current per Amplifier
5.5
6.5
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
SR
AV = −1, RL = 2 kΩ
AV = 1, RL = 2 kΩ
To 0.01%, step = 10 V
14
14
2
V/μs
V/μs
μs
Settling Time
tS
Gain Bandwidth Product
Phase Margin
GBP
ΦM
10
60
MHz
Degrees
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
f = 10 Hz
76
1.07
nV p-p
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
dB
1.15
1.5
Correlated Current Noise
2.0
4.2
2.4
5.2
−120
−120
Uncorrelated Current Noise
Total Harmonic Distortion + Noise
Channel Separation
THD + N
CS
G = 1, RL ≥ 1 kΩ, f = 1 kHz, VRMS = 1 V
f = 10 kHz
dB
Rev. B | Page 3 of 20
AD8597/AD8599
VS = 15 V, VCM = 0 V, VO = 0 V, TA = +25°C, unless otherwise specified.
Table 3.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
10
120
180
μV
μV
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
Input Offset Current
ΔVOS/ΔT
0.8
25
50
2.2
μV/°C
IB
200
300
200
300
nA
nA
nA
nA
V
dB
dB
dB
dB
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
IOS
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
−12.5
120
115
110
106
+12.5
−12.5 V ≤ VCM ≤ +12.5 V
−40°C ≤ TA ≤ +125°C
RL ≥ 600 Ω, VO = −11 V to +11 V
−40°C ≤ TA ≤ +125°C
135
116
Large Signal Voltage Gain
AVO
Input Capacitance
Differential Capacitance
Common-Mode Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
CDIFF
CCM
12.1
5.1
pF
pF
VOH
RL = 600 Ω
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ
−40°C ≤ TA ≤ +125°C
RL = 600 Ω
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ
13.1
12.8
13.5
13.2
13.4
V
V
V
V
V
V
V
V
13.7
Output Voltage Low
VOL
−13.2
−13.5
−12.9
−12.8
−13.4
−13.3
−40°C ≤ TA ≤ +125°C
Output Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
52
5
mA
Ω
At 1 MHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY
=
18 V to 4.5 V
120
118
140
5.0
dB
dB
mA
mA
−40°C ≤ TA ≤ +125°C
Supply Current per Amplifier
5.7
6.75
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
SR
AV = −1, RL = 2 kΩ
AV = 1, RL = 2 kΩ
To 0.01%, step = 10 V
16
15
2
V/μs
V/μs
μs
Settling Time
ts
Gain Bandwidth Product
Phase Margin
GBP
ΦM
10
65
MHz
Degrees
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
nV p-p
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
dB
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
f = 10 Hz
f = 1 kHz
f = 10 Hz
76
1.07
1.15
1.5
Correlated Current Noise
1.9
4.3
2.3
5.3
−120
−120
Uncorrelated Current Noise
Total Harmonic Distortion + Noise
Channel Separation
THD + N
CS
G = 1, RL ≥ 1 kΩ, f = 1 kHz, VRMS = 3 V
f = 10 kHz
dB
Rev. B | Page 4 of 20
AD8597/AD8599
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified with the device soldered on a circuit board with
its exposed paddle soldered to a pad (if applicable) on a 4-layer
JEDEC standard PCB with zero air flow.
Parameter
Rating
Supply Voltage
Input Voltage
18 V
−V ≤ VIN ≤ +V
1 V
Indefinite
−65°C to +150°C
−40°C to +125°C
300°C
Differential Input Voltage1
Output Short-Circuit to GND
Storage Temperature Range
Operating Temperature Range
Lead Temperature Range (Soldering 60 sec)
Junction Temperature
Table 5.
Package Type
θJA
78
140
120
θJC
20
39
36
Unit
°C/W
°C/W
°C/W
8-Lead LFCSP_VD (CP-8-2)
8-Lead SOIC (R-8) (AD8597)
8-Lead SOIC (R-8) (AD8599)
150°C
1 If the differential input voltage exceeds 1 V, the current should be limited
to 5 mA.
POWER SEQUENCING
The op amp supplies should be applied simultaneously. The
op amp supplies should be stable before any input signals are
applied. In any case, the input current must be limited to 5 mA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 5 of 20
AD8597/AD8599
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
70
60
50
40
30
20
10
0
70
AD8599
MEAN = 8.23
STDEV = 24.47
MIN = –72.62
MAX = 62.09
AD8599
MEAN = 7.91
STDEV = 21.89
MIN = –63.02
MAX = 57.5
60
V
= ±5V
50
40
30
20
10
0
V
= ±15V
SY
SY
–75 –65 –55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75
–75 –65 –55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75
V
(µV)
V
(µV)
OS
OS
Figure 4. Input Offset Voltage Distribution
Figure 7. Input Offset Voltage Distribution
60
50
40
30
45
40
AD8599
MEAN = 0.346
STDEV = 0.218
MIN = 0.010
MAX = 1.155
AD8599
MEAN = 0.765
STDEV = 0.234
MIN = 0.338
MAX = 1.709
35
30
25
20
15
10
5
V
= ±5V
V
= ±15V
SY
SY
20
10
0
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TCV (µV)
OS
TCV (µV)
OS
Figure 8. TCVOS Distribution, −40°C ≤ TA ≤ +125°C
Figure 5. TCVOS Distribution, −40°C ≤ TA ≤ +125°C
60
50
40
30
60
50
40
30
AD8599
MEAN = 0.342
STDEV = 0.221
MIN = 0.013
MAX = 1.239
AD8599
MEAN = 0.461
STDEV = 0.245
MIN = 0.026
MAX = 1.26
V
= ±15V
V
= ±5V
SY
SY
20
10
0
20
10
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TCV (µV)
OS
TCV (µV)
OS
Figure 6. TCVOS Distribution, −40°C ≤ TA ≤ +85°C
Figure 9. TCVOS Distribution, −40°C ≤ TA ≤ +85°C
Rev. B | Page 6 of 20
AD8597/AD8599
100
75
100
75
AD8599
= ±5V
AD8599
= ±15V
V
V
SY
SY
50
50
25
25
0
0
–25
–50
–25
–50
–75
–75
–100
–5.0
–100
–2.5
0
2.5
5.0
–15
–10
–5
0
5
10
15
V
(V)
V
(V)
CM
CM
Figure 10. Offset Voltage vs. VCM
Figure 13. Offset Voltage vs. VCM
350
350
AD8599
AD8599
300
250
V
V
= ±5V
= 0V
300
250
V
V
= ±15V
= 0V
SY
SY
CM
CM
200
150
100
50
200
150
100
50
0
0
–50
–100
–150
–200
–50
–100
–150
–200
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Input Bias Current vs. Temperature
Figure 14. Input Bias Current vs. Temperature
50
40
350
AD8597
= ±15V
AD8597
300
250
200
150
100
50
V
SY
30
20
T
= –40°C
A
10
T
= +25°C
A
0
0
T
= +85°C
A
–50
–100
–150
–200
–250
–300
–350
±15V
–10
–20
–30
–40
–50
T
= +125°C
A
±5V
–50
–25
0
25
50
75
100
125
150
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12
TEMPERATURE (°C)
V
(V)
CM
Figure 12. Input Offset Voltage vs. Temperature
Figure 15. Input Bias Current vs. Temperature
Rev. B | Page 7 of 20
AD8597/AD8599
150
100
50
80
AD8597
AD8599
70
60
50
40
±15V
0
±5V
I
@ V = ±5V
SY
OS
30
20
–50
–100
–150
I
@ V = ±15V
SY
OS
10
0
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Input Offset Current vs. Temperature
Figure 19. Input Offset Current vs. Temperature
114
112
120
AD8599
= ±5V
AD8599
= ±15V
V
V
SY
SY
118
116
114
112
110
R
= 2kΩ, V = ±11V
O
L
110
108
106
R
= 2kΩ, V = ±2V
O
L
R
= 600Ω, V = ±11V
O
R
= 600Ω, V = ±2V
O
L
L
104
102
100
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Large Signal Voltage Gain vs. Temperature
Figure 20. Large Signal Voltage Gain vs. Temperature
8
7
6
5
4
3
2
1
0
350
300
250
200
150
AD8597
AD8599
V
= ±15V
SY
T
= –40°C
A
T
= +125°C
A
T
= +85°C
A
T
= +25°C
A
100
50
T
= +25°C
= +85°C
A
T
= –40°C
A
0
T
A
–50
–100
–150
T
= +125°C
A
–200
–250
–300
–350
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12
V
V
(V)
CM
SY
Figure 18. Supply Current vs. Supply Voltage
Figure 21. Input Bias Current vs. VCM
Rev. B | Page 8 of 20
AD8597/AD8599
80
60
40
20
0
80
60
AD8599
= ±5V
AD8599
V
V
= ±15V
SY
SY
I
I
SINK
SINK
40
20
0
–20
–40
–60
–80
–20
–40
–60
–80
I
I
SOURCE
SOURCE
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. ISC vs. Temperature
Figure 25. ISC vs. Temperature
10k
10k
AD8599
AD8599
V
= ±5V
V
= ±15V
SY
SY
I
I
SINK
SINK
1k
1k
I
SOURCE
I
SOURCE
100
0.001
100
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
100
I
(mA)
I (mA)
L
L
Figure 23. Output Saturation Voltage vs. Current Load
Figure 26. Output Saturation Voltage vs. Current Load
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
AD8599
AD8599
V
= ±5V
V
= ±15V
SY
SY
V
– V @ R = 600Ω
OH
CC
L
V
– V @ R = 600Ω
OH
CC
L
V
– V @ R = 2kΩ
OH
CC
L
V
– V @ R = 2kΩ
OH
CC
L
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. Output Saturation Voltage vs. Temperature
Figure 27. Output Saturation Voltage vs. Temperature
Rev. B | Page 9 of 20
AD8597/AD8599
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
AD8599
AD8599
= ±15V
V
= ±5V
V
SY
SY
–0.5
–1.0
–1.5
–2.0
–2.5
V
– V @ R = 2kΩ
OL
EE
L
V
– V @ R = 2kꢀ
OL
EE
L
V
– V @ R = 600Ω
OL
EE
L
V
– V @ R = 600ꢀ
OL
EE
L
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 28. Output Saturation Voltage vs. Temperature
Figure 31. Output Saturation Voltage vs. Temperature
–13.0
–13.5
15.0
14.8
14.6
V
@ R = 600Ω
L
AD8599
OL
V
= ±15V
SY
14.4
14.2
14.0
13.8
13.6
V
@ R = 2kΩ
OL
L
–14.0
–14.5
–15.0
V
@ R = 2kꢀ
L
OH
13.4
13.2
13.0
V
@ R = 600ꢀ
OH
L
AD8599
= ±15V
V
SY
–50
0
50
100
150
–50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE (°C)
Figure 29. Output Voltage Low vs. Temperature
Figure 32. Output Voltage High vs. Temperature
100
80
120
100
80
60
40
60
C
= 20pF
L
20
40
C
= 20pF
L
0
20
–20
–40
–60
–80
–100
0
C
= 200pF
L
–20
–40
–60
–80
C
= 200pF
L
AD8597
SY
AD8597
SY
V
= ±5V
V
= ±15V
R
= 2kꢀ
R
= 2kꢀ
L
L
10
100
1k
FREQUENCY (kHz)
10k
50k
1
10
100
1k
10k
50k
FREQUENCY (kHz)
Figure 30. Gain and Phase vs. Frequency
Figure 33. Gain and Phase vs. Frequency
Rev. B | Page 10 of 20
AD8597/AD8599
50
40
50
40
A
A
= 100
= 10
A
A
= 100
= 10
V
V
30
30
20
20
V
V
10
10
0
0
A
= 1
A
= 1
V
V
–10
–20
–30
–40
–10
–20
–30
–40
AD8597
= ±5V
AD8597
V = ±15V
V
SY
= 2kꢀ
SY
R = 2kꢀ
L
R
L
1
10
100
1k
10k
50k
100k
10k
1
10
100
1k
10k
50k
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 34. Closed-Loop Gain vs. Frequency
Figure 37. Closed-Loop Gain vs. Frequency
100
10
100
10
A
= –100
= –10
A
= –100
= –10
V
V
A
A
V
V
A
= +1
A = +1
V
V
1
1
0.1
0.1
AD8597
AD8597
V
= ±5V
V
= ±15V
SY
SY
0.01
0.01
10
100
1k
FREQUENCY (kHz)
10k
10
100
1k
FREQUENCY (kHz)
10k
100k
Figure 35. Closed-Loop Output Impedance vs. Frequency
Figure 38. Closed-Loop Output Impedance vs. Frequency
110
120
100
80
AD8599
100
90
80
70
60
50
40
30
20
±5V ≤ V ≤ ±15V
SY
PSRR+ (dB)
PSRR– (dB)
60
AD8597
= ±5V, ±15V
40
V
SY
20
0
–20
1
10
100
1k
100
1k
10k
100k
1M
10M
FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 36. Common-Mode Rejection Ratio vs. Frequency
Figure 39. Power Supply Rejection Ratio vs. Frequency
Rev. B | Page 11 of 20
AD8597/AD8599
600
500
400
300
200
100
0
90
AD8599
MEAN = 1.07
STDEV = 0.02
MIN = 1.05
MAX = 1.15
AD8599
MEAN = 1.30
STDEV = 0.09
MIN = 1.1
MAX = 1.5
80
70
60
50
±5V ≤ V ≤ ±15V
±5V ≤ V ≤ ±15V
SY
SY
40
30
20
10
0
0.95 0.98 1.01 1.04 1.07 1.10 1.13 1.16 1.19
VOLTAGE NOISE DENSITY (nV/ Hz)
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
VOLTAGE NOISE DENSITY (nV/ Hz)
Figure 43. Voltage Noise Density @ 1 kHz
Figure 40. Voltage Noise Density @ 10 Hz
100
100
AD8599
AD8599
±5V ≤ V ≤ ±15V
±5V ≤ V ≤ ±15V
SY
SY
10
10
1
1
0.1
0.1
1
1
10
100
FREQUENCY (Hz)
1k
1
1
10
100
FREQUENCY (Hz)
1k
Figure 44. Current Noise Density vs. Frequency
Figure 41. Voltage Noise Density vs. Frequency
0.1
0.01
0.1
0.01
R
= 600ꢀ
L
AD8597
= ±5V
AD8597
V
V
= ±15V
= +1
SY
= +1
SY
A
A
V
V
R
1
= 600ꢀ
L
0.001
0.001
R
= 100kꢀ
R
= 100kꢀ
L
L
0.0001
0.0001
0.001
0.01
0.1
1
10
0.001
0.01
0.1
10
V rms (V)
V rms (V)
Figure 42. THD + N vs. Amplitude
Figure 45. THD + N vs. Amplitude
Rev. B | Page 12 of 20
AD8597/AD8599
0.1
0.01
0.1
0.01
AD8599
AD8599
= ±15V
V
V
V
= 3V rms
= 5V rms
= 7V rms
V
V
= ±15V
= 3V rms
IN
IN
IN
V
SY
IN
SY
0.001
0.0001
0.001
0.0001
R
= 600ꢀ
L
R
= 2kꢀ
L
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 46. THD + N vs. Frequency
Figure 49. THD + N vs. Frequency
20
15
10
5
20
15
10
5
AD8599
AD8599
V
V
A
R
R
C
= ±15V
= 20V p-p
= –1
= 2kꢀ
= 2kꢀ
SY
0
0
V
V
A
R
R
= ±15V
= 20V p-p
= 1
= 1kꢀ
= 2kꢀ
IN
SY
V
F
S
L
IN
–5
–10
–5
–10
V
F
L
= 0pF
VERTICAL AXIS = 5V/DIV
VERTICAL AXIS = 5V/DIV
HORIZONTAL AXIS = 4µs/DIV
HORIZONTAL AXIS = 4µs/DIV
–15
–20
–15
–20
–8.6 –4.6 –0.6 3.4
7.4 11.4 15.4 19.4 23.4 27.4 31.4
TIME (µs)
–8.6 –4.6 –0.6 3.4
7.4 11.4 15.4 19.4 23.4 27.4 31.4
TIME (µs)
Figure 47. Large Signal Response
Figure 50. Large Signal Response
80
45
40
AD8599
AD8599
±5V ≤ V ≤ ±15V
SY
60
40
A
R
= 1
V
L
= 10kꢀ
35
30
20
25
20
15
0
V
V
A
= ±15V, ±5V
= 100mV p-p
= 1
SY
IN
–20
–40
V
EXTERNAL C = 100pF
EXTERNAL R = 10kꢀ
VERTICAL AXIS = 20mV/DIV
HORIZONTAL AXIS = 400ns/DIV
L
10
5
L
–60
–80
0
10
–800 –400
0
400 800 1200 1600 2000 2400 2800 3200
TIME (ns)
100
1k
CAPACITANCE (pF)
Figure 48. Small Signal Response
Figure 51. Overshoot vs. Capacitance
Rev. B | Page 13 of 20
AD8597/AD8599
45
45
40
35
30
25
20
15
10
5
AD8597
AD8597
V = ±15V
SY
V
= ±5V
SY
40
35
30
25
20
15
10
5
OS–
OS–
OS+
OS+
0
0
10
100
CAPACITANCE (pF)
1k
10
100
1k
CAPACITANCE (pF)
Figure 52. Overshoot vs. Capacitive Load
Figure 55. Overshoot vs. Capacitive Load
0
15.0
AD8599
AD8599
V
A
R
= ±15V
= 100
= 1kꢀ
SY
–20
V
L
–40
–60
V
V
= 10V p-p
= 20V p-p
12.5
10.0
7.5
IN
IN
–80
–100
–120
–140
–160
V
= ±15V
SY
V
= ±5V
SY
5.0
–50
100
1k
10k
100k
1M
–25
0
25
50
75
100
125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 53. Channel Separation vs. Frequency
Figure 56. Supply Current vs. Temperature
6.0
5.5
5.0
4.5
4.0
800
600
400
200
0
AD8597
AD8599
±5V ≤ V ≤ ±15V
SY
V
= ±15V
SY
V
= ±5V
SY
–200
–400
–600
–800
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
TEMPERATURE (°C)
Figure 54. Peak-to-Peak Noise
Figure 57. Supply Current vs. Temperature
Rev. B | Page 14 of 20
AD8597/AD8599
FUNCTIONAL OPERATION
The AD8597/AD8599 amplifiers have been carefully designed
to prevent any output phase reversal if both inputs are main-
tained within the specified input voltage range. If one or both
inputs exceed the input voltage range but remain within the
supply rails, the op amp specifications, such as CMRR, are not
guaranteed, but the output remains close to the correct value.
INPUT VOLTAGE RANGE
The AD8597/AD8599 are not rail-to-rail input amplifiers;
therefore, care is required to ensure that both inputs do not
exceed the input voltage range. Under normal negative feedback
operating conditions, the amplifier corrects its output to ensure
that the two inputs are at the same voltage. However, if either
input exceeds the input voltage range, the loop opens and large
currents begin to flow through the ESD protection diodes in the
amplifier.
NOISE AND SOURCE IMPEDANCE CONSIDERATIONS
The AD8597/AD8599 ultralow voltage noise of 1.1 nV/√Hz is
achieved with special input transistors running at high collector
current. Therefore, it is important to consider the total input-
referred noise (eN total), which includes contributions from
voltage noise (eN), current noise (iN), and resistor noise
(√4 kTRS).
These diodes are connected between the inputs and each supply
rail to protect the input transistors against an electrostatic discharge
event and they are normally reverse-biased. However, if the
input voltage exceeds the supply voltage, these ESD diodes
can become forward-biased. Without current limiting, excessive
amounts of current may flow through these diodes, causing
permanent damage to the device. If inputs are subject to over-
voltage, insert appropriate series resistors to limit the diode
current to less than 5 mA maximum.
eN total = [eN2 + 4 kTRS + (iN × RS)2]1/2
(1)
where RS is the total input source resistance.
This equation is plotted for the AD8597/AD8599 in Figure 58.
Because optimum dc performance is obtained with matched
source resistances, this case is considered even though it is clear
from Equation 1 that eliminating the balancing source resistance
lowers the total noise by reducing the total RS by a factor of 2.
The input stage has two diodes between the input pins to
protect the differential pair. Under high slew rate conditions,
when the op amp is connected as a voltage follower, the diodes
may become forward-biased and the source may try to drive
the output. A small resistor should be placed in the feedback
loop and in the noninverting input. The noise of a 100 Ω
resistor at room temperature is ~1.25 nV/√Hz, which is higher
than the AD8597/AD8599. Thus, there is a tradeoff between
noise performance and protection. If possible, limiting should
be placed earlier in the signal path. For further details, see the
Amplifier Input Protection…Friend or Foe article at
At a very low source resistance (RS < 50 Ω), the voltage noise of the
amplifier dominates. As source resistance increases, the Johnson
noise of RS dominates until a higher resistance of RS > 2 kΩ is
achieved; the current noise component is larger than the
resistor noise.
100
http://www.analog.com/amplifier_input.
10
Because of the large transistors used to achieve low noise, the
input capacitance may seem rather high. To take advantage of
the low noise performance, impedance around the op amp should
be low, less than 500 Ω. Under these conditions, the pole from
the input capacitance should be greater than 50 MHz, which
does not affect the signal bandwidth.
TOTAL NOISE
RESISTOR NOISE
ONLY
1
OUTPUT PHASE REVERSAL
0.1
10
Output phase reversal occurs in some amplifiers when the
input common-mode voltage range is exceeded. As the common-
mode voltage is moved outside the input voltage range, the
outputs of these amplifiers can suddenly jump in the opposite
direction to the supply rail. This is the result of the differential
input pair shutting down that causes a radical shifting of
internal voltages that results in the erratic output behavior.
100
1k
10k
SOURCE RESISTANCE (ꢀ)
Figure 58. Noise vs. Source Resistance
Rev. B | Page 15 of 20
AD8597/AD8599
The AD8597/AD8599 are the optimum choice for low noise
performance if the source resistance is kept < 1 kΩ. At higher
values of source resistance, optimum performance with respect
to only noise is obtained with other amplifiers from Analog
Devices. Both voltage noise and current noise need to be consi-
dered. For more information on avoiding noise from grounding
problems and inadequate bypassing, see the AN-345 Application
Note, Grounding for Low- and High-Frequency Circuits. For
general noise theory with extensive calculations, see the
AN-358 Application Note, Noise and Operational Amplifier
Circuits. A good selection table for low noise op amps can
be found in AN-940 Application Note, Low Noise Amplifier
Selection Guide for Optimal Noise Performance. An interesting
note on using one section of a monolithic dual to phase compen-
sate the other section is in the AN-107 Application Note, Active
Feedback Improves Amplifier Phase Accuracy.
V+
7
Q36
D31
R18
R19
D1
D2
R31
R32
D34
R1
6
2
–
OUTPUT
INVERTING
INPUT
C1
Q18 Q19
V
B
Q19
Q20
D39
D40
D41
D42
D3
3
+
NONINVERTING
INPUT
Q32
D2
Q27
Q28
4
V–
Figure 59. Simplified Schematic
Rev. B | Page 16 of 20
AD8597/AD8599
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 60. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.25
3.00 SQ
2.75
0.60 MAX
0.50
BSC
0.60 MAX
5
8
2.95
2.75 SQ
2.55
1.60
1.45
1.30
EXPOSED
PAD
TOP
VIEW
PIN 1
INDICATOR
(BOTTOM VIEW)
4
1
PIN 1
INDICATOR
0.50
0.40
0.30
1.89
1.74
1.59
12° MAX
0.70 MAX
0.65TYP
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATIONS
0.30
0.23
0.18
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 61. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8597ACPZ-R21
AD8597ACPZ-REEL1
AD8597ACPZ-REEL71
AD8597ARZ1
AD8597ARZ-REEL1
AD8597ARZ-REEL71
AD8599ARZ1
AD8599ARZ-REEL1
AD8599ARZ-REEL71
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
Branding
A22
A22
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
CP-8-2
CP-8-2
CP-8-2
R-8
R-8
R-8
A22
R-8
R-8
R-8
1 Z = RoHS Complaint Part.
Rev. B | Page 17 of 20
AD8597/AD8599
NOTES
Rev. B | Page 18 of 20
AD8597/AD8599
NOTES
Rev. B | Page 19 of 20
AD8597/AD8599
NOTES
©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06274-0-10/08(B)
Rev. B | Page 20 of 20
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