AD8450 [ADI]
Precision Analog Front End and Controller;
| 型号： | AD8450 |
| 厂家： | 
ADI |
| 描述： | Precision Analog Front End and Controller |
| 文件： | 总42页 (文件大小：1336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Analog Front End and Controller
for Battery Test/Formation Systems
Data Sheet
AD8450
FEATURES
GENERAL DESCRIPTION
Integrated constant current and voltage modes with
automatic switchover
Charge and discharge modes
The AD8450 is a precision analog front end and controller for
testing and monitoring battery cells. A precision programmable
gain instrumentation amplifier (PGIA) measures the battery
charge/discharge current, and a programmable gain difference
amplifier (PGDA) measures the battery voltage (see Figure 1).
Internal laser trimmed resistor networks set the gains for the
PGIA and the PGDA, optimizing the performance of the
AD8450 over the rated temperature range. PGIA gains are 26,
66, 133, and 200. PGDA gains are 0.2, 0.27, 0.4, and 0.8.
Precision voltage and current measurement
Integrated precision control feedback blocks
Precision interface to PWM or linear power converters
Programmable gain settings
Current sense gains: 26, 66, 133, and 200
Voltage sense gains: 0.2, 0.27, 0.4, and 0.8
Programmable OVP and OCP fault detection
Current sharing and balancing
Excellent ac and dc performance
Maximum offset voltage drift: 0.6 µV/°C
Maximum gain drift: 3 ppm/°C
Low current sense amplifier input voltage noise: ≤9 nV/√Hz
Current sense CMRR: 126 dB minimum (gain = 200)
TTL compliant logic
Voltages at the ISET and VSET inputs set the desired constant
current (CC) and constant voltage (CV) values. CC to CV
switching is automatic and transparent to the system.
A TTL logic level input, MODE, selects the charge or discharge
mode (high for charge, low for discharge). An analog output,
VCTRL, interfaces directly with the Analog Devices, Inc.,
ADP1972 PWM controller.
The AD8450 includes resistor programmable overvoltage and
overcurrent detection and current sharing circuitry. Current
sharing is used to balance the output current of multiple
bridged channels.
APPLICATIONS
Battery cell formation and testing
Battery module testing
The AD8450 simplifies designs by providing excellent accuracy,
performance over temperature, flexibility with functionality,
and overall reliability in a space-saving package. The AD8450 is
available in an 80-lead, 14 mm × 14 mm × 1 mm LQFP package
and is rated for an operating temperature of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ISREFH/
ISREFL
IVE0/
ISET IVE1
ISMEA
VINT
AD8450
CSH
CURRENT
SHARING
ISVP
ISVN
CONSTANT
CURRENT LOOP
FILTER
GAIN
NETWORK
AND MUX
IMAX
26, 66,
133, 200
VCLP
VCTRL
VCLN
CURRENT
SENSE PGIA
1×
(CHARGE/
DISCHARGE)
SWITCHING
MODE
BVPx
VOLTAGE
SENSE PGDA
VOLTAGE
REFERENCE
VREF
GAIN
NETWORK
0.2, 0.27,
0.4, 0.8
CONSTANT
VOLTAGE LOOP
FILTER
FAULT
DETECTION
BVNx
FAULT
BVREFH/ BVMEA VSET VVE0/
VVP0 VSETBF VINT OVPS/ OCPS/
OVPR OCPR
BVREFL
VVE1
Figure 1.
Rev. B
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Technical Support
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AD8450* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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REFERENCE MATERIALS
Press
• Analog Devices Introduces the First Integrated Analog
Controller Optimizing High-Efficiency Rechargeable
Battery Manufacturing
EVALUATION KITS
• AD8450 Evaluation Board
DESIGN RESOURCES
• AD8450 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-1319: Compensator Design for a Battery Charge/
Discharge Unit Using the AD8450 or the AD8451
Data Sheet
• AD8450: Precision Analog Front End and Controller for
DISCUSSIONS
Battery Test/Formation Systems Data Sheet
User Guides
View all AD8450 EngineerZone Discussions.
• UG-845: AD8450/ADP1972 Battery Testing and Formation
Evaluation Board
SAMPLE AND BUY
Visit the product page to see pricing options.
TOOLS AND SIMULATIONS
• AD8450 SPICE Macro Model
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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AD8450
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Overcurrent and Overvoltage Comparators........................... 27
Current Sharing Bus and IMAX Output................................. 28
Applications Information .............................................................. 29
Functional Description.............................................................. 29
Power Supply Connections ....................................................... 29
Power Supply Sequencing ......................................................... 29
Power-On Sequence................................................................... 29
Power-Off Sequence................................................................... 30
PGIA Connections ..................................................................... 30
PGDA Connections ................................................................... 31
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
PGIA Characteristics ................................................................. 11
PGDA Characteristics................................................................ 13
Battery Current and Voltage Control Inputs (ISET and VSET)
....................................................................................................... 31
Loop Filter Amplifiers ............................................................... 32
Connecting to a PWM Controller (VCTRL Pin) ...................... 32
Overvoltage and Overcurrent Comparators........................... 32
Step by Step Design Example.................................................... 32
Additional Information ............................................................. 33
Evaluation Board ............................................................................ 34
Introduction................................................................................ 34
Features and Tests....................................................................... 34
Testing the AD8450-EVALZ ..................................................... 34
Using the AD8450...................................................................... 36
Schematic and Artwork............................................................. 37
Outline Dimensions....................................................................... 41
Ordering Guide .......................................................................... 41
CC and CV Loop Filter Amplifiers, Uncommitted Op Amp,
and VSET Buffer......................................................................... 15
VINT Buffer ................................................................................ 17
Current Sharing Amplifier........................................................ 18
Comparators................................................................................ 19
Reference Characteristics .......................................................... 20
Theory of Operation ...................................................................... 21
Introduction ................................................................................ 21
Programmable Gain Instrumentation Amplifier (PGIA)..... 23
Programmable Gain Difference Amplifier (PGDA).............. 24
CC and CV Loop Filter Amplifiers.......................................... 24
Compensation............................................................................. 26
VINT Buffer ................................................................................ 26
MODE Pin, Charge and Discharge Control ........................... 26
7/14—Rev. 0 to Rev. A
REVISION HISTORY
Changes to General Description .....................................................1
Changes to Pin 39 and Pin 80 Descriptions................................ 10
Changes to Introduction Section and Figure 50 ........................ 22
Changes to Figure 52...................................................................... 24
Changes to Figure 55...................................................................... 26
Changes to Current Sharing Bus and IMAX Output Section .. 27
Changes to Figure 58...................................................................... 28
Changes to Figure 59...................................................................... 30
Changes to Evaluation Board Section.......................................... 33
8/15—Rev. A to Rev. B
Changes to Table 2 ............................................................................ 8
Added Power Supply Sequencing Section and Power-On
Sequence Section ............................................................................ 29
Added Power-Off Sequence .......................................................... 30
Added Additional Information Section....................................... 33
Changes to Step 4: Determine the Control Voltage for the CC
Loop, the Shunt Resistor, and the PGIA Gain Section .............. 33
1/14—Revision 0: Initial Version
Rev. B | Page 2 of 41
Data Sheet
AD8450
SPECIFICATIONS
AVCC = +25 V, AVEE = −5 V; AVCC = +15 V, AVEE = −15 V; DVCC = +5 V; PGIA gain = 26, 66, 133, or 200; PGDA gain = 0.2, 0.27,
0.4, or 0.8; TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CURRENT SENSE PGIA
Internal Fixed Gains
Gain Error
Gain Drift
Gain Nonlinearity
Offset Voltage (RTI)
26, 66, 133, 200
V/V
%
ppm/°C
ppm
µV
VISMEA = 10 V
TA = TMIN to TMAX
VISMEA = 10 V, RL = 2 kΩ
Gain = 200, ISREFH and ISREFL pins
grounded
0.1
3
3
−110
+110
Offset Voltage Drift
Input Bias Current
Temperature Coefficient
Input Offset Current
Temperature Coefficient
TA = TMIN to TMAX
TA = TMIN to TMAX
TA = TMIN to TMAX
0.6
30
150
2
µV/°C
nA
pA/°C
nA
pA/°C
V
V
V
GΩ
GΩ
V
V
pF
mA
V
µA
15
10
Input Common-Mode Voltage Range VISVP − VISVN = 0 V
AVEE + 2.3
AVEE + 2.6
AVCC − 55
AVCC − 2.4
AVCC − 2.6
AVEE + 55
Over Temperature
Overvoltage Input Range
Differential Input Impedance
Input Common-Mode Impedance
Output Voltage Swing
Over Temperature
Capacitive Load Drive
Short-Circuit Current
Reference Input Voltage Range
Reference Input Bias Current
Output Voltage Level Shift
Maximum
TA = TMIN to TMAX
150
150
AVEE + 1.5
AVEE + 1.7
AVCC − 1.2
AVCC − 1.4
1000
TA = TMIN to TMAX
40
5
ISREFH and ISREFL pins tied together
VISVP = VISVN = 0 V
ISREFL pin grounded
ISREFH pin connected to VREF pin
VISMEA/VISREFH
AVEE
AVCC
17
6.8
20
8
23
9.2
mV
mV/V
Scale Factor
CMRR
ΔVCM = 20 V
Gain = 26
Gain = 66
Gain = 133
Gain = 200
108
116
122
126
dB
dB
dB
dB
Temperature Coefficient
PSRR
TA = TMIN to TMAX
ΔVS = 20 V
0.01
µV/V/°C
Gain = 26
Gain = 66
Gain = 133
Gain = 200
108
116
122
126
122
130
136
140
dB
dB
dB
dB
Voltage Noise
f = 1 kHz
Gain = 26
Gain = 66
Gain = 133
Gain = 200
Voltage Noise, Peak-to-Peak
Current Noise
Current Noise, Peak-to-Peak
9
8
7
7
0.2
80
5
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
fA/√Hz
pA p-p
f = 0.1 Hz to 10 Hz, all fixed gains
f = 1 kHz
f = 0.1 Hz to 10 Hz
Rev. B | Page 3 of 41
AD8450
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Small Signal −3 dB Bandwidth
Gain = 26
Gain = 66
Gain = 133
Gain = 200
1.5
630
330
220
5
MHz
kHz
kHz
kHz
V/µs
Slew Rate
ΔVISMEA = 10 V
VOLTAGE SENSE PGDA
Internal Fixed Gains
Gain Error
0.2, 0.27, 0.4, 0.8
V/V
%
ppm/°C
ppm
µV
VIN = 10 V
TA = TMIN to TMAX
0.1
3
3
500
4
Gain Drift
Gain Nonlinearity
Offset Voltage (RTO)
Offset Voltage Drift
Differential Input Voltage Range
VBVMEA = 10 V, RL = 2 kΩ
BVREFH and BVREFL pins grounded
TA = TMIN to TMAX
Gain = 0.8, VBVN0 = 0 V, VBVREFL = 0 V
AVCC = +15 V, AVEE = −15 V
AVCC = +25 V, AVEE = −5 V
µV/°C
−16
−4
+16
+29
V
V
Input Common-Mode Voltage Range Gain = 0.8, VBVMEA = 0 V
AVCC = +15 V, AVEE = −15 V
AVCC = +25 V, AVEE = −5 V
−27
−7
+27
+50
V
V
Differential Input Impedance
Gain = 0.2
Gain = 0.27
Gain = 0.4
Gain = 0.8
800
600
400
200
kΩ
kΩ
kΩ
kΩ
Input Common-Mode Impedance
Gain = 0.2
Gain = 0.27
Gain = 0.4
Gain = 0.8
240
190
140
90
kΩ
kΩ
kΩ
kΩ
Output Voltage Swing
AVEE + 1.5
AVEE + 1.7
AVCC − 1.5
AVCC − 1.7
1000
V
V
pF
mA
V
Over Temperature
Capacitive Load Drive
Short-Circuit Current
Reference Input Voltage Range
Output Voltage Level Shift
Maximum
Scale Factor
CMRR
Temperature Coefficient
PSRR
Output Voltage Noise
Gain = 0.2
TA = TMIN to TMAX
30
BVREFH and BVREFL pins tied together AVEE
BVREFL pin grounded
AVCC
BVREFH pin connected to VREF pin
VBVMEA/VBVREFH
ΔVCM = 10 V, all fixed gains, RTO
TA = TMIN to TMAX
ΔVS = 20 V, all fixed gains, RTO
f = 1 kHz, RTI
4.5
1.8
80
5
2
5.5
2.2
mV
mV/V
dB
µV/V/°C
dB
0.05
100
325
250
180
105
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Gain = 0.27
Gain = 0.4
Gain = 0.8
Voltage Noise, Peak-to-Peak
Gain = 0.2
Gain = 0.27
Gain = 0.4
Gain = 0.8
f = 0.1 Hz to 10 Hz, RTI
6
5
3
2
µV p-p
µV p-p
µV p-p
µV p-p
Rev. B | Page 4 of 41
Data Sheet
AD8450
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Small Signal −3 dB Bandwidth
Gain = 0.2
Gain = 0.27
Gain = 0.4
Gain = 0.8
420
730
940
1000
0.8
kHz
kHz
kHz
kHz
V/µs
Slew Rate
CONSTANT CURRENT AND CONSTANT
VOLTAGE LOOP FILTER AMPLIFIERS
Offset Voltage
150
µV
Offset Voltage Drift
Input Bias Current
Over Temperature
TA = TMIN to TMAX
TA = TMIN to TMAX
0.6
+5
+5
µV/°C
nA
nA
−5
−5
Input Common-Mode Voltage Range
Output Voltage Swing
Over Temperature
AVEE + 1.5
AVEE + 1.5
AVEE + 1.7
AVCC − 1.8
AVCC − 1
AVCC − 1
V
V
V
VVCLN = AVEE + 1 V, VVCLP = AVCC − 1 V
TA = TMIN to TMAX
Closed-Loop Output Impedance
Capacitive Load Drive
Source Short-Circuit Current
Sink Short-Circuit Current
Open-Loop Gain
0.01
Ω
pF
mA
mA
dB
1000
1
40
140
CMRR
PSRR
ΔVCM = 10 V
ΔVS = 20 V
100
100
dB
dB
Voltage Noise
Voltage Noise, Peak-to-Peak
Current Noise
Current Noise, Peak-to-Peak
Small Signal Gain Bandwidth Product
Slew Rate
CC to CV Transition Time
UNCOMMITTED OP AMP
Offset Voltage
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
10
0.3
80
5
3
1
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/μs
µs
f = 0.1 Hz to 10 Hz
ΔVVINT = 10 V
1.5
150
µV
Offset Voltage Drift
Input Bias Current
Over Temperature
TA = TMIN to TMAX
TA = TMIN to TMAX
0.6
+5
+5
µV/°C
nA
nA
−5
−5
Input Common-Mode Voltage Range
Output Voltage Swing
Over Temperature
AVEE + 1.5
AVEE + 1.5
AVEE + 1.7
AVCC − 1.8
AVCC − 1.5
AVCC − 1.5
V
V
V
TA = TMIN to TMAX
Closed-Loop Output Impedance
Capacitive Load Drive
Short-Circuit Current
Open-Loop Gain
0.01
Ω
pF
mA
dB
1000
40
140
RL = 2 kΩ
CMRR
PSRR
ΔVCM = 10 V
ΔVS = 20 V
100
100
dB
dB
Voltage Noise
Voltage Noise, Peak-to-Peak
Current Noise
Current Noise, Peak-to-Peak
Small Signal Gain Bandwidth Product
Slew Rate
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
10
0.3
80
5
3
1
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/µs
f = 0.1 Hz to 10 Hz
ΔVOAVO = 10 V
Rev. B | Page 5 of 41
AD8450
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CURRENT SHARING BUS AMPLIFIER
Nominal Gain
1
V/V
Offset Voltage
150
0.6
AVCC − 1.5
AVCC − 1.7
1000
µV
µV/°C
V
V
Offset Voltage Drift
Output Voltage Swing
Over Temperature
Capacitive Load Drive
Source Short-Circuit Current
Sink Short-Circuit Current
CMRR
TA = TMIN to TMAX
TA = TMIN to TMAX
AVEE + 1.5
AVEE + 1.7
pF
40
0.5
mA
mA
dB
ΔVCM = 10 V
ΔVS = 20 V
100
100
PSRR
dB
Voltage Noise
f = 1 kHz
f = 0.1 Hz to 10 Hz
10
0.4
3
1
1.5
nV/√Hz
µV p-p
MHz
V/µs
µs
Voltage Noise, Peak-to-Peak
Small Signal −3 dB Bandwidth
Slew Rate
ΔVCS = 10 V
Transition Time
CURRENT SHARING, VINT, AND
CONSTANT VOLTAGE BUFFERS
Nominal Gain
Offset Voltage
1
V/V
µV
150
Offset Voltage Drift
Input Bias Current
Over Temperature
Input Voltage Range
Output Voltage Swing
TA = TMIN to TMAX
CV buffer only
TA = TMIN to TMAX
0.6
+5
+5
µV/°C
nA
nA
−5
−5
AVEE + 1.5
AVCC − 1.8
V
Current Sharing and Constant
Voltage Buffers
AVEE + 1.5
AVCC − 1.5
V
Over Temperature
VINT Buffer
Over Temperature
Output Clamps Voltage Range
VCLP Pin
TA = TMIN to TMAX
AVEE + 1.7
VVCLN − 0.6
VVCLN − 0.6
AVCC − 1.5
VVCLP + 0.6
VVCLP + 0.6
V
V
V
TA = TMIN to TMAX
VINT buffer only
VVCLN
AVEE + 1
AVCC − 1
VVCLP
V
V
VCLN Pin
Closed-Loop Output Impedance
Capacitive Load Drive
Short-Circuit Current
PSRR
1
Ω
pF
mA
dB
1000
100
40
ΔVS = 20 V
Voltage Noise
Voltage Noise, Peak-to-Peak
Current Noise
Current Noise, Peak-to-Peak
Small Signal −3 dB Bandwidth
Slew Rate
f = 1 kHz
10
0.3
80
5
3
1
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/µs
f = 0.1 Hz to 10 Hz
f = 1 kHz, CV buffer only
f = 0.1 Hz to 10 Hz
ΔVOUT = 10 V
OVERCURRENT AND OVERVOLTAGE
FAULT COMPARATORS
High Threshold Voltage
Temperature Coefficient
Low Threshold Voltage
Temperature Coefficient
Input Bias Current
With respect to OVPR and OCPR pins
With respect to OVPR and OCPR pins
30
45
mV
µV/°C
mV
µV/°C
nA
100
−30
−100
250
−45
Input Voltage Range
Differential Input Voltage Range
OVPR, OCPR, OVPS, and OCPS pins
Rev. B | Page 6 of 41
AVEE
−7
AVCC − 3
+7
V
V
Data Sheet
AD8450
Parameter
Test Conditions/Comments
FAULT pin (Pin 46)
ILOAD = 200 µA
ILOAD = 200 µA
CLOAD = 10 pF
Min
Typ
Max
Unit
Fault Output Logic Levels
Output Voltage High, VOH
Output Voltage Low, VOL
Propagation Delay
Fault Rise Time
4.5
V
V
ns
ns
ns
0.5
500
150
150
CLOAD = 10 pF
CLOAD = 10 pF
Fault Fall Time
VOLTAGE REFERENCE
Nominal Output Voltage
Output Voltage Error
Temperature Drift
Line Regulation
Load Regulation
Output Current, Sourcing
Voltage Noise
Voltage Noise, Peak-to-Peak
DIGITAL INTERFACE, MODE INPUT
Input Voltage High, VIH
Input Voltage Low, VIL
Mode Switching Time
POWER SUPPLY
With respect to AGND
2.5
V
%
1
10
40
400
10
TA = TMIN to TMAX
ΔVS = 10 V
ΔIVREF = 1 mA (source only)
ppm/°C
ppm/V
ppm/mA
mA
nV/√Hz
µV p-p
f = 1 kHz
100
5
f = 0.1 Hz to 10 Hz
MODE pin (Pin 39)
With respect to DGND
With respect to DGND
2.0
DGND
DVCC
0.8
V
V
ns
500
Operating Voltage Range
AVCC
AVEE
Analog Supply Range
DVCC
5
−31
5
36
0
36
5
V
V
V
V
AVCC − AVEE
3
Quiescent Current
AVCC
AVEE
7
6.5
40
10
10
70
mA
mA
µA
DVCC
TEMPERATURE RANGE
For Specified Performance
Operational
−40
−55
+85
+125
°C
°C
Rev. B | Page 7 of 41
AD8450
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
The θJA value assumes a 4-layer JEDEC standard board with
zero airflow.
Parameter
Rating
36 V
36 V
Analog Supply Voltage (AVCC − AVEE)
Digital Supply Voltage (DVCC − DGND)
Maximum Voltage at Input Pins (ISVP, ISVN,
BVPx, and BVNx)
Table 3. Thermal Resistance
AVEE + 55 V
Package Type
θJA
Unit
80-Lead LQFP
54.7
°C/W
Minimum Voltage at Input Pins (ISVP, ISVN, BVPx, AVCC − 55 V
and BVNx)
Maximum Voltage at All Input Pins, Except ISVP,
ISVN, BVPx, and BVNx
Minimum Voltage at All Input Pins, Except ISVP,
ISVN, BVPx, and BVNx
Maximum Digital Supply Voltage with Respect
to the Positive Analog Supply (DVCC − AVCC)
AVCC
AVEE
+0.5 V
ESD CAUTION
Minimum Digital Supply Voltage with Respect to −0.5 V
the Negative Analog Supply (DVCC − AVEE)
Maximum Digital Ground with Respect to the
Positive Analog Supply (DGND − AVCC)
Minimum Digital Ground with Respect to the
Negative Analog Supply (DGND − AVEE)
Maximum Analog Ground with Respect to the
Positive Analog Supply (AGND − AVCC)
Minimum Analog Ground with Respect to the
Negative Analog Supply (AGND − AVEE)
Maximum Analog Ground with Respect to the
Digital Ground (AGND − DGND)
Minimum Analog Ground with Respect to the
Digital Ground (AGND − DGND)
+0.5 V
−0.5 V
+0.5 V
−0.5 V
+0.5 V
−0.5 V
Operating Temperature Range
−40°C to
+85°C
Storage Temperature Range
−65°C to
+150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 8 of 41
Data Sheet
AD8450
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
ISVP
VCLP
VCTRL
VCLN
AVCC
VINT
PIN 1
2
3
RGP
RGPS
ISGP0
ISGP0S
ISGP1
ISGP1S
ISGP2
ISGP3
RFBP
4
5
6
NC
7
VVE1
VVE0
NC
8
AD8450
TOP VIEW
(Not to Scale)
9
10
11
12
13
14
15
16
17
18
19
20
VVP0
VSETBF
VSET
NC
RFBN
ISGN3
ISGN2
ISGN1S
ISGN1
ISGN0S
ISGN0
RGNS
RGN
DVCC
FAULT
DGND
OCPS
OCPR
VREF
OVPR
ISVN
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NOTES
1. NC = NO CONNECT.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Input/
Pin No.
Mnemonic
Output1 Description
1, 20
ISVP, ISVN
Input
Current Sense Instrumentation Amplifier Positive (Noninverting) and Negative (Inverting) Inputs.
Connect these pins across the current sense shunt resistor.
2, 19
3, 18
4, 6,
8, 9,
RGP, RGN
N/A
Current Sense Instrumentation Amplifier Gain Setting Pins. Connect these pins to the appropriate
resistor network gain pins to select the current sense gain (see Table 5).
Kelvin Sense Pins for the Current Sense Instrumentation Amplifier Gain Setting Pins (RGP and RGN).
Current Sense Instrumentation Amplifier Resistor Network Gain Pins (see Table 5).
RGPS, RGNS
N/A
N/A
ISGP0, ISGP1,
ISGP2, ISGP3,
ISGN3, ISGN2,
ISGN1, ISGN0
12, 13,
15, 17
5, 7,
14, 16
ISGP0S, ISGP1S, N/A
ISGN1S, ISGN0S
Kelvin Sense Pins for the ISGP0, ISGP1, ISGN1, and ISGN0 Pins.
10, 11
21, 35
RFBP, RFBN
BVP3S, BVN3S
Output
N/A
Current Sense Preamplifier Positive and Negative Outputs.
Kelvin Sense Pins for the Voltage Sense Difference Amplifier Inputs BVP3 and BVN3.
22, 23,
24, 25,
31, 32,
33, 34
BVP3, BVP2,
BVP1, BVP0,
BVN0, BVN1,
BVN2, BVN3
Input
Voltage Sense Difference Amplifier Inputs. Each input pair (BVPx and BVNx) corresponds to a
different voltage sense gain (see Table 6).
26, 42, 73 VREF
Output
Input
Voltage Reference Output Pins. VREF = 2.5 V.
27
BVREFH
Reference Input for the Voltage Sense Difference Amplifier. To level shift the voltage sense
difference amplifier output by approximately 5 mV, connect this pin to the VREF pin. Otherwise,
connect this pin to the BVREFL pin.
28, 75
29
30
AGND
BVREFL
BVREFLS
N/A
Input
N/A
Analog Ground Pins.
Reference Input for the Voltage Sense Difference Amplifier. The default connection is to ground.
Kelvin Sense Pin for the BVREFL Pin.
Rev. B | Page 9 of 41
AD8450
Data Sheet
Input/
Pin No.
Mnemonic
Output1 Description
36, 61, 72 AVEE
38, 57, 70 AVCC
N/A
N/A
Output
Input
Analog Negative Supply Pins. The default voltage is −5 V.
Analog Positive Supply Pins. The default voltage is +25 V.
Voltage Sense Difference Amplifier Output.
TTL-Compliant Logic Input to Select the Charge or Discharge Mode. Low = discharge, high =
charge.
37
39
BVMEA
MODE
40
41
OVPS
OVPR
Input
Input
Noninverting Sense Input of the Overvoltage Protection Comparator.
Inverting Reference Input of the Overvoltage Protection Comparator. Typically, this pin connects
to the 2.5 V reference voltage (VREF).
43
OCPR
Input
Inverting Reference Input of the Overcurrent Protection Sense Comparator. Typically, this pin
connects to the 2.5 V reference voltage (VREF).
44
45
46
47
OCPS
DGND
FAULT
DVCC
Input
N/A
Output
N/A
Noninverting Sense Input of the Overcurrent Protection Sense Comparator.
Digital Ground Pin.
Overvoltage or Overcurrent Fault Detection Logic Output (Active Low).
Digital Supply. The default voltage is +5 V.
48, 52, 55, NC
63, 66
N/A
No Connect. There are no internal connections to these pins.
49
50
51
53
54
56, 62
58
VSET
Input
Output
Input
Input
Input
Output
Input
Output
Target Voltage for the Voltage Sense Control Loop.
Buffered Voltage VSET.
VSETBF
VVP0
VVE0
VVE1
VINT
Noninverting Input of the Voltage Sense Integrator for Discharge Mode.
Inverting Input of the Voltage Sense Integrator for Discharge Mode.
Inverting Input of the Voltage Sense Integrator for Charge Mode.
Minimum Output of the Voltage Sense and Current Sense Integrator Amplifiers.
Low Clamp Voltage for VCTRL.
VCLN
VCTRL
59
Controller Output Voltage. Connect this pin to the input of the PWM controller (for example, the
COMP pin of the ADP1972).
60
64
65
67
68
69
71
74
VCLP
IVE1
IVE0
Input
Input
Input
Input
Output
Input
Output
Input
High Clamp Voltage for VCTRL.
Inverting Input of the Current Sense Integrator for Charge Mode.
Inverting Input of the Current Sense Integrator for Discharge Mode.
Target Voltage for the Current Sense Control Loop.
Output of the Uncommitted Operational Amplifier.
Inverting Input of the Uncommitted Operational Amplifier.
Current Sense Instrumentation Amplifier Output.
Reference Input for the Current Sense Amplifier. To level shift the current sense instrumentation
amplifier output by approximately 20 mV, connect this pin to the VREF pin. Otherwise, connect
this pin to the ISREFL pin.
ISET
OAVO
OAVN
ISMEA
ISREFH
76
77
78
79
80
ISREFL
ISREFLS
OAVP
IMAX
Input
N/A
Input
Output
N/A
Reference Input for the Current Sense Amplifier. The default connection is to ground.
Kelvin Sense Pin for the ISREFL Pin.
Noninverting Input of the Uncommitted Operational Amplifier.
Maximum Voltage of All Voltages Applied to the Current Sharing (CSH) Pin.
Current Sharing Bus.
CSH
1 N/A means not applicable.
Rev. B | Page 10 of 41
Data Sheet
AD8450
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, AVCC = +25 V, AVEE = −5 V, RL = ∞, unless otherwise noted.
PGIA CHARACTERISTICS
30
20
15
VALID FOR ALL GAINS
VALID FOR ALL GAINS
25
20
15
10
5
10
5
0
–5
0
–10
–15
–20
–5
AVCC = +25V
AVEE = –5V
–10
AVCC = +15V
AVEE = –15V
–10
–5
0
5
10
15
20
25
30
–20
–15
–10
–5
0
5
10
15
20
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 3. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +25 V and AVEE = −5 V
Figure 6. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +15 V and AVEE = −15 V
15
15
AVCC = +15V
AVEE = –15V
10
5
10
5
GAIN = 200
GAIN = 200
0
0
GAIN = 26
GAIN = 26
–5
–10
–15
–5
–10
–15
AVCC = +25V
AVEE = –5V
–35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40 45
–45–40–35–30–25–20–15–10 –5
0
5
10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 4. Input Overvoltage Performance
for AVCC = +25 V and AVEE = −5 V
Figure 7. Input Overvoltage Performance
for AVCC = +15 V and AVEE = −15 V
17.0
16.8
16.6
16.4
16.2
16.0
15.8
15.6
15.4
15.2
15.0
20
19
18
17
16
15
14
13
12
VALID FOR ALL GAINS
AVCC = +15V
AVEE = –15V
+I
–I
B
AVCC = +25V
AVEE = –5V
B
–15
–10
–5
0
5
10
15
20
25
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
INPUT COMMON-MODE VOLTAGE (V)
Figure 5. Input Bias Current vs. Input Common-Mode Voltage
Figure 8. Input Bias Current vs. Temperature
Rev. B | Page 11 of 41
AD8450
Data Sheet
20
160
150
140
130
120
110
100
90
GAIN = 200
GAIN = 133
GAIN = 66
GAIN = 26
0
GAIN = 200
GAIN = 66
–20
–40
–60
–80
–100
GAIN = 133
GAIN = 26
80
70
60
50
0.1
1
10
100
1k
10k
100k
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 9. Gain Error vs. Temperature
Figure 12. CMRR vs. Frequency
0.3
160
140
120
100
80
AVCC = +25V
AVEE = –5V
0.2
0.1
0
60
–0.1
–0.2
–0.3
GAIN AVCC
AVEE
100
40
GAIN = 200
GAIN = 133
GAIN = 66
GAIN = 26
200
133
66
20
26
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
1
10
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 13. PSRR vs. Frequency
Figure 10. Normalized CMRR vs. Temperature
100
10
1
50
40
GAIN = 200
GAIN = 200
GAIN = 133
GAIN = 66
GAIN = 26
GAIN = 133
GAIN = 66
30
GAIN = 26
RTI
20
10
0
–10
AVCC = +15V
AVEE = –15V
–20
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. Spectral Density Voltage Noise, RTI vs. Frequency
Figure 11. Gain vs. Frequency
Rev. B | Page 12 of 41
Data Sheet
AD8450
PGDA CHARACTERISTICS
60
50
40
GAIN = 0.80
GAIN = 0.40
GAIN = 0.27
GAIN = 0.20
GAIN = 0.80
GAIN = 0.40
GAIN = 0.27
GAIN = 0.20
50
40
30
30
20
20
10
10
0
0
–10
–20
–30
–40
–50
–10
–20
–30
–40
–10
–5
0
5
10
15
20
25
30
–20
–15
–10
–5
0
5
10
15
20
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 15. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +25 V and AVEE = −5 V
Figure 18. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +15 V and AVEE = −15 V
0
50
GAIN = 0.80
GAIN = 0.40
GAIN = 0.27
GAIN = 0.20
–10
0
–20
–30
–40
–50
–50
–100
–150
–200
GAIN = 0.80
GAIN = 0.40
GAIN = 0.27
GAIN = 0.20
VALID FOR ALL RATED
SUPPLY VOLTAGES
100
1k
10k
100k
1M
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. Gain vs. Frequency
Figure 19. Gain Error vs. Temperature
0
–20
3
2
VALID FOR ALL RATED
SUPPLY VOLTAGES
–40
1
–60
0
–80
–1
–2
–3
GAIN = 0.80
GAIN = 0.40
GAIN = 0.27
GAIN = 0.20
GAIN = 0.80
GAIN = 0.40
GAIN = 0.27
GAIN = 0.20
–100
–120
100
1k
10k
100k
1M
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 20. Normalized CMRR vs. Temperature
Figure 17. CMRR vs. Frequency
Rev. B | Page 13 of 41
AD8450
Data Sheet
0
1k
100
10
GAIN = 0.80
GAIN = 0.40
GAIN = 0.27
GAIN = 0.20
GAIN AVCC
AVEE
0.80
0.40
0.27
0.20
–20
–40
RTI
–60
–80
–100
–120
–140
VALID FOR ALL RATED
SUPPLY VOLTAGES
10
100
1k
FREQUENCY (Hz)
10k
100k
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 21. PSRR vs. Frequency
Figure 22. Spectral Density Voltage Noise, RTI vs. Frequency
Rev. B | Page 14 of 41
Data Sheet
AD8450
CC AND CV LOOP FILTER AMPLIFIERS, UNCOMMITTED OP AMP, AND VSET BUFFER
500
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CONSTANT CURRENT LOOP AND
CONSTANT VOLTAGE LOOP AMPLIFIERS
400
300
AVCC = +15V
AVEE = –15V
AVCC = +25V
AVEE = –5V
200
AVCC = +25V
AVEE = –5V
100
0
AVCC = +15V
AVEE = –15V
–100
–200
–300
–400
–500
–15
–10
–5
0
5
10
15
20
25
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
INPUT COMMON-MODE VOLTAGE (V)
Figure 23. Input Offset Voltage vs. Input Common-Mode Voltage
for Two Supply Voltage Combinations
Figure 26. Output Source Current vs. Temperature
for Two Supply Voltage Combinations
100
90
120
100
80
–45.0
–67.5
80
PHASE
GAIN
–90.0
AVCC = +25V
AVEE = –5V
70
60
50
40
30
20
10
0
60
–112.5
–135.0
–157.5
–180.0
–202.5
–225.0
40
AVCC = +15V
AVEE = –15V
20
0
–20
–40
–15
–10
–5
0
5
10
15
20
25
10
100
1k
10k
100k
1M
10M
INPUT COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 24. Input Bias Current vs. Input Common-Mode Voltage
for Two Supply Voltage Combinations
Figure 27. Open-Loop Gain and Phase vs. Frequency
100
80
60
40
20
0
160
140
120
100
80
UNCOMMITTED
OP AMP
60
40
CONSTANT CURRENT LOOP
AND
CONSTANT VOLTAGE
LOOP FILTER
–20
20
–I
+I
B
B
AMPLIFIERS
–40
–40 –30 –20 –10
0
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 25. Input Bias Current vs. Temperature
Figure 28. CMRR vs. Frequency
Rev. B | Page 15 of 41
AD8450
Data Sheet
1.5
1.0
140
120
100
80
AVCC = +15V
AVEE = –15V
+PSRR
0.5
TRANSITION
0
60
–0.5
–1.0
–1.5
–PSRR
40
20
ISET
VCTRL
0
10
–15 –10
–5
0
5
10
15
20
25
30
35
100
1k
10k
100k
1M
TIME (µs)
FREQUENCY (Hz)
Figure 29. PSRR vs. Frequency
Figure 31. CC to CV Transition
1k
100
10
1
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 30. Range of Spectral Density Voltage Noise vs. Frequency
for the Op Amps and Buffers
Rev. B | Page 16 of 41
Data Sheet
AD8450
VINT BUFFER
0.5
6
5
C
R
= 100pF
= 2kΩ
VCTRL OUTPUT WRT VCLP
L
L
0.4
0.3
4
0.2
0.1
3
VCLP AND VCLN REFERENCE
0
VALID FOR ALL RATED
SUPPLY VOLTAGES
2
–0.1
–0.2
–0.3
–0.4
–0.5
1
VCTRL OUTPUT WRT VCLN
0
–1
0
5
10
15
20
25
30
35
40
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TIME (µs)
Figure 32. Output Voltage Swing with Respect to VCLP and VCLN
vs. Temperature
Figure 35. Large Signal Transient Response, RL = 2 kΩ, CL = 100 pF
15
10
5
0.20
C
C
C
C
C
= 10pF
L
L
L
L
L
= 100pF
= 510pF
= 680pF
= 1000pF
0.15
0.10
0.05
0
TEMP VCLP
VCLN
–40°C
+25°C
+85°C
0
–5
–0.05
–0.10
–0.15
–0.20
–10
–15
0
1
2
3
4
5
6
7
8
9
10
100
1k
10k
LOAD RESISTANCE (Ω)
100k
1M
TIME (µs)
Figure 33. Output Voltage Swing vs. Load Resistance at Three Temperatures
Figure 36. Small Signal Transient Response vs. Capacitive Load
6
100
5
VCLP
4
10
TEMP VCLP
VCLN
3
2
–40°C
0°C
+25°C
+85°C
V
= +6V/–1V
IN
1
1
VCLN
0
–1
0.1
10
15
20
25
30
35
40
10
100
1k
10k
100k
1M
OUTPUT CURRENT (mA)
FREQUENCY (Hz)
Figure 34. Clamped Output Voltage vs. Output Current
at Four Temperatures
Figure 37. Output Impedance vs. Frequency
Rev. B | Page 17 of 41
AD8450
Data Sheet
CURRENT SHARING AMPLIFIER
–0.20
3
2
VALID FOR ALL RATED
SUPPLY VOLTAGES
AVCC = +15V
AVEE = –15V
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
1
TRANSITION
0
–1
–2
–3
ISMEA
IMAX
–15 –10
–5
0
5
10
15
20
25
30
35
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TIME (µs)
Figure 38. Output Sink Current vs. Temperature
Figure 39. Current Sharing Bus Transition Characteristics
Rev. B | Page 18 of 41
Data Sheet
AD8450
COMPARATORS
500
5
4
3
2
1
0
450
400
350
VALID FOR ALL
RATED SUPPLY
VOLTAGES
HIGH TO LOW
TRANSITION
TEMP
I
I
SINK
SOURCE
–40°C
+25°C
+85°C
LOW TO HIGH
TRANSITION
300
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
100
200
300
400
500
OUTPUT CURRENT (µA)
Figure 40. Propagation Delay vs. Temperature
Figure 43. Output Voltage vs. Output Current at Three Temperatures
1600
1400
1200
1000
800
6
5
4
3
HIGH TO LOW
TRANSITION
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
2
1
LOW TO HIGH
TRANSITION
600
400
0
200
–1
0
100 200 300 400 500 600 700 800 900 1000
LOAD CAPACITANCE (pF)
2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55
INPUT VOLTAGE (V)
Figure 44. Comparator Transfer Function at Three Temperatures
Figure 41. Propagation Delay vs. Load Capacitance
1000
900
800
700
600
500
400
300
200
100
0
HIGH TO LOW
TRANSITION
LOW TO HIGH
TRANSITION
10
100
1k
10k
SOURCE RESISTANCE (Ω)
Figure 42. Propagation Delay vs. Source Resistance
Rev. B | Page 19 of 41
AD8450
Data Sheet
REFERENCE CHARACTERISTICS
2.51
1200
1100
1000
900
T
T
T
T
T
= +85°C
= +25°C
= 0°C
= –20°C
= –40°C
AVCC = +25V
AVEE = –5V
A
A
A
A
A
2.50
2.49
2.48
2.47
800
700
AVCC = +25V
AVEE = –5V
2.46
600
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
1
2
3
4
5
6
7
8
9
10
OUTPUT CURRENT—SOURCING (mA)
Figure 45. Output Voltage vs. Output Current (Sourcing) over Temperature
Figure 47. Source and Sink Load Regulation vs. Temperature
2.9
1k
AVCC = +25V
AVEE = –5V
2.8
2.7
2.6
100
T
T
T
T
T
= +85°C
= +25°C
= 0°C
= –20°C
= –40°C
A
A
A
A
A
2.5
2.4
10
0.1
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
10
100
1k
10k
100k
OUTPUT CURRENT—SINKING (mA)
FREQUENCY (Hz)
Figure 46. Output Voltage vs. Output Current (Sinking) over Temperature
Figure 48. Spectral Density Voltage Noise vs. Frequency
Rev. B | Page 20 of 41
Data Sheet
AD8450
THEORY OF OPERATION
The analog front end of the AD8450 includes a precision current
sense programmable gain instrumentation amplifier (PGIA)
to measure the battery current, and a precision voltage sense
programmable gain difference amplifier (PGDA) to measure the
battery voltage. The gain programmability of the PGIA allows the
system to set the battery charge/discharge current to any of four
discrete values with the same shunt resistor. The gain program-
mability of the PGDA allows the system to handle up to four
batteries in series (4S).
INTRODUCTION
To form and test a battery, the battery must undergo charge and
discharge cycles. During these cycles, the battery terminal current
and voltage must be precisely controlled to prevent battery failure
or a reduction in the capacity of the battery. Therefore, battery
formation and test systems require a high precision analog front
end to monitor the battery current and terminal voltage.
75
72
70
66
63
61
80
79
78
77
76
74
73
71
69
68
67
65
64
62
1
2.5V
60
59
58
VINT
BUFFER
ISVP
RGP
VCLP
VCTRL
VCLN
AVCC
VINT
VREF
–
AGND
2
1×
+
–
UNCOMMITTED
OP AMP
+/–
+
–
100kΩ
3
RGPS
ISGP0
ISGP0S
ISGP1
+
AVEE
1.1mA
CC LOOP
FILTER
AMPLIFIER
CS
BUFFER
4
57
56
CS BUS
AMPLIFIER
AVCC
AVCC
5
1×
+
–
6
55
54
NC
CV LOOP
FILTER
AMPLIFIER
0.2mA
AVEE
0.2mA
7
VVE1
VVE0
NC
ISGP1S
ISGP2
+
–
53
8
AVEE
BATTERY
CURRENT
SENSING
PGIA
9
52
51
ISGP3
RFBP
RFBN
VSET
BUFFER
10kΩ
10kΩ
10
11
12
13
14
15
16
17
18
19
VVP0
VSETBF
VSET
NC
+
50
49
48
–
1×
CONSTANT
CURRENT AND
20kΩ
ISGN3
ISGN2
ISGN1S
ISGN1
ISGN0S
ISGN0
RGNS
RGN
VOLTAGE LOOP
FILTER AMPLIFIERS
47
46
DVCC
FAULT
DGND
OCPS
OCPR
VREF
OVPR
AD8450
OVERCURRENT
FAULT COMPARATOR
45
44
+
+
–
–
BATTERY
VOLTAGE
SENSING
PGDA
80kΩ
OVERVOLTAGE
FAULT
COMPARATOR
–
NOR
43
42
–
+
+
+/–
100Ω
100kΩ 100kΩ 100kΩ
100kΩ 100kΩ 100kΩ
41
20
MODE
1 = CHARGE
0 = DISCHARGE
ISVN
26
28
21
22
23
24
25
27
29
30
31
32
33
34
35
37
39
40
36
38
Figure 49. AD8450 Detailed Block Diagram
Rev. B | Page 21 of 41
AD8450
Data Sheet
Battery formation and test systems charge and discharge
batteries using a constant current/constant voltage (CC/CV)
algorithm. In other words, the system first forces a set constant
current in or out of the battery until the battery voltage reaches
a target value. At this point, a set constant voltage is forced
across the battery terminals.
Battery formation and test systems used to condition high
current battery cells often employ multiple independent
channels to charge or discharge high currents to or from the
battery. To maximize efficiency, these systems benefit from
circuitry that enables precise current sharing (or balancing)
among the channels—that is, circuitry that actively matches
the output current of each channel. The AD8450 includes a
specialty precision amplifier that detects the maximum output
current among several channels by identifying the channel with
the maximum voltage at its PGIA output. This maximum
voltage can then be compared to all the PGIA output voltages
to actively adjust the output current of each channel.
The AD8450 provides two control loops—a constant current
(CC) loop and a constant voltage (CV) loop—that transition
automatically after the battery reaches the user defined target
voltage. These loops are implemented via two precision specialty
amplifiers with external feedback networks that set the transfer
function of the CC and CV loops. Moreover, in the AD8450,
these loops reconfigure themselves to charge or discharge the
battery by toggling the MODE pin.
Figure 49 is a block diagram of the AD8450 that illustrates the
distinct sections of the AD8450, including the PGIA and PGDA
measurement blocks, the loop filter amplifiers, the fault com-
parators, and the current sharing circuitry. Figure 50 is a block
diagram of a battery formation and test system.
Battery formation and test systems must also be able to detect
overvoltage and overcurrent conditions in the battery to prevent
damage to the battery and/or the control system.
The AD8450 includes two comparators to detect overcurrent
and overvoltage events. These comparators output a logic low at
the FAULT pin when either comparator is tripped.
SET
BATTERY
VINT
CURRENT
ISET
BUFFER
+
–
V
ISET
VCTRL
1×
CONSTANT
VOLTAGE LOOP
FILTER AMPLIFIER
POWER CONVERTER
(SWITCHED OR LINEAR)
SET
+
–
BATTERY
VOLTAGE
VSET
1×
CONSTANT
CURRENT LOOP
FILTER AMPLIFIER
AVEE
AD8450
CONTROLLER
V
VSET
C
D
C
D
C
D
MODE
CV
BUFFER
SWITCHES (3)
C = CHARGE
FAULT
BATTERY
CURRENT
D = DISCHARGE
VINT
NOR
OVERVOLTAGE
COMPARATOR
OVERCURRENT
COMPARATOR
ISVP
+
SENSE
RESISTOR
–
–
PGIA
VREF
OVPS
OVPR
OCPR
OCPS
–
ISVN
SYSTEM LOOP COMPENSATION
ISMEA
BVPx
BVNx
+
BVMEA
PGDA
BATTERY
–
Figure 50. Signal Path of a Li-Ion Battery Formation and Test System Using the AD8450
Rev. B | Page 22 of 41
Data Sheet
AD8450
The external PGIA gain is set by tying 10 kΩ feedback resistors
between the inverting inputs of the PGIA preamplifiers (RGP and
RGN pins) and the outputs of the PGIA preamplifiers (RFBP and
RFBN pins) and by tying a gain resistor (RG) between the RGP
and RGN pins. When using external resistors, the PGIA gain is
PROGRAMMABLE GAIN INSTRUMENTATION
AMPLIFIER (PGIA)
Figure 51 is a block diagram of the PGIA, which is used to monitor
the battery current. The architecture of the PGIA is the classic
3-op-amp topology, similar to the Analog Devices industry-
standard AD8221 and AD620. This architecture provides the
highest achievable CMRR at a given gain, enabling high-side
battery current sensing without the introduction of significant
errors in the measurement. For more information about instru-
mentation amplifiers, see A Designer's Guide to Instrumentation
Amplifiers.
Gain = 2 × (1 + 20 kꢁ/RG)
Note that the PGIA subtractor has a closed-loop gain of 2 to
increase the common-mode range of the preamplifiers.
Reversing Polarity When Charging and Discharging
Figure 50 shows that during the charge cycle, the power converter
feeds current into the battery, generating a positive voltage across
the current sense resistor. During the discharge cycle, the power
converter draws current from the battery, generating a negative
voltage across the sense resistor. In other words, the battery current
polarity reverses when the battery discharges.
VREF
POLARITY
100kΩ
INVERTER
ISREFH
ISREFL
PGIA
ISVP
+ CURRENT
SHUNT
+/–
+
–
10kΩ
19.2kΩ 806Ω
RGP
In the constant current (CC) control loop, this change in
polarity can be problematic if the polarity of the target current
is not reversed. To solve this problem, the AD8450 PGIA includes
a multiplexer preceding its inputs that inverts the polarity of the
PGIA gain. This multiplexer is controlled via the MODE pin.
When the MODE pin is logic high (charge mode), the PGIA gain
is noninverting, and when the MODE pin is logic low (discharge
mode), the PGIA gain is inverting.
RFBP
ISGP0,
ISGP1,
ISGP2,
ISGP3
G = 2 SUBTRACTOR
ISMEA
CONNECT
FOR DESIRED
GAIN
GAIN
ISGN0,
ISGN1,
ISGN2,
ISGN3
NETWORKS
(4)
RFBN
RGN
ISVN
PGIA Offset Option
–
As shown in Figure 51, the PGIA reference node is connected
to the ISREFL and ISREFH pins via an internal resistor divider.
This resistor divider can be used to introduce a temperature
insensitive offset to the output of the PGIA such that the PGIA
output always reads a voltage higher than zero for a zero differ-
ential input. Because the output voltage of the PGIA is always
positive, a unipolar ADC can digitize it.
– CURRENT
SHUNT
+
10kΩ
20kΩ
+/–
POLARITY
INVERTER
MODE
Figure 51. PGIA Simplified Block Diagram
Gain Selection
When the ISREFH pin is tied to the VREF pin with the ISREFL
pin grounded, the voltage at the ISMEA pin is increased by
20 mV, guaranteeing that the output of the PGIA is always
positive for zero differential inputs. Other voltage shifts can be
realized by tying the ISREFH pin to an external voltage source.
The gain from the ISREFH pin to the ISMEA pin is 8 mV/V.
For zero offset, tie the ISREFL and ISREFH pins to ground.
The PGIA includes four fixed internal gain options. The PGIA
can also use an external gain network for arbitrary gain selection.
The internal gain options are established via four independent
three-resistor networks, which are laser trimmed to a matching
level better than 0.1ꢀ. The internal gains are optimized to
minimize both PGIA gain error and gain error drift, allowing
the controller to set a stable charge/discharge current over
temperature. If the built in internal gains are not adequate, the
PGIA gain can be set via an external three-resistor network.
Battery Reversal and Overvoltage Protection
The AD8450 PGIA can be configured for high-side or low-side
current sensing. If the PGIA is configured for high-side current
sensing (see Figure 50) and the battery is connected backward,
the PGIA inputs may be held at a voltage that is below the
negative power rail (AVEE), depending on the battery voltage.
The internal gains of the PGIA are selected by tying the inverting
inputs of the PGIA preamplifiers (RGP and RGN pins) to the
corresponding gain pins of the internal three-resistor network
(ISGP[0:3] and ISGN[0:3] pins). For example, to set the PGIA
gain to 26, tie the RGP pin to the ISGP0 pin, and tie the RGN
pin to the ISGN0 pin. See Table 5 for information about the
gain selection connections.
To prevent damage to the PGIA under these conditions, the
PGIA inputs include overvoltage protection circuitry that allows
them to be held at voltages of up 55 V from the opposite power
rail. In other words, the safe voltage span for the PGIA inputs
extends from AVCC − 55 V to AVEE + 55 V.
Rev. B | Page 23 of 41
AD8450
Data Sheet
When the BVREFH pin is tied to the VREF pin with the BVREFL
pin grounded, the voltage at the BVMEA pin is increased by 5 m V,
guaranteeing that the output of the PGDA is always positive for
zero differential inputs. Other voltage shifts can be realized by
tying the BVREFH pin to an external voltage source. The gain
from the BVREFH pin to the BVMEA pin is 2 mV /V. For zero
offset, tie the BVREFL and BVREFH pins to ground.
PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER
(PGDA)
Figure 52 is a block diagram of the PGDA, which is used to
monitor the battery voltage. The architecture of the PGDA is a
subtractor amplifier with four selectable inputs: the BVP[0:3]
and BVN[0:3] pins. Each input pair corresponds to one of the
internal gains of the PGDA: 0.2, 0.27, 0.4, and 0.8. These gain
values allow the PGDA to funnel the voltage of up to four 5 V
batteries in series (4S) to a level that can be read by a 5 V ADC.
See Table 6 for information about the gain selection connections.
CC AND CV LOOP FILTER AMPLIFIERS
The constant current (CC) and constant voltage (CV) loop filter
amplifiers are high precision, low noise specialty amplifiers with
very low offset voltage and very low input bias current. These
amplifiers serve two purposes:
BVP2
BVP1
BVP0
100kΩ
100kΩ
100kΩ
100kΩ
79.9kΩ
100Ω
50kΩ
BVP3
BVREFL
•
Using external components, the amplifiers implement active
loop filters that set the dynamics (transfer function) of the
CC and CV loops.
BVREFH
VREF
+
PGDA
–
•
The amplifiers perform a seamless transition from CC to
CV mode after the battery reaches its target voltage.
100kΩ
100kΩ
100kΩ
100kΩ
80kΩ
BVMEA
BVN3
Figure 53 is the functional block diagram of the AD8450 CC
and CV feedback loops for charge mode (MODE pin is logic high).
For illustration purposes, the external networks connected to
the loop amplifiers are simple RC networks configured to form
single-pole inverting integrators. The outputs of the CC and CV
loop filter amplifiers are coupled to the VINT pin via an analog
NOR circuit (minimum output selector circuit), such that they can
only pull the VINT node down. In other words, the loop amplifier
that requires the lowest voltage at the VINT pin is in control of
the node. Thus, only one loop amplifier, CC or CV, can be in
control of the system charging control loop at any given time.
BVN2
BVN1
BVN0
Figure 52. PGDA Simplified Block Diagram
The resistors that form the PGDA gain network are laser
trimmed to a matching level better than 0.1%. This level of
matching minimizes the gain error and gain error drift of the
PGDA while maximizing the CMRR of the PGDA. This match-
ing also allows the controller to set a stable target voltage for the
battery over temperature while rejecting the ground bounce in
the battery negative terminal.
Like the PGIA, the PGDA can also level shift its output voltage
via an internal resistor divider that is tied to the PGDA refer-
ence node. This resistor divider is connected to the BVREFH
and BVREFL pins.
I POWER
IOUT
BUS
VCTRL
R1
POWER
CONVERTER
C1
I
V
BAT
ISET
ISMEA
ISET
IVE1
CC LOOP
AMPLIFIER
VINT
VINT
PGIA
ISVP
ISVN
–
+
BUFFER
+
SENSE
RESISTOR
R
VCLP
G
S
IA
ANALOG
NOR
–
VCTRL
VCLN
1×
MINIMUM
OUTPUT
BVPx
BVNx
PGDA
DA
+
–
+
+
SELECTOR
VBAT
G
V3
V4
–
–
CV LOOP
AMPLIFIER
MODE
5V
BVMEA
VSET
VSET
VVE1
R2
VINT
V
V3 < VCTRL < V4
C2
Figure 53. Functional Block Diagram of the CC and CV Loops in Charge Mode (MODE Pin High)
Rev. B | Page 24 of 41
Data Sheet
AD8450
The unity-gain amplifier (VINT buffer) buffers the VINT pin
and drives the VCTRL pin. The VCTRL pin is the control
output of the AD8450 and the control input of the power
converter. The VISET and VVSET voltage sources set the target
constant current and the target constant voltage, respectively.
When the CC and CV feedback loops are in steady state, the
charging current is set at
The following steps describe how the AD8450 implements the
CC/CV charging profile (see Figure 53). In this scenario, the
battery begins in the fully discharged state, and the system has
just been turned on such that IBAT = 0 A at Time 0.
1. Because the voltages at the ISMEA and BVMEA pins
are below the target voltages (VISET and VVSET) at Time 0,
both integrators begin to ramp, increasing the voltage at
the VINT node.
2. As the voltage at the VINT node increases, the voltage at
the VCRTL node rises, and the output current of the power
converter, IBAT, increases (assuming that an increasing
voltage at the VCRTL node increases the output current
of the power converter).
VISET
IBAT_SS
=
G
IA ×RS
where:
IA is the PGIA gain.
G
RS is the value of the shunt resistor.
The target voltage is set at
VVSET
3. When the IBAT current reaches the CC steady state value,
I
BAT_SS, the battery voltage is still below the target steady
VBAT_SS
=
state value, VBAT_SS. Therefore, the CV loop tries to keep
pulling the VINT node up while the CC loop tries to keep
it at its current voltage. At this point, the voltage at the
ISMEA pin equals VISET, so the CC loop stops integrating.
4. Because the loop amplifiers can only pull the VINT node
down due to the analog NOR circuit, the CC loop takes
control of the charging feedback loop and the CV loop is
disabled.
GDA
where GDA is the PGDA gain.
Because the offset voltage of the loop amplifiers is in series with
the target voltage sources, VISET and VVSET, the high precision of
these amplifiers minimizes this source of error.
Figure 54 shows a typical CC/CV charging profile for a Li-Ion
battery. In the first stage of the charging process, the battery is
charged with a constant current (CC) of 1 A. When the battery
voltage reaches a target voltage of 4.2 V, the charging process
transitions such that the battery is charged with a constant
voltage (CV) of 4.2 V.
5. As the charging process continues, the battery voltage
increases until it reaches the steady state value, VBAT_SS
and the voltage at the BVMEA pin reaches the target
,
voltage, VVSET
.
6. The CV loop tries to pull the VINT node down to reduce
the charging current (IBAT) and prevent the battery voltage
from rising any farther. At the same time, the CC loop tries
to keep the VINT node at its current voltage to keep the
1.25
1.00
0.75
0.50
0.25
0
5
4
3
2
1
0
TRANSITION FROM CC TO CV
CC
CHARGE
BEGINS
battery current at IBAT_SS
.
7. Because the loop amplifiers can only pull the VINT node
down due to the analog NOR circuit, the CV loop takes
control of the charging feedback loop and the CC loop is
disabled.
The analog NOR (minimum output selector) circuit that couples
the outputs of the loop amplifiers is optimized to minimize the
transition time from CC to CV control. Any delay in the trans-
ition causes the CC loop to remain in control of the charge
feedback loop after the battery voltage reaches its target value.
Therefore, the battery voltage continues to rise beyond VBAT_SS
until the control loop transitions; that is, the battery voltage
overshoots its target voltage. When the CV loop takes control
of the charge feedback loop, it reduces the battery voltage to the
target voltage. A large overshoot in the battery voltage due to
transition delays can damage the battery; thus, it is crucial to
minimize delays by implementing a fast CC to CV transition.
CC
CHARGE
ENDS
0
1
2
3
4
5
TIME (Hours)
Figure 54. Representative Constant Current to Constant Voltage Transition
Near the End of a Battery Charging Cycle
Rev. B | Page 25 of 41
AD8450
Data Sheet
I POWER
BUS
IOUT
VCTRL
R1
POWER
CONVERTER
V
C1
I
ISET
BAT
ISMEA
ISET
IVE0
CC LOOP
AMPLIFIER
VINT
VINT
PGIA
ISVP
ISVN
–
+
BUFFER
+
SENSE
RESISTOR
R
VCLP
G
S
IA
ANALOG
NOR
–
VCTRL
VCLN
1×
VSET
CV LOOP
AMPLIFIER
MINIMUM
OUTPUT
SELECTOR
BUFFER
BVPx
BVNx
PGDA
+
–
+
–
+
VBAT
G
DA
V3
V4
1×
–
MODE
BVMEA VSET
VSETBF VVP0 VVE0
VINT
V3 < VCTRL < V4
0V
V
VSET
C2
R2
C2
R2
Figure 55. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low)
Figure 55 is the functional block diagram of the AD8450 CC
and CV feedback loops for discharge mode (MODE pin is logic
low. In discharge mode, the feedback loops operate in a similar
manner as in charge mode. The only difference is in the CV
loop amplifier, which operates as a noninverting integrator in
discharge mode. For illustration purposes, the external networks
connected to the loop amplifiers are simple RC networks
configured to form single-pole integrators (see Figure 55).
VINT BUFFER
The unity-gain amplifier (VINT buffer) is a clamp amplifier
that drives the VCTRL pin. The VCTRL pin is the control
output of the AD8450 and the control input of the power
converter (see Figure 53 and Figure 55). The output voltage
range of this amplifier is bounded by the clamp voltages at
the VCLP and VCLN pins such that
VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V
COMPENSATION
The reduction in the output voltage range of the amplifier is a
safety feature that allows the AD8450 to drive devices such as the
ADP1972 pulse-width modulation (PWM) controller, whose
input voltage range must not exceed 5.5 V (that is, the voltage at
the COMP pin of the ADP1972 must be below 5.5 V).
In battery formation and test systems, the CC and CV feedback
loops have significantly different open-loop gain and crossover
frequencies; therefore, each loop requires its own frequency
compensation. The active filter architecture of the AD8450 CC
and CV loops allows the frequency response of each loop to be set
independently via external components. Moreover, due to the
internal switches in the CC and CV amplifiers, the frequency
response of the loops in charge mode does not affect the frequency
response of the loops in discharge mode.
MODE PIN, CHARGE AND DISCHARGE CONTROL
The MODE pin is a TTL logic input that configures the AD8450
for either charge or discharge mode. A logic low (VMODE < 0.8 V)
corresponds to discharge mode, and a logic high (VMODE > 2 V)
corresponds to charge mode. Internal to the AD8450, the MODE
pin toggles all SPDT switches in the CC and CV loop amplifiers
and inverts the gain polarity of the PGIA.
Unlike simpler controllers that use passive networks to ground
for frequency compensation, the AD8450 allows the use of feed-
back networks for its CC and CV loop filter amplifiers. These
networks enable the implementation of both PD (Type II) and
PID (Type III) compensators. Note that in charge mode, both
the CC and CV loops implement inverting compensators, whereas
in discharge mode, the CC loop implements an inverting compen-
sator and the CV loop implements a noninverting compensator.
As a result, the CV loop in discharge mode includes an additional
amplifier, VSET buffer, to buffer the VSET node from the feed-
back network (see Figure 55).
Rev. B | Page 26 of 41
Data Sheet
AD8450
Alternatively, the outputs of the PGIA and PGDA can be tied
OVERCURRENT AND OVERVOLTAGE
COMPARATORS
directly to the sense inputs of the comparators (OCPS and
OVPS pins) such that the voltages at the ISMEA and BVMEA
pins are compared to the external reference voltages, VOCP_REF
and VOVP_REF (see Figure 57). In this configuration, the FAULT
pin registers a logic low (a fault condition) when
The AD8450 includes overcurrent protection (OCP) and over-
voltage protection (OVP) comparators to detect overvoltage
and overcurrent conditions in the battery. Because the outputs
of the comparators are combined by a NOR logic gate, these
comparators output a logic low at the FAULT pin when either
comparator is tripped (see Figure 49).
VISMEA > VOCP_REF
or
The OCP and OVP comparators can be configured to detect a
fault in one of two ways. In the configuration shown in Figure 56,
the voltages at the ISMEA and BVMEA pins are divided down
and compared to the internal 2.5 V reference of the AD8450. In
this configuration, the FAULT pin registers a logic low (a fault
condition) when
V
BVMEA > VOVP_REF
ISVP
ISVN
+
ISMEA
PGIA
–
BVPx
BVNx
R1+ R2
+
–
BVMEA
VISMEA
>
× 2.5 V
PGDA
R2
or
R3 + R4
OVPS
OVPR
+
–
VBVMEA
>
× 2.5 V
V
V
OVP_REF
R3
+
–
FAULT
NOR
ISVP
ISVN
OCPR
OCPS
OCP_REF
+
–
+
ISMEA
PGIA
+
–
–
R1
BVPx
BVNx
+
–
Figure 57. OVP and OCP Comparator Configuration
Using an External Reference (For Example, a DAC)
BVMEA
PGDA
R3
OVPS
OVPR
+
–
R4
FAULT
NOR
VREF
OCPR
OCPS
–
+
R2
Figure 56. OVP and OCP Comparator Configuration
Using the Internal Reference
Rev. B | Page 27 of 41
AD8450
Data Sheet
By means of external resistors, the uncommitted operational
amplifier is configured as a difference amplifier to measure the
voltage difference between the IMAX and ISMEA nodes.
CURRENT SHARING BUS AND IMAX OUTPUT
Battery formation and test systems that use multiple channels
bridged together to condition high current battery cells require
circuitry to balance the total output current among the channels.
Current balance, or current sharing (CS), can be implemented
by actively matching the output current of each channel during
the battery charge/discharge process.
During the charge process, the charging current and, therefore,
the voltage at the ISMEA pin, is slightly different in each channel
due to mismatches in the components that make up each channel.
Because the CS bus amplifiers are driven by their respective PGIAs
and have output stages that can only pull up their output nodes,
the amplifier that requires the highest voltage takes control of the
CS bus. Therefore, the voltage at the CS bus is pulled up to match
the VISMEA voltage of the channel with the largest output current.
The current sharing bus amplifier is a precision unity-gain
specialty amplifier with an output stage that can only pull up its
output node (the CSH pin). The amplifier is configured as a
unity-gain buffer with its input connected to the ISMEA pin
(the output of the PGIA). If the CSH pin is left unconnected, the
voltage at the pin is a replica of the voltage at the ISMEA pin.
The output voltage of the uncommitted op amp in each channel
is proportional to the difference between the channel’s output
current and the largest output current. This output voltage can
then be used to form a feedback loop that actively corrects the
channel’s output current by adjusting the channel’s target current
and target voltage, that is, adjusting VISET and VVSET voltages.
Figure 58 is a functional block diagram of the current sharing
circuit. In this example, Channel 0 through Channel n are
bridged together to charge a high current battery.
The CS output of each channel is tied to a common bus (CS bus),
which is buffered by the CS buffer amplifier to the IMAX pin.
I_0
CHANNEL 0
CS BUS
AMPLIFIER
UNCOMMITTED
CS
OP AMP
BUFFER
+
ISVP
ISVN
+
+
–
R
PGIA
–
1
S0
I_0
I_1
I_n
–
AVEE
ISMEA
CS
IMAX
OAVP
OAVN
OAVO
R
IBAT
R
R
R
CORRECTION
SIGNAL
V
− V
CS
ISMEA
CHANNEL 0
CHANNEL 1
CHANNEL n
CS BUS
Figure 58. Functional Block Diagram of the Current Sharing Circuit
Rev. B | Page 28 of 41
Data Sheet
AD8450
APPLICATIONS INFORMATION
This section describes how to use the AD8450 in the context of
a battery formation and test system. This section includes a design
example of a small scale model of an actual system. An evaluation
board for the AD8450 is available and is described in the
Evaluation Board section.
POWER SUPPLY CONNECTIONS
The AD8450 requires two analog power supplies (AVCC and
AVEE), one digital power supply (DVCC), one analog ground
(AGND), and one digital ground (DGND). AVCC and AVEE
power all the analog blocks, including the PGIA, PGDA, op amps,
and comparators. DVCC powers the MODE input logic circuit
and the FAULT output logic circuit. AGND provides a reference
and return path for the 2.5 V reference, and DGND provides a
reference and return path for the digital circuitry.
FUNCTIONAL DESCRIPTION
The AD8450 is a precision analog front end and controller for
battery formation and test systems. These systems use precision
controllers and power stages to put batteries through charge and
discharge cycles. Figure 59 shows the signal path of a simplified
switching battery formation and test system using the AD8450
controller and the ADP1972 PWM controller. For more
The rated absolute maximum value for AVCC − AVEE is 36 V,
and the minimum operating AVCC and AVEE voltages are +5 V
and −5 V, respectively. Due to the high PSRR of the AD8450
analog blocks, AVCC can be connected directly to the high current
power bus (the input voltage of the power converter) without
risking the injection of supply noise to the controller outputs.
information about the ADP1972, see the ADP1972 data sheet.
The AD8450 is suitable for systems that form and test NiCad,
NiMH, and Li-Ion batteries and is designed to operate in
conjunction with both linear and switching power stages.
A commonly used power supply combination is +25 V and
−5 V for AVCC and AVEE, and +5 V for DVCC. The +25 V rail
for AVCC provides enough headroom to the PGIA such that it
can be connected in a high-side current sensing configuration
with up to four batteries in series (4S). The −5 V rail for AVEE
allows the PGDA to sense accidental reverse battery conditions
(see the Reverse Battery Conditions section).
The AD8450 includes the following blocks (see Figure 49 and
the Theory of Operation section for more information).
Pin programmable gain instrumentation amplifier (PGIA)
that senses low-side or high-side battery current.
Pin programmable gain difference amplifier (PGDA) that
measures the terminal voltage of the battery.
Two loop filter error amplifiers that receive the battery target
current and voltage and establish the dynamics of the constant
current (CC) and constant voltage (CV) feedback loops.
Minimum output selector circuit that combines the outputs
of the loop filter error amplifiers to perform automatic CC
to CV switching.
Output clamp amplifier that drives the VCTRL pin. The
voltage range of this amplifier is bounded by the voltage
at the VCLP and VCLN pins such that it cannot overrange
the subsequent stage. The output clamp amplifier can drive
switching and linear power converters. Note that an increas-
ing voltage at the VCTRL pin must translate to a larger
output current in the power converter.
Connect decoupling capacitors to all the supply pins. A 1 μF
capacitor in parallel with a 0.1 μF capacitor is recommended.
POWER SUPPLY SEQUENCING
As detailed in the absolute maximum ratings table (see Table 2),
the voltage at any input pin other than ISVP, ISVN, BVPx, and
BVNx cannot exceed the positive analog supply (AVCC) by
more than 0.5 V and cannot be exceeded by the analog negative
supply (AVEE) by 0.5V.
Additionally, supply and ground pins (DVCC, DGND, and
AGND) cannot exceed the positive analog supply (AVCC) by
more than 0.5 V and cannot be exceeded by the analog negative
supply (AVEE) by 0.5V.
Therefore, power-on and power-off sequencing may be
required to comply with the absolute maximum ratings.
Overcurrent and overvoltage comparators whose outputs are
combined using a NOR gate to drive the FAULT pin. The
FAULT pin presents a logic low when either comparator is
tripped.
Failure to comply with the absolute maximum ratings can result
in functional failure or damage to the internal ESD diodes.
Damaged ESD diodes can cause parametric failures and cannot
provide full ESD protection, reducing reliability.
2.5 V reference that can be used as the reference voltage for
the overcurrent and overvoltage comparators. The output
node of the 2.5 V reference is the VREF pin.
Current sharing amplifier that detects the maximum battery
current among several charging channels and whose output
can be used to implement current balancing.
Logic input pin (MODE) that changes the configuration of
the controller from charge to discharge mode. A logic high
at the MODE pin configures charge mode; a logic low
configures discharge mode.
POWER-ON SEQUENCE
To power on the device, take the following steps:
1. Turn on AVCC
2. Turn on AVEE
3. Turn on DVCC
4. Turn on the input signals
The positive analog supply (AVCC) and the negative analog
supply (AVEE) may be turned on simultaneously.
Rev. B | Page 29 of 41
AD8450
Data Sheet
Table 5. PGIA Gain Connections
PGIA Gain Connect RGP (Pin 2) to Connect RGN (Pin 19) to
POWER-OFF SEQUENCE
To power off the device, take the following steps:
26
ISGP0 (Pin 4)
ISGP1 (Pin 6)
ISGP2 (Pin 8)
ISGP3 (Pin 9)
ISGN0 (Pin 17)
ISGN1 (Pin 15)
ISGN2 (Pin 13)
ISGN3 (Pin 12)
1. Turn off the input signals.
2. Turn off DVCC.
3. Turn off AVEE.
66
133
200
4. Turn off AVCC.
If a different gain value is desired, connect 10 kΩ feedback resistors
between the inverting inputs of the PGIA preamplifiers (RGP
and RGN pins) and the outputs of the PGIA preamplifiers (RFBP
and RFBN pins). Also, connect a gain resistor (RG) between the
RGP and RGN pins. When using external resistors, the gain of
the PGIA is
The positive analog supply (AVCC) and the negative analog
supply (AVEE) may be turned off simultaneously.
PGIA CONNECTIONS
For a description of the PGIA, see the Theory of Operation
section, Figure 49, and Figure 51. The internal gains of the
PGIA (26, 66, 133, and 200) are selected by hardwiring the
appropriate pin combinations (see Table 5).
Gain = 2 × (1 + 20 kΩ/RG)
SET
BATTERY
CURRENT
CONSTANT
AVCC
VINT
VOLTAGE LOOP
FILTER AMPLIFIER
ISET
BUFFER
+
–
OUTPUT
FILTER
VCTRL
LEVEL
SHIFTER
OUTPUT
DRIVERS
ADP1972
PWM
1×
CC AND CV
GATES
CONSTANT
CURRENT LOOP
FILTER AMPLIFIER
SET
BATTERY
VOLTAGE
+
–
VSET
1×
DC-TO-DC
POWER CONVERTER
AVEE
AD8450
CONTROLLER
MODE
SWITCHES (3)
C
D
C
D
C
D
C = CHARGE
D = DISCHARGE
CV
BUFFER
FAULT
BATTERY
CURRENT
VINT
NOR
OVERVOLTAGE
COMPARATOR
OVERCURRENT
COMPARATOR
ISVP
ISVN
+
SENSE
RESISTOR
–
–
PGIA
VREF
OVPS
OVPR
OCPR
OCPS
–
EXTERNAL PASSIVE
COMPENSATION
NETWORK
ISMEA
BVPx
BVNx
+
BVMEA
PGDA
BATTERY
–
Figure 59. Complete Signal Path of a Battery Test or Formation System Suitable for Li-Ion Batteries
Rev. B | Page 30 of 41
Data Sheet
AD8450
Current Sensors
Set the PGDA gain value to attenuate the voltage of up to four 5 V
battery cells in series to a full-scale voltage of 4 V. For example, a
5 V battery voltage is attenuated to 4 V using the gain of 0.8, and
a 20 V battery voltage (four 5 V batteries in series) is attenuated
to 4 V using the gain of 0.2. This voltage scaling enables the use of
a 5 V ADC to read the battery voltage at the BVMEA output pin.
Two common options for current sensors are isolated current
sensing transducers and shunt resistors. Isolated current sensing
transducers are galvanically isolated from the power converter
and are affected less by the high frequency noise generated by
switch mode power supplies. Shunt resistors are less expensive
and easier to deploy.
Reverse Battery Conditions
If a shunt resistor sensor is used, a 4-terminal, low resistance shunt
resistor is recommended. Two of the four terminals conduct the
battery current, whereas the other two terminals conduct virtually
no current. The terminals that conduct no current are sense
terminals that are used to measure the voltage drop across the
resistor (and, therefore, the current flowing through it) using an
amplifier such as the PGIA of the AD8450. To interface the PGIA
with the current sensor, connect the sense terminals of the sensor
to the ISVP and ISVN pins of the AD8450 (see Figure 60).
The output voltage of the AD8450 PGDA can be used to detect
a reverse battery connection. A −5 V rail for AVEE allows the
output of the PGDA to go below ground when the battery is
connected backward. Therefore, the condition can be detected
by monitoring the BVMEA pin for a negative voltage.
BATTERY CURRENT AND VOLTAGE CONTROL
INPUTS (ISET AND VSET)
The voltages at the ISET and VSET input pins set the target
battery current and voltage for the constant current (CC) and
constant voltage (CV) loops. These inputs must be driven by a
precision voltage source (or a DAC connected to a precision
reference) whose output voltage is referenced to the same voltage
as the PGIA and PGDA reference pins (ISREFH/ISREFL and
BVREFH/BVREFL, respectively). For example, if the PGIA ref-
erence pins are connected to AGND, the voltage source connected
to ISET must also be referenced to AGND. In the same way, if
the PGDA reference pins are connected to AGND, the voltage
source connected to VSET must also be referenced to AGND.
Optional Low-Pass Filter
The AD8450 is designed to control both linear regulators and
switching power converters. Linear regulators are generally
noise free, whereas switch mode power converters generate
switching noise. Connecting an external differential low-pass
filter between the current sensor and the PGIA inputs reduces
the injection of switching noise into the PGIA (see Figure 60).
ISVP
+
RGP
–
In constant current mode, when the CC feedback loop is in
steady state, the ISET input sets the battery current as follows:
RFBP
20kΩ
10kΩ
10kΩ
10kΩ
ISGPx
VISET
IBAT_SS
=
+
–
LPF
G
IA ×RS
RGn
10kΩ
ISGNx
RFBN
where:
IA is the PGIA gain.
RS is the value of the shunt resistor.
20kΩ
DUT
G
RGN
ISVN
–
+
In constant voltage mode, when the CV feedback loop is in
steady state, the VSET input sets the battery voltage as follows:
Figure 60. 4-Terminal Shunt Resistor Connected to the Current Sense PGIA
VVSET
GDA
PGDA CONNECTIONS
VBAT_SS
=
For a description of the PGDA, see the Theory of Operation
section, Figure 49, and Figure 52. The internal gains of the
PGDA (0.2, 0.27, 0.4, and 0.8) are selected by connecting the
appropriate input pair to the battery terminals (see Table 6).
where GDA is the PGDA gain.
Therefore, the accuracy and temperature stability of the formation
and test system are dependent not only on the precision of the
AD8450, but also on the accuracy of the ISET and VSET inputs.
Table 6. PGDA Gain Connections
PGDA
Gain
Connect Battery
Positive Terminal to
Connect Battery
Negative Terminal to
0.8
0.4
0.27
0.2
BVP0 (Pin 25)
BVP1 (Pin 24)
BVP2 (Pin 23)
BVP3 (Pin 22)
BVN0 (Pin 31)
BVN1 (Pin 32)
BVN2 (Pin 33)
BVN3 (Pin 34)
Rev. B | Page 31 of 41
AD8450
Data Sheet
LOOP FILTER AMPLIFIERS
OVERVOLTAGE AND OVERCURRENT
COMPARATORS
The AD8450 has two loop filter amplifiers, also known as error
amplifiers (see Figure 59). One amplifier is for constant current
control (CC loop filter amplifier), and the other amplifier is for
constant voltage control (CV loop filter amplifier). The outputs
of these amplifiers are combined using a minimum output
selector circuit to perform automatic CC to CV switching.
The reference inputs of the overvoltage and overcurrent comparators
can be driven with external voltage references or with the internal
2.5 V reference (adjacent VREF pin). If external voltage references
are used, the sense inputs can be driven directly by the PGIA and
PGDA output nodes, ISMEA and BVMEA, respectively. If the
internal 2.5 V reference is used, the sense inputs can be driven
by resistor dividers, which attenuate the voltage at the ISMEA
and BVMEA nodes. For more information, see the Overcurrent
and Overvoltage Comparators section.
Table 7 lists the inputs of the loop filter amplifiers for charge
mode and discharge mode.
Table 7. Integrator Input Connections
Reference Feedback
STEP BY STEP DESIGN EXAMPLE
Feedback Loop Function
Input
Terminal
This section describes the systematic design of a 1 A battery
charger/discharger using the AD8450 controller and the ADP1972
pulse-width modulation (PWM) controller. The power converter
used in this design is a nonisolated buck boost dc-to-dc converter.
The target battery is a 4.2 V fully charged, 2.7 V fully discharged
Li-Ion battery.
Control the Current While
Discharging a Battery
Control the Current While Charging a
Battery
Control the Voltage While
Discharging a Battery
Control the Voltage While Charging a
Battery
ISET
IVE0
ISET
IVE1
VSET
VSET
VVE0
VVE1
Step 1: Design the Switching Power Converter
Select the switches and passive components of the buck boost
power converter to support the 1 A maximum battery current.
The design of the power converter is beyond the scope of this
data sheet; however, there are many application notes and other
helpful documents available from manufacturers of integrated
driver circuits and power MOSFET output devices that can be
used for reference.
The CC and CV amplifiers in charge mode and the CC amplifier
in discharge mode are inverting integrators, whereas the CV
amplifier in discharge mode is a noninverting integrator. There-
fore, the CV amplifier in discharge mode uses an extra amplifier,
the VSET buffer, to buffer the VSET input pin (see Figure 49).
Also, the CV amplifier in discharge mode uses the VVP0 pin to
couple the signal from the BVMEA pin to the integrator.
Step 2: Identify the Control Voltage Range of the
ADP1972
CONNECTING TO A PWM CONTROLLER (VCTRL PIN)
The VCTRL output pin of the AD8450 is designed to interface
with linear power converters and with pulse-width modulation
(PWM) controllers such as the ADP1972. The voltage range of
the VCTRL output pin is bounded by the voltages at the VCLP
and VCLN pins, as follows:
The control voltage range of the ADP1972 (voltage range of the
COMP input pin) is 0.5 V to 4.5 V. An input voltage of 4.5 V
results in the highest duty cycle and output current, whereas an
input voltage of 0.5 V results in the lowest duty cycle and output
current. Because the COMP pin connects directly to the VCTRL
output pin of the AD8450, the battery current is proportional to
the voltage at the VCTRL pin.
VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V
Because the maximum rated input voltage at the COMP pin of
the ADP1972 is 5.5 V, connect the clamp voltages of the output
amplifier to +5 V (VCLP) and ground (VCLN) to prevent over-
ranging of the COMP input. As an additional precaution, install
an external 5.1 V Zener diode from the COMP pin to ground
with a series 1 kΩ resistor connected between the VCTRL and
COMP pins. Consult the ADP1972 data sheet for additional
applications information.
For information about how to interface the ADP1972 to the
power converter switches, see the ADP1972 data sheet.
Step 3: Determine the Control Voltage for the CV Loop
and the PGDA Gain
The relationship between the control voltage for the CV loop
(the voltage at the VSET pin), the target battery voltage, and the
PGDA gain is as follows:
Given the architecture of the AD8450, the controller requires
that an increasing voltage at the VCTRL pin translate to a larger
output current in the power converter. If this is not the case, a
unity-gain inverting amplifier can be added in series with the
AD8450 output to add an extra inversion.
VVSET
CV Battery Target Voltage =
PGDAGain
In charge mode, for a CV battery target voltage of 4.2 V, the
PGDA gain of 0.8 maximizes the dynamic range of the PGDA.
Therefore, select a CV control voltage of 3.36 V. In discharge
mode, for a CV battery target voltage of 2.7 V, the CV control
voltage is 2.16 V.
Rev. B | Page 32 of 41
Data Sheet
AD8450
Step 4: Determine the Control Voltage for the CC Loop,
the Shunt Resistor, and the PGIA Gain
Step 5: Choose the Control Voltage Sources
The input control voltages (the voltages at the ISET and VSET pins)
can be generated by an analog voltage source such as a voltage
reference or by a digital-to-analog converter (DAC). In both
cases, select a device that provides a stable, low noise output
voltage. If a DAC is preferred, Analog Devices offers a wide
range of precision converters. For example, the AD5668 16-bit
DAC provides up to eight 0 V to 4 V sources when connected to
an external 2 V reference.
The relationship between the control voltage for the CC loop
(the voltage at the ISET pin), the target battery current, and the
PGIA gain is as follows:
VISET
CC Battery Target Current =
RS × PGIA Gain
The voltage across the shunt resistor is as follows:
VISET
Shunt Resistor Voltage =
PGIA Gain
To maximize accuracy, the control voltage sources must be
referenced to the same potential as the outputs of the PGIA and
PGDA. For example, if the PGIA and PGDA reference pins are
connected to AGND, connect the reference pins of the control
voltage sources to AGND.
Selecting the highest PGIA gain of 200 reduces the voltage across
the shunt resistor, minimizing dissipated power and inaccuracies
due to self heating. For a PGIA gain of 200 and a target current
of 1 A, choosing a 20 mΩ shunt resistor results in a control
voltage of 4 V.
Step 6: Select the Compensation Devices
Feedback controlled switching power converters require frequency
compensation to guarantee loop stability. There are many refer-
ences available about how to design the compensation for such
power converters. The AD8450 provides active loop-filter error-
amplifiers for the CC and CV control loops that can implement
PI, PD, and PID compensators using external passive components.
When selecting a shunt resistor, pay close attention to the
resistor style and construction. For low power applications,
many surface-mount (SMD), temperature stable styles are
available that solder to a mating pad on a printed circuit board
(PCB). For optimum accuracy, specify a 4-terminal shunt
resistor that provides separate high current and sense terminals.
This type of resistor directs the majority of the battery current
through a high current path. An additional pair of terminals
provides a separate connection for the input leads to the PGIA,
avoiding the power loss inherent to forcing the full battery
current through the distance to the PGIA pins. Because the bias
current is so low, the sense error is significantly less than if the
battery current were to transverse the additional lead length.
ADDITIONAL INFORMATION
Additional information relative to using the AD8450 is available in
the AN-1319, Compensator Design for a Battery Charge/Discharge
Unit Using the AD8450 or the AD8451.
Rev. B | Page 33 of 41
AD8450
Data Sheet
EVALUATION BOARD
INTRODUCTION
FEATURES AND TESTS
Figure 61 is a photograph of the AD8450-EVALZ. The evaluation
board is a convenient standalone platform for evaluating the
major elements of the AD8450 (such as the PGIA and PGDA).
The circuit architecture is particularly suitable for evaluating
PID loop compensation when connected within an operating
charge/discharge system. Four separate loop dynamic networks are
available for constant current charge and discharge, and constant
voltage charge and discharge. The network subcircuits are shown
on the right hand side of the board schematic (Figure 62).
The AD8450-EVALZ contains many user friendly features to
facilitate evaluation of the AD8450 performance. Numerous
connectors, test loops, and points facilitate the attachment of
scope probes and cables, and I/O switches conveniently exercise
various device options.
TESTING THE AD8450-EVALZ
The schematic item abbreviation TP signifies a test loop. Prior
to testing, install Jumpers TST1 through TST5 and move the
Shunts RUN1 through RUN5 to a single pin to open the
connection. Connect +25 V at AVCC, −5 V at AVEE, and
+5 V at DVCC.
SMA connectors provide shielded access to the highly sensitive
programmable gain instrumentation amplifier (PGIA) and the
programmable gain difference amplifier (PGDA). SMA connectors
ISET and VSET are the constant current and constant voltage
control inputs. The ISMEA and VCTRL outputs, current and
voltage alarm references, and trigger voltages are accessible for
testing. The MODE switch selects either the charge or discharge
option. Figure 62 is a schematic of the AD8450-EVALZ. Table 8
lists and describes the various switches and their functions and
lists the SMA connector I/O.
PGIA and Offset
PGIA Gain Test
Apply 10 mV dc across TPISVP and TPISVN. For bench testing,
connect ISVN to ground using an external jumper. Use the
ISGN switch to select the desired PGIA gain option, and measure
the output voltage at TPISMEA or TPIMAX (referenced to
ground). For gains of 26, 66, 133, and 200, the output voltages
are 260 mV, 660 mV, 1.33 V, and 2 V, respectively. Subtract any
residual offset voltages from the output reading before
calculating the gain.
Figure 61. Photograph of the AD8450-EVALZ
Rev. B | Page 34 of 41
Data Sheet
AD8450
Table 8. AD8450-EVALZ Test Switches and Their Functions
Default
Switch
ISGN
Function
Operation
Position1
PGIA gain switch
PGDA gain switch
The ISGN switch selects one of four fixed gain values: 26, 66, 133, or 200.
The BVGN switch selects one of four fixed gain values: 0.2, 0.27, 0.4, or 0.8.
User select
N/A
BVGN
IS_REF
Selects between offset options for NORM: 0 V reference.
NORM
the PGIA
20mV: offsets the PGIA reference by 20 mV.
EXT: An externally supplied reference voltage is applied to the PGIA.
NORM: Overvoltage (OV) reference applied.
5mV: The BVDA is offset by 5 mV.
EXT: An externally supplied reference voltage is applied to the BVDA.
The MODE switch selects CHG (logic high) or DISCH (logic low).
BV_REF
MODE
Selects input source option for
the BVREFH pin
NORM
Selects charge or discharge mode
CHG
RUN
RUN_TEST1 Configures the ISET and VSET
inputs to test the integrators.
RUN: The ISET and VSET inputs are connected to SMA connectors ISET
and VSET.
TEST: connectors the ISET and VSET inputs to the 2.5 V reference.
RUN: configures the ISET and VSET outputs as integrators.
TEST: configures the ISET and VSET outputs as followers.
RUN_TEST2 Configures the ISET and VSET
outputs to test the integrators.
RUN
1 N/A means not applicable.
Table 9. AD8450-EVALZ SMA Connector Functions
Connector
Function
ISVP
ISVN
BVP
BVN
Input from the battery current sensor to the PGIA positive input.
Input from the battery current sensor to the PGIA negative input.
Input from the battery positive voltage terminal to the PGDA positive input.
Input from the battery negative voltage terminal to the PGDA negative input.
Input to the AD8450 ISET pin.
ISET
VSET
Input to the AD8450 VSET pin.
VCTRL
CS_BUS
AD8450 control voltage output to the PWM or analog power supply COMP input.
AD8450 current sharing input/output bus.
PGDA and Offset
PGIA in an Application
Simple Test
The differential inputs of the PGIA assume the use of a high-
side current shunt in series with the battery. To connect the
evaluation board in an application, simply connect the ISVP
and ISVN to the positive and negative shunt connections. Be
sure that both inputs are floating (ungrounded). The ISVP and
ISVN inputs tolerate the full AVCC common-mode voltage
applied to the board.
The PGDA has four gain options (0.8, 0.4, 0.27, and 0.2) selected
with the four-position BVGN slide switch. Set the BV_REF
switch to the NORM position. Test the PGDA amplifier in the
same manner as PGIA. Apply 1 V dc between TPBVP and TPBVN.
Measure the output voltages at TPBVMEA. The output voltages
are 0.8 V, 0.4 V, 0.27 V, and 0.2 V, respectively, at the four BVGN
switch positions.
Simple Offset Test
PGDA in an Application
Short the PGIA inputs from TPISVP to TPISVN to one of the
black ground loops. The ISMEA output is 0 V the residual
offset voltage multiplied by the gain. Move the IS_REF switch
to the 20 mV position to increase ISMEA by 20 mV.
For connection to an application, simply connect the input
terminal across the battery. It is good practice to take advantage of
the differential input to achieve the most accurate measurements.
Offset in an Application
PGDA Offset
In certain instances, the system operates with various ground
voltage levels. Although the PGIA is differential and floating, it
may be advantageous to refer the PGIA to a ground at or near
the battery load.
The BV_REF offset works just the same as the IS_REF except
that the fixed offset is 5 mV. Simply use the BV_REF switch to
select the option. For an external offset reference, move the
BV_REF switch to EXT and connect a wire from the TPBREFL
and TPBREFH test loops to the desired reference points.
Rev. B | Page 35 of 41
AD8450
Data Sheet
Overload Comparators
CC and CV Integrator Tests
The AD8450 features identical fault sensing comparators for
overcurrent (OCPS pin) and overvoltage (OVPS pin) to help
protect against battery damage. The reference pins, OVPR and
OCPR, are hardwired via 0 Ω resistors, R27 and R28, to the 2.5 V
reference. The outputs of the comparators are connected together
internally, and are active low in the event of an overdrive of
either parameter.
The RUN_TEST1 and RUN_TEST2 switches provide all the circuit
switching required to test the integrator. Set RUN_TEST1 to the
TEST position and apply 2.5 V to the ISET and VSET inputs;
then read 2.5 V at the VCTRL output. Set RUN_TEST2 to
TEST_CC, then TEST_CV, and the VCTRL output voltage still
measures 2.5 V.
Uncommitted Op Amp
For reference, the sense pins are set at 20% greater than the
reference. For other sense voltage ratios, simply calculate a new
value for the resistor divider. The 2.49 kΩ resistor was selected
as an easy equivalent to the 2.5 V reference, the 499 Ω resistors
to the ISMEA and BVMEA as 20% greater. These values were
selected for an experimental 1 A charge/discharge system built
in the lab. Other ratios and values are user selected.
The uncommitted op amp is configured as a follower (R24 is
installed between the OAVN pin and the OAVO pin). The input
pin, OAVP, is jumper connected to ground via OAVP. To test
the uncommitted op amp, simply connect a jumper from TP2.5V
and Pin 1 of Jumper OAV P. T h e output TPOAVO reads 2.5 V.
USING THE AD8450
Except for the power converter and accessories, such as filters
and current sensing, the AD8450-EVALZ includes all of the
signal path elements necessary to implement a battery charging/
forming system (see Figure 59).
As a basic test or experiment, simply apply enough voltage at
the PGIA or PGDA inputs to exceed 3 V at ISMEA or BVMEA.
The FAULT output pin switches from 5 V to 0 V if either input
exceeds the sense trigger level.
The AD8450 is usable with either linear or switch mode power
converters. Switching converters typically generate higher noise
levels than linear; however, switching converters are the most
popular by far because of significantly higher efficiency and
lower cost. Regardless of the power converter architecture used, the
PID loop must be configured to reflect the phase shift and gain of
the power stage. Circuit simulation is helpful with this task.
VSET Buffer
The VSET buffer is a unity gain, voltage follower pin accessible
for testing. Apply a voltage up to 5 V at the VSET input, and
measure the output at TPVSETBF.
CV and CC Loop Filter Amplifiers
The constant voltage (CV) and constant current (CC) integrators
are identical circuits and are the two active integrator elements of
the master loop compensation and switching block (see Figure 49).
Except for their external connections, the two circuits are identical
and are tested in the same way, sequentially. The integrator
outputs are analog OR’ed together, creating the VCTRL output to
the input of an external pulse-width modulation controller.
On the right hand side of Figure 62 are four universal loop
compensation circuits. All or part of the circuits are usable
for installing fixed components when the AD8450-EVALZ is
connected to a battery system for design verification. There are
two feedback amplifiers, but four potentially distinctive separate
configurations. The types and values of passive components
vary according to the power converter and its characteristics.
As shown in Figure 49, the integrator op amp inputs are called
IVE0, IVE1, VVE0, VVE1, and VVP0. The first two letters (IV
or VV) signify the constant current or constant voltage integrator.
The third letter identifies the noninverting input (P) or the
inverting input (E for error input). The final digit (0 or 1)
indicates the state of the mode circuit (0 for discharge and 1
for charge). Because the integrators are connected in parallel,
a static test of either integrator requires disabling the other by
forcing the output to the supply rail, reverse biasing the
transistor/diode gate.
To use the board for setting up a charging system, replace the
10 kΩ resistors in the feedback (there are no capacitors installed)
and connect the measured feedback voltages by installing
jumpers RUN1 through RUN5. Remove jumpers TST1 through
TST5 and install capacitors associated with the integrator.
Rev. B | Page 36 of 41
Data Sheet
AD8450
SCHEMATIC AND ARTWORK
E E V A
T N I V
C N
V P O S
D E O M
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
4 0
3 9
3 8
3 7
3 6
3 5
V P O S
D E O M
C N
C N
C C A V
E A V M B
1
0
V I E
V I E
E A V M B
V 5 −
V E A E
C N
S 3 N B V
3 N B V
2 N B V
1 N B V
0 N B V
S L F R E B V
L F R E B V
N D A G
S 3 N B V
T E S I
3 4 3 N B V
O V A O
N V A O
C C V A
E A M S I
3 3
3 2
2 N B V
1 N B V
O V A O
2 5
V
3 1 0 N B V
3 0
S L F B R E
E E V A
F E R V
H F E R S I
D N G A
L F E R S I
L F S E R S I
P V A O
X A M I
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
L F B R E
L F B P R T E
H F R E B V
E F V R
H F B R E
E F V R
0 P B V
1 P B V
2 P B V
S L E F S I R
3 P B V
0 P B V
1 P B V
2 P B V
3 P B V
S 3 P B V
S C H
Figure 62. Schematic of the AD8450 Evaluation Board
Rev. B | Page 37 of 41
AD8450
Data Sheet
Figure 63. Top Silkscreen of the AD8450-EVALZ
Figure 64. AD8450-EVALZ Primary Side Copper
Rev. B | Page 38 of 41
Data Sheet
AD8450
Figure 65. AD8450-EVALZ Secondary Side Copper
Figure 66. AD8450-EVALZ Power Plane
Rev. B | Page 39 of 41
AD8450
Data Sheet
Figure 67. AD8450-EVALZ Ground Plane
Rev. B | Page 40 of 41
Data Sheet
AD8450
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
0.75
0.60
0.45
1.60
MAX
61
80
60
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.10
COPLANARITY
20
41
0.15
0.05
40
21
SEATING
PLANE
VIEW A
0.65
0.38
0.32
0.22
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 68. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
AD8450ASTZ
AD8450ASTZ-RL
AD8450-EVALZ
80-Lead Low Profile Quad Flat Package [LQFP]
80-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
ST-80-2
ST-80-2
1 Z = RoHS Compliant Part.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11966-0-8/15(B)
Rev. B | Page 41 of 41
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