AD8451-EVALZ [ADI]
Low Cost, Precision Analog Front End and Controller for Battery Test/Formation Systems;
| 型号： | AD8451-EVALZ |
| 厂家： | 
ADI |
| 描述： | Low Cost, Precision Analog Front End and Controller for Battery Test/Formation Systems 电池 |
| 文件： | 总33页 (文件大小：949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, Precision Analog Front End and
Controller for Battery Test/Formation Systems
Data Sheet
AD8451
FEATURES
GENERAL DESCRIPTION
Integrated constant current and voltage modes with
automatic switchover
Charge and discharge modes
Precision voltage and current measurement
Integrated precision control feedback blocks
Precision interface to PWM or linear power converters
Fixed gain settings
Current sense gain: 26 V/V (typ)
Voltage sense gain: 0.8 V/V (typ)
Excellent ac and dc performance
Maximum offset voltage drift: 0.9 µV/°C
Maximum gain drift: 3 ppm/°C
The AD8451 is a precision analog front end and controller for
testing and monitoring battery cells. A precision fixed gain
instrumentation amplifier (IA) measures the battery charge/
discharge current, and a fixed gain difference amplifier (DA)
measures the battery voltage (see Figure 1). Internal laser
trimmed resistor networks set the gains for the IA and the DA,
optimizing the performance of the AD8451 over the rated
temperature range. The IA gain is 26 V/V and the DA gain is
0.8 V/V.
Voltages at the ISET and VSET inputs set the desired constant
current (CC) and constant voltage (CV) values. CC to CV
switching is automatic and transparent to the system.
Low current sense amplifier input voltage noise: 9 nV/√Hz typ
Current sense CMRR: 108 dB min
TTL compliant logic
A TTL logic level input, MODE, selects the charge or discharge
mode (high for charge, and low for discharge). An analog output,
VCTRL, interfaces directly with the Analog Devices, Inc.,
ADP1972 pulse-width modulation (PWM) controller.
APPLICATIONS
The AD8451 simplifies designs by providing excellent accuracy,
performance over temperature, flexibility with functionality,
and overall reliability in a space-saving package. The AD8451 is
available in an 80-lead, 14 mm × 14 mm × 1.40 mm LQFP and
is rated for an operating temperature of −40°C to +85°C.
Battery cell formation and testing
Battery module testing
FUNCTIONAL BLOCK DIAGRAM
ISREFH/
ISREFL ISMEA ISET IVE0/IVE1
VINT
AD8451
ISVP
CONSTANT
VCLP
CURRENT LOOP
MUX
FILTER
26
×1
VCTRL
VCLN
ISVN
MODE
BVP
CURRENT
SENSE IA
(CHARGE/
DISCHARGE)
SWITCHING
VOLTAGE
SENSE DA
VOLTAGE
REFERENCE
VREF
0.8
CONSTANT
VOLTAGE LOOP
FILTER
BVN
BVREFH/
BVREFL
BVMEA VSET VVE0/
VVE1
VVP0
VSETBF VINT
Figure 1.
Rev. 0
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Tel: 781.329.4700
Technical Support
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www.analog.com
AD8451* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• AD8451 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD8451 Evaluation Board
DOCUMENTATION
Application Notes
DISCUSSIONS
View all AD8451 EngineerZone Discussions.
• AN-1319: Compensator Design for a Battery Charge/
Discharge Unit Using the AD8450 or the AD8451
SAMPLE AND BUY
Visit the product page to see pricing options.
Data Sheet
• AD8451: Low Cost, Precision Analog Front End and
Controller for Battery Test/Formation Systems Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
User Guides
• UG-845: AD8450/ADP1972 Battery Testing and Formation
Evaluation Board
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
• AD8451 SPICE Macro Model
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AD8451
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
MODE Pin, Charge and Discharge Control ........................... 21
Applications Information .............................................................. 22
Functional Description.............................................................. 22
Power Supply Connections ....................................................... 23
Current Sense IA Connections................................................. 23
Voltage Sense DA Connections................................................ 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
IA Characteristics ......................................................................... 9
DA Characteristics ..................................................................... 11
CC and CV Loop Filter Amplifiers, and VSET Buffer .......... 13
VINT Buffer ................................................................................ 15
Reference Characteristics .......................................................... 16
Theory of Operation ...................................................................... 17
Overview...................................................................................... 17
Instrumentation Amplifier (IA) ............................................... 18
Difference Amplifier (DA)........................................................ 19
CC and CV Loop Filter Amplifiers.......................................... 19
Battery Current and Voltage Control Inputs (ISET and VSET)
....................................................................................................... 23
Loop Filter Amplifiers ............................................................... 24
Connecting to a PWM Controller (VCTRL Pin) ...................... 24
Step-by-Step Design Example................................................... 24
Evaluation Board ............................................................................ 26
Introduction................................................................................ 26
Features and Tests....................................................................... 26
Evaluating the AD8451.............................................................. 27
Schematic and Artwork............................................................. 28
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
3/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
AD8451
SPECIFICATIONS
AVCC = +15 V, AVEE = −15 V; DVCC = +5 V; TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ Max
Unit
CURRENT SENSE INSTRUMENTATION AMPLIFIER
Internal Fixed Gain
Gain Error
Gain Drift
Gain Nonlinearity
Offset Voltage (RTI)
26
0.1
3
V/V
%
ppm/°C
ppm
µV
VISMEA = 10 V
TA = TMIN to TMAX
VISMEA = 10 V, RL = 2 kΩ
ISREFH and ISREFL pins grounded
TA = TMIN to TMAX
3
−110
+110
0.9
Offset Voltage Drift
Input Bias Current
µV/°C
nA
15
30
Temperature Coefficient
Input Offset Current
TA = TMIN to TMAX
150
2
pA/°C
nA
Temperature Coefficient
Input Common-Mode Voltage Range
Over Temperature
Overvoltage Input Range
Differential Input Impedance
Input Common-Mode Impedance
Output Voltage Swing
Over Temperature
Capacitive Load Drive
Short-Circuit Current
Reference Input Voltage Range
Reference Input Bias Current
Output Voltage Level Shift
Maximum
TA = TMIN to TMAX
VISVP − VISVN = 0 V
TA = TMIN to TMAX
10
pA/°C
V
V
AVEE + 2.3
AVEE + 2.6
AVCC − 55
AVCC − 2.4
AVCC − 2.6
AVEE + 55
V
150
150
GΩ
GΩ
V
V
pF
mA
V
µA
AVEE + 1.5
AVEE + 1.7
AVCC − 1.2
AVCC − 1.4
1000
TA = TMIN to TMAX
40
5
ISREFH and ISREFL pins tied together
VISVP = VISVN = 0 V
ISREFL pin grounded
ISREFH pin connected to VREF pin
VISMEA/VISREFH
ΔVCM = 20 V
TA = TMIN to TMAX
ΔVS = 20 V
f = 1 kHz
AVEE
AVCC
17
6.8
108
20
8
23
9.2
mV
mV/V
dB
µV/V/°C
dB
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
Scale Factor
Common-Mode Rejection Ratio (CMRR)
Temperature Coefficient
Power Supply Rejection Ratio (PSRR)
Voltage Noise
Voltage Noise, Peak to Peak
Current Noise
Current Noise, Peak to Peak
Small Signal −3 dB Bandwidth
Slew Rate
0.01
108
122
9
0.2
80
5
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
1.5
5
ΔVISMEA = 10 V
V/µs
VOLTAGE SENSE DIFFERENCE AMPLIFER
Internal Fixed Gains
Gain Error
Gain Drift
Gain Nonlinearity
Offset Voltage (RTO)
0.8
V/V
%
ppm/°C
ppm
µV
µV/°C
V
V
kΩ
kΩ
V
V
pF
VIN = 10 V
TA = TMIN to TMAX
0.1
3
3
500
4
+16
+27
VBVMEA = 10 V, RL = 2 kΩ
BVREFH and BVREFL pins grounded
TA = TMIN to TMAX
VBVN = 0 V, VBVREFL = 0 V
VBVMEA = 0 V
Offset Voltage Drift
Differential Input Voltage Range
Input Common-Mode Voltage Range
Differential Input Impedance
Input Common-Mode Impedance
Output Voltage Swing
Over Temperature
−16
−27
200
90
AVEE + 1.5
AVEE + 1.7
AVCC − 1.5
AVCC − 1.7
1000
TA = TMIN to TMAX
Capacitive Load Drive
Short-Circuit Current
30
mA
Rev. 0 | Page 3 of 32
AD8451
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ Max
Unit
Reference Input Voltage Range
Output Voltage Level Shift
Maximum
Scale Factor
CMRR
BVREFH and BVREFL pins tied together AVEE
BVREFL pin grounded
AVCC
V
BVREFH pin connected to VREF pin
VBVMEA/VBVREFH
4.5
1.8
80
5
2
5.5
2.2
mV
mV/V
dB
ΔVCM = 10 V, RTO
Temperature Coefficient
PSRR
TA = TMIN to TMAX
ΔVS = 20 V, RTO
0.05
µV/V/°C
dB
100
Output Voltage Noise
Voltage Noise, Peak to Peak
Small Signal −3 dB Bandwidth
Slew Rate
f = 1 kHz, RTI
f = 0.1 Hz to 10 Hz, RTI
105
2
1
nV/√Hz
µV p-p
MHz
0.8
V/µs
CONSTANT CURRENT AND CONSTANT VOLTAGE
LOOP FILTER AMPLIFIERS
Offset Voltage
Offset Voltage Drift
Input Bias Current
150
0.6
+5
µV
µV/°C
nA
TA = TMIN to TMAX
TA = TMIN to TMAX
−5
−5
Over Temperature
+5
nA
Input Common-Mode Voltage Range
Output Voltage Swing
Over Temperature
AVEE + 1.5
AVEE + 1.5
AVEE + 1.7
AVCC − 1.8
AVCC − 1
AVCC − 1
V
V
V
VVCLN = AVEE + 1 V, VVCLP = AVCC − 1 V
TA = TMIN to TMAX
Closed-Loop Output Impedance
Capacitive Load Drive
Source Short-Circuit Current
Sink Short-Circuit Current
Open-Loop Gain
0.01
Ω
pF
mA
mA
dB
1000
1
40
140
CMRR
PSRR
ΔVCM = 10 V
ΔVS = 20 V
100
100
dB
dB
Voltage Noise
Voltage Noise, Peak to Peak
Current Noise
Current Noise, Peak to Peak
Small Signal Gain Bandwidth Product
Slew Rate
CC to CV Transition Time
VINT AND CONSTANT VOLTAGE BUFFER
Nominal Gain
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
10
0.3
80
5
3
1
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/µs
µs
f = 0.1 Hz to 10 Hz
ΔVVINT = 10 V
1.5
1
V/V
µV
Offset Voltage
150
Offset Voltage Drift
Input Bias Current
Over Temperature
TA = TMIN to TMAX
CV buffer only
TA = TMIN to TMAX
0.6
+5
+5
µV/°C
nA
nA
−5
−5
Input Voltage Range
Output Voltage Swing
Current Sharing and Constant Voltage Buffers
Over Temperature
VINT Buffer
Over Temperature
Output Clamps Voltage Range
VCLP Pin
VCLN Pin
AVEE + 1.5
AVCC − 1.8
V
AVEE + 1.5
AVEE + 1.7
VVCLN − 0.6
VVCLN − 0.6
AVCC − 1.5
AVCC − 1.5
VVCLP + 0.6
VVCLP + 0.6
V
V
V
V
TA = TMIN to TMAX
TA = TMIN to TMAX
VINT buffer only
VVCLN
AVEE + 1
AVCC − 1
VVCLP
V
V
Closed-Loop Output Impedance
Capacitive Load Drive
Short-Circuit Current
PSRR
1
Ω
1000
100
pF
mA
dB
40
ΔVS = 20 V
Rev. 0 | Page 4 of 32
Data Sheet
AD8451
Parameter
Test Conditions/Comments
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz, CV buffer only
f = 0.1 Hz to 10 Hz
Min
Typ Max
Unit
Voltage Noise
Voltage Noise, Peak to Peak
Current Noise
Current Noise, Peak to Peak
Small Signal −3 dB Bandwidth
Slew Rate
10
0.3
80
5
3
1
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
ΔVOUT = 10 V
V/µs
VOLTAGE REFERENCE
Nominal Output Voltage
Output Voltage Error
Temperature Drift
Line Regulation
Load Regulation
Output Current, Sourcing
Voltage Noise
Voltage Noise, Peak to Peak
DIGITAL INTERFACE, MODE INPUT
Input Voltage High, VIH
Input Voltage Low, VIL
Mode Switching Time
POWER SUPPLY
With respect to AGND
2.5
V
%
1
TA = TMIN to TMAX
ΔVS = 10 V
ΔIVREF = 1 mA (source only)
10
40
400
10
100
5
ppm/°C
ppm/V
ppm/mA
mA
nV/√Hz
µV p-p
f = 1 kHz
f = 0.1 Hz to 10 Hz
MODE pin (Pin 39)
With respect to DGND
With respect to DGND
2.0
DGND
DVCC
0.8
V
V
ns
500
Operating Voltage Range
AVCC
AVEE
Analog Supply Range
DVCC
5
−31
5
36
0
36
5
V
V
V
V
AVCC − AVEE
3
Quiescent Current
AVCC
AVEE
7
6.5
40
10
10
70
mA
mA
µA
DVCC
TEMPERATURE RANGE
For Specified Performance
Operational
−40
−55
+85
+125
°C
°C
Rev. 0 | Page 5 of 32
AD8451
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
The θJA value assumes a 4-layer JEDEC standard board with
zero airflow.
Parameter
Rating
Analog Supply Voltage (AVCC − AVEE)
36 V
Digital Supply Voltage (DVCC − DGND) 36 V
Table 3. Thermal Resistance
Package Type
Maximum Voltage at Any Input Pin
Minimum Voltage at Any Input Pin
Operating Temperature Range
Storage Temperature Range
AVCC
AVEE
−40°C to +85°C
−65°C to +150°C
θJA
Unit
80-Lead LQFP
54.7
°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 6 of 32
Data Sheet
AD8451
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
ISVP
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
PIN 1
INDENTFIER
VCLP
VCTRL
VCLN
AVCC
VINT
RGP
NC
NC
NC
NC
NC
NC
NC
NC
VVE1
53 VVE0
52 NC
51
50
49
48
47
46
NC 10
AD8451
VVP0
VSETBF
VSET
NC
TOP VIEW
11
12
NC
NC
NC 13
NC
14
DVCC
NC
NC 15
NC 16
45 DGND
44 NC
NC 17
NC 18
43 NC
42 VREF
41 NC
RGN 19
ISVN 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Input/Output1 Description
1, 20
ISVP, ISVN
RGP, RGN
NC
Input
Current Sense Instrumentation Amplifier Positive (Noninverting) and Negative
(Inverting) Inputs. Connect these pins across the current sense shunt resistor.
Negative Input of the Preamplifiers of the Current Sense Instrumentation
Amplifier.
2, 19
N/A
3 to 18, 21, 23, 25, 31, 33,
34, 40, 41, 43, 44, 46, 48,
52, 55, 63, 66, 69, 78 to 80
N/A
No Connect. Do not connect to this pin.
22, 35
24, 32
26, 42, 73
27
BVPS, BVNS Input
Kelvin Sense Pins for the BVP and BVN Voltage Sense Difference Amplifier Inputs.
Voltage Sense Difference Amplifier Inputs.
Voltage Reference Output Pins. VREF = 2.5 V.
Reference Input for the Voltage Sense Difference Amplifier. To level shift the
voltage sense difference amplifier output by approximately 5 mV, connect this
pin to the VREF pin. Otherwise, connect this pin to the BVREFL pin.
BVP, BVN
VREF
Input
Output
Input
BVREFH
28, 75
29
AGND
BVREFL
N/A
Input
Analog Ground Pins.
Reference Input for the Voltage Sense Difference Amplifier. The default connection
is to ground.
30
BVREFLS
Input
Kelvin Sense Pin for the BVREFL Pin.
Rev. 0 | Page 7 of 32
AD8451
Data Sheet
Pin No.
36, 61, 72
37
38, 57, 70
39
Mnemonic Input/Output1 Description
AVEE
BVMEA
AVCC
N/A
Output
N/A
Analog Negative Supply Pins. The default voltage is −15 V.
Voltage Sense Difference Amplifier Output.
Analog Positive Supply Pins. The default voltage is 15 V.
MODE
Input
TTL Compliant Logic Input Selects Charge or Discharge Mode. Low =
discharge, high = charge.
45
47
49
50
51
53
54
56, 62
58
DGND
DVCC
VSET
VSETBF
VVP0
VVE0
VVE1
VINT
N/A
N/A
Digital Ground Pin.
Digital Supply. The default voltage is 5 V.
Target Voltage for the Voltage Sense Control Loop.
Buffered Voltage VSET.
Noninverting Input of the Voltage Sense Integrator for Discharge Mode.
Inverting Input Voltage for the Voltage Sense Integrator for Discharge Mode.
Inverting Input of the Voltage Sense Integrator for Charge Mode.
Minimum Output of the Voltage Sense and Current Sense Integrator Amplifiers.
Low Clamp Voltage for VCTRL.
Input
Output
Input
Input
Input
Output
Input
Output
VCLN
VCTRL
59
Controller Output Voltage. Connect this pin to the input of the PWM controller
(for example, the COMP pin of the ADP1972).
60
64
65
67
68
71
74
VCLP
IVE1
IVE0
Input
Input
Input
Input
Output
Output
Input
High Clamp Voltage for VCTRL.
Inverting Input of the Current Sense Integrator for Charge Mode.
Inverting Input of the Current Sense Integrator for Discharge Mode.
Target Voltage for the Current Sense Control Loop.
Buffered Voltage ISREFL.
ISET
ISREFB
ISMEA
ISREFH
Current Sense Instrumentation Amplifier Output.
Reference Input for the Current Sense Amplifier. To level shift the current sense
instrumentation amplifier output by approximately 20 mV, connect this pin to
the VREF pin. Otherwise, connect this pin to the ISREFL pin.
76
ISREFL
Input
Input
Reference Input for the Current Sense Amplifier. The default connection is to
ground.
Kelvin Sense Pin for the ISREFL Pin.
77
ISREFLS
1 N/A means not applicable.
Rev. 0 | Page 8 of 32
Data Sheet
AD8451
TYPICAL PERFORMANCE CHARACTERISTICS
AVCC = +15 V, AVEE = −15 V, TA = 25°C, and RL = ∞, unless otherwise noted.
IA CHARACTERISTICS
30
20
15
25
20
15
10
5
10
5
0
–5
–10
–15
–20
0
−5
AVCC = +15V
AVEE = –15V
AVCC = +25V
AVEE = −5V
−10
−10
–20
–15
–10
–5
0
5
10
15
20
−5
0
10
15
20
30
5
25
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 3. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +25 V and AVEE = −5 V
Figure 6. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +15 V and AVEE = −15 V
15
10
5
15
AVCC = +15V
AVEE = –15V
10
5
0
0
–5
–5
–10
–15
–10
AVCC = +25V
AVEE = –5V
–15
–35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40 45
–45–40–35–30–25–20–15–10 –5
0
5 10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 4. Input Overvoltage Performance
for AVCC = +25 V and AVEE = −5 V
Figure 7. Input Overvoltage Performance
for AVCC = +15 V and AVEE = −15 V
17.0
16.8
16.6
16.4
16.2
16.0
15.8
15.6
15.4
15.2
15.0
20
19
18
17
16
15
14
13
12
AVCC = +15V
AVEE = –15V
+I
–I
B
AVCC = +25V
AVEE = –5V
B
–15
–10
–5
0
5
10
15
20
25
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
INPUT COMMON-MODE VOLTAGE (V)
Figure 5. Input Bias Current vs. Input Common-Mode Voltage
Figure 8. Input Bias Current vs. Temperature
Rev. 0 | Page 9 of 32
AD8451
Data Sheet
20
160
150
140
130
120
110
100
90
0
–20
–40
–60
–80
–100
80
70
60
50
0.1
1
10
100
1k
10k
100k
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 9. Gain Error vs. Temperature
Figure 12. CMRR vs. Frequency
0.3
160
140
120
100
80
AVCC = +25V
AVEE = –5V
0.2
0.1
AVCC
AVEE
0
60
–0.1
–0.2
–0.3
40
20
0
1
10
100
1k
10k
100k
1M
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 13. PSRR vs. Frequency
Figure 10. Normalized CMRR vs. Temperature
50
40
100
30
20
RTI
10
10
0
−10
−20
AVCC = +15V
AVEE = −15V
1
0.1
1
10
100
1k
10k
100k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Gain vs. Frequency
Figure 14. Spectral Density Voltage Noise, RTI vs. Frequency
Rev. 0 | Page 10 of 32
Data Sheet
AD8451
DA CHARACTERISTICS
60
50
40
50
40
30
30
20
20
10
10
0
0
–10
–20
–30
–40
–50
–10
–20
–30
–40
AVCC = +15V
AVCC = +25V
AVEE = −15V
AVEE = −5V
–10
–5
0
5
10
15
20
25
30
–20
–15
–10
–5
0
5
10
15
20
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 15. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +25 V and AVEE = −5 V
Figure 18. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +15 V and AVEE = −15 V
0
50
–10
0
–20
–30
–40
–50
–50
–100
–150
–200
VALID FOR ALL RATED
SUPPLY VOLTAGES
100
1k
10k
100k
1M
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. Gain vs. Frequency
Figure 19. Gain Error vs. Temperature
0
–20
3
2
VALID FOR ALL RATED
SUPPLY VOLTAGES
–40
1
–60
0
–80
–1
–2
–3
–100
–120
100
1k
10k
100k
1M
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 17. CMRR vs. Frequency
Figure 20. Normalized CMRR vs. Temperature
Rev. 0 | Page 11 of 32
AD8451
Data Sheet
0
1k
100
10
–20
AVEE
–40
–60
RTI
–80
AVCC
–100
–120
VALID FOR ALL RATED
SUPPLY VOLTAGES
–140
10
100
1k
FREQUENCY (Hz)
10k
100k
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
Figure 21. PSRR vs. Frequency
Figure 22. Spectral Density Voltage Noise, RTI vs. Frequency
Rev. 0 | Page 12 of 32
Data Sheet
AD8451
CC AND CV LOOP FILTER AMPLIFIERS, AND VSET BUFFER
500
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CONSTANT CURRENT LOOP AND
CONSTANT VOLTAGE LOOP AMPLIFIERS
400
300
AVCC = +15V
AVEE = –15V
AVCC = +25V
AVEE = –5V
200
100
AVCC = +25V
AVEE = –5V
0
AVCC = +15V
AVEE = –15V
–100
–200
–300
–400
–500
–15
–10
–5
0
5
10
15
20
25
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
INPUT COMMON-MODE VOLTAGE (V)
Figure 23. Input Offset Voltage vs. Input Common-Mode Voltage
for Two Supply Voltage Combinations
Figure 26. Output Source Current vs. Temperature
for Two Supply Voltage Combinations
100
90
120
100
80
–45.0
–67.5
80
PHASE
GAIN
–90.0
AVCC = +25V
AVEE = –5V
70
60
50
40
30
20
10
0
60
–112.5
–135.0
–157.5
–180.0
–202.5
–225.0
40
AVCC = +15V
AVEE = –15V
20
0
–20
–40
–15
–10
–5
0
5
10
15
20
25
10
100
1k
10k
100k
1M
10M
INPUT COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 24. Input Bias Current vs. Input Common-Mode Voltage
for Two Supply Voltage Combinations
Figure 27. Open-Loop Gain and Phase vs. Frequency
100
80
60
40
20
0
160
140
120
100
80
60
40
CONSTANT CURRENT LOOP
AND
CONSTANT VOLTAGE
LOOP FILTER
–20
20
–I
+I
B
B
AMPLIFIERS
–40
–40 –30 –20 –10
0
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 25. Input Bias Current vs. Temperature
Figure 28. CMRR vs. Frequency
Rev. 0 | Page 13 of 32
AD8451
Data Sheet
1.5
1.0
140
120
100
80
AVCC = +15V
AVEE = –15V
+PSRR
0.5
TRANSITION
0
60
–0.5
–1.0
–1.5
–PSRR
40
20
ISET
VCTRL
0
10
100
1k
10k
100k
1M
–15 –10
–5
0
5
10
15
20
25
30
35
FREQUENCY (Hz)
TIME (µs)
Figure 29. PSRR vs. Frequency
Figure 31. CC to CV Transition
1k
100
10
1
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 30. Range of Spectral Density Voltage Noise vs. Frequency
for the Op Amps and Buffers
Rev. 0 | Page 14 of 32
Data Sheet
AD8451
VINT BUFFER
0.5
6
5
C
R
= 100pF
= 2kΩ
VCTRL OUTPUT WITH RESPECT TO VCLP
L
L
0.4
0.3
4
0.2
0.1
3
VCLP AND VCLN REFERENCE
0
VALID FOR ALL RATED
SUPPLY VOLTAGES
2
–0.1
–0.2
–0.3
–0.4
–0.5
1
VCTRL OUTPUT WITH RESPECT TO VCLN
0
–1
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
5
10
15
20
25
30
35
40
TIME (µs)
Figure 32. Output Voltage Swing with Respect to VCLP and VCLN
vs. Temperature
Figure 35. Large Signal Transient Response, RL = 2 kΩ, CL = 100 pF
15
0.20
C
C
C
C
C
= 10pF
L
L
L
L
L
= 100pF
= 510pF
= 680pF
= 1000pF
0.15
0.10
0.05
0
VCLP
10
5
TEMP = –40°C
TEMP = +25°C
TEMP = +85°C
0
–5
–0.05
–0.10
–0.15
–0.20
–10
VCLN
–15
100
1k
10k
LOAD RESISTANCE (Ω)
100k
1M
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
Figure 36. Small Signal Transient Response vs. Capacitive Load
Figure 33. Output Voltage Swing vs. Load Resistance at Three Temperatures
100
6
5
VCLP
4
10
3
2
TEMP = –40°C
TEMP = 0°C
TEMP = +25°C
TEMP = +85°C
V
= +6V/–1V
IN
1
1
VCLN
0
0.1
–1
10
100
1k
10k
100k
1M
10
15
20
25
30
35
40
FREQUENCY (Hz)
OUTPUT CURRENT (mA)
Figure 34. Clamped Output Voltage vs. Output Current
at Four Temperatures
Figure 37. Output Impedance vs. Frequency
Rev. 0 | Page 15 of 32
AD8451
Data Sheet
REFERENCE CHARACTERISTICS
2.51
1200
1100
1000
900
T
T
T
T
T
= +85°C
= +25°C
= 0°C
= –20°C
= –40°C
AVCC = +25V
AVEE = –5V
A
A
A
A
A
2.50
2.49
2.48
2.47
800
700
AVCC = +25V
AVEE = –5V
2.46
600
0
1
2
3
4
5
6
7
8
9
10
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
OUTPUT CURRENT—SOURCING (mA)
Figure 38. Output Voltage vs. Output Current (Sourcing) over Temperature
Figure 40. Source and Sink Load Regulation vs. Temperature
2.9
1k
AVCC = +25V
AVEE = –5V
2.8
2.7
2.6
100
T
T
T
T
T
= +85°C
= +25°C
= 0°C
= –20°C
= –40°C
A
A
A
A
A
2.5
2.4
10
0.1
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
10
100
1k
10k
100k
OUTPUT CURRENT—SINKING (mA)
FREQUENCY (Hz)
Figure 41. Spectral Density Voltage Noise vs. Frequency
Figure 39. Output Voltage vs. Output Current (Sinking) over Temperature
Rev. 0 | Page 16 of 32
Data Sheet
AD8451
THEORY OF OPERATION
The AD8451 provides two control loops—CC loop and a CV
OVERVIEW
loop—that transition automatically after the battery reaches the
user defined target voltage. These loops are implemented via two
precision specialty amplifiers with external feedback networks
that set the transfer function of the CC and CV loops.
Moreover, in the AD8451, these loops reconfigure themselves to
charge or discharge the battery by toggling the MODE pin.
To form and test a battery, the battery must undergo charge and
discharge cycles. During these cycles, the battery terminal current
and voltage must be precisely controlled to prevent battery failure
or a reduction in the capacity of the battery. Therefore, battery
formation and test systems require a high precision analog front
end to monitor the battery current and terminal voltage. The
analog front end of the AD8451 includes a precision current
sense fixed gain instrumentation amplifier (IA) to measure the
battery current and a precision voltage sense fixed gain difference
amplifier (DA) to measure the battery voltage.
Figure 42 is a block diagram of the AD8451 that illustrates
the distinct sections of the AD8451, including the IA and DA
measurement blocks, and the loop filter amplifiers. Figure 43 is a
block diagram of a battery formation and test system.
Battery formation and test systems charge and discharge batteries
using a constant current/constant voltage (CC/CV) algorithm. In
other words, the system first forces a set constant current into
or out of the battery until the battery voltage reaches a target
value. At this point, a set constant voltage is forced across the
battery terminals.
75
72
70
66
63
61
80
79
78
77
76
74
73
71
69
68
67
65
64
62
1
2.5V
60
59
58
VINT
BUFFER
ISVP
RGP
NC
VCLP
VCTRL
VCLN
AVCC
VINT
NC
VREF
ISREFL
BUFFER
2
MODE
+/–
1×
1×
–
+
–
3
+
AVEE
CC LOOP
FILTER
AMPLIFIER
4
57
56
NC
1.1mA
10kΩ
5
NC
AVCC
6
55
54
NC
CV LOOP
FILTER
7
VVE1
VVE0
NC
AMPLIFIER
NC
NC
+
–
53
8
AVEE
BATTERY
CURRENT
9
52
51
NC
NC
NC
SENSING IA
VSET
BUFFER
10kΩ
10
11
12
13
14
15
16
17
18
19
20
VVP0
VSETBF
VSET
NC
+
1667Ω
10kΩ
50
49
48
–
1×
CONSTANT
CURRENT AND
VOLTAGE LOOP
FILTER AMPLIFIERS
20kΩ
NC
NC
47
46
NC
DVCC
NC
AD8451
NC
10kΩ
45
44
NC
DGND
NC
+
–
BATTERY
VOLTAGE
SENSING
DA
NC
80kΩ
43
42
–
+
NC
NC
+/–
100Ω
RGN
ISVN
VREF
NC
MODE
41
40
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Figure 42. Detailed Block Diagram
Rev. 0 | Page 17 of 32
AD8451
Data Sheet
SET
CONSTANT
BATTERY
VOLTAGE LOOP
FILTER AMPLIFIER
VINT
CURRENT
ISET
BUFFER
+
–
V1
VCTRL
POWER CONVERTER
1×
CONSTANT
CURRENT LOOP
FILTER AMPLIFIER
SWITCHED OR LINEAR
SET
+
–
BATTERY
VOLTAGE
VSET
1×
MODE
SWITCHES AVEE
(3)
V2
C
D C
D C
D
CV
BUFFER
C = CHARGE
BATTERY
CURRENT
D = DISCHARGE
AD8451
CONTROLLER
VINT
ISVP
+
SENSE
RESISTOR
IA
ISVN
–
ISMEA
SYSTEM LOOP COMPENSATION
BVP
BVN
+
BVMEA
DA
BATTERY
–
Figure 43. Signal Path of an Li-Ion Battery Formation and Test System Using the AD8451
VREF
INSTRUMENTATION AMPLIFIER (IA)
POLARITY
INVERTER
100kΩ
ISREFH
ISREFL
IA
Figure 44 is a block diagram of the IA, which is used to monitor the
battery current. The architecture of the IA is the classic 3-op-amp
topology, similar to the Analog Devices industry-standard
AD8221 and AD620, with a fixed gain of 26. This architecture
provides the highest achievable CMRR at a given gain, enabling
high-side battery current sensing without the introduction of
significant errors in the measurement. For more information
about instrumentation amplifiers, see A Designer's Guide to
Instrumentation Amplifiers.
ISVP
+CURRENT
SHUNT
±
+
10kΩ 19.2kΩ
806Ω
RGP
–
10kΩ
G = 2 SUBTRACTOR
+
–
ISMEA
1667Ω
10kΩ
RGN
ISVN
–
+
10kΩ
20kΩ
Reversing Polarity When Charging and Discharging
–CURRENT
SHUNT
±
Figure 43 shows that during the charge cycle, the power converter
feeds current into the battery, generating a positive voltage across
the current sense resistor. During the discharge cycle, the power
converter draws current from the battery, generating a negative
voltage across the sense resistor. In other words, the battery current
polarity reverses when the battery discharges.
POLARITY
INVERTER
MODE
Figure 44. IA Simplified Block Diagram
IA Offset Option
As shown in Figure 44, the IA reference node is connected to
the ISREFL and ISREFH pins via an internal resistor divider.
This resistor divider can be used to introduce a temperature
insensitive offset to the output of the IA such that it always
reads a voltage higher than zero for a zero differential input.
Because the output voltage of the IA is always positive, a
unipolar analog-to-digital converter (ADC) can digitize it.
In the CC control loop, this change in polarity can be problematic
if the polarity of the target current is not reversed. To solve this
problem, the AD8451 IA includes a multiplexer preceding its
inputs that inverts the polarity of the IA gain. This multiplexer
is controlled via the MODE pin. When the MODE pin is logic
high (charge mode), the IA gain is noninverting, and when the
MODE pin is logic low (discharge mode), the IA gain is
inverting.
Rev. 0 | Page 18 of 32
Data Sheet
AD8451
When the ISREFH pin is tied to the VREF pin with the ISREFL
pin grounded, the voltage at the ISMEA pin is increased by 20 m V,
guaranteeing that the output of the IA is always positive for zero
differential inputs. Other voltage shifts can be realized by tying
the ISREFH pin to an external voltage source. The gain from the
ISREFH pin to the ISMEA pin is 8 mV /V. For zero offset, tie
the ISREFL and ISREFH pins to ground.
The resistors that form the DA gain network are laser trimmed
to a matching level better than 0.1%. This level of matching
minimizes the gain error and gain error drift of the DA while
maximizing the CMRR of the DA. This matching also allows
the controller to set a stable target voltage for the battery over
temperature while rejecting the ground bounce in the battery
negative terminal.
Battery Reversal and Overvoltage Protection
Like the IA, the DA can also level shift its output voltage via an
internal resistor divider that is tied to the DA reference node. This
resistor divider is connected to the BVREFH and BVREFL pins.
The AD8451 IA can be configured for high-side or low-side
current sensing. If the IA is configured for high-side current
sensing (see Figure 43) and the battery is connected backward,
the IA inputs may be held at a voltage that is below the negative
power rail (AVEE), depending on the battery voltage.
When the BVREFH pin is tied to the VREF pin with the BVREFL
pin grounded, the voltage at the BVMEA pin is increased by 5 m V,
guaranteeing that the output of the DA is always positive for
zero differential inputs. Other voltage shifts can be realized by
tying the BVREFH pin to an external voltage source. The gain
from the BVREFH pin to the BVMEA pin is 2 mV /V. For zero
offset, tie the BVREFL and BVREFH pins to ground.
To prevent damage to the IA under these conditions, the IA
inputs include overvoltage protection circuitry that allows them
to be held at voltages of up to 55 V from the opposite power
rail. In other words, the safe voltage span for the IA inputs
extends from AVCC − 55 V to AVEE + 55 V.
CC AND CV LOOP FILTER AMPLIFIERS
DIFFERENCE AMPLIFIER (DA)
The CC and CV loop filter amplifiers are high precision, low
noise specialty amplifiers with very low offset voltage and very
low input bias current. These amplifiers serve two purposes:
Figure 45 is a block diagram of the DA, which is used to monitor
the battery voltage. The architecture of the DA is a subtractor
amplifier with a fixed gain of 0.8. This gain value allows the DA to
funnel the voltage of a 5 V battery to a level that can be read by
a 5 V ADC with a 4.096 V reference.
•
Using external components, the amplifiers implement active
loop filters that set the dynamics (transfer function) of the
CC and CV loops.
•
The amplifiers perform a seamless transition from CC to
CV mode after the battery reaches its target voltage.
DA
100kΩ
79.9kΩ 100kΩ
BVP
BVREFL
BVREFH
VREF
50kΩ
Figure 46 is the functional block diagram of the AD8451 CC
and CV feedback loops for charge mode (MODE logic pin is high).
For illustration purposes, the external networks connected to
the loop amplifiers are simple RC networks configured to form
single-pole inverting integrators. The outputs of the CC and CV
loop filter amplifiers are coupled to the VINT pins via an analog
NOR circuit (minimum output selector circuit), such that they can
only pull the VINT node down. In other words, the loop amplifier
that requires the lowest voltage at the VINT pins is in control of
the node. Thus, only one loop amplifier, CC or CV, can be in
control of the system charging control loop at any given time.
+
–
100kΩ
80kΩ
BVN
BVMEA
Figure 45. DA Simplified Block Diagram
Rev. 0 | Page 19 of 32
AD8451
Data Sheet
CURRENT
POWER
BUS
IOUT
VCTRL
R1
I
C1
POWER
CONVERTER
BAT
V1
CC LOOP
AMPLIFIER
VINT
ISMEAS
ISET
IVE1
VINT
IA
ISVP
ISVN
BUFFER
+
–
SENSE
RESISTOR
VCLP
G
R
IA
S
ANALOG
+
–
‘NOR’
VCTRL
1×
MINIMUM
OUTPUT
BVP
BVN
VCLN
DA
+
G
+
–
+
SELECTOR
V3 V4
V
BAT
–
DA
–
CV LOOP
MODE
5V
VVE1
R2
BVMEA
VSET
V2
AMPLIFIER
VINT
V3 < VCTRL < V4
C2
Figure 46. Functional Block Diagram of the CC and CV Loops in Charge Mode (MODE Pin High)
1.25
5
4
3
2
1
The unity-gain amplifier (VINT buffer) buffers the VINT pins
and drives the VCTRL pin. The VCTRL pin is the control output
of the AD8451 and the control input of the power converter. The
TRANSITION FROM CC TO CV
CC
CHARGE
BEGINS
1.00
0.75
0.50
0.25
0
VISET and VVSET voltage sources set the target constant current and
the target constant voltage, respectively. When the CC and CV
feedback loops are in a steady state, the charging current is set at
VISET
IBAT_SS
=
G
IA ×RS
where:
BAT_SS = is the steady state charging current.
IA is the IA gain.
CC
CHARGE
ENDS
I
G
0
RS is the value of the shunt resistor.
The target voltage is set at
VVSET
0
1
2
3
4
5
TIME (Hours)
Figure 47. Representative Constant Current to Constant Voltage Transition
near the End of a Battery Charging Cycle
VBAT_SS
=
GDA
2. As the voltage at the VINT node increases, the voltage at
the VCRTL node rises, and the output current of the power
converter, IBAT, increases (assuming that an increasing voltage
at the VCRTL node increases the output current of the
power converter).
where:
VBAT_SS = steady state battery voltage.
GDA is the DA gain.
Because the offset voltage of the loop amplifiers is in series with
the target voltage sources, VISET and VVSET, the high precision of
these amplifiers minimizes this source of error.
3. When the IBAT current reaches the CC steady state value,
I
BAT_SS, the battery voltage is still less than the target steady
state value, VBAT_SS. Therefore, the CV loop tries to keep
pulling the VINT node up while the CC loop tries to keep
it at its current voltage. At this point, the voltage at the ISMEA
pin equals VISET; therefore, the CC loop stops integrating.
4. Because the loop amplifiers can only pull the VINT node
down due to the analog NOR circuit, the CC loop takes
control of the charging feedback loop, and the CV loop is
disabled.
Figure 47 shows a typical CC/CV charging profile for a Li-Ion
battery. In the first stage of the charging process, the battery is
charged with a CC of 1 A. When the battery voltage reaches a
target voltage of 4.2 V, the charging process transitions such that
the battery is charged with a CV of 4.2 V.
The following steps describe how the AD8451 implements the
CC/CV charging profile (see Figure 46). In this scenario, the
battery begins in the fully discharged state, and the system has
just been turned on such that IBAT = 0 A at Time 0.
5. As the charging process continues, the battery voltage
increases until it reaches the steady state value, VBAT_SS, and
the voltage at the BVMEA pin reaches the target voltage, VVSET
.
1. Because the voltages at the ISMEA and BVMEA pins
are less than the target voltages (VISET and VVSET) at Time 0,
both integrators begin to ramp, increasing the voltage at
the VINT node.
Rev. 0 | Page 20 of 32
Data Sheet
AD8451
6. The CV loop tries to pull the VINT node down to reduce
the charging current (IBAT) and prevent the battery voltage
from rising any further. At the same time, the CC loop tries
to keep the VINT node at its current voltage to keep the
the internal switches in the CC and CV amplifiers, the frequency
response of the loops in charge mode does not affect the
frequency response of the loops in discharge mode.
Unlike simpler controllers that use passive networks to ground
for frequency compensation, the AD8451 allows the use of
feedback networks for its CC and CV loop filter amplifiers.
These networks enable the implementation of both
proportional differentiator (PD) Type II and proportional
integrator differentiator (PID) Type III compensators. Note
that in charge mode, both the CC and CV loops implement
inverting compensators, whereas in discharge mode, the CC
loop implements an inverting compensator, and the CV loop
implements a noninverting compensator. As a result, the CV loop
in discharge mode includes an additional amplifier, VSET buffer, to
buffer the VSET node from the feedback network (see Figure 48).
battery current at IBAT_SS
.
7. Because the loop amplifiers can only pull the VINT node
down due to the analog NOR circuit, the CV loop takes
control of the charging feedback loop, and the CC loop is
disabled.
The analog NOR (minimum output selector) circuit that couples
the outputs of the loop amplifiers is optimized to minimize the
transition time from CC to CV control. Any delay in the transition
causes the CC loop to remain in control of the charge feedback
loop after the battery voltage reaches its target value. Therefore,
the battery voltage continues to rise beyond VBAT_SS until the
control loop transitions; that is, the battery voltage overshoots
its target voltage. When the CV loop takes control of the charge
feedback loop, it reduces the battery voltage to the target voltage.
A large overshoot in the battery voltage due to transition delays
can damage the battery; thus, it is crucial to minimize delays by
implementing a fast CC to CV transition.
VINT Buffer
The unity-gain amplifier (VINT buffer) is a clamp amplifier
that drives the VCTRL pin. The VCTRL pin is the control
output of the AD8451 and the control input of the power
converter (see Figure 46 and Figure 48). The output voltage
range of this amplifier is bounded by the clamp voltages at the
VCLP and VCLN pins such that
Figure 48 is the functional block diagram of the AD8451 CC
and CV feedback loops for discharge mode (MODE logic pin is
low). In discharge mode, the feedback loops operate in a similar
manner as in charge mode. The only difference is in the CV
loop amplifier, which operates as a noninverting integrator in
discharge mode. For illustration purposes, the external networks
connected to the loop amplifiers are simple RC networks
configured to form single-pole integrators (see Figure 48).
VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V
The reduction in the output voltage range of the amplifier is a
safety feature that allows the AD8451 to drive devices such as
the ADP1972 PWM controller, whose input voltage range must
not exceed 5.5 V (that is, the voltage at the COMP pin of the
ADP1972 must be below 5.5 V).
MODE PIN, CHARGE AND DISCHARGE CONTROL
Compensation
The MODE pin is a TTL logic input that configures the AD8451
for either charge or discharge mode. A logic low (VMODE < 0.8 V)
corresponds to discharge mode, and a logic high (VMODE > 2 V)
corresponds to charge mode. Internal to the AD8451, the MODE
pin toggles all single-pole, double throw (SPDT) switches in the
CC and CV loop amplifiers and inverts the gain polarity of the IA.
In battery formation and test systems, the CC and CV feedback
loops have significantly different open-loop gain and crossover
frequencies; therefore, each loop requires its own frequency
compensation. The active filter architecture of the AD8451 CC
and CV loops allows the frequency response of each loop to be
set independently via external components. Moreover, due to
CURRENT
IOUT
POWER
BUS
VCTRL
R1
V1
I
C1
BAT
POWER
CONVERTER
CC LOOP
VINT
ISMEAS
ISET
IVE0
VINT
IA
ISVP
ISVN
AMPLIFIER
BUFFER
+
–
SENSE
RESISTOR
VCLP
G
R
IA
S
ANALOG
+
–
‘NOR’
VCTRL
1×
VSET
MINIMUM
OUTPUT
SELECTOR
BUFFER
BVP
BVN
VCLN
DA
+
G
+
–
+
V3 V4
V
BAT
DA
1×
–
CV LOOP
AMPLIFIER
–
MODE
BVMEA
VSET VSETBF VVP0 VVE0
VINT
V3 < VCTRL < V4
V2
C2
R2
C2
R2
Figure 48. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low)
Rev. 0 | Page 21 of 32
AD8451
Data Sheet
APPLICATIONS INFORMATION
This section describes how to use the AD8451 in the context of
a battery formation and test system. This section includes a
design example of a small scale model of an actual system.
•
•
•
Two loop filter error amplifiers that receive the battery target
current and voltage and establish the dynamics of the CC and
CV feedback loops.
A minimum output selector circuit that combines the
outputs of the loop filter error amplifiers to perform
automatic CC to CV switching.
An output clamp amplifier that drives the VCTRL pin. The
voltage range of this amplifier is limited by the voltage at
the VCLP and VCLN pins such that it cannot overrange
the subsequent stage. The output clamp amplifier can drive
switching and linear power converters. Note that an
increasing voltage at the VCTRL pin must translate to a
larger output current in the power converter.
FUNCTIONAL DESCRIPTION
The AD8451 is a precision analog front end and controller for
battery formation and test systems. These systems use precision
controllers and power stages to put batteries through charge and
discharge cycles. Figure 49 shows the signal path of a simplified
switching battery formation and test system using the AD8451
controller and the ADP1972 PWM controller. For more
information on the ADP1972, see the ADP1972 data sheet.
The AD8451 is suitable for systems that form and test NiCad,
NiMH, and Li-Ion batteries and is designed to operate in
conjunction with both linear and switching power stages.
•
A 2.5 V reference whose output node is the VREF pin.
A logic input pin (MODE) that changes the configuration of the
controller from charge to discharge mode. A logic high at the
MODE pin configures charge mode; a logic low configures
discharge mode.
The AD8451 includes the following blocks (see Figure 42 and
the Theory of Operation section for more information).
•
A fixed gain IA that senses low-side or high-side battery
current.
•
A fixed gain DA that measures the terminal voltage of the
battery.
SET
CONSTANT
BATTERY
AVCC
VOLTAGE LOOP
VINT
CURRENT
ISET
FILTER AMPLIFIER
BUFFER
+
–
OUTPUT
FILTER
VCTRL
ADP1972
PWM
LEVEL
SHIFTER
OUTPUT
DRIVERS
1×
CONSTANT
CURRENT LOOP
FILTER AMPLIFIER
SET
BATTERY
VOLTAGE
+
–
DC-TO-DC POWER CONVERTER
VSET
1×
MODE
SWITCHES AVEE
(3)
C
D C
D C
D
CV
BUFFER
C = CHARGE
BATTERY
CURRENT
D = DISCHARGE
AD8451
CONTROLLER
VINT
ISVP
+
SENSE
RESISTOR
IA
–
ISVN
ISMEA
BVP
BVN
+
BVMEA
DA
BATTERY
–
EXTERNAL
PASSIVE
COMPENSATION
NETWORK
Figure 49. Complete Signal Path of a Battery Test or Formation System Suitable for Li-Ion Batteries
Rev. 0 | Page 22 of 32
Data Sheet
AD8451
Optional Low-Pass Filter
POWER SUPPLY CONNECTIONS
The AD8451 is designed to control both linear regulators and
switching power converters. Linear regulators are generally
noise free, whereas switch mode power converters generate
switching noise. Connecting an external differential low-pass
filter between the current sensor and the IA inputs reduces the
injection of switching noise into the IA (see Figure 50).
ISVP
The AD8451 requires two analog power supplies (AVCC and
AVEE), one digital power supply (DVCC), one analog ground
(AGND), and one digital ground (DGND). AVCC and AVEE
power all the analog blocks, including the IA, DA, and op amps,
and DVCC powers the MODE input logic. AGND provides a
reference and return path for the 2.5 V reference, and DGND
provides a reference and return path for the digital circuitry.
+
10kΩ
RGP
The rated absolute maximum value for AVCC − AVEE is 36 V,
and the minimum operating AVCC and AVEE voltages are +5 V
and −5 V, respectively. Due to the high PSRR of the AD8451
analog blocks, AVCC can be connected directly to the high current
power bus (the input voltage of the power converter) without
risking the injection of supply noise to the controller outputs.
–
20kΩ
10kΩ
+
–
4 TERMINAL
SHUNT
1667Ω
10kΩ
LPF
RGN
ISVN
DUT
–
+
10kΩ
20kΩ
A commonly used power supply combination is +15 V for
AVCC, −15 V for AVEE, and +5 V for DVCC. The +15 V rail
for AVCC provides enough headroom to the IA such that it can
be connected in a high-side current sensing configuration. The
−15 V rail for AVEE allows the DA to sense accidental reverse
battery conditions (see the Reverse Battery Conditions section).
Figure 50. 4-Terminal Shunt Resistor Connected to the Current Sense IA
VOLTAGE SENSE DA CONNECTIONS
For a description of the DA, see the Theory of Operation
section, Figure 42, and Figure 45. The DA fixed gain is 0.8.
Connect decoupling capacitors to all the supply pins. A 1 µF
capacitor in parallel with a 0.1 µF capacitor is recommended.
Reverse Battery Conditions
The output voltage of the AD8451 DA can be used to detect a
reverse battery connection. A −15 V rail for AVEE allows the
output of the DA to go below ground when the battery is
connected backward. Therefore, the condition can be detected
by monitoring the BVMEA pin for a negative voltage.
CURRENT SENSE IA CONNECTIONS
For a description of the IA, see the Theory of Operation section,
Figure 42, and Figure 44. The IA fixed gain is 26.
Current Sensors
BATTERY CURRENT AND VOLTAGE CONTROL
INPUTS (ISET AND VSET)
Two common options for current sensors are isolated current
sensing transducers and shunt resistors. Isolated current sensing
transducers are galvanically isolated from the power converter
and are affected less by the high frequency noise generated by
switch mode power supplies. Shunt resistors are less expensive
and easier to deploy.
The voltages at the ISET and VSET input pins set the target
battery current and voltage for the CC and CV loops. These
inputs must be driven by a precision voltage source (or a digital-
to-analog converter [DAC] connected to a precision reference)
whose output voltage is referenced to the same voltage as the IA
and DA reference pins (ISREFH/ISREFL and BVREFH/BVREFL,
respectively). For example, if the IA reference pins are connected
to AGND, the voltage source connected to ISET must also be
referenced to AGND. In the same way, if the DA reference pins
are connected to AGND, the voltage source connected to VSET
must also be referenced to AGND.
If a shunt resistor sensor is used, a 4-terminal, low resistance shunt
resistor is recommended. Two of the four terminals conduct the
battery current, whereas the other two terminals conduct virtually
no current. The terminals that conduct no current are sense
terminals that are used to measure the voltage drop across the
resistor (and, therefore, the current flowing through it) using an
amplifier such as the IA of the AD8451. To interface the IA with
the current sensor, connect the sense terminals of the sensor to
the ISVP and ISVN pins of the AD8451 (see Figure 50).
In constant current mode, when the CC feedback loop is in a
steady state, the ISET input sets the battery current as follows:
VISET
IA ×RS
VISET
26×RS
IBAT_SS
=
=
G
where:
IA is the IA gain.
RS is the value of the shunt resistor.
G
Rev. 0 | Page 23 of 32
AD8451
Data Sheet
In constant voltage mode, when the CV feedback loop is in
steady state, the VSET input sets the battery voltage as follows:
Given the architecture of the AD8451, the controller requires
that an increasing voltage at the VCTRL pin translates to a
larger output current in the power converter. If this is not the
case, a unity-gain inverting amplifier can be added in series
with the AD8451 output to add an extra inversion.
VVSET
GDA
VVSET
0.8
VBAT_SS
=
=
where GDA is the DA gain.
STEP-BY-STEP DESIGN EXAMPLE
Therefore, the accuracy and temperature stability of the formation
and test system are not only dependent on the precision of the
AD8451, but also on the accuracy of the ISET and VSET inputs.
This section describes the systematic design of a 1 A battery
charger/discharger using the AD8451 controller and the
ADP1972 PWM controller. The power converter used in this
design is a nonisolated buck boost dc-to-dc converter. The target
battery is a 4.2 V fully charged, 2.7 V fully discharged Li-Ion
battery.
LOOP FILTER AMPLIFIERS
The AD8451 has two loop filter amplifiers, also known as error
amplifiers (see Figure 49). One amplifier is for constant current
control (CC loop filter amplifier), and the other amplifier is for
constant voltage control (CV loop filter amplifier). The outputs
of these amplifiers are combined using a minimum output
selector circuit to perform automatic CC to CV switching.
Step 1: Design the Switching Power Converter
Select the switches and passive components of the buck boost
power converter to support the 1 A maximum battery current.
The design of the power converter is beyond the scope of this
data sheet; however, there are many application notes and other
helpful documents available from manufacturers of integrated
driver circuits and power MOSFET output devices that can be
used for reference.
Table 5 lists the inputs of the loop filter amplifiers for charge
mode and discharge mode.
Table 5. Integrator Input Connections
Reference Feedback
Step 2: Identify the Control Voltage Range of the
ADP1972
Feedback Loop Function
Input
Terminal
Control the Current While Discharging ISET
a Battery
IVE0
The control voltage range of the ADP1972 (voltage range of the
COMP input pin) is 0.5 V to 4.5 V. An input voltage of 4.5 V
results in the highest duty cycle and output current, whereas an
input voltage of 0.5 V results in the lowest duty cycle and output
current. Because the COMP pin connects directly to the VCTRL
output pin of the AD8451, the battery current is proportional to
the voltage at the VCTRL pin.
Control the Current While Charging
a Battery
ISET
IVE1
Control the Voltage While Discharging VSET
a Battery
VVE0
VVE1
Control the Voltage While Charging
a Battery
VSET
The CC and CV amplifiers in charge mode and the CC amplifier
in discharge mode are inverting integrators, whereas the CV
amplifier in discharge mode is a noninverting integrator. Therefore,
the CV amplifier in discharge mode uses an extra amplifier, the
VSET buffer, to buffer the VSET input pin (see Figure 42). In
addition, the CV amplifier in discharge mode uses the VVP0
pin to couple the signal from the BVMEA pin to the integrator.
For information about how to interface the ADP1972 to the
power converter switches, see the ADP1972 data sheet.
Step 3: Determine the Control Voltage for the CV Loop
The relationship between the control voltage for the CV loop
(the voltage at the VSET pin), the target battery voltage, and the
DA gain is as follows:
CONNECTING TO A PWM CONTROLLER (VCTRL PIN)
VVSET VVSET
CV Battery Target Voltage =
=
GDA
0.8
The VCTRL output pin of the AD8451 is designed to interface
with linear power converters and with PWM controllers such as
the ADP1972. The voltage range of the VCTRL output pin is
bound by the voltages at the VCLP and VCLN pins, as follows:
In charge mode, for a CV battery target voltage of 4.2 V, select a
CV control voltage of 3.36 V. In discharge mode, for a CV
battery target voltage of 2.7 V, select a CV control voltage of
2.16 V.
VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V
Because the maximum rated input voltage at the COMP pin of
the ADP1972 is 5.5 V, connect the clamp voltages of the output
amplifier to 5 V (VCLP) and ground (VCLN) to prevent over-
ranging of the COMP input. As an additional precaution, install
an external 5.1 V Zener diode from the COMP pin to ground
with a series 1 kΩ resistor connected between the VCTRL and
COMP pins. Consult the ADP1972 data sheet for additional
applications information.
Rev. 0 | Page 24 of 32
Data Sheet
AD8451
Step 4: Determine the Control Voltage for the CC Loop
and the Shunt Resistor
Step 5: Choose the Control Voltage Sources
The input control voltages (the voltages at the ISET and VSET
pins) can be generated by an analog voltage source such as a
voltage reference or by a DAC. In both cases, select a device that
provides a stable, low noise output voltage. If a DAC is preferred,
Analog Devices offers a wide range of precision converters. For
example, the AD5668 16-bit DAC provides up to eight 0 V to
4 V sources when connected to an external 2 V reference.
The relationship between the control voltage for the CC loop
(the voltage at the ISET pin), the target battery current, and the
IA gain is as follows:
VISET
IA × RS 26 × RS
VISET
CC Battery Target Current =
=
G
The voltage across the shunt resistor is as follows:
To maximize accuracy, the control voltage sources must be
referenced to the same potential as the outputs of the IA and
DA. For example, if the IA and DA reference pins are connected
to AGND, connect the reference pins of the control voltage
sources to AGND.
VISET VISET
Shunt Resistor Voltage =
=
GIA
26
For target current of 1 A, choosing a 20 mΩ shunt resistor
results in a control voltage of 4 V.
Step 6: Select the Compensation Devices
When selecting a shunt resistor, consider the resistor style and
construction. For low power dissipation applications, many
temperature stable SMD styles can be soldered to a heat sink
pad on a printed circuit board (PCB). For optimum accuracy,
choose a shunt resistor that provides force and sense terminals.
In these resistors, the battery current flows through the force
terminals and the voltage drop in the resistor is read at the sense
terminals.
Feedback controlled switching power converters require
frequency compensation to guarantee loop stability. There are
many references available about how to design the compensation
for such power converters. The AD8451 provides active loop
filter error amplifiers for the CC and CV control loops that
can implement proportional integrator (PI), PD, and PID
compensators using external passive components.
Rev. 0 | Page 25 of 32
AD8451
Data Sheet
EVALUATION BOARD
INTRODUCTION
FEATURES AND TESTS
The AD8451-EVALZ evaluation board is a convenient
standalone platform for evaluating the major elements of the
AD8451, either as a standalone component or connected to a
battery test/formation system.
SMA connectors provide access for input voltages to the
sensitive instrumentation (IA) and difference (DA) amplifiers.
ISVP and ISVN connectors are the IA inputs, and BVP and
BVN are the DA inputs. These inputs accept the dc voltages
from battery current and voltage measurement sources, or from
a precision dc voltage source. SMA connectors ISET and VSET
are available for precision dc control voltages for CC or CV
battery charging voltages. SMA ISREFLO is available for
applying a nonzero reference voltage to the IA. SMA VCTRL
connects to the input of a dc-to-dc power converter as seen in
Figure 52. Convenient test loops are provided connecting scope
probes or instruments for the remainder of the input/output.
In the latter configuration, the AD8451-EVALZ operates just as
it would within a system including the PWM and dc-to-dc
power converter. Simply connect the current and voltage sense
voltages from the system directly to the board terminus. This
feature is used when setting or evaluating loop compensation
using a field of passive compensation components. Figure 51 is
a photograph of the AD8451-EVALZ.
The MODE switch selects between the charge and discharge
option. Figure 52 is a schematic of the AD8451-EVALZ. Table 6
lists and describes the various switches and functions.
Figure 51. Photograph of the AD8451-EVALZ
Rev. 0 | Page 26 of 32
Data Sheet
AD8451
Table 6. AD8451-EVALZ Test Switches and Functions
Default
Position
Switch
Function
Operation
MODE
Selects the charge or the discharge The MODE switch selects CHG (logic high) or DISCH (logic low).
mode.
CHG
RUN
RUN
RUN_TEST1 Selects between the user inputs and The AD8451 operates normally when the RUN_TEST1 switch is in the RUN
the 2.5 V AD8451 reference voltage.
position. When in the TEST position, 2.5 V is applied to the ISET and VSET inputs.
RUN_TEST2 Tests the CC or CV loop filter
amplifiers.
The voltage at the VCTRL output (TPVCTRL) for all positions is 0 V when
RUN_TEST1 is in RUN position and 2.5 V when RUN_TEST1 in TEST position.
ISREF_HI
The ISREF_HI switch connects
Pin 74 (ISREFH) to the internal 2.5 V internal 100 kΩ resistor) to Pin 73 (VREF, the 2.5 V reference). When the
When in the 2.5V position, the ISREF_HI switch connects Pin 74 (ISREFH, an EXT
reference (2.5 position) or to the
SMA connector EXT (the external
input for a user defined VREF input).
ISREF_LO switch is in the NORM position, the output at Pin 71 (ISMEA)
shifts positive by 20 mV.
ISREF_LO
Connects Pin 76 (ISREFL) to ground When in the NORM position and the ISREF_HI switch is in the EXT position, NORM
(NORM) or to the ISREFL SMA input
connector.
there is no offset applied to the ISMEA output. When in the EXT position,
the ISREFLO SMA is selected.
EVALUATING THE AD8451
Test the Instrumentation Amplifier
Note the four compensation networks, CC-CHARGE, CC-
DISCHARGE, CV-CHARGE, and CV-DISCHARGE, located
Connect the TPISVN jumper to ground, and then apply
100 mV dc to TPISVP. Measure 2.6 V at the TPISMEA output.
Subtract any offset voltages from the output reading before
calculating the gain.
on the right-hand side of the schematic shown in Figure 52. To
make it easier to locate these components, the configuration of
these networks on the AD8451-EVALZ PCB approximates that
shown in the schematic (see Figure 52). Each of the components
locations accommodates both standard, 1206 size, surface-mount
chip resistors and capacitors or leaded components inserted into
the pairs of TP thru holes spanning the SM footprints. The TP
holes accept the popular 0.025” test pins if leaded devices are
preferred for multiple loop tests.
20 mV Offset at IMEAS Output
Connect a jumper from TPISVP to TPISVN to ground by using
another jumper and any one of the convenient black test loops.
Measure 0 V 2.86 mV at the TPISMEA output (that is, the IA
residual offset voltage multiplied by gain). Move the ISREFLO
switch to the EXT position, and the ISREFHI switch to the
20 mV (EXT) position. The output will then increase by 20 mV.
As shipped, CC and CV loop amplifier filters are configured as
voltage followers by replacing feedback capacitors to the inverting
inputs with resistors, and removing the dc coupling resistors from
the IA and DA outputs. The feedback loops must be reconfigured
to close the loops to operate as precision feedback loops.
Test the Difference Amplifier
Insert a shorting jumper at Header GND_BVN. With 1 V dc
applied to TPBVP, measure 0.8 V at TPBVMEA. For the most
accurate gain measurement, subtract the offset voltage from the
output voltage before calculating gain.
Loop compensation requires knowledge of the output dc-to-dc
power converter. It is assumed that the AD8451 is most often
used with a switching converter. The scope and breadth of this
switching converter design architecture is quite broad, and a
thorough discussion of all the types and variants of this type of
converter is well beyond the scope of this data.
5 mV Offset at BVMEAS Output
Insert jumpers in the GND_BVP and GND_BVN headers.
Measure 0 V 0.4mV at the TPBVMEA output (that is, the DA
residual offset voltage multiplied by gain). Connect a jumper
between TPBREFH and TP2.5V. The output will then increase
by 5 mV.
When the circuit and component details of the power converter
are known, proceed with a calculation of the loop parameters
and components, and the values necessary to achieve loop
compensation.
CC and CV Integrator Tests
Because the loop is of the type proportional/integrating (PI), a
direct dc path is required from the IA and DA amplifiers to the
error inputs of the CC and CV loop amplifiers. Install these
resistors at the R1, R6, R7, R11, and R12 locations.
Switches RUN_TEST1 and RUN_TEST2 set up the required
circuit conditions to test the integrators. RUN_TEST1 disconnects
the external inputs ISET and VSET and applies 2.5 V dc from
the reference, simultaneously, to both of the CC and CV.
Likewise, the CC and CV amplifiers must be reconfigured from
voltage followers to integrators by replacing the 0 Ω capacitors
at C6, C10, C11, C19, and C24 with appropriate capacitors.
RUN_TEST2 has three positions: RUN, TEST_CC, and
TEST_CV.
Loop Compensation
The AD8451-EVALZ is suitable for use as a test platform for
system loop compensation experiments. However, before
installing the platform in a system, component changes are necessary.
Rev. 0 | Page 27 of 32
AD8451
Data Sheet
SCHEMATIC AND ARTWORK
N C
O D M
C C A V
E E V A
T I N V
E
N C
1 E I V
A E M V B
E E V A
N S B V
N C
0 E I V
N C
S N V B P T
N C
T E S I
N C
B F E R S I
N C
N C
N V B
N C
N V B
N C
C C A V
A E M S I
E E V A
F E R V
F L E S R V B T P
F L E R B T P
F L E S R B
L F
B R E
N D A G
B R E
H F
H F E R S I
N D A G
F E R V
N C
P V B
N C
S P V B
N C
L F E R S I
F L E S R S I
N C
N C
N C
Figure 52. AD8451-EVALZ Schematic
Rev. 0 | Page 28 of 32
Data Sheet
AD8451
Figure 53. AD8451-EVALZ Top Silkscreen
Figure 54. AD8451-EVALZ Primary Side Copper
Rev. 0 | Page 29 of 32
AD8451
Data Sheet
Figure 55. AD8451-EVALZ Secondary Side Copper
Figure 56. AD8451-EVALZ Power Plane
Rev. 0 | Page 30 of 32
Data Sheet
AD8451
Figure 57. AD8451-EVALZ Ground Plane
Rev. 0 | Page 31 of 32
AD8451
Data Sheet
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
0.75
0.60
0.45
1.60
MAX
61
80
60
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.10
COPLANARITY
20
41
0.15
0.05
40
21
SEATING
PLANE
VIEW A
0.65
0.38
0.32
0.22
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 58. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
Package Description
80-Lead LQFP
Package Option
ST-80-2
AD8451ASTZ
AD8451ASTZ-RL
AD8451-EVALZ
−40°C to +85°C
80-Lead LQFP
Evaluation Board
ST-80-2
1 Z = RoHS Compliant Part.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12137-0-3/14(0)
Rev. 0 | Page 32 of 32
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