AD8058ARZ-REEL7 [ADI]
Low Cost, High Performance Voltage Feedback, 325 MHz Amplifiers; 低成本，高性能电压反馈型， 325 MHz的放大器
| 型号： | AD8058ARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Cost, High Performance Voltage Feedback, 325 MHz Amplifiers |
| 文件： | 总16页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, High Performance
Voltage Feedback, 325 MHz Amplifiers
AD8057/AD8058
FEATURES
CONNECTION DIAGRAMS (TOP VIEW)
Low Cost Single (AD8057) and Dual (AD8058)
High Speed
RT-5 (SOT-23-5)
R-8 (SOIC)
325 MHz –3 dB Bandwidth (G = +1)
1000 V/s Slew Rate
Gain Flatness 0.1 dB to 28 MHz
Low Noise
7 nV/√Hz
Low Power
AD8057
1
2
3
4
V
1
2
3
+V
8
7
6
5
4
NC
+V
NC
–IN
+IN
OUT
S
S
–V
S
V
OUT
AD8057
(Not to Scale)
–IN
+IN
5
–V
NC
S
(Not to Scale)
5.4 mA/Amplifier Typical Supply Current @ 5 V
Low Distortion
NC = NO CONNECT
–85 dBc @ 5 MHz, RL = 1 k⍀
Wide Supply Range from 3 V to 12 V
Small Packaging
RM-8 (MSOP)
R-8 (SOIC)
AD8057 Available in SOIC-8 and SOT-23-5
AD8058 Available in SOIC-8 and MSOP
AD8058
OUT1
1
2
3
4
+V
S
8
APPLICATIONS
Imaging
DVD/CD
Photodiode Preamp
A-to-D Driver
Professional Cameras
Filters
–IN1
+IN1
7
6
5
OUT2
–IN2
+IN2
–V
S
(Not to Scale)
GENERAL DESCRIPTION
The AD8057 (single) and AD8058 (dual) are very high perfor-
mance amplifiers with a very low cost. The balance between
cost and performance make them ideal for many applications.
The AD8057 and AD8058 will reduce the need to qualify a
variety of specialty amplifiers.
5
4
3
2
1
The AD8057 and AD8058 are voltage feedback amplifiers with
the bandwidth and slew rate normally found in current feedback
amplifiers. The AD8057 and AD8058 are low power amplifiers
having low quiescent current and a wide supply range from 3 V
to 12 V. They have noise and distortion performance required
for high end video systems as well as dc performance parameters
rarely found in high speed amplifiers.
G = +1
G = +2
0
–1
–2
–3
–4
–5
G = +5
G = +10
The AD8057 and AD8058 are available in standard SOIC
packaging as well as tiny SOT-23-5 (AD8057) and MSOP
(AD8058) packages. These amplifiers are available in the indus-
trial temperature range of –40°C to +85°C.
1
10
100
1000
FREQUENCY (MHz)
Figure 1. Small Signal Frequency Response
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(@ TA = 25؇C, VS = ؎5 V, RL = 100 ⍀, RF = 0 ⍀, Gain = +1,
AD8057/AD8058–SPECIFICATIONS unless otherwise noted.)
AD8057/AD8058
Typ
Parameter
Conditions
Min
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VO = 0.2 V p-p
G = –1, VO = 0.2 V p-p
G = +1, VO = 2 V p-p
G = +1, VO = 0.2 V p-p
G = +1, VO = 2 V Step, RL = 2 kΩ
G = +1, VO = 4 V Step, RL = 2 kΩ
G = +2, VO = 2 V Step
325
95
175
30
850
1150
30
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, VO = 2 V p-p, RL = 150 Ω
f = 5 MHz, VO = 2 V p-p
f = 5 MHz, G = +2
–85
–62
–68
–35
–60
7
dBc
dBc
dB
dBm
dB
nV/√Hz
pA/√Hz
%
SFDR
Third Order Intercept
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error
f = 100 kHz
f = 100 kHz
0.7
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
VIN = 200 mV p-p, G = +1
0.01
0.02
0.15
0.01
30
%
Differential Phase Error
Degree
Degree
ns
Overload Recovery
DC PERFORMANCE
Input Offset Voltage
1
2.5
3
0.5
3.0
5
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
2.5
TMIN to TMAX
µA
Input Offset Current
Open-Loop Gain
0.75
µA
dB
dB
VO = 2.5 V, RL = 2 kΩ
VO = 2.5 V, RL = 150 Ω
50
50
55
52
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
10
2
MΩ
pF
V
+Input
RL = 1 kΩ
VCM = 2.5 V
–4.0
48
+4.0
+4.0
60
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 2 kΩ
RL = 150 Ω
30% Overshoot
–4.0
V
V
pF
3.9
30
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current for AD8057
Quiescent Current for AD8058
Power Supply Rejection Ratio
5.0
6.0
14.0
59
V
7.5
15
mA
mA
dB
VS = 5 V to 1.5 V
54
Specifications subject to change without notice.
–2–
REV. B
AD8057/AD8058
(@ TA = 25؇C, VS = 5 V, RL = 100 ⍀, RF = 0 ⍀, Gain = +1, unless otherwise noted.)
SPECIFICATIONS
AD8057/AD8058
Min Typ
Parameter
Conditions
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VO = 0.2 V p-p
G = +1, VO = 2 V p-p
VO = 0.2 V p-p
G = +1, VO = 2 V Step, RL = 2 kΩ
G = +2, VO = 2 V Step
300
155
28
700
35
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = +2
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
–75
–54
–60
7
dBc
dBc
dB
nV/√Hz
pA/√Hz
%
%
Degree
Degree
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
0.7
Differential Gain Error
0.05
0.05
0.10
0.02
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
1
2.5
3
0.5
3.0
5
mV
mV
µV/°C
µA
T
MIN to TMAX
Input Offset Voltage Drift
Input Bias Current
2.5
TMIN to TMAX
µA
Input Offset Current
Open-Loop Gain
0.75
µA
dB
dB
VO = 1.25 V, RL = 2 kΩ to Midsupply
VO = 1.25 V, RL = 150 Ω to Midsupply
50
45
55
52
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
10
2
MΩ
pF
V
+Input
RL = 1 kΩ
0.9 to 3.4
60
VCM
=
2.5 V
48
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 2 kΩ
RL = 150 Ω
30% Overshoot
0.9 to 4.1
1.2 to 3.8
30
V
V
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
5.0
5.4
13.5
58
V
Quiescent Current for AD8057
Quiescent Current for AD8058
Power Supply Rejection Ratio
7.0
14
mA
mA
dB
54
Specifications subject to change without notice.
REV. B
–3–
AD8057/AD8058
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . . . . . 12.6 V
The maximum power that can be safely dissipated by the
AD8057/AD8058 is limited by the associated rise in junction
temperature. Exceeding a junction temperature of 175°C for an
extended period can result in device failure. While the AD8057/
AD8058 is internally short-circuit protected, this may not be
sufficient to guarantee that the maximum junction temperature
(150°C) is not exceeded under all conditions.
Internal Power Dissipation2
SOIC Package (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W
SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
MSOP Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
To ensure proper operation, it is necessary to observe the maxi-
mum power derating curves.
2.0
T
= 150؇C
J
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
1.5
1.0
0.5
0
8-LEAD SOIC
8-LEAD MSOP
8-Lead SOIC Package: JA = 160°C/W
5-Lead SOT-23-5 Package: JA = 240°C/W
8-Lead MSOP Package: JA = 200°C/W
SOT-23-5
–50 –40 –30 –20 –10
10 20 30 40 50 60 70 80 90
0
AMBIENT TEMPERATURE (؇C)
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
AD8057AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Narrow Body SOIC
Die
8-Lead SOIC, 13" Reel
8-Lead SOIC, 7" Reel
5-Lead SOT-23
5-Lead SOT-23, 13" Reel
5-Lead SOT-23, 7" Reel
5-Lead SOT-23, 7" Reel
8-Lead Narrow Body SOIC
Die
8-Lead SOIC, 13" Reel
8-Lead SOIC, 7" Reel
8-Lead SOIC, 7" Reel
8-Lead MSOP
R-8
Waffle Pak
R-8
Standard
N/A
Standard
Standard
H7A
H7A
H7A
H7A
Standard
N/A
Standard
Standard
Standard
H8A
H8A
H8A
AD8057ACHIPS
AD8057AR-REEL
AD8057AR-REEL7
AD8057ART-R2
AD8057ART-REEL
AD8057ART-REEL7
AD8057ARTZ-REEL7*
AD8058AR
AD8058ACHIPS
AD8058AR-REEL
AD8058AR-REEL7
AD8058ARZ-REEL7*
AD8058ARM
AD8058ARM-REEL
AD8058ARM-REEL7
AD8058ARMZ-REEL7*
R-8
RT-5
RT-5
RT-5
RT-5
R-8
Waffle Pak
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
8-Lead MSOP, 13" Reel
8-Lead MSOP, 7" Reel
8-Lead MSOP, 7" Reel
H8A
*Lead free
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8057/AD8058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. B
Typical Performance Characteristics–AD8057/AD8058
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0
–1.5V SWING R = 150⍀
L
(+) OUTPUT
VOLTAGE
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–2.5V SWING R = 150⍀
L
ABS (–)
OUTPUT
–5V SWING R = 150⍀
L
10
100
1k
LOAD RESISTANCE (⍀)
10k
100k
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 85
TEMPERATURE (؇C)
TPC 1. Output Swing vs. Load Resistance
TPC 4. Negative Output Voltage Swing vs. Temperature
6
4
2
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
V
@ ؎1.5V
OS
–I
@ ؎1.5V
SUPPLY
0
V
@ ؎5V
OS
–I
@ ؎5V
SUPPLY
–2
–4
–6
0
–40 –30 –20 –10
10 20 30 40 50 60 70 80
–40 –30 –20 –10
0
10 20 30 40 50 60 70 8085
TEMPERATURE ( C)
TEMPERATURE (؇C)
TPC 5. VOS vs. Temperature
TPC 2. –ISUPPLY vs. Temperature
3.5
3.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
A
@ ؎5V
VOL
+5V SWING R = 150⍀
L
2.5
2.0
1.5
1.0
A
@ ؎2.5V
VOL
+2.5V SWING R = 150⍀
L
0.5
0
+1.5V SWING R = 150⍀
L
0
–40 –30 –20 –10
10 20 30 40 50 60 70 80 85
–40 –30 –20 –10
0
10 20 30 40 50 60 70 8085
TEMPERATURE (؇C)
TEMPERATURE (؇C)
TPC 6. Open-Loop Gain vs. Temperature
TPC 3. Positive Output Voltage Swing vs. Temperature
REV. B
–5–
AD8057/AD8058
0.00
–0.10
–0.20
–0.30
–0.40
+V
S
4.7F
0.01F
0.001F
HP8130A
PULSE
V
IN
V
GENERATOR
OUT
50⍀
T
/T = 1ns
R
F
AD8057/58
4.7F
0.01F
0.001F
1k⍀
+I @ ؎5V
B
–0.50
–0.60
–0.70
–0.80
+I @ ؎2.5V
B
–I @ ؎2.5V
B
–I @ ؎5V
B
+I @ ؎1.5V
B
–I @ ؎1.5V
B
–V
S
–40 –30 –20 –10
0
10 20 30 40 50 60 70 8085
TEMPERATURE ( C)
TPC 10. Test Circuit G = +1, RL = 1 kΩ for TPCs 11 and 12
TPC 7. Input Bias Current vs. Temperature
4
100mV
3
PSRR @ ؎1.5V ؎5V
20mV/
DIV
2
1
0
–100mV
4ns/DIV
–40 –30 –20 –10
0
10 20 30 40 50 60 70 8085
TEMPERATURE ( C)
TPC 11. Small Signal Step Response G = +1,
RL = 1 kΩ, VS = 5 V
TPC 8. PSRR vs. Temperature
0
–10
–20
–30
–40
–50
–60
5V
1V/DIV
–PSRR V = ؎2.5V
S
+PSRR V = ؎2.5V
S
–5V
4ns/DIV
0.1
1
10
FREQUENCY (MHz)
100
1000
TPC 12. Large Signal Step Response G = +1,
RL = 1 kΩ, VS = 5.0 V
TPC 9. PSRR vs. Frequency
–6–
REV. B
AD8057/AD8058
5
4
1k⍀
3
+V
S
4.7F
2
0.01F
1
0.001F
G = +1
0
HP8130A
PULSE
V
1k⍀
IN
GENERATOR
–1
–2
–3
–4
–5
V
OUT
50⍀
T
/T = 1ns
R
F
AD8057/58
G = +5
4.7F
0.01F
0.001F
1k⍀
G = +2
G = +10
1
10
100
1000
–V
FREQUENCY (MHz)
S
TPC 13. Test Circuit G = –1, RL = 1 kΩ for TPCs 14 and 15
TPC 16. Small Signal Frequency Response,
V
OUT = 0.2 V p-p
5
4
3
100mV
2
1
G = +1
20mV/
DIV
0
G = +5
–1
–2
0V
G = +2
–3
–4
–5
G = +10
1
10
100
1000
–100mV
4ns/DIV
FREQUENCY (MHz)
TPC 17. Large Signal Frequency Response, VOUT = 2 V p-p
TPC 14. Small Signal Step Response G = –1, RL = 1 kΩ
5
4
3
2
5V
1
G = –2
G = –1
0
–1
–2
–3
–4
–5
1V/DIV
G = –5
G = –10
10
1
100
FREQUENCY (MHz)
1000
–5V
4ns/DIV
TPC 18. Large Signal Frequency Response
TPC 15. Large Signal Step Response G = –1, RL = 1 kΩ
REV. B
–7–
AD8057/AD8058
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.5
V
= 0.2V
OUT
G = +2
L
F
0.4
R
R
= 1.0k⍀
= 1.0k⍀
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
FALL TIME
RISE TIME
–0.5
1
0
1
2
3
4
10
100
1000
V
(V p-p)
OUT
FREQUENCY (MHz)
TPC 22. Rise Time and Fall Time vs. VOUT, G = +1,
RL = 1 kΩ, RF = 0 Ω
TPC 19. 0.1 dB Flatness G = +2
5
4
3
–50
–60
–70
–80
THD
SECOND
THIRD
RISE TIME
2
–90
–100
–110
FALL TIME
1
0
0
1
2
3
4
0.1
1
10
FREQUENCY (MHz)
100
V
(V p-p)
OUT
TPC 20. Distortion vs. Frequency, RL = 150 Ω
TPC 23. Rise Time and Fall Time vs. VOUT, G = +2,
RL = 100 Ω, RF = 402 Ω
–40
V
= –1V TO + 1V OR +1V TO –1V
G = +2
OUT
0.4%
0.3%
0.2%
0.1%
0.0%
–0.1%
R
= 100⍀/1k⍀
L
–50
20MHz
–60
5MHz
–0.2%
–0.3%
–0.4%
–70
0
10 20 30 40 50 60
TIME (ns)
–80
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6 4.0
V
(V p-p)
OUT
TPC 21. Distortion vs. VOUT @ 20 MHz, 5 MHz,
TPC 24. Settling Time
RL = 150 Ω, VS = 5.0 V
–8–
REV. B
AD8057/AD8058
1.8V
V
= ؎2.5V
= 1k⍀
V
= ؎2.5V
S
L
S
R
R1 = 1k⍀
G = +4
OUTPUT SIGNAL 1.7V
INPUT SIGNAL
G = +1
2.5V
OUTPUT RESPONSE
500mV/
DIV
200mV/
DIV
INPUT SIGNAL = 0.6V
0V
20ns/DIV
20ns/DIV
TPC 25. Input Overload Recovery, VS = 2.5 V
TPC 28. Output Overload Recovery, VS = 2.5 V
4.5V
V
= ؎5.0V
= 1k⍀
S
L
V
= ؎5.0V
R
S
G = +1
R1 = 1k⍀
G = +4
INPUT SIGNAL 5V
5.0V
1V/DIV
500mV/
DIV
OUTPUT SIGNAL = 4.0V
0V
20ns/DIV
20ns/DIV
37ns
TPC 26. Output Overload Recovery, VS = 5.0 V
TPC 29. Output Overload Recovery, VS = 5.0 V
0
0
–20
–40
–60
–10
–20
–30
–40
–50
–60
–70
SIDE B DRIVEN
–80
SIDE A DRIVEN
–100
–120
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
100
FREQUENCY (MHz)
TPC 27. CMRR vs. Frequency
TPC 30. Crosstalk (Output-to-Output) vs. Frequency
REV. B
–9–
AD8057/AD8058
DIFFERENTIAL GAIN (%)
0.00 –0.00 0.00 0.00 –0.00–0.00–0.00–0.00–0.00 –0.00–0.00
DIFFERENTIAL GAIN (%)
0.00 –0.00–0.00–0.01 –0.01–0.01–0.01–0.01–0.02 –0.03–0.04
0.015
0.010
0.01
0.00
V
R
= +5V
= 150⍀
S
V
= ؎5.0V
= 150⍀
S
L
R
0.005
L
–0.01
–0.02
–0.03
–0.04
–0.05
0.000
–0.005
–0.010
–0.015
DIFFERENTIAL PHASE (Degrees)
0.00 0.00 0.02 0.03 0.05 0.07 0.09 0.10 0.11 0.12 0.13
DIFFERENTIAL PHASE (Degrees)
0.00 0.01 0.03 0.05 0.07 0.09 0.11 0.12 0.12 0.13 0.13
0.14
0.12
0.10
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
0.08
0.06
0.04
0.02
0.00
–0.02
V
R
= ؎5.0V
= 150⍀
S
V
R
= +5V
= 150⍀
S
L
L
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
a.
a.
DIFFERENTIAL GAIN (%)
DIFFERENTIAL GAIN (%)
0.00 0.00 0.00 0.01 0.01 0.00 0.00 0.00 –0.00 –0.01–0.01
0.00 0.01 –0.00–0.01 –0.01–0.01–0.02–0.02–0.03 –0.04–0.05
0.015
0.010
0.01
0.00
V
= +5V
S
V
= ؎5.0V
= 1k⍀
S
R
= 1k⍀
L
R
L
0.005
–0.01
–0.02
–0.03
–0.04
–0.05
0.000
–0.005
–0.010
–0.015
DIFFERENTIAL PHASE (Degrees)
0.00 0.00 0.00 –0.00 –0.00 –0.00 –0.01 –0.01–0.01 –0.01 –0.01`
DIFFERENTIAL PHASE (Degrees)
0.00 –0.00 0.00 0.00 –0.00–0.00–0.00 –0.00–0.01 –0.01–0.02
0.14
0.12
0.10
0.14
0.12
0.10
V
= +5V
V
= ؎5.0V
= 1k⍀
S
S
R
= 1k⍀
R
L
L
0.08
0.06
0.04
0.02
0.00
–0.02
0.08
0.06
0.04
0.02
0.00
–0.02
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
b.
b.
TPC 31. Differential Gain and Differential Phase
One Back Terminated Load (150 Ω) (Video Op
Amps Only)
TPC 33. Differential Gain and Differential Phase,
a. RL = 150 Ω, b. RL = 1 kΩ
180
100
10
1
80
60
40
20
0
135
90
45
0
–45
–90
–20
1000
0.1
10
100
1k
10k
100k
1M
10M
100M
0.01
0.1
1
10
100
FREQUENCY (Hz)
FREQUENCY (MHz)
TPC 32. Open-Loop Gain and Phase vs. Frequency
TPC 34. Voltage Noise vs. Frequency
–10–
REV. B
AD8057/AD8058
100
10
1
100
10
1
0.1
0.1
0.1
10
100
1k
10k
100k
1M
10M
100M
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (MHz)
TPC 35. Current Noise vs. Frequency
TPC 36. Output Impedance vs. Frequency
APPLICATIONS
Driving Capacitive Loads
Table I. Recommended Value for Resistors RS, RF, RG vs.
Capacitive Load, CL, Which Results in 30% Overshoot
When driving a capacitive load, most op amps will exhibit over-
shoot in their pulse response.
Gain
RF
(Ω)
RG
(Ω)
CL w/RS = 0 Ω
CL w/RS = 2.4 Ω
(pF)
(pF)
Figure 3 shows the relationship between the capacitive load
that results in 30% overshoot and the closed-loop gain of an
AD8058. It can be seen that, under the Gain = +2 condition,
the device is stable with capacitive loads of up to 69 pF.
1
2
3
4
5
10
100
100
100
100
100
100
11
51
104
186
245
870
13
69
153
270
500
1580
100
50
33.2
25
In general, to minimize peaking or to ensure device stability for
larger values of capacitive loads, a small series resistor, RS, can
be added between the op amp output and the load capacitor,
CL, as shown in Figure 4.
11
R
F
For the setup shown in Figure 4, the relationship between RS
and CL was empirically derived and is shown in Table I.
+2.5V
0.1F
10F
500
400
300
200
R
G
FET PROBE
R
S
V
OUT
AD8058
V
= 200mV p-p
IN
C
L
50k⍀
0.1F
10F
–2.5V
R
= 2.4⍀
S
Figure 4. Capacitive Load Drive Circuit
100
0
R
= 0⍀
S
+ OVERSHOOT
29.0%
1
2
3
4
5
200mV
100mV
CLOSED-LOOP GAIN
Figure 3. Capacitive Load Drive vs. Closed-Loop Gain
–100mV
–200mV
100mV/DIV
50ns/DIV
Figure 5. Typical Pulse Response with CL = 65 pF,
Gain = +2, and VS = 2.5 V
REV. B
–11–
AD8057/AD8058
Video Filter
Differential A-to-D Driver
Some composite video signals that are derived from a digital
source contain some clock feedthrough that can cause problems
with downstream circuitry. This clock feedthrough is usually at
27 MHz, which is a standard clock frequency for both NTSC
and PAL video systems. A filter that passes the video band and
rejects frequencies at 27 MHz can be used to remove these
frequencies from the video signal.
As system supply voltages are dropping, many ADCs provide
differential analog inputs to increase the dynamic range of the
input signal while still operating on a low supply voltage. Differ-
ential driving can also reduce second and other even-order
distortion products.
Analog Devices offers an assortment of 12- and 14-bit high
speed converters that have differential inputs and can be run
from a single 5 V supply. These include the AD9220, AD9221,
AD9223, AD9224, and AD9225 at 12 bits, and the AD9240,
AD9241, and AD9243 at 14 bits. Although these devices can
operate over a range of common-mode voltages at their analog
inputs, they work best when the common-mode voltage at the
input is at the midsupply or 2.5 V.
Figure 6 shows a circuit that uses an AD8057 to create a single
5 V supply, 3-pole Sallen-Key filter. This circuit uses a single
RC pole in front of a standard 2-pole active section. To shift the
dc operating point to midsupply, ac coupling is provided by R4,
R5, and C4.
C2
680pF
Op amp architectures that require upwards of 2 V of headroom
at the output have significant problems when trying to drive
such ADCs while operating with a 5 V positive supply. The low
headroom output design of the AD8057 and AD8058 make
them ideal for driving these types of ADCs.
R
F
1k⍀
+5V
7
+
0.1F
10F
+5V
R4
2
3
The AD8058 can be used to make a dc-coupled, single-ended-
to-differential driver for one of these ADCs. Figure 8 is a
schematic of such a circuit for driving an AD9225, 12-bit,
25 MSPS ADC.
C4
6
R1
200⍀
R2
499⍀
R3
49.9⍀
AD8057
4
10k⍀
0.1F
C1
100pF
C3
36pF
R5
10k⍀
1k⍀
+2.5V
+
+5V
10F
0.1F
Figure 6. Low-Pass Filter for Video
+5V
+
10F
0.1F
Figure 7 shows a frequency sweep of this filter. The response is
down 3 dB at 5.7 MHz, so it passes the video band with little
attenuation. The rejection at 27 MHz is 42 dB, which provides
more than a factor of 100 in suppression of the clock compo-
nents at this frequency.
8
1k⍀
1k⍀
3
2
REF
50⍀
1
V
IN
VINA
AD8058
0V
1k⍀
AD9225
10
0
1k⍀
1k⍀
1k⍀
6
5
50⍀
7
VINB
AD8058
–10
–20
4
10F
0.1F
1k⍀
+
–30
–40
–50
–60
–70
–80
–90
–5V
Figure 8. Schematic Circuit for Driving AD9225
In this circuit, one of the op amps is configured in the inverting
mode, while the other is in the noninverting mode. However, to
provide better bandwidth matching, each op amp is configured
for a noise gain of +2. The inverting op amp is configured for a
gain of –1, while the noninverting op amp is configured for a
gain of +2. Each of these produces a noise gain of +2, which is
only determined by the inverse of the feedback ratio. The input
signal to the noninverting op amp is divided by 2 in order to
normalize its level and make it equal to the inverting output.
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 7. Video Filter Response
–12–
REV. B
AD8057/AD8058
For 0 V input, the outputs of the op amps want to be at 2.5 V,
which is the midsupply level of the ADCs. This is accomplished by
first taking the 2.5 V reference output of the ADC and divid-
ing it by two by a pair of 1 kΩ resistors. The resulting 1.25 V is
applied to each op amp’s positive input. This voltage is then
multiplied by the gain of +2 of the op amps to provide a 2.5 V
level at each output.
not have this problem because its common-mode input voltage
remains fixed at 1.25 V. If dc coupling is not required, various
ac coupling techniques can be used to eliminate this problem.
Layout
The AD8057 and AD8058 are high speed op amps and should
be used in a board layout that follows standard high speed design
rules. All the signal traces should be as short and direct as pos-
sible. In particular, the parasitic capacitance on the inverting
input of each device should be kept to a minimum to avoid
excessive peaking and other undesirable performance.
The assumption for this circuit is that the input signal is bipolar
with respect to ground and the circuit must be dc-coupled. This
implies the existence of a negative supply elsewhere in the sys-
tem. This circuit uses –5 V as the negative supply for the AD8058.
The power supplies should be bypassed very close to the power
pins of the package with 0.1 µF in parallel with a larger, approxi-
mately 10 µF tantalum capacitor. These capacitors should be
connected to a ground plane that is either on an inner layer or
fills the area of the board that is not used for other signals.
If the AD8058 negative supply were tied to ground, there would
be a problem at the input of the noninverting op amp. The
input common-mode voltage can only go to within 1 V of the
negative rail. Since this circuit requires that the positive inputs
operate with a 1.25 V bias, there is not enough room to swing
this voltage in the negative direction. The inverting stage does
REV. B
–13–
AD8057/AD8058
OUTLINE DIMENSIONS
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC]
(R-8)
(RM-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
3.00
BSC
8
1
5
4
8
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
4.90
BSC
3.00
BSC
1
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
؋
45؇ PIN 1
1.75 (0.0688)
1.35 (0.0532)
0.65 BSC
0.25 (0.0098)
0.10 (0.0040)
1.10 MAX
0.15
0.00
8؇
0.51 (0.0201)
0.31 (0.0122)
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
0.80
0.60
0.40
SEATING
PLANE
0.40 (0.0157)
8؇
0؇
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012AA
SEATING
PLANE
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-187AA
5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
2.90 BSC
5
1
4
3
2.80 BSC
1.60 BSC
2
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
10؇
5؇
0؇
0.15 MAX
0.60
0.45
0.30
0.50
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
–14–
REV. B
AD8057/AD8058
Revision History
Location
Page
8/03—Data Sheet changed from REV. A to REV. B.
Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REV. B
–15–
–16–
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