AD8061ART-R2 [ADI]
Low Cost, 300 MHz Rail-to-Rail Amplifiers; 低成本， 300 MHz轨到轨放大器
| 型号： | AD8061ART-R2 |
| 厂家： | 
ADI |
| 描述： | Low Cost, 300 MHz Rail-to-Rail Amplifiers |
| 文件： | 总20页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, 300 MHz
Rail-to-Rail Amplifiers
AD8061/AD8062/AD8063
FEATURES
APPLICATIONS
Low cost
Imaging
Single (AD8061), dual (AD8062)
Single with disable (AD8063)
Rail-to-rail output swing
Photodiode preamps
Professional video and cameras
Hand sets
Low offset voltage: 6 mV
DVDs/CDs
High speed
300 MHz, −3 dB bandwidth (G = 1)
650 V/μs slew rate
Base stations
Filters
ADC drivers
8.5 nV/√Hz at 5 V
CONNECTION DIAGRAMS
35 ns settling time to 0.1% with 1 V step
Operates on 2.7 V to 8 V supplies
Input voltage range = −0.2 V to +3.2 V with VS = 5
Excellent video specs (RL = 150 Ω, G = 2)
Gain flatness 0.1 dB to 30 MHz
0.01% differential gain error
0.04° differential phase error
35 ns overload recovery
AD8062
AD8061/
AD8063
V
+V
V
1
2
3
4
8
7
6
5
OUT1
–IN1
S
DISABLE
1
2
3
4
8
7
6
5
NC
–IN
+IN
(AD8063 ONLY)
OUT2
+V
V
S
–IN2
+IN2
+IN1
OUT
–V
NC
S
–V
S
(Not to Scale)
(Not to Scale)
NC = NO CONNECT
Figure 1. 8-Lead SOIC (R)
Figure 2. 8-Lead SOIC (R)/MSOP (RM)
Low power
6.8 mA/amplifier typical supply current
AD8063 400 μA when disabled
AD8061
AD8063
V
+V
S
1
2
3
6
5
4
V
5
+V
S
OUT
1
2
3
OUT
–V
S
DISABLE
–IN
–V
S
+IN
4
–IN
+IN
(Not to Scale)
(Not to Scale)
Figure 3. 6-Lead SOT-23 (RT)
Figure 4. 5-Lead SOT-23 (RT)
GENERAL DESCRIPTION
The AD8061, AD8062, and AD8063 are rail-to-rail output
voltage feedback amplifiers offering ease of use and low cost.
They have bandwidth and slew rate typically found in current
feedback amplifiers. All have a wide input common-mode
voltage range and output voltage swing, making them easy to
use on single supplies as low as 2.7 V.
3
0
R
= 50Ω
F
V
R
= 0.2V p-p
= 1kΩ
= 1V
O
R
= 0Ω
L
F
V
BIAS
–3
–6
Despite being low cost, the AD8061, AD8062, and AD8063
provide excellent overall performance. For video applications
their differential gain and phase errors are 0.01% and 0.04° into
a 150 Ω load, along with 0.1 dB flatness out to 30 MHz. Addi-
tionally, they offer wide bandwidth to 300 MHz along with
650 V/μs slew rate.
R
F
OUT
IN
R
L
50Ω
–9
±
V
BIAS
–12
The AD8061, AD8062, and AD8063 offer a typical low power
of 6.8 mA/amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400 μA. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.
1
10
100
1k
FREQUENCY (MHz)
Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD8061/AD8062/AD8063
TABLE OF CONTENTS
Features .............................................................................................. 1
Overload Behavior and Recovery ............................................ 15
Capacitive Load Drive ............................................................... 15
Disable Operation ...................................................................... 16
Board Layout Considerations................................................... 16
Applications..................................................................................... 17
Single-Supply Sync Stripper...................................................... 17
RGB Amplifier............................................................................ 17
Multiplexer .................................................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Circuit Description......................................................................... 14
Headroom Considerations........................................................ 14
REVISION HISTORY
12/05—Rev. C to Rev. D
Updated Format..................................................................Universal
Change to Features and General Description............................... 1
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
5/01—Rev. B to Rev. C
Replaced TPC 9 with new graph .................................................... 7
11/00—Rev. A to Rev. B
2/00—Rev. 0 to Rev. A
11/99—Revision 0: Initial Version
Rev. D | Page 2 of 20
AD8061/AD8062/AD8063
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
150
60
320
115
280
30
650
500
35
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
G = 1, VO = 0.2 V p-p
G = 1, VO = 2 V step, RL = 2 kΩ
G = 2, VO = 2 V step, RL = 2 kΩ
G = 2, VO = 2 V step
500
300
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2, AD8062
f = 100 kHz
f = 100 kHz
G = 2, RL = 150 Ω
G = 2, RL = 150 Ω
f = 10 MHz
f = 5 MHz
−77
−50
−90
8.5
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dBc
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Third Order Intercept
SFDR
1.2
0.01
0.04
28
62
dB
DC PERFORMANCE
Input Offset Voltage
1
2
3.5
3.5
4
6
6
mV
mV
μV/°C
μA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
9
9
TMIN to TMAX
μA
Input Offset Current
Open-Loop Gain
0.3
70
90
4.5
μA
dB
dB
VO = 0.5 V to 4.5 V, RL = 150 Ω
VO = 0.5 V to 4.5 V, RL = 2 kΩ
68
74
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing—Load Resistance
Is Terminated at Midsupply
Output Current
13
1
MΩ
pF
V
−0.2 to +3.2
80
VCM = –0.2 V to +3.2 V
62
dB
RL = 150 Ω
RL = 2 kΩ
VO = 0.5 V to 4.5 V
30% overshoot: G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
0.3
0.25
25
0.1 to 4.5
0.1 to 4.9
50
25
300
4.75
4.85
V
V
mA
pF
pF
Capacitive Load Drive, VOUT = 0.8 V
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off
DISABLE Voltage—On
40
ns
ns
V
300
2.8
3.2
V
POWER SUPPLY
Operating Range
2.7
72
5
8
9.5
V
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6.8
0.4
80
mA
mA
dB
∆VS = 2.7 V to 5 V
Rev. D | Page 3 of 20
AD8061/AD8062/AD8063
TA = 25°C, VS = 3 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
150
60
300
115
250
30
280
230
40
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
–3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
G = 1, VO = 0.2 V p-p
G = 1, VO = 1 V step, RL = 2 kΩ
G = 2, VO = 1.5 V step, RL = 2 kΩ
G = 2, VO = 1 V step
190
180
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2
f = 100 kHz
f = 100 kHz
−60
−44
−90
8.5
dBc
dBc
dBc
nV/√Hz
pA/√Hz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
1.2
DC PERFORMANCE
Input Offset Voltage
1
2
6
6
mV
mV
μV/°C
μA
μA
μA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
3.5
3.5
4
0.3
70
90
8.5
8.5
4.5
TMIN to TMAX
Input Offset Current
Open-Loop Gain
VO = 0.5 V to 2.5 V, RL = 150 Ω
VO = 0.5 V to 2.5 V, RL = 2 kΩ
66
74
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
13
1
MΩ
pF
V
−0.2 to +12
80
VCM = –0.2 V to +1.2 V
dB
RL = 150 Ω
RL = 2 kΩ
VO = 0.5 V to 2.5 V
30% overshoot, G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
0.3
0.3
0.1 to 2.87
0.1 to 2.9
25
25
300
2.85
2.90
V
V
mA
pF
pF
Output Current
Capacitive Load Drive, VOUT = 0.8 V
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off
DISABLE Voltage—On
40
ns
ns
V
300
0.8
1.2
V
POWER SUPPLY
Operating Range
2.7
72
3
9
V
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6.8
0.4
80
mA
mA
dB
Rev. D | Page 4 of 20
AD8061/AD8062/AD8063
TA = 25°C, VS = 2.7 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
G = 1, VO = 0.2 V p-p, VO dc = 1 V
G = 1, VO = 0.7 V step, RL = 2 kΩ
G = 2, VO = 1.5 V step, RL = 2 kΩ
G = 2, VO = 1 V step
150
60
300
115
230
30
150
130
40
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
110
95
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2
f = 100 kHz
f = 100 kHz
–60
–44
–90
8.5
dBc
dBc
dBc
nV/√Hz
pA/√Hz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
1.2
DC PERFORMANCE
Input Offset Voltage
1
2
6
6
mV
mV
μV/°C
μA
μA
μA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
3.5
3.5
4
0.3
70
90
TMIN to TMAX
8.5
4.5
Input Offset Current
Open-Loop Gain
VO = 0.5 V to 2.2 V, RL = 150 Ω
VO = 0.5 V to 2.2 V, RL = 2 kΩ
63
74
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
13
1
MΩ
pF
V
–0.2 to +0.9
0.8
VCM = –0.2 V to +0.9 V
dB
RL = 150 Ω
RL = 2 kΩ
VO = 0.5 V to 2.2 V
30% overshoot: G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
0.3
0.25
0.1 to 2.55
0.1 to 2.6
25
2.55
2.6
V
V
mA
pF
pF
Output Current
Capacitive Load Drive, VOUT = 0.8 V
25
300
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
40
ns
ns
V
300
0.5
0.9
DISABLE
DISABLE
Voltage—Off
Voltage—On
V
POWER SUPPLY
Operating Range
2.7
8
V
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6.8
0.4
80
8.5
mA
mA
dB
Rev. D | Page 5 of 20
AD8061/AD8062/AD8063
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Internal Power Dissipation1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Rating
8 V
8-lead SOIC (R)
0.8 W
0.5 W
0.5 W
0.6 W
5-lead SOT-23 (RT)
6-lead SOT-23 (RT)
8-lead MSOP (RM)
MAXIMUM POWER DISSIPATION
Input Voltage (Common-Mode)
(−VS − 0.2 V) to (+VS − 1.8 V)
The maximum power that can be safely dissipated by the
AD806x is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of 175°C for an extended period can result in
device failure. While the AD806x is internally short-circuit
protected, this may not be sufficient to guarantee that the
maximum junction temperature (150°C) is not exceeded
under all conditions.
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
R-8, RM-8, SOT-23-5, SOT-23-6
Operating Temperature Range −40°C to +85°C
VS
Observe Power Derating Curves
−65°C to +125°C
Lead Temperature Range
(Soldering 10 sec)
300°C
1Specification is for device in free air.
8-Lead SOIC: θJA = 160°C/W; θJC = 56°C/W.
5-Lead SOT-23: θJA = 240°C/W; θJC = 92°C/W.
6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.
8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W.
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
2.0
T
= 150°C
8-LEAD SOIC
PACKAGE
J
1.5
1.0
0.5
0
MSOP
SOT-23-5, -6
–50 –40 –30
90
–20 –10
0
10 20 30 40 50 60 70 80
C)
AMBIENT TEMPERATURE (
°
Figure 6. Maximum Power Dissipation vs. Temperature for
AD8061/AD8062/AD8063
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 6 of 20
AD8061/AD8062/AD8063
TYPICAL PERFORMANCE CHARACTERISTICS
3
1.2
G = 1
1.0
+V
@ +85°C
OUT
0
–3
–6
+V
@ +25°C
OUT
0.8
0.6
0.4
0.2
0
G = 2
G = 5
+V
@ –40
°
C
OUT
–V
@ –40°C
OUT
V
R
V
= 0.2V p-p
= 1kΩ
O
–9
–V
@ +85
80
°C
L
OUT
= 1V
BIAS
–V
@ +25°C
OUT
50
–12
1
1
1
10
100
1k
1k
1k
10
20
30
40
60
70
90
0
FREQUENCY (MHz)
LOAD CURRENT (mA)
Figure 7. Output Saturation Voltage vs. Load Current
Figure 10. Small Signal Frequency Response
18
16
14
12
10
8
3
V
R
V
= 1.0V p-p
= 1kΩ
O
AD8062
L
G = 1
= 1V
BIAS
0
–3
–6
G = 2
AD8061
G = 5
6
4
–9
2
0
–12
5
8
2
3
4
6
7
10
100
SINGLE POWER SUPPLY (V)
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response
Figure 8. ISUPPLY vs. VSUPPLY
3
3
R
= 50Ω
F
V
V
= 5V
= 0.2V p-p
S
O
0
–3
–6
R
= 1kΩ
L
V
R
V
= 0.2V p-p
= 1kΩ
= 1V
0
–3
–6
O
V
= 1V
BIAS
R
= 0Ω
L
F
BIAS
G = –1
G = –2
G = –5
R
F
R
F
OUT
IN
OUT
R
L
IN
R
50
Ω
L
–9
50
Ω
–9
V
BIAS
V
BIAS
–12
1
10
100
1k
–12
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Small Signal Response, RF = 0 Ω, 50 Ω
Figure 12. Small Signal Frequency Response
Rev. D | Page 7 of 20
AD8061/AD8062/AD8063
3
0
V
V
R
= 5V
= 1V p-p
= 1kΩ
V
= 5V
S
S
–10
R
= 1kΩ
O
L
G = 1
L
–20
–30
0
V
= 1V
BIAS
G = –1
2ND @ 1MHz
–3
–40
–50
3RD @ 10MHz
G = –2
–6
–60
–70
G = –5
–9
–80
–90
3RD @ 1MHz
2.5
2ND @ 10MHz
1.5 2.0
–12
–100
0.5
1.0
3.5
1
3.0
10
100
1k
FREQUENCY (MHz)
INPUT SIGNAL BIAS (V)
Figure 13. Large Signal Frequency Response
Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias
–40
0.1
0
604
Ω
V
R
V
G = 1
= 0.2V p-p
= 1kΩ
V
= 2.7V
O
S
10μF
5V
L
+
–50
–60
= 1V
BIAS
0.1μF
1kΩ
50
Ω
1MΩ INPUT
52.3Ω
–0.1
–0.2
0.1
1.25V
μF
+
–
1k
(R
Ω
LOAD
V
= 5V
S
dc
)
–70
–80
V
= 3V
S
2ND H
–0.3
–0.4
–90
–100
–110
3RD H
–0.5
1
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)
50
1
0.01
0.1
10
100
1k
10
FREQUENCY (MHz)
Figure 14. 0.1 dB Flatness
Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs.
Input Signal DC Bias
80
200
150
100
50
–30
V
R
= 5V
= 1kΩ
S
L
–40
–50
G = 5
= 1V p-p
60
40
V
SERIES 1
O
2ND
3RD
10MHz
–60
SERIES 2
0
–70
20
–50
–100
–150
–200
–250
–300
–80
2ND
0
–90
3RD
2ND
5MHz
–100
–110
–120
1MHz
– 20
3RD
– 40
0.01
0.1
1
10
100
1k
0
1
5
2
3
4
FREQUENCY (MHz)
OUTPUT SIGNAL DC BIAS (V)
Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency,
VS = 5 V, RL = 1 kΩ
Figure 18. Harmonic Distortion vs. Output Signal DC Bias
Rev. D | Page 8 of 20
AD8061/AD8062/AD8063
–40
–50
V
R
G = 2
= 5V
S
0.01
0
= R = 1kΩ
F
L
2ND @ 10MHz
–0.01
–0.02
–0.04
–0.06
–60
–70
–80
–90
5V
+
10
0.1
1k
μF
1M
INPUT
TO
Ω
μ
F
50
Ω
Ω
50
Ω
Ω
2ND @ 2MHz
1k
Ω
3589A
1k
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
2ND @ 500kHz
0.02
0
3RD @ 2MHz
–0.02
–0.04
–0.06
–100
–110
3RD @ 500kHz
1.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
RTO OUTPUT (V p-p)
Figure 19. Harmonic Distortion vs. Output Signal Amplitude
Figure 22. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 1 kΩ, VS = 5 V
–30
V
= 5V
S
R = R = 1k
Ω
I
L
0.010
0.005
0
–40
–50
–60
V
= 2V p-p
O
G = 2
S1 3RD HARMONIC/
DUAL 2.5V SUPPLY
–0.005
–0.010
±
S1 2ND HARMONIC/
DUAL 2.5V SUPPLY
–70
–80
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
±
S1 2ND HARMONIC/
SINGLE +5V SUPPLY
0.04
0.03
0.02
0.01
0
–90
–100
–110
S1 3RD HARMONIC/
SINGLE +5V SUPPLY
–0.01
–0.02
0.01
0.1
1
10
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)
Figure 20. Harmonic Distortion vs. Frequency
Figure 23. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 150 Ω, VS = 5 V
1.0
1000
V
= 5V
S
FALLING EDGE
R
G = 1
= 1kΩ
0.9
0.8
L
900
800
700
600
500
V
R
G = 1
= 5V
= 1kΩ
S
L
0.7
0.6
RISING EDGE
0.5
0.4
0.3
0.2
0.1
400
300
200
100
0
0
0
0.1
0.2
TIME (μs)
0.3
0.4
0.5
1.5
OUTPUT STEP AMPLITUDE (V)
3.0
1.0
2.0
2.5
Figure 21. 400 mV Pulse Response
Figure 24. Slew Rate vs. Output Step Amplitude
Rev. D | Page 9 of 20
AD8061/AD8062/AD8063
1400
V
= ±2.5V
S
G = 1
= 1kΩ
FALLING EDGE
V
R
IN
L
1200
1000
800
V
= ±4V
S
2.5V
FALLING EDGE
= +5V
V
S
V
OUT
600
400
200
0
RISING EDGE
V
= ±4V
S
0V
RISING EDGE
V
= +5V
S
500mV/DIV
0
20
40
60
80 100 120 140 160
TIME (ns)
180 200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT STEP (V)
Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V
Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, RL = 1 kΩ, VS = 5 V
1k
V
= ±2.5V
S
G = 5
= 1kΩ
V
R
= 5V
= 1kΩ
S
R
L
L
V
OUT
2.5V
1.0V
100
10
1
V
IN
0V
500mV/DIV
0
20
40
60
80 100 120 140 160
TIME (ns)
180 200
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 29. Output Overload Recovery, Input Step = 0 V to 1 V
Figure 26. Voltage Noise vs. Frequency
0
100
10
1
V
= 0.2V p-p
CM
–10
–20
–30
R
V
= 100
Ω
V
R
= 5V
= 1kΩ
L
S
= ±2.5V
SIDE 2
S
L
SIDE 1
–40
–50
–60
–70
–80
–90
–100
604
Ω
604
Ω
50
Ω
V
154
Ω
IN
200mV p-p
154
Ω
57.6
Ω
0
10
0.01
0.1
1
10
100
500
10M
100
1k
10k
100k
1M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 27. Current Noise vs. Frequency
Figure 30. CMRR vs. Frequency
Rev. D | Page 10 of 20
AD8061/AD8062/AD8063
0
–10
–20
7
6
5
4
3
2
1
0
Δ
V = 0.2V p-p
S
V
= 5V
S
R
= 1kΩ
= 5V
L
S
V
–PSRR
+PSRR
–30
–40
–50
–60
–70
–80
–90
–100
0.01
0.1
1
10
100
500
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
DISABLE VOLTAGE
Figure 31. PSRR vs. Frequency Delta
DISABLE
Voltage vs. Supply Current
Figure 34.
–20
–30
6
5
V
G = 2
= 5V
1kΩ
1kΩ
S
V
+2.5V
f
= 10MHz
@ 1.3V
DISABLE
IN
–40
BIAS
R
= 100Ω
L
OUT
–50
4
IN
1k
Ω
50Ω
–60
–2.5V
3
–70
INPUT = SIDE 2
INPUT = SIDE 1
2
–80
–90
V
V
= 5V
S
1
= 400mV rms
IN
–100
–110
–120
R
G = 2
= 1kΩ
L
0
V
OUT
–1
0.01
0.1
1
10
100
500
0
0.4
0.8
1.2
1.6
2.0
FREQUENCY (MHz)
TIME (μs)
Figure 32. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 kΩ, G = 2, VS = 5 V
DISABLE
Function, Voltage = 0 V to 5 V
Figure 35.
1k
100
10
0
V
V
R
= 5V
= 0.2V p-p
= 1kΩ
= 1V
V
V
R
V
= 5V
= 0.2V p-p
= 1kΩ
S
S
O
O
–10
–20
–30
–40
–50
–60
–70
–80
–90
L
L
V
= 1V
BIAS
BIAS
1
0.1
0.01
0.1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. Output Impedance vs. Frequency,
VOUT = 0.2 V p-p, RL = 1 kΩ, VS = 5 V
Figure 33. Disabled Output Isolation Frequency Response
Rev. D | Page 11 of 20
AD8061/AD8062/AD8063
V
R
= 5V
= 1kΩ
V
G = 2
= 5V
S
S
L
R
= 1kΩ
L
V
= 1V p-p
IN
3.5V
2.5V
1.5V
+0.1%
–0.1%
1kΩ
1kΩ
R
= 1kΩ
L
50Ω
500mV/DIV
10 20
t = 0
0
30
40
50
60
70
80
90
100
20ns/DIV
TIME (ns)
Figure 37. Output Settling Time to 0.1%
Figure 40. 1 V Step Response
50
45
40
35
30
25
20
15
10
5
V
G = 2
R
V
= 5V
S
FALLING EDGE
= 1kΩ
= 100mV
L
2.6V
IN
RISING EDGE
2.5V
2.4V
V
R
G = 1
= 5V
= 1kΩ
S
L
20mV/DIV
0
0.5
0
10
20
30
40
50
60
70
80
90
100
1.0
1.5
OUTPUT VOLTAGE STEP
2.0
2.5
TIME (ns)
Figure 41. 100 mV Step Response
Figure 38. Settling Time vs. VOUT
V
= 5V
S
G = –1
V
G = 2
R
V
= 5V
S
R
R
= 1kΩ
= 1kΩ
F
L
= R = 1kΩ
F
L
= 4V p-p
IN
4.86
2.43
0V
0V
1V
2μs
2μs/DIV
1V/DIV
Figure 39. Output Swing
Figure 42. Output Rail-to-Rail Swing
Rev. D | Page 12 of 20
AD8061/AD8062/AD8063
V
G = 2
R
V
= 5V
S
V
G = 1
R
= 5V
S
= R = 1kΩ
L
F
= 1kΩ
L
= 2V p-p
IN
2.6V
2.5V
2.4V
4.5V
2.5V
0.5V
50mV/DIV
10
1V/DIV
5
0
5
15
20
25
30
35
40
45
50
0
10
15
20
25
30
35
40
45
50
TIME (ns)
TIME (ns)
Figure 44. 2 V Step Response
Figure 43. 200 mV Step Response
Rev. D | Page 13 of 20
AD8061/AD8062/AD8063
CIRCUIT DESCRIPTION
The AD8061/AD8062/AD8063 family is comprised of high
speed voltage feedback op amps. The high slew rate input stage
is a true, single-supply topology, capable of sensing signals at or
below the minus supply rail. The rail-to-rail output stage can
pull within 30 mV of either supply rail when driving light loads
and within 0.3 V when driving 150 Ω. High speed perform-
ance is maintained at supply voltages as low as 2.7 V.
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
–2.8
–3.2
–3.6
–4.0
HEADROOM CONSIDERATIONS
These amplifiers are designed for use in low voltage systems.
To obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier’s headroom limits.
–0.5
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
4.0
CM
The AD806x’s input common-mode voltage range extends
from the negative supply voltage (actually 200 mV below this),
or ground for single-supply operation, to within 1.8 V of the
positive supply voltage. Thus, at a gain of 2, the AD806x can
provide full rail-to-rail output swing for supply voltage as low as
3.6 V, assuming the input signal swing from −VS (or ground) to
+VS/2. At a gain of 3, the AD806x can provide a rail-to-rail
output range down to 2.7 V total supply voltage.
Figure 45. VOS vs. Common-Mode Voltage, VS = 5 V
2
0
V
V
V
V
V
= 3.0
= 3.1
= 3.2
= 3.3
= 3.4
CM
CM
CM
CM
CM
–2
–4
–6
–8
Exceeding the headroom limit is not a concern for any inverting
gain on any supply voltage, as long as the reference voltage at
the amplifier’s positive input lies within the amplifier’s input
common-mode range.
0.1
1
10
100
1k
10k
The input stage is the headroom limit for signals when the
amplifier is used in a gain of 1 for signals approaching the
positive rail. Figure 45 shows a typical offset voltage vs.
input common-mode voltage for the AD806x amplifier on
a 5 V supply. Accurate dc performance is maintained from
approximately 200 mV below the minus supply to within
1.8 V of the positive supply. For high-speed signals, however,
there are other considerations. Figure 46 shows −3 dB
bandwidth vs. dc input voltage for a unity-gain follower. As
the common-mode voltage approaches the positive supply,
the amplifier holds together well, but the bandwidth begins to
drop at 1.9 V within +VS.
FREQUENCY (MHz)
Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V
Higher frequency signals require more headroom than lower
frequencies to maintain distortion performance. Figure 47
illustrates how the rising edge settling time for the amplifier
configured as a unity-gain follower stretches out as the top of
a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.
For signals approaching the minus supply and inverting gain
and high positive gain configurations, the headroom limit is
the output stage. The AD806x amplifiers use a common emitter
style output stage. This output stage maximizes the available
output range, limited by the saturation voltage of the output
transistors. The saturation voltage increases with the drive
current the output transistor is required to supply, due to the
output transistors’ collector resistance. The saturation voltage is
estimated using the equation VSAT = 25 mV + IO × 8 Ω, where IO
is the output current, and 8 Ω is a typical value for the output
transistors’ collector resistance.
This manifests itself in increased distortion or settling time.
Figure 16 plots the distortion of a 1 V p-p signal with the
AD806x amplifier used as a follower on a 5 V supply vs. signal
common-mode voltage. Distortion performance is maintained
until the input signal center voltage gets beyond 2.5 V, as the
peak of the input sine wave begins to run into the upper
common-mode voltage limit.
Rev. D | Page 14 of 20
AD8061/AD8062/AD8063
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.7
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
VOLTAGE STEP
FROM 2.4V TO 3.4V
2V TO 3V STEP
2.1V TO 3.1V STEP
VOLTAGE STEP
FROM 2.4V TO 3.6V
2.2V TO 3.2V STEP
2.3V TO 3.3V STEP
VOLTAGE STEP
FROM 2.4V TO 3.8V,
4V AND 5V
2.4V TO 3.4V STEP
0
100
200
300
400
500
600
0
4
8
12
16
20
24
28
32
TIME (ns)
TIME (ns)
Figure 48. Pulse Response for G = 1 Follower,
Input Step Overloading the Input Stage
Figure 47. Output Rising Edge for 1 V Step at
Input Headroom Limits, G = 1, VS = 5 V, 0 V
Output
As the saturation point of the output stage is approached, the
output signal shows increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than lower frequency
signals. Figure 16, Figure 17, and Figure 18 illustrate this point,
plotting typical distortion vs. output amplitude and bias for
gains of 2 and 5.
Output overload recovery is typically within 40 ns after the
amplifier’s input is brought to a nonoverloading value. Figure 49
shows output recovery transients for the amplifier recovering
from a saturated output from the top and bottom supplies to a
point at midsupply.
5.0
4.6
OVERLOAD BEHAVIOR AND RECOVERY
Input
OUTPUT VOLTAGE
4.2
5V TO 2.5V
3.8
OUTPUT VOLTAGE
3.4
The specified input common-mode voltage of the AD806x
is −200 mV below the negative supply to within 1.8 V of
the positive supply. Exceeding the top limit results in lower
bandwidth and increased settling time as seen in Figure 46
and Figure 47. Pushing the input voltage of a unity-gain
follower beyond 1.6 V within the positive supply leads to the
behavior shown in Figure 48—an increasing amount of output
error and much increased settling time. Recovery time from
input voltages 1.6 V or closer to the positive supply is approxi-
mately 35 ns, which is limited by the settling artifacts caused by
transistors in the input stage coming out of saturation.
0V TO 2.5V
3.0
2.6
2.2
1.8
1.4
1.0
INPUT VOLTAGE
EDGES
R
5V
R
V
–
IN
2.5V
V
O
–
0.6
0.2
–0.2
0
10
20
30
40
TIME (ns)
50
60
70
Figure 49. Overload Recovery, G = −1, VS = 5 V
The AD806x family does not exhibit phase reversal, even for
input voltages beyond the voltage supply rails. Going more
than 0.6 V beyond the power supplies will turn on protection
diodes at the input stage, which will greatly increase the device’s
current draw.
CAPACITIVE LOAD DRIVE
The AD806x family is optimized for bandwidth and speed, not
for driving capacitive loads. Output capacitance creates a pole
in the amplifier’s feedback path, leading to excessive peaking
and potential oscillation. If dealing with load capacitance is a
requirement of the application, the two strategies to consider
are as follows:
1. Use a small resistor in series with the amplifier’s output and
the load capacitance.
2. Reduce the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
Rev. D | Page 15 of 20
AD8061/AD8062/AD8063
VCC
Figure 50 shows a unity-gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
2V
TO AMPLIFIER
BIAS
DISABLE
R
SERIES
V
AD8061
O
C
LOAD
VEE
V
IN
Figure 52. Disable Circuit of the AD8063
Figure 50. Series Resistor Isolating Capacitive Load
DISABLE
Figure 34 shows the AD8063 supply current vs.
voltage. Figure 35 plots the output seen when the AD8063 input
DISABLE
Voltage feedback amplifiers like those in the AD806x family are
able to drive more capacitive load without excessive peaking
when used in higher gain configurations, because the increased
noise gain reduces the bandwidth of the overall feedback loop.
Figure 51 plots the capacitance that produces 30% overshoot vs.
noise gain for a typical amplifier.
is driven with a 10 MHz sine wave, and the
is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off
time. Figure 33 shows the input/output isolation response with
the AD8063 shut off.
10k
BOARD LAYOUT CONSIDERATIONS
Maintaining the high speed performance of the AD806x family
requires the use of high speed board layout techniques and low
parasitic components.
R
= 4.7
S
1k
100
10
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. Remove the ground plane near the package to reduce
parasitic capacitance.
R
= 0
S
Proper bypassing is critical. Use a ceramic 0.1 μF chip capacitor
to bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 μF to
10 μF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
1
2
3
4
5
CLOSED-LOOP GAIN
Figure 51. Capacitive Load vs. Closed-Loop Gain
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. Locate the feedback resistor close to
the inverting input pin. The value of the feedback resistor may
come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown
DISABLE
in Figure 52. When the
node is pulled below 2 V
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 μA, and the AD8063 output
will enter a high impedance state. If the
connected and allowed to float, the AD8063 stays biased at
full power.
DISABLE
node is not
Rev. D | Page 16 of 20
AD8061/AD8062/AD8063
APPLICATIONS
The circuit can be modified to provide the sync stripping
function for such a waveform. Instead of connecting RG to
ground, connect it to a dc voltage that is two times the black
level of the input signal. The gain from the +input to the output
is two, which means the black level will be amplified by two to
the output. However, the gain through RG is –unity to the
output. It takes a dc level of twice the input black level to shift
the black level to ground at the output. When this occurs, the
sync will be stripped, and the active video will be passed as in
the ground-referenced case.
SINGLE-SUPPLY SYNC STRIPPER
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of A-to-D conversion, the sync
pulses consume some of the dynamic range, so removing them
increases the converter’s available dynamic range for the video
information.
Figure 53 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the negative
supply is at ground potential, the lowest potential to which the
output can go is ground. This feature is exploited to create a
waveform whose lowest amplitude is the black level of the video
and does not include the sync level.
RED
DAC
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
MONITOR
#1
GREEN
DAC
BLUE
DAC
3V
0.1μF
10μF
75Ω
7
3
2
1kΩ
VIDEO IN
VIDEO OUT
6
75Ω
AD8061
3V
75Ω
R
1kΩ
4
F
0.1μF
10μF
7
1kΩ
2
3
R
1kΩ
G
PIN NUMBERS ARE
FOR 8-LEAD PACKAGE
75Ω
RED
75Ω
6
AD8061
4
Figure 53. Single 3 V Sync Stripper Using AD8061
1kΩ
In this case, the input video signal has its black level at ground, so
it comes out at ground at the input. Since the sync level is below
the black level, it will not show up at the output. However, all of
the active video portion of the waveform will be amplified by a
gain of two and then be normalized to unity gain by the back-
terminated transmission line. Figure 54 is an oscilloscope plot
of the input and output waveforms.
3V
8
MONITOR
#2
0.1μF
10μF
1kΩ
1kΩ
2
75Ω
75Ω
GREEN
1
AD8062
3
5
75Ω
BLUE
7
AD8062
75Ω
6
1
4
1kΩ
INPUT
Figure 55. RGB Cable Driver Using AD8061 and AD8062
RGB AMPLIFIER
2
Most RGB graphics signals are created by video DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and the voltage of the video
is also zero. Before the availability of high speed rail-to rail op
amps, it was essential that an amplifier have a negative supply
to amplify such a signal. Such an amplifier is necessary if one
wants to drive a second monitor from the same DAC outputs.
OUTPUT
10μs
500mV
Figure 54. Input and Output Waveforms for a Single-Supply
Video Sync Stripper Using an AD8061
However, high speed, rail-to-rail output amplifiers like the
AD8061 and AD8062 accept ground level input signals and
output ground level signals. They are used as RGB signal
amplifiers. A combination of the AD8061 (single) and the
AD8062 (dual) amplifies the three video channels of an RGB
system. Figure 55 shows a circuit that performs this function.
Some video signals with sync are derived from single-supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not
at ground but at some positive voltage.
Rev. D | Page 17 of 20
AD8061/AD8062/AD8063
The SELECT signal and the output waveforms for this circuit
are shown in Figure 57. For synchronization clarity, two differ-
ent frequency synthesizers, whose time bases are locked to each
other, generate the signals.
MULTIPLEXER
The AD8063 has a disable pin used to power down the ampli-
fier to save power or to create a mux circuit. If two (or more)
AD8063 outputs are connected together, and only one is enabled,
then only the signal of the enabled amplifier will appear at the
output. This configuration is used to select from various input
signal sources. Additionally, the same input signal is applied to
different gain stages, or differently tuned filters, to make a gain-
step amplifier or a selectable frequency amplifier.
2μs
OUTPUT
Figure 56 shows a schematic of two AD8063s used to create a
mux that selects between two inputs. One of these is a 1 V p-p,
3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave.
SELECT
+4V
1V
2V
0.1μF
10μF
10μF
Figure 57. AD8063 Mux Output
1
TIME
BASE
OUT
49.9Ω
AD8063
1V p-p
3MHz
0.1μF
1kΩ
–4V
+4V
V
49.9Ω
OUT
1kΩ
49.9Ω
0.1μF
10μF
10μF
1
49.9Ω
AD8063
–4V
2V p-p
1MHz
TIME
BASE
IN
0.1μF
1kΩ
1kΩ
HCO4
SELECT
Figure 56. Two-to-One Multiplexer Using Two AD8063s
Rev. D | Page 18 of 20
AD8061/AD8062/AD8063
OUTLINE DIMENSIONS
2.90 BSC
5.00 (0.1968)
4.80 (0.1890)
5
4
3
2.80 BSC
1.60 BSC
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
2
4.00 (0.1574)
3.80 (0.1497)
PIN 1
0.95 BSC
1.90
BSC
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
1.30
1.15
0.90
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
1.45 MAX
8°
0.22
0.08
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
10°
5°
0°
0.15 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 58. 5-Lead Small Outline Transistor Package [SOT-23]
Figure 59. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
(RT-5)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
2.90 BSC
3.00
BSC
6
1
5
2
4
3
2.80 BSC
1.60 BSC
8
1
5
4
4.90
BSC
3.00
BSC
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
PIN 1
1.30
1.15
0.90
0.65 BSC
1.10 MAX
1.45 MAX
0.15
0.00
0.22
0.08
0.80
0.60
0.40
10°
4°
0°
0.60
0.45
0.30
8°
0°
0.50
0.30
0.38
0.22
COPLANARITY
0.10
0.23
0.08
0.15 MAX
SEATING
PLANE
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AB
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 60. 6-Lead Small Outline Transistor Package [SOT-23]
Figure 61. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
(RT-6)
Dimensions shown in millimeters
Dimensions shown in millimeters
Rev. D | Page 19 of 20
AD8061/AD8062/AD8063
ORDERING GUIDE
Model
AD8061AR
Temperature Range
Package Description
Package Option
R-8
Branding
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
–40°C to +85°C
−40°C to +85°C
−40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
40°C to +85°C
40°C to +85°C
40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
AD8061AR-REEL
AD8061AR-REEL7
AD8061ARZ1
8-Lead SOIC, 13-Inch Tape and Reel
8-Lead SOIC, 7-Inch Tape and Reel
8-Lead SOIC
R-8
R-8
R-8
R-8
AD8061ARZ-REEL1
AD8061ARZ-REEL71
AD8061ART-R2
AD8061ART-REEL
AD8061ART-REEL7
AD8061ARTZ-R21
AD8061ARTZ-REEL1
AD8061ARTZ-REEL71
AD8062AR
AD8062AR-REEL
AD8062AR-REEL7
AD8062ARZ1
AD8062ARZ-RL1
AD8062ARZ-R71
AD8062ARM
AD8062ARM-REEL
AD8062ARM-REEL7
AD8062ARMZ3
AD8062ARMZ-RL3
AD8062ARMZ-R73
AD8063AR
AD8063AR-REEL
AD8063AR-REEL7
AD8063ARZ1
AD8063ARZ-REEL1
AD8063ARZ-REEL71
AD8063ART-R2
AD8063ART-REEL
AD8063ART-REEL7
AD8063ARTZ-R21
AD8063ARTZ-REEL1
AD8063ARTZ-REEL71
8-Lead SOIC, 13-Inch Tape and Reel
8-Lead SOIC, 7-Inch Tape and Reel
5-Lead SOT-23, 250 piece Tape and Reel
5-Lead SOT-23, 13-Inch Tape and Reel
5-Lead SOT-23, 7-Inch Tape and Reel
5-Lead SOT-23, 250 piece Tape and Reel
5-Lead SOT-23, 13-Inch Tape and Reel
5-Lead SOT-23, 7-Inch Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13-Inch Tape and Reel
8-Lead SOIC, 7-Inch Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13-Inch Tape and Reel
8-Lead SOIC, 7-Inch Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13-Inch Tape and Reel
8-Lead MSOP, 7-Inch Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13-Inch Tape and Reel
8-Lead MSOP, 7-Inch Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13-Inch Tape and Reel
8-Lead SOIC, 7-Inch Tape and Reel
8-Lead SOIC
R-8
RT-5
RT-5
RT-5
RT-5
RT-5
RT-5
R-8
R-8
R-8
R-8
R-8
HGA
HGA
HGA
H0D2
H0D2
H0D2
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
HCA
HCA
HCA
#HCA
#HCA
#HCA
8-Lead SOIC, 13-Inch Tape and Reel
8-Lead SOIC, 7-Inch Tape and Reel
6-Lead SOT-23, 250 Piece Tape and Reel
6-Lead SOT-23, 13-Inch Tape and Reel
6-Lead SOT-23, 7-Inch Tape and Reel
6-Lead SOT-23, 250 Piece Tape and Reel
6-Lead SOT-23, 13-Inch Tape and Reel
6-Lead SOT-23, 7-Inch Tape and Reel
R-8
RT-6
RT-6
RT-6
RT-6
RT-6
RT-6
HHA
HHA
HHA
H0E4
H0E4
H0E4
1 Z = Pb-free part.
2 New branding after data code 0542, previously branded HGA.
3 Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
4 New branding after data code 0542, previously branded HHA.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01065-0-12/05(D)
Rev. D | Page 20 of 20
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