AD805BN [ADI]
DATA RETIMING PHASE LOCKED LOOP; 数据再定时锁相环
| 型号： | AD805BN |
| 厂家： | 
ADI |
| 描述： | DATA RETIMING PHASE LOCKED LOOP |
| 文件： | 总12页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Retiming
Phase-Locked Loop
a
AD805*
CLOCK RECOVERY AND
FEATURES
DATA RETIMING APPLICATION
155 Mbps Clock Recovery and Data Retiming
Permits CCITT G.958 Type A Jitter Tolerance
Permits CCITT G.958 Type B Jitter Transfer
Random Jitter: 0.6؇ rms
Pattern Jitter: Virtually Eliminated
Jitter Peaking: Fundamentally None
Acquisition: 30 Bit Periods
Accepts NRZ Data without Preamble
Single Supply Operation: –5.2 V or +5 V
10 KH ECL Compatible
VOLTAGE
CONTROLLED
PHASE
LOOP
FILTER
PHASE
DETECTOR
DATA
INPUT
GAIN
SHIFTER
RETIMING
MODULE
VCXO
(EXTERNAL)
RECOVERED
CLOCK
RETIMED
DATA
AD805
PRODUCT DESCRIPTION
The AD805 is a data retiming phase-locked loop designed for
use with a Voltage-Controlled Crystal Oscillator (VCXO) to
perform clock recovery and data retiming on Nonreturn to Zero
(NRZ) data. The circuit provides clock recovery and data
retiming on standard telecommunications STS-3 or STM-1
data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit
is used with the AD805 for specification purposes. Similar
circuit performance can be obtained using other commercially
available VCXO circuits. The AD805-VCXO circuit used for
clock recovery and data retiming can also be used for large
factor frequency multiplication.
phase shifter, phase detector, and loop filter, act to align input
data phase errors to the stable recovered clock provided by the
VCXO. The range of the voltage-controlled phase shifter, at
least 2 Unit Intervals (UI), and the bandwidth of this loop, at
roughly 3 MHz, provide the circuit with its wideband jitter
tolerance characteristic.
The circuit can acquire lock to input data very quickly, within
44 bit periods, due to the accuracy of the VCXO and the action
of the data retiming loop. Typical integrated second-order PLLs
take at least several thousand bit periods to acquire lock. This is
due to their having a wide tuning range VCO. Decreasing the
loop damping of a traditional second-order PLL shortens the
length of the circuit’s acquisition time, but at the expense of
greater jitter peaking.
The AD805-VCXO circuit meets or exceeds CCITT G.958
regenerator specifications for STM-I Type A jitter tolerance and
STM-1 Type B jitter transfer. The simultaneous Type A, wide-
band jitter tolerance and Type B, narrow-band jitter transfer
allows the use of the AD805-VCXO circuit in a regenerative
application to overcome optical line system interworking limit-
ations based on signal retiming using Type A passive tuned
device technology such as Surface-Acoustic-Wave (SAW) or
dielectric resonator filters, with Type B active devices such as
Phase-Locked Loops (PLLs).
The AD805-VCXO circuit is a second- order PLL that has no
jitter peaking. The zero used to stabilize the control loop of the
traditional second-order PLL effects the closed-loop transfer
function, causing jitter peaking in the jitter transfer function. In
the AD805-VCXO circuit, the zero needed to stabilize the loop
is implemented in the feedback path, in the voltage-controlled
phase shifter. Placing the zero in the feedback path results in
fundamentally no jitter peaking since the zero is absent from the
closed-loop transfer function.
The circuit VCXO provides a stable and accurate clock fre-
quency signal with or without input data. The AD805 works
with the VCXO to dynamically adjust the recovered clock fre-
quency to the frequency associated with the input data. This
frequency control loop tracks any low frequency component of
jitter on the input data. Since the circuit uses the VCXO for
clock recovery, it has a high Q for excellent wideband jitter at-
tenuation. The jitter transfer characteristic of the circuit is with-
in the jitter transfer requirements for a CCITT G.958 STM-1
Type B regenerator, which has a corner frequency of 30 kHz.
Output jitter, determined primarily by the VCXO, is a very low
0.6° rms. Jitter due to variations in input data density, pattern
jitter, is virtually eliminated in the circuit due to the AD805’s
patented phase detector.
The data retiming loop of the AD805 can be used with a passive
tuned circuit (155.52 MHz) such as a bandpass or a SAW filter
for clock recovery and data retiming. The data retiming loop
acts to servo the phase of the input data to the phase of the
recovered clock from the passive tuned circuit in this type of
application (see APPLICATIONS).
The AD805 overcomes the higher frequency jitter tolerance
limitations associated with traditional high Q, PLL based clock
and data recovery circuits through the use of its data retiming
loop. This loop, made up of the AD805’s voltage-controlled
The AD805 uses 10 KH ECL levels and consumes 375 mW
from a +5 V or a –5.2 V supply. The device is specified for
operation over the industrial temperature range of –40°C to
+85°C and is available in a 20-pin plastic DIP.
*Protected by U.S. Patent No. 5,036,298
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
(V = VMIN to VMAX, TA = TMIN to TMAX ( unless otherwise noted)
AD805–SPECIFICATIONS
EE
AD805BN
Parameter
Condition
Min
Typ
Max
Units
NOMINAL DATA RATE1
155.52
Mbps
TRACKING RANGE/CAPTURE RANGE1
STATIC PHASE ERROR1
±50
±70
ppm of Nominal Data Rate
27–1 PRN Sequence
223–1 PRN Sequence
7
7
33
33
Degrees
Degrees
OUTPUT JITTER1
27–1 PRN Sequence
0.6
0.6
1.0
1.0
Degrees rms
Degrees rms
223–1 PRN Sequence
JITTER TOLERANCE1
f = 10 Hz
f = 30 Hz
f = 300 Hz
f = 6.5 kHz
f = 65 kHz
f = 650 kHz
f = 1.3 MHz
375
125
12.5
2.2
2.2
0.84
0.65
440
147
16
3.2
3.0
1.4
0.85
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
JITTER TRANSFER1
Peaking
Bandwidth
27–1 PRN Sequence
0
10
0.12
1.1
dB
kHz
RECOVERED CLOCK SKEW
TRANSITIONLESS DATA RUN1
ACQUISITION TIME
TRCS
0.2
0.6
ns
1000 500
Bit Periods
Bit Periods
27–1 PRN Sequence
30
44
VCXO CONTROL OUTPUT RESISTANCE
VCXO Control Voltage High Level (VCC – VOH
VCXO Control Voltage Low Level (VOL – VEE
1000
1
0.8
Ω
Volts
Volts
)
No Load
No Load
1.3
1.15
)
POWER SUPPLY
Voltage (VMIN to VMAX
Current
)
–4.5
–5.2
70
–5.5
90
95
Volts
mA
mA
TA = +25°C, VEE = –5.2 V
TA = +25°C
INPUT VOLTAGE LEVELS
Input Logic High, VIH
Input Logic Low, VIL
–1.08
–1.95
–0.72 Volts
–1.59 Volts
OUTPUT VOLTAGE LEVELS
Output Logic High, VOH
Output Logic Low, VOL
TA = +25°C
TA = +25°C
–1.08
–1.95
–0.72 Volts
–1.60 Volts
INPUT CURRENT LEVELS
Input Logic High, IIH
Input Logic Low, IIL
125
80
µA
µA
OUTPUT SLEW TIMES
Rise Time (tR)
Fall Time (tF)
TA = +25°C
20%–80%
80%–20%
0.75
0.75
1.5
1.5
ns
ns
BUFFERED CLOCK DISTORTION
(DUTY CYCLE DISTORTION)
Recovered Clock Output
ρ = 1/2, TA = +25°C,
VEE = –5.2 V
±0.5
%
OPERATING TEMPERATURE RANGE1
(TMIN to TMAX
)
–40
+85
°C
VCXO CIRCUIT SPECIFICATIONS
Parameter
Condition
Min
Typ
Max
Units
CENTER FREQUENCY
CONTROL VOLTAGE
155.52
MHz
–4
–1
Volts
VCXO TUNING RANGE
MODULATION BANDWIDTH
±50
100
±70
ppm of Center Frequency
500
kHz
N/A
TRANSFER FUNCTION
NOTES
Positive, Monotonic
1These specifications reflect the performance of the circuit shown in Figure 12. VCXO circuit parameters critical to overall circuit performance are listed above.
2This specification results from tests accurate to ±0.1 dB, and from statistical analysis of the test results distribution. The AD805-VCXO circuit has no jitter peaking.
Reference the discussion in the THEORY OF OPERATION section.
Specifications subject to change without notice.
REV. 0
–2–
AD805
ABSOLUTE MAXIMUM RATINGS*
DATAOUT 50%
CLKOUT 50%
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Input Voltage (Pin 19 or 20 to VEE) . . . . . . . . VEE to +300 mV
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . .+300°C
T
RCS
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of the specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
Figure 1. Recovered Clock Skew (See Specifications Page)
PIN DESCRIPTIONS
Number Mnemonic
Description
PIN CONFIGURATION
1
2
3
4
5
6
7
8
DATAOUT
DATAOUT
VCC2
CLKOUT
CLKOUT
SUBST
VEE
VCC1
AVEE
ASUBST
NC
Differential Retimed Data Output
Differential Retimed Data Output
Digital Ground
Differential Recovered Clock Output
Differential Recovered Clock Output
Substrate
Digital VEE
Digital Ground
Analog VEE
Analog Substrate
1
2
20
19 DATAIN
DATAOUT
DATAOUT
DATAIN
SUBST
CLKIN
V
3
18
17
CC2
NOTES:
PIN 6 AND 18
ARE DIGITAL SUBSTRATE
AND SHOULD BE CONNECTED
TO PINS 7 AND 15 WHICH
4
CLKOUT
CLKOUT
SUBST
AD805
9
5
16 CLKIN
TOP VIEW
ARE DIGITAL V
.
10
11
12
13
14
15
16
17
18
19
20
EE
15
14
6
V
V
(Not to Scale)
EE
No Connection
PIN 10 IS ANALOG SUBSTRATE
AND SHOULD BE CONNECTED
TO PIN 9, WHICH IS ANALOG V
V
7
VCXO CONTROL VCXO Control Voltage Output
AVCC
VCC1
VEE
CLKIN
CLKIN
SUBST
DATAIN
DATAIN
CC1
EE
.
EE
Analog Ground
Digital Ground
Digital VEE
Differential Clock Input
Differential Clock Input
Substrate
Differential Data Input
Differential Data Input
8
V
13 AV
CC
CC1
VCXO
CONTROL
9
AV
EE
12
11
10
ASUBST
NC
NC = NO CONNECT
ORDERING GUIDE AND THERMAL CHARACTERISTICS
Operating
Temperature
Package
Option
Device
Description
JA
AD805BN 20-Pin Plastic DIP –40°C to +85°C
80°C/W
N-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD805 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD805
GLOSSARY
Jitter Tolerance
AD805 performance is specified using a Vectron C0-434Y ECL
Series Hybrid VCXO, SCD No. 434Y2365.
Jitter tolerance is a measure of the circuit’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation and is usually specified in Unit Intervals
(UI). The circuit will have a bit error rate less than 1 × 10–10
when in lock and retiming input data that has the specified jitter
applied to it.
Nominal Data Rate
This is the data rate that the circuit is specified to operate on.
The data format is Nonreturn to Zero (NRZ).
Operating Temperature Range (TMIN to TMAX
)
Refer to the THEORY OF OPERATION section for a descrip-
tion of the jitter tolerance of the AD805-VCXO circuit.
This is the operating temperature range of the AD805 in the
circuit. Each of the additional components of the circuit is held
at 25°C, nominal. The operating temperature range of the
circuit can be extended to the operating temperature range of
the AD805 through the selection of circuit components that
Jitter Transfer
The circuit exhibits a low-pass filter response to jitter applied to
its input data. The circuit jitter transfer characteristics are
measured using the method described in CCITT Recommenda-
tion G.958, Geneva 1990, Section 6.3.2. This method involves
applying sinusoidal input jitter up to the jitter tolerance mask
level for an STM-1 Type A regenerator.
operate from TMIN to TMAX
.
Tracking Range
This is the range of input data rates over which the circuit will
remain in lock. The VCXO CONTROL voltage range and the
VCXO frequency range determine circuit tracking range.
Bandwidth
This describes the frequency at which the circuit attenuates
sinusoidal input jitter by 3 dB.
Capture Range
This is the range of frequencies over which the circuit can
acquire lock. The VCXO CONTROL voltage range and the
VCXO frequency range determine circuit capture range.
Peaking
This describes the maximum jitter gain of the circuit in dB.
Static Phase Error
Acquisition Time
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error and IC input and output signals
prohibit direct measurement of static phase error.
This is the transient time, measured in bit periods, required for
the circuit to lock on input data from its free-running state.
Buffered Clock Distortion
This is a measure of the duty cycle distortion at the AD805
CLKOUT signals relative to the duty cycle distortion at the
AD805 CLKIN signals.
Recovered Clock Skew, TRCS
Bit Error Rate vs. Signal-to-Noise Ratio
This is the time difference, in ns, between the recovered clock
signal rising edge midpoint and midpoint of the rising or falling
edge of the output data signal. Refer to Figure 1.
The AD805 is intended to operate with standard ECL signal
levels at the data input. Although not recommended, smaller
input signals are tolerable. Figure 6 shows the bit error rate
performance versus input signal-to-noise ratio for input signal
amplitudes of full 900 mV ECL, and decreased amplitudes of
80 mV and 20 mV. Wideband amplitude noise is summed with
the data signals as shown in Figure 2. The full ECL, 80 mV,
and 20 mV input signals give virtually indistinguishable results.
Data Transition Density,
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
Transitionless Data Run
This is measured by interrupting an input data pattern with
ρ = 1/2 with a block of data bits without transitions, and then
reapplying the ρ = 1/2 input data. The circuit will handle this
sequence without making a bit error. The length of the block of
input data without transitions that an AD805-VCXO circuit can
handle is a function of the VCXO K0. The VCXO in the circuit
of Figure 12 has a K0 of 60 radians/volt, nominally.
The axes used for Figure 6 are scaled so that the theoretical Bit
Error Rate vs. Signal to Noise Ratio curve appears as a straight
line. The curve that fits the actual data points has a slope that
matches the slope of the theoretical curve for all but the higher
values of signal-to-noise ratio and lower values of bit error rate.
For high values of signal-to-noise ratio, the noise generator used
clips, and therefore is not true Gaussian. The extreme peaks of
the noise cause bit errors for high signal to noise ratios and low
bit error rates. The clipping of the noise waveform limits bit
errors in these cases.
Jitter
This is the dynamic displacement of digital signals from their
long term average positions, measured in degrees rms, or Unit
Intervals (UI). Jitter on the input data can cause dynamic phase
errors on the recovered clock. Jitter on the recovered clock
causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudo-random input data sequence
(PRN Sequence). The random output jitter of the VCXO
contributes to Output Jitter.
REV. 0
–4–
AD805
POWER
COMBINER
+
+
DATAIN
∑
∑
100
10
0.47µF
50Ω
+
–
DIFFERENTIAL
SIGNAL
SOURCE
CIRCUIT
UNDER
TEST
50Ω
0.47µF
POWER
DATAIN
COMBINER
180Ω
75Ω
1.0µF
POWER
SPLITTER
–5.2 V
GND
1
CCITT TYPE A MASK
FILTER
0.1
NOISE
0.1
1
10
100
1000
SOURCE
FREQUENCY – kHz
Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:
Block Diagram
Figure 5. Jitter Tolerance
0
E-1
0.3 UI
INPUT JITTER
5E-2
3E-2
2E-2
20mV
–5
E-2
5E-3
3E-3
2E-3
TYPE A
MASK
INPUT
80mV
JITTER
3
–10
5E-4
3E-4
2E-4
CCITT TYPE B
MASK
1.3 UI
4
INPUT
JITTER
5
6
8
ECL
–15
–20
10
12
E-15
1
10
100
1000
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S/N – dB
JITTER FREQUENCY – kHz
Figure 3. Jitter Transfer – Bandwidth
Figure 6. Bit Error Rate vs. Signal-to-Noise Ratio
0.3 UI
VCC
INPUT JITTER
–1
–3
–5
2.0
IOUT
AD805
1.3 UI
INPUT JITTER
VEE = –5.2V
1.5
V
– V
OH
CC
1.0
0.5
0
CCITT
TYPE A MASK
INPUT JITTER
V
– V
EE
OL
1
10
–200
0
200
400
JITTER FREQUENCY – kHz
I
– A
OUT
Figure 4. Jitter Transfer – Peaking
Figure 7. VCXO Control Voltage vs. Load
REV. 0
–5–
AD805
THEORY OF OPERATION
peaking in any regenerative stage can contribute to hazardous
jitter accumulation.
The AD805 is a delay- and phase- locked loop circuit for clock
recovery and data retiming from an NRZ-encoded data stream.
Figure 8 is a block diagram of the device shown with an external
VCXO. The AD805-VCXO circuit tracks the phase of the input
data using two feedback loops that share a common control
voltage. A high speed delay-locked loop path uses an on-chip
voltage-controlled phase shifter (VCPS) to track the high
frequency components of jitter on the input data. A separate
frequency control loop, using the external VCXO, tracks the low
frequency components of jitter on the input data.
ORDINARY PLL
JITTER OUT
JITTER IN
(dB)
Y(s)
X(s)
0 dB
AD805 – VCXO
Z(s)
X(s)
LOG ω
1
s
s
HIGH
LOW
τ
AD805
DATA
INPUT
VOLTAGE
CONTROLLED
PHASE
INTERNAL LOOP
CONTROL VOLTAGE
LOOP
FILTER
PHASE
DETECTOR
Figure 10. Circuit Jitter Transfer Functions
SHIFTER
The error transfer function, e(s)/X(s), has the same high pass
form as an ordinary phase-locked loop. This transfer function is
free to be optimized to give excellent wide-band jitter accommo-
dation since the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering. The circuit has an error transfer
bandwidth of 3 MHz and a jitter transfer bandwidth of 10 kHz.
VCXO
CONTROL VOLTAGE
RETIMING
MODULE
VCXO
(EXTERNAL)
RECOVERED
CLOCK
RETIMED
DATA
Figure 8. AD805-VCXO Clock Recovery Block Diagram
The circuit’s two loops contribute to overall jitter accommoda-
tion. At low frequencies, the integrator provides high gain so
that large jitter amplitudes can be tracked with small phase
errors between inputs of the phase detector. In this case, the
VCXO is frequency modulated and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCXO tuning range. A
wider tuning range corresponds to increased accommodation of
low frequency jitter. The internal loop control voltage remains
small for small phase errors, so the VCPS remains close to the
center of its range, contributing little to jitter accommodation.
The two loops work together to null out phase error. For
example, when the clock is behind the data, the phase detector
drives the VCXO to a higher frequency and also increases the
delay through the VCPS. These actions serve to reduce the
phase error. The faster clock picks up phase while the delayed
data loses phase. When considering a static phase error, it is
easy to see that since the control voltage is developed by a loop
integrator, the phase error will eventually reduce to zero.
Another view of the circuit is that the AD805 VCPS implements
the zero that is required to stabilize a second order phase-locked
loop and that the zero is placed in the feedback path so it does
not appear in the closed-loop transfer function. Jitter peaking in
an ordinary second order phase-locked loop is caused by the
presence of this zero in the closed-loop transfer function. Since
the AD805-VCXO circuit is free of any zero in its closed-loop
transfer function, the circuit is free of jitter peaking.
At medium jitter frequencies, the gain and tuning range of the
VCXO are not enough to track input jitter. In this case the
VCXO control voltage input starts to hit the rails of its maxi-
mum voltage swing and the VCXO frequency output spends
most of the time at one or the other extreme of its tuning range.
The size of the VCXO tuning range therefore has a small effect
on the jitter accommodation. The AD805 internal loop control
voltage is now larger, so the VCPS takes on the burden of
tracking input jitter. The VCPS range (in UI) is seen as the
plateau on the jitter tolerance curve (Figure 11). The VCPS has
a minimum range of 2 UI.
A linearized block diagram of the AD805-VCXO circuit is
shown in Figure 9. The two loops simultaneously provide wide-
band jitter accommodation and narrow-band jitter filtering.
Y
τ
100
e
–
1
s
VCO
1
s
INT
Z
X
+
+
∑
∑
K
–
PHASE
SHIFTER
10
PHASE
DETECTOR
AD805-VCXO
JITTER TOLERANCE
2
Z(s)
=
e(s)
X(s)
1
s
=
2
X(s)
2
s
s + Kτs + K
+
τ
s + 1
K
1
Figure 9. AD805-VCXO Circuit Linearized Block Diagram
CCITT TYPE A MASK
The jitter transfer function, Z(s)/X(s), is second order and low
pass, providing excellent filtering. Note that the jitter transfer
function has no zero, unlike ordinary second-order phase-locked
loops. This means that the circuit has fundamentally no jitter
peaking (see Figure 10). Having no jitter peaking makes this
circuit ideal for signal regeneration applications where jitter
0.1
0.1
1
10
100
1000
10000
FREQUENCY – kHz
Figure 11. Jitter Accommodation Design Limit
REV. 0
–6–
AD805
The gain of the loop integrator is small for high jitter frequen-
cies, so that larger phase differences between the phase detector
inputs are needed to make the internal loop control voltage big
enough to tune the range of the VCPS. Large phase errors at
high jitter frequencies cannot be tolerated. In this region, the
gain of the loop integrator determines the jitter accommodation.
Since the gain of the loop integrator declines linearly with
frequency, jitter accommodation decreases with increasing jitter
frequency. At the highest frequencies, the loop gain is very small
and little tuning of the VCPS can be expected. In this case, jitter
accommodation is determined by the eye opening of the input
data, the static phase error and the residual loop jitter. The jitter
accommodation is roughly 0.5 UI in this region. The corner
frequency between the declining slope and the flat region is the
3 MHz closed-loop bandwidth of the AD805’s internal
delay-locked loop.
APPLICATIONS
155.52 MBPS CLOCK RECOVERY AND DATA RETIMING
USING AT&T 157-TYPE VHF VOLTAGE-CONTROLLED
CRYSTAL OSCILLATOR
The AD805 design can be used with any VCXO circuit that has
a gain of roughly 1 ϫ 106 rad/volt-sec, a frequency pull range of
at least ±50 ppm, a positive slope (a greater VCXO control
voltage corresponds to a greater output frequency) and a
modulation bandwidth of 500 kHz. These VCXO parameters
contribute to overall circuit low frequency jitter tolerance and
jitter transfer.
The output jitter of the overall circuit is largely determined by
the output jitter of the VCXO. The AD805 adds little jitter
since it just buffers the VCXO frequency output, adding
distortion (duty cycle distortion) of only ±0.5%.
Overall circuit jitter bandwidth is determined by the slope of the
VCXO output frequency vs. control voltage curve. A greater
slope corresponds to a greater jitter bandwidth.
USING THE AD805
Ground Planes
Use of two ground planes, an analog ground plane and a digital
ground plane, is recommended. This will isolate noise that may
be on the digital ground plane from the analog ground plane.
Figure 12 shows a schematic of the AD805 in a 155.52 Mbps
clock recovery and data retiming application with an AT&T
157-Type VCXO (see insert). Figures 15 and 16 show typical
jitter tolerance and jitter transfer curves for the circuit.
Power Supply Connections
Power supply decoupling should take place as close to the IC as
possible. This will keep noise that may be on a power supply
from affecting circuit performance.
Note that the 157-Type VCXO control voltage bandwidth
(modulation bandwidth) varies with respect to control voltage
from 80 kHz to 500 kHz. The low value of this modulation
bandwidth causes some jitter peaking when used with the
AD805. The limited modulation bandwidth introduces excess
phase in the frequency control loop through the VCXO. This
causes the frequency control loop to become less damped. Jitter
peaking of 1 dB or 2 dB results in the jitter transfer function.
The compensation network on the VCXO control voltage
between the AD805 and the 157-Type VCXO shown in Figure
12, effectively reduces the high frequency loop gain through the
frequency control loop. The addition of this compensation
network eliminates jitter peaking. The compensation network
1 kΩ resistor works with the AD805 VCXO CONTROL 1 kΩ
output impedance to halve the loop crossover frequency. This
avoids excess phase caused by the limited modulation band-
width of the 157-Type VCXO.
Use of a 10 µF tantalum capacitor between VEE and ground is
recommended.
Use of 0.1 µF ceramic capacitors between IC power supply or
substrate pins and either analog or digital ground is recom-
mended. Refer to schematic, Figure 12, for advised connections.
The ceramic capacitors should be placed as close to the IC pins
as possible.
Connections from VEE to load resistors for DATAIN, DATAOUT,
CLKIN, and CLKOUT signals should be individual, not daisy
chained. This will avoid crosstalk on these signals.
Transmission Lines
Use of 50 Ω transmission lines are recommended for DATAIN,
DATAOUT, CLKIN, and CLKOUT signals.
Terminations
Termination resistors should be used for DATAIN, CLKIN,
DATAOUT, and CLKOUT signals. Metal, thick film, 1%
tolerance resistors are recommended. Termination resistors for
the DATAIN and CLKIN signals should be placed as close as
possible to the DATAIN and CLKIN pins.
Input Buffer
Use of an input buffer, such as a 10H116 Line Receiver IC, is
suggested for an application where the DATAIN signals do not
come directly from an ECL gate, or where noise immunity on
the DATAIN signals is an issue.
REV. 0
–7–
AD805
–5.2V
C9
0.1µF
R15
130Ω
R16
130Ω
–5.2V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C11
0.1µF
R13
R14
–5.2V
80.6Ω
80.6Ω
Z2
R19
130Ω
R20
R1
R2
J1
J2
C3
10H116
130Ω
R10
154Ω
100Ω
100Ω
0.1µF
R9
DATAOUT
DATAOUT
154Ω
R5 100Ω
J5
J6
C7
0.1µF
1
2
20
19
18
DATAIN
DATAIN
DATAOUT
DATAOUT
DATAIN
DATAIN
SUBST
CLKIN
R6
100Ω
–5.2V
C10
C4
0.1µF
–5.2V
V
3
4
CC2
–5.2V
J3
J4
CLKOUT
CLKOUT
SUBST
17
16
15
14
0.1µF
–5.2V
R12
154Ω
R11
154Ω
R17
80.6Ω
C12
0.1µF
R18
80.6Ω
CLOCKOUT
CLOCKOUT
5
CLKIN
R7 100Ω
V
6
–5.2V
EE
R22
130Ω
C8
0.1µF
R23
80.6Ω
R21
130Ω
R8 100Ω
R3
100Ω
V
V
7
R4
EE
CC1
100Ω
C5
0.1µF
V
AV
CC
8
13
12
CC1
16
8
9
VCXO
CONTROL
AV
EE
9
10
–5.2V
VECTRON
–5.2V
–5.2V
R24
80.6Ω
ASUBST
NC 11
10
CO-434V VCXO
Z1
C2
10µF
C16
0.1µF
C6
0.1µF
AD805
6
A
B C
20mh
OPTIONAL
NOTCH
FILTER
*
1nF
A
16
15
14
13
12
11
10
9
1
2
3
R25
–5.2V
1kΩ
Z3
C13
0.1µF
AT&T
157-TYPE
VCXO
DIGITAL
ANALOG
GROUND
C1
1.0µF
4
5
6
7
8
GROUND
NC = NO CONNECT
*
A NOTCH FILTER MAY BE USED TO
FILTER A VCXO CIRCUIT'S SPURIOUS
RESPONSE EFFECTIVELY.
C
B
157
AT&T TYPE VCXO CIRCUIT
Figure 12. Evaluation Board Schematic, Negative Supply
Figure 13. Evaluation Board, Component Side
Figure 14. Evaluation Board, Solder Side
REV. 0
–8–
AD805
Table I. Evaluation Board,
Negative Supply: Components List
155.52 MBPS CLOCK RECOVERY AND DATA RETIMING
USING A SURFACE ACOUSTIC WAVE (SAW) FILTER
The AD805 can be used with a 155.52 MHz SAW filter circuit
for clock recovery and data retiming. In this type of application
(refer to Figure 17), the SAW filter circuit is used to generate a
155.52 MHz clock from the input data. The AD805 data retiming
loop formed by the voltage-controlled phase shifter, the phase
detector and the loop filter, act to servo the phase of the input
data to the phase of the recovered clock. The AD805 can
compensate up to ±180° phase variance through the SAW filter
circuit. The AD805 replaces the D Flip-Flop and phase shifter
components found in traditional SAW filter-based clock recovery
and data retiming circuits. Use of the AD805 eliminates the
phase shifter to SAW filter matching needed to get traditional
SAW filter-based circuits to perform over operating conditions.
Reference
Designator
Description
Quantity
R1–8
R9–12
Resistor, 100 Ω, 1%
Resistor, 154 Ω, 1%
R13, 14, 17, 18, 23, 24 Resistor, 80.6 Ω, 1%
8
4
6
6
1
11
1
R15, 16, 19–22
C2
C3–12, C15
Z1
Z2
Resistor, 130 Ω, 1%
10 µF, Tantalum
0.1 µF, Ceramic Chip
AD805
10H116, ECL Line Receiver 1
Vectron CO-434Y VCXO
AT&T 157-Type VCXO
1
1
Z3
The jitter bandwidth and the output jitter of the overall circuit is
determined largely by the SAW filter used. The AD805 retimes
the input data to the recovered clock and buffers the recovered
clock from the SAW filter circuit. The AD805 plays a role in the
jitter accommodation of the overall circuit. The AD805’s phase
shifter range and the bandwidth of the data retiming loop
provide for at least 2 UI p-p jitter tolerance to 1 MHz. The
length of a transitionless block of data that will not cause the
circuit to lose lock or start making bit errors is determined by
the Q of the SAW filter used.
100
10
VECTRON
AT&T
Figure 17 shows a schematic of the AD805 used with a
Toyocom TQS-610J-6R SAW filter. The circuit that precedes
the SAW filter feeds the filter with a pulse at each data transi-
tion. The line receiver circuit that immediately follows the SAW
filter provides gain to the SAW filter output to drive the AD805
CLKIN signals.
1
CCITT TYPE A MASK
0.1
0.1
1
10
100
1000
JITTER FREQUENCY – kHz
Figure 15. AD805-VCXO Circuit Jitter Tolerance
0
–5
AT&T 1.3 UI
INPUT JITTER
–10
CCITT TYPE B
MASK
VECTRON 1.3 UI
INPUT JITTER
–15
–20
1
10
100
1000
JITTER FREQUENCY – kHz
Figure 16. AD805-VCXO Circuit Jitter Transfer
REV. 0
–9–
AD805
–5.2V
C9
0.1µF
R15
130Ω
R16
130Ω
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
–5.2V
R13
80.6Ω
R14
80.6Ω
–5.2V
C11
Z2
0.1µF
R19
R20
130Ω
R1
100Ω
R2
J1
J2
C3
0.1µF
10H116
130Ω
R10
154Ω
100Ω
R9
DATAOUT
DATAOUT
154Ω
R5 100Ω
C7
0.1µF
J5
1
2
20
19
DATAIN
DATAOUT
DATAOUT
DATAIN
DATAIN
SUBST
C10
0.1µF
J6
R6
100Ω
–5.2V
DATAIN
C4
0.1µF
–5.2V
18
V
3
4
CC2
J3
J4
CLKOUT
CLKOUT
SUBST
CLKIN 17
–5.2V
R11
154Ω
R12
154Ω
R17
80.6Ω
R18
80.6Ω
CLOCKOUT
CLOCKOUT
16
15
14
CLKIN
5
6
R7 100Ω
C12
0.1µF
V
–5.2V
EE
R34
R35
130Ω
C8
0.1µF
R8 100Ω
R3
100Ω
7
V
V
130Ω
R4
EE
CC1
R 80.6Ω
100Ω
C5
0.1Ω
V
AV
CC
8
13
12
11
CC1
VCXO
CONTROL
AV
EE
9
–5.2V
C2
R32
80.6Ω
R33
80.6Ω
–5.2V
ASUBST
NC
10
Z1
C6
10µF
0.1µF
AD805
C21
0.47µF
R30
10kΩ
R28
10kΩ
C20
0.47µF
C10
0.1µF
C19
0.47µF
R31
10kΩ
R29
10kΩ
1/3 Z3
1/3 Z3 10H116
8
C14
1nF
DIGITAL
GROUND
ANALOG
GROUND
R23
590Ω
R22
590Ω
3
2
5
4
7
6
10
9
15
14
13
12
NC = NO CONNECT
TOYOCOM
TQS-610J-6R
R21
226Ω
L1
1µh
C15
1nF
16
1
1/3 Z3
R27
274Ω
R25
274Ω
R26
274Ω
R24
274Ω
C13
0.1µF
–5.2V
T50-10 CORE,
18 TURNS
C17
0.1µF
C16
0.1µF
–5.2V
–5.2V
Figure 17. AD805-SAW Filter Clock Recovery and Data Retiming Circuit Schematic
Table II. AD805-SAW Filter Clock Recovery and Data Retiming Components List
Reference
Designator
Description
Quantity
R1–R8
R9–R12
R13, R14, R17, R18, R32, R33
R15, R16, R19, R20, R34, R35
Resistor, 100 Ω, 1%
Resistor, 154 Ω, 1%
Resistor, 80.6 Ω, 1%
Resistor, 130 Ω, 1%
Resistor, 226 Ω, 1%
Resistor, 590 Ω, 1%
Resistor, 274 Ω, 1%
Resistor, 10 kΩ, 1%
10 µF, Tantalum
0.1 µF, Ceramic Chip
1 nF
0.47 mF
1 µh, T50-10 Core, 18 Turns,
Micrometals, Inc.
AD805
1OH116, ECL Line Receiver
Toyocom TQS-610J-6R SAW
8
4
6
6
1
2
4
4
1
14
2
3
1
R21
R22, R23
R24–R27
R28–R31
C2
C3–C13, C16–C18
C14, C15
C19–C21
L1
Z1
Z2, Z3
Z4
1
2
1
REV. 0
–10–
AD805
LARGE FACTOR FREQUENCY MULTIPLICATION —
TO 155.52 MHZ
DESKEWING ISOCHRONOUS 155.52 MBPS DATA
STREAMS
The AD805-VCXO combination can be used to multiply a
frequency at the AD805’s DATAIN by a large integer multiple.
This is useful for generating a 155.52 MHz bit clock from a
19.44 MHz byte clock (multiplication factor of 8). The highly
accurate center frequency of the VCXO makes even larger
factor frequency multiplication possible. The VCXO will not
lock on a false harmonic even for large multiplication factors.
For example, a VCXO with center frequency accuracy of
100 ppm will allow frequency multiplication by a factor as large
as 5000. This is because the 5000th harmonic of 31.104 kHz is
155.52 MHz, and the 4999th and the 5001st harmonics are 200
ppm away from the VCXO center frequency. Since the accuracy
and tuning range of the VCXO constrain its output frequency to
within 100 ppm of center frequency, the circuit will reliably pick
the 5000th harmonic.
The AD805 can be used for deskewing a 155.52 Mbps data
stream to a reference 155.52 MHz clock when the clock is
isochronous with the data. Figure 19 shows a diagram of an
AD805 in a deskewing application. The data input to the
AD802-155 clock recovery circuit and the data input to the
AD805 were generated using the same 155.52 MHz clock. The
AD805 data retiming loop formed by the voltage-controlled
phase shifter, the phase detector, and the loop filter act to align
the phase of the input data to the phase of the recovered clock.
This eliminates skew that can exist between two isochronous
data paths.
The AD805 will track ±180° change in skew after initial locking
without bit errors. If the skew changes by more than ±180° after
lock, it is possible to exceed the range of the voltage controlled
phase shifter. Exceeding the phase shifter range will force the
AD805 data retiming loop to reacquire to the center of the
phase shifter. During this reacquisition, it is possible to make
3000 bit errors.
Frequency multiplication by an odd factor is possible using the
AD805-VCXO combination. This is not obvious. Consider a
51.84 MHz input multiplied by a factor of 3 to get to 155.52 MHz.
In this case, the edge spacing of the 51.84 MHz signal is 9.65 ns,
or 1-1/2 periods of the expected 155.52 MHz output. In theory,
every other edge of the 51.84 MHz at the AD805’s DATAIN is
interpreted as 180° out of phase. In practice, however, the
inherent loop jitter dithers these edges to give +179° then –179°
out of phase measurements on alternate edges. Measurements
on these alternate edges cancel. The circuit phase locks to the
other set of alternate edges. The very low gain of the VCXO and
the narrow bandwidth of the jitter transfer function gives an
output that has low jitter even though alternate input edges are
out of phase. When multiplying by a factor of 3, the DATAOUT
will have a repeating 110 or 100 pattern. Either pattern can
occur since either the rising or falling edges of the 51.84 MHz
signal at the DATAIN can be the out of phase set of alternate
edges.
CD
PHASE
DETECTOR
LOOP
FILTER
REFERENCE
DATA INPUT
COMPENSATING
ZERO
∑
VCO
RECOVERED
CLOCK
FREQUENCY
DETECTOR
RETIMING
MODULE
RETIMED
DATA
FRAC
OUTPUT
AD802-155
VOLTAGE
CONTROLLED
PHASE
Figure 18 shows the output jitter performance of an AD805-
VCXO circuit for different integer frequency multiplication
factors.
VCXO
CONTROL
OUTPUT
PHASE
DETECTOR
LOOP
FILTER
DATA
INPUT
GAIN
SHIFTER
RETIMING
MODULE
60
50
40
30
20
BUFFERED
CLOCK
AD805
RETIMED
DATA
Figure 19. AD805 Deskewing Circuit Diagram
10
0
10
100
INPUT CLOCK FREQUENCY – MHz
Figure 19. AD805-VCXO Circuit Clock Output Jitter vs.
Integer Multiplier
REV. 0
–11–
AD805
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Plastic Dual In-Line Package
(N-20)
1.060 (26.90)
0.925 (23.50)
20
11
10
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
–12–
REV. 0
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