AD7765_07 [ADI]
24-Bit, 156 kSPS, 112 dB ヒ-ツ ADC with On-Chip Buffers and Serial Interface; 24位156 kSPS时， 112分贝ヒ - ツADC ，带有片上缓冲器和串行接口
| 型号： | AD7765_07 |
| 厂家： | 
ADI |
| 描述： | 24-Bit, 156 kSPS, 112 dB ヒ-ツ ADC with On-Chip Buffers and Serial Interface |
| 文件： | 总32页 (文件大小：1046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24-Bit, 156 kSPS, 112 dB Σ-Δ ADC
with On-Chip Buffers and Serial Interface
AD7765
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
A–
V
A+
V
+
V –
IN
MCLK
GND
OUT
OUT
IN
High performance 24-bit ∑-∆ ADC
115 dB dynamic range at 78 kHz output data rate
112 dB dynamic range at 156 kHz output data rate
156 kHz maximum fully filtered output word rate
Pin-selectable oversampling rate (128× and 256×)
Low power mode
AV
AV
AV
AV
DV
1
2
3
4
DD
DD
DD
DD
DD
V
V
A+
A–
IN
DIFF
BUF
MULTIBIT
IN
Σ-Δ
MODULATOR
V
+
REF
RECONSTRUCTION
DECIMATION
OVERRANGE
DEC_RATE
Flexible SPI
REFGND
SYNC
Fully differential modulator input
On-chip differential amplifier for signal buffering
On-chip reference buffer
INTERFACE LOGIC AND
OFFSET AND GAIN
CORRECTION REGISTERS
FIR FILTER ENGINE
R
BIAS
RESET/PWRDWN
AD7765
Full band low-pass finite impulse response (FIR) filter
Overrange alert pin
Digital gain correction registers
FSO SCO SDI SDO FSI
Figure 1.
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of
low-pass filters. The external clock frequency applied to the
AD7765 determines the sample rate, filter corner frequencies,
and output word rate.
Power-down mode
Synchronization of multiple devices via
Daisy chaining
SYNC
pin
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
The AD7765 device boasts a full band on-board FIR filter. The
full stop-band attenuation of the filter is achieved at the Nyquist
frequency. This feature offers increased protection from signals
that lie above the Nyquist frequency being aliased back into the
input signal bandwidth.
GENERAL DESCRIPTION
The AD7765 is a high performance, 24-bit Σ-Δ analog-to-digital
converter (ADC). It combines wide input bandwidth, high
speed, and performance of 112 dB dynamic range at a 156 kHz
output data rate. With excellent dc specifications, the converter
is ideal for high speed data acquisition of ac signals where dc
data is also required.
The reference voltage supplied to the AD7765 determines the
input range. With a 4 V reference, the analog input range is
±±.2768 V differential biased around a common mode of
2.048 V. This common-mode biasing can be achieved using
the on-chip differential amplifier, further reducing the external
signal conditioning requirements.
Using the AD7765 eases the front-end antialias filtering
requirements, simplifying the design process significantly. The
AD7765 offers pin-selectable decimation rates of 128× and
256×. Other features include an integrated buffer to drive the
reference as well as a fully differential amplifier to buffer and
level shift the input to the modulator.
The AD7765 is available in a 28-lead TSSOP package and is
specified over the industrial temperature range from −40°C
to +85°C.
Table 1. Related Devices
Part No.
AD7760
AD7762
AD7763
AD7764
AD7766
AD7767
Description
An overrange alert pin indicates when an input signal has
exceeded the acceptable range. The addition of internal gain
and internal overrange registers make the AD7765 a compact,
highly integrated data acquisition device requiring minimal
peripheral components.
2.5 MSPS, 100 dB, parallel output on-chip buffers
625 kSPS, 109 dB, parallel output on-chip buffers
625 kSPS, 109 dB, serial output, on-chip buffers
312 kSPS, 109 dB, serial output, on-chip buffers
125 kSPS, 108 dB, serial output, 20 mW max power
125 kSPS, 108 dB, serial output, 20 mW max power
The AD7765 also offers a low power mode, significantly
reducing power dissipation without reducing the output data
rate or available input bandwidth.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD7765
TABLE OF CONTENTS
Synchronization.......................................................................... 20
Overrange Alerts ........................................................................ 20
Power Modes............................................................................... 20
Decimation Rate Pin.................................................................. 21
Daisy Chaining ............................................................................... 22
Reading Data in Daisy-Chain Mode ....................................... 22
Writing Data in Daisy-Chain Mode ........................................ 2±
Clocking the AD7765 .................................................................... 24
MCLK Jitter Requirements ....................................................... 24
Decoupling and Layout Information........................................... 25
Supply Decoupling ..................................................................... 25
Reference Voltage Filtering ....................................................... 25
Differential Amplifier Components ........................................ 25
Layout Considerations............................................................... 25
Using the AD7765...................................................................... 26
Bias Resistor Selection ............................................................... 26
AD7765 Registers........................................................................... 27
Control Register ......................................................................... 27
Status Register............................................................................. 27
Gain Register—Address 0x0004............................................... 28
Overrange Register—Address 0x0005..................................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... ±
Timing Specifications .................................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Functional Descriptions.......................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Σ-Δ Modulation and Digital Filtering...................................... 15
AD7765 Input Structure ................................................................ 16
On-Chip Differential Amplifier ............................................... 17
Modulator Input Structure........................................................ 18
AD7765 Interface............................................................................ 19
Reading Data............................................................................... 19
Reading Status and Other Registers......................................... 19
Writing to the AD7765 .............................................................. 19
AD7765 Functionality.................................................................... 20
REVISION HISTORY
6/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7765
SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD± = AVDD4 = 5 V, VREF+ = 4.096 V, MCLK amplitude = 5 V, TA = +25°C, normal power
mode, using the on-chip amplifier with components as shown in row one of Table 7, unless otherwise noted.1
Table 2
Parameter
Test Conditions/Comments
Specification
Unit
DYNAMIC PERFORMANCE
Decimate 256×
Normal Power Mode
Dynamic Range
MCLK = 40 MHz, ODR = 78.125 kHz, fIN = 1 kHz sine wave
Modulator inputs shorted
115
110
113.4
109
106
dB typ
dB min
dB typ
dB typ
dB min
dBFS typ
dB typ
dB typ
dB typ
Differential amplifier inputs shorted
Input amplitude = −0.5 dB
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR) Nonharmonic
Total Harmonic Distortion (THD)
130
Input amplitude = −0.5 dB
Input amplitude = −6 dB
Input amplitude = −60 dB
−105
−103
−71
Low Power Mode
Dynamic Range
MCLK = 40 MHz, ODR = 78.125 kHz, fIN = 1 kHz sine wave
Modulator inputs shorted
113
110
112
109
dB typ
dB min
dB typ
dB typ
dB min
dB typ
dB typ
dB max
dB typ
Differential amplifier inputs shorted
Input amplitude = −0.5 dB
Signal-to-Noise Ratio (SNR)2
106
Total Harmonic Distortion (THD)
Input amplitude = −0.5 dB
Input amplitude = −6 dB
Input amplitude = −6 dB
Input amplitude = −60 dB
−105
−111
−100
−76
Decimate 128×
Normal Power Mode
Dynamic Range
MCLK = 40 MHz, ODR = 156.25 kHz, fIN = 1 kHz sine wave
Modulator inputs shorted
112
108
110.4
107
105
130
−105
−103
dB typ
dB min
dB typ
dB typ
dB min
dBFS typ
dB typ
dB typ
Differential amplifier inputs shorted
Signal to Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR) Nonharmonic
Total Harmonic Distortion (THD)
Input amplitude = −0.5 dB
Input amplitude = −6 dB
Intermodulation Distortion (IMD)
Input amplitude = −6 dB, fIN A = 50.3 kHz, fIN B = 47.3 kHz
Second-order terms
−117
−108
dB typ
dB typ
Third-order terms
Low Power Mode
Dynamic Range
MCLK = 40 MHz, ODR = 156.25 kHz, fIN = 1 kHz sine wave
Modulator inputs shorted
110
109
109
107
dB typ
dB min
dB typ
dB typ
dB min
dB typ
dB typ
dB max
Differential amplifier inputs shorted
Input amplitude = −0.5 dB
Signal-to-Noise Ratio (SNR)2
105
Total Harmonic Distortion (THD)
Input amplitude = −0.5 dB
Input amplitude = −6 dB
Input amplitude = −6 dB
−105
−111
−100
Intermodulation Distortion (IMD)
Input amplitude = −6 dB, fIN A= 50.3 kHz, fIN B = 47.3 kHz
Second-order terms
−134
−110
dB typ
dB typ
Third-order terms
Rev. 0 | Page 3 of 32
AD7765
Parameter
Test Conditions/Comments
Specification
Unit
DC ACCURACY
Resolution
Guaranteed monotonic to 24 bits
Normal power mode
Low power mode
24
Bits
0.0036
0.0014
0.006
0.03
% typ
% typ
% typ
% max
% typ
% typ
% max
% typ
% typ
%FS/°C typ
Integral Nonlinearity
Normal power mode
Zero Error
Gain Error
Including on-chip amplifier
Low power mode
0.04
0.002
0.024
0.018
0.04
Including on-chip amplifier
0.00006
Zero Error Drift
Gain Error Drift
0.00005
%FS/°C typ
DIGITAL FILTER CHARACTERISTICS
Pass-Band Ripple
0.1
dB typ
kHz
kHz
kHz
dB typ
Pass Band3
−1 dB frequency
ODR × 0.4016
ODR × 0.4096
ODR × 0.5
120
−3dB Bandwidth3
Stop Band3
Stop-Band Attenuation
Beginning of stop band
Decimate 128×
Decimate 256×
115
Group Delay
Decimate 128×
Decimate 256×
MCLK = 40 MHz
MCLK = 40 MHz
177
358
μs typ
μs typ
ANALOG INPUT
Differential Input Voltage
Input Capacitance
Modulator input pins: VIN(+) − VIN(−), VREF = 4.096 V
At on-chip differential amplifier inputs
At modulator inputs
3.2768
V p-p
pF typ
pF typ
5
29
REFERENCE INPUT/OUTPUT
VREF Input Voltage
VREF Input DC Leakage Current
VREF Input Capacitance
DIGITAL INPUT/OUTPUT
MCLK Input Amplitude
Input Capacitance
Input Leakage Current
VINH
AVDD3 = 5 V 5%
4.096
1
5
V
μA max
pF typ
2.25 to 5.25
7.3
1
0.8 × DVDD
0.2 × DVDD
2.2
V
pF typ
ꢀA/pin max
V min
V max
V min
V max
VINL
VOH
4
VOL
0.1
ON-CHIP DIFFERENTIAL AMPLIFIER
Input Impedance
>1
125
−0.5 to +2.2
2.048
MΩ
kHz
V
Bandwidth for 0.1 dB Flatness
Common-Mode Input Voltage
Common-Mode Output Voltage
POWER REQUIREMENTS
AVDD1 (Modulator Supply)
AVDD2 (General Supply)
AVDD3 (Differential Amplifier Supply)
AVDD4 (Ref Buffer Supply)
DVDD
Voltage range at input pins: VINA− and VINA+.
On-chip differential amplifier pins: VOUT+ and VOUT
−
V
5%
5%
5%
5%
5%
2.5
5
5
5
2.5
V
V
V min/max
V min/max
V
Rev. 0 | Page 4 of 32
AD7765
Parameter
Test Conditions/Comments
Specification
Unit
Normal Power Mode
AIDD1 (Modulator)
19
13
10
9
mA typ
mA typ
mA typ
mA typ
mA typ
AIDD2 (General)5
MCLK = 40 MHz
AVDD3 = 5 V
AVDD4 = 5 V
AIDD3 (Differential Amplifier)
AIDD4 (Reference Buffer)
5
DIDD
MCLK = 40 MHz
37
Low Power Mode
AIDD1 (Modulator)
10
7
5.5
5
mA typ
mA typ
mA typ
mA typ
mA typ
AIDD2 (General)5
MCLK = 40 MHz
AVDD3 = 5 V
AVDD4 = 5 V
AIDD3 (Differential Amplifier)
AIDD4 (Reference Buffer)
5
DIDD
MCLK = 40 MHz
20
POWER DISSIPATION
Normal Power Mode
MCLK = 40 MHz, decimate 128×
MCLK = 40 MHz, decimate 128×
PWRDWN held logic low
300
371
160
215
1
mW typ
mW max
mW typ
mW max
mW typ
Low Power Mode
Power-Down Mode6
1 See Terminology section.
2 SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5dB below full scale, unless otherwise specified.
3 Output Data Rate (ODR) = [(MCLK/2)]/Decimation Rate. That is, the maximum ODR for AD7765 = [(40 MHz)/2)/128] = 156.25 kHz.
4 Tested with a 400 μA load current.
5 Tested at MCLK = 40 MHz. This current scales linearly with MCLK frequency applied.
6 Tested at 125°C.
Rev. 0 | Page 5 of 32
AD7765
TIMING SPECIFICATIONS
AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD± = AVDD4 = 5 V, VREF+ = 4.096 V, TA = 25°C, CLOAD = 25 pF.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMCLK
500
40
250
20
1 × tICLK
1 × tICLK
1
2
kHz min
MHz max
kHz min
MHz max
typ
Applied master clock frequency
fICLK
Internal modulator clock derived from MCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
SCO high period
SCO low period
typ
ns typ
ns typ
ns max
ns min
ns max
ns typ
max
SCO rising edge to FSO falling edge
Data access time, FSO falling edge to data active
MSB data access time, SDO active to SDO valid
Data hold time (SDO valid to SCO rising edge)
Data access time (SCO rising edge to SDO valid)
SCO rising edge to FSO rising edge
FSO low period
8
40
9.5
2
32 × tSCO
12
ns min
min
Setup time from FSI falling edge to SCO falling edge
FSI low period
1 × tSCO
32 × tSCO
12
12
0
1
t12
max
FSI low period
t13
t14
t15
ns min
ns min
ns max
SDI setup time for the first data bit
SDI setup time
SDI hold time
1
FSI
This is the maximum time
can be held low when writing to an individual device (a device that is not daisy chained).
Rev. 0 | Page 6 of 32
AD7765
TIMING DIAGRAMS
32 × tSCO
t1
SCO (O)
t8
t2
t9
t3
FSO (O)
t4
t6
t5
t7
D19
SDO (O)
D23
D22
D21
D20
D1
D0
ST4
ST3
ST2
ST1
ST0
0
0
0
Figure 2. Serial Read Timing Diagram
t1
SCO (O)
t2
t12
t10
t11
FSI (I)
SDI (I)
t14
t13
RA15
t15
RA9
RA14
RA13
RA12
RA11
RA10
RA8
RA1
RA0
D15
D14
D1
D0
Figure 3. AD7765 Register Write
SCO (O)
FSO (O)
SDO (O)
FSI (I)
≥8 × tSCO
STATUS REGISTER
CONTENTS [31:16]
DON’T CARE
BITS [15:0]
NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER
CONTROL REGISTER
ADDR (0x0001)
CONTROL REGISTER
INSTRUCTION
SDI (I)
Figure 4. AD7765 Status Register Read Cycle
Rev. 0 | Page 7 of 32
AD7765
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TA = 25°C, unless otherwise noted.
Table 4
Parameters
Rating
AVDD1 to GND
AVDD2, AVDD3, AVDD4 to GND
DVDD to GND
VINA+ , VINA− to GND1
VIN+ , VIN− to GND1
Digital Input Voltage to GND2
VREF to GND3
−0.3 V to +2.8 V
−0.3 V to +6 V
−0.3 V to +2.8 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +2.8 V
−0.3 V to +6 V
−0.3 V to +0.3 V
10 mA
ESD CAUTION
AGND to DGND
Input Current to Any Pin Except Supplies4
Operating Temperature Range
Commercial
−40°C to +85°C
−65°C to +150°C
150°C
Storage Temperature Range
Junction Temperature
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
143°C/W
45°C/W
215°C
220°C
1 kV
ESD
1 Absolute maximum voltage for VIN−, VIN+, VINA−, and VINA+ is 6.0 V or
AVDD3 + 0.3 V, whichever is lower.
2 Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,
whichever is lower.
3 Absolute maximum voltage on VREF input is 6.0 V or AVDD4 + 0.3 V,
whichever is lower.
4 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. 0 | Page 8 of 32
AD7765
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A–
IN
AV
3
DD
V
A+
A+
A–
V
+
OUT
REF
3
V
REFGND
IN
4
V
AV
AV
4
1
OUT
DD
DD
5
V
V
–
IN
6
AD7765
+
AGND1
IN
TOP VIEW
7
AV
2
R
DD
BIAS
(Not to Scale)
8
AGND3
OVERRANGE
SCO
AV
2
DD
9
AGND2
10
11
12
13
14
MCLK
FSO
DEC_RATE
SDO
DV
DD
SDI
RESET/PWRDWN
SYNC
FSI
Figure 5. 28-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
24
7 and 21
AVDD
AVDD
1
2
2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor.
5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be
decoupled to AGND1 (Pin 23) with a 100 nF capacitor.
28
25
17
22
AVDD
3
4
3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with a
100 nF capacitor.
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF
capacitor.
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with
a 100 nF capacitor.
Bias Current Setting Pin. A resistor must be inserted between this pin and AGND. For more details, see the
Bias Resistor Selection section.
AVDD
DVDD
RBIAS
23
20
8
26
27
1
2
3
4
5
AGND1
AGND2
AGND3
REFGND
Power Supply Ground for Analog Circuitry.
Power Supply Ground for Analog Circuitry.
Power Supply Ground for Analog Circuitry.
Reference Ground. Ground connection for the reference voltage.
Reference Input.
Negative Input to Differential Amplifier.
Positive Output from Differential Amplifier.
Positive Input to Differential Amplifier.
Negative Output from Differential Amplifier.
Negative Input to the Modulator.
VREF
+
VINA−
VOUTA+
VINA+
VOUTA−
VIN−
6
VIN+
Positive Input to the Modulator.
9
OVERRANGE
Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is
approaching the limit of the analog input to the modulator.
10
SCO
Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal
to ICLK. See the Clocking the AD7765 section for further details.
11
12
FSO
Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide.
SDO
Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an
SCO rising edge and is valid on the falling edge. See the AD7765 Interface section for further details.
13
SDI
Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched.
32 bits are required for each write; the first 16-bit word contains the device and register address and the
second word contains the data. See the AD7765 Interface section for further details.
Rev. 0 | Page 9 of 32
AD7765
Pin No.
Mnemonic
Description
14
FSI
Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first
data bit is latched in on the next SCO falling edge. See the AD7765 Interface section for further details.
15
16
SYNC
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize
multiple devices in a system. See the Synchronization section for further details.
Reset/Powerdown Pin. When a logic low is sensed on this pin, the part is powered down and all internal
circuitry is reset.
RESET
PWRDWN
/
19
18
MCLK
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the
frequency of this clock. See the Clocking the AD7765 section for more details.
Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a
decimation rate of 128× is selected. A decimation rate of 256× is selected by setting the pin to ground.
DEC_RATE
Rev. 0 | Page 10 of 32
AD7765
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD± = AVDD4 = 5 V, VREF+ = 4.096 V, MCLK amplitude = 5 V, TA = 25°C. Linearity plots are
measured to 16-bit accuracy. The input signal is reduced to avoid modulator overload and digital clipping. Fast Fourier transforms (FTTs)
of −0.5 dB tones are generated from 262,144 samples in normal power mode. All other FFTs are generated from 8,192 samples.
0
0
–25
–25
–50
–50
–75
–75
–100
–125
–150
–175
–100
–125
–150
–175
0
20k
40k
60k
78.124k
0
10k
20k
30k
40k
50k
60k
70k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Normal Power Mode; FFT,1 kHz, −0.5 dB Input Tone,
128× Decimation Rate
Figure 9. Low Power Mode; FFT,1 kHz, −0.5 dB Input Tone,
128× Decimation Rate
0
0
–25
–25
–50
–75
–50
–75
–100
–125
–150
–175
–100
–125
–150
–175
0
10k
20k
30k
39.062k
0
5k
10k
15k
20k
25k
30k
35k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10. Low Power Mode; FFT,1 kHz, −0.5 dB Input Tone,
256× Decimation Rate
Figure 7. Normal Power Mode; FFT,1 kHz, −0.5 dB Input Tone,
256× Decimation Rate
0
–25
–50
–75
0
–25
–50
–75
–100
–100
–125
–150
–175
–125
–150
–175
0
25k
50k
FREQUENCY (Hz)
75k
0
25k
50k
FREQUENCY (Hz)
75k
Figure 8. Normal Power Mode; FFT,1 kHz, −6 dB Input Tone,
128× Decimation Rate
Figure 11. Low Power Mode; FFT,1 kHz, − dB Input Tone,
128× Decimation Rate
Rev. 0 | Page 11 of 32
AD7765
0
0
–25
–25
–50
–50
–75
–75
–100
–125
–150
–100
–125
–150
–175
–175
0
25k
50k
FREQUENCY (Hz)
75k
0
5k
10k
15k
20k
25k
30k
35k
FREQUENCY (Hz)
Figure 12. Normal Power Mode; FFT,1 kHz, −6 dB Input Tone,
256× Decimation Rate
Figure 15 Low Power Mode; FFT,1 kHz, −6 dB Input Tone,
256× Decimation Rate
25
40
DV
DD
35
30
25
20
15
10
5
DV
DD
20
15
10
5
AV
1
DD
AV
1
DD
AV
2
DD
AV
2
DD
AV
3
DD
AV
3
DD
AV
30
4
AV
30
4
DD
DD
0
0
0
5
10
15
20
25
35
40
45
0
5
10
15
20
25
35
40
45
MCLK FREQUENCY (MHz)
MCLK FREQUENCY (MHz)
Figure 13. Normal Power Mode; Current Consumption vs. MCLK Frequency,
128× Decimation Rate
Figure 16. Low Power Mode; Current Consumption vs. MCLK Frequency,
128× Decimation Rate
40
35
20
18
DV
DD
DV
DD
16
14
12
10
8
30
25
20
15
10
5
AV
1
DD
AV
1
DD
AV
2
DD
AV
2
DD
6
4
AV
3
AV
3
DD
DD
2
AV
4
AV
4
DD
DD
0
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
MCLK FREQUENCY (MHz)
MCLK FREQUENCY (MHz)
Figure 14. Normal Power Mode; Current Consumption vs. MCLK Frequency,
256× Decimation Rate
Figure 17. Low Power Mode; Current Consumption vs. MCLK Frequency,
256× Decimation Rate
Rev. 0 | Page 12 of 32
AD7765
0.003225
0.003000
0.00300
0.00225
0.00150
0.00075
0
–40°C
+25°C
+85°C
0.002250
0.001500
0.000075
+25°C
–40°C
–0.00075
–0.00150
–0.00225
–0.00300
+85°C
0
–0.000120
6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59535
16-BIT CODE SCALING
6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59535
16-BIT CODE SCALING
Figure 18. Normal Power Mode INL
Figure 21. Low Power Mode INL
0
–20
110
109
108
107
106
105
104
103
102
LOW SNR
–40
NORMAL SNR
–60
–80
–100
–120
–140
–160
–180
0
20k
40k
60k
78124
0
64
128
192
256
FREQUENCY (Hz)
DECIMATION RATE
Figure 19. Normal Power Mode; IMD, fIN A = 49.7 kHz, fIN B = 50.3 kHz,
50 kHz Center Frequency, 128× Decimation Rate
Figure 22. Normal and Low Power Mode; SNR vs. Decimation Rate,
1 kHz, −0.5 dB Input Tone
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59535
CODE
Figure 20. DNL Plot
Rev. 0 | Page 13 of 32
AD7765
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
Zero Error Drift
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, excluding harmonics and dc. The value for SNR is
expressed in decibels (dB).
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental.
The change in the actual zero error value due to a temperature
change of 1°C. It is expressed as a percentage of full scale at
room temperature.
Gain Error
The first transition (from 100…000 to 100…001) should occur
for an analog voltage 1/2 LSB above the nominal negative full
scale. The last transition (from 011…110 to 011…111) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale. The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition, from the difference between the ideal levels.
For the AD7765, it is defined as
V22 +V32 +V42 +V52 +V62
THD
where:
dB = 20 log
( )
V1
Gain Error Drift
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
to the sixth harmonics.
The change in the actual gain error value due to a temperature
change of 1°C. It is expressed as a percentage of full scale at
room temperature.
Nonharmonic Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, excluding harmonics.
Dynamic Range
The ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in dB.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, ±, and so on. Intermodulation distortion terms are those
for which neither m nor n is equal to 0. For example, the second-
order terms include (fa + fb) and (fa − fb), while the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The AD7765 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves and the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, that is, the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dB.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero Error
The difference between the ideal midscale input voltage (when
both inputs are shorted together) and the actual voltage
producing the midscale output code.
Rev. 0 | Page 14 of 32
AD7765
THEORY OF OPERATION
The AD7765 employs three FIR filters in series. By using
different combinations of decimation ratios, data can be
obtained from the AD7765 at three data rates.
The AD7765 features an on-chip fully differential amplifier to
feed the Σ-Δ modulator pins , an on-chip reference buffer, and a
FIR filter block to perform the required digital filtering of the
Σ-Δ modulator output. Using this Σ-Δ conversion technique
with the added digital filtering, the analog input is converted
into an equivalent digital word.
The first filter receives data from the modulator at ICLK MHz
where it is decimated 4× to output data at (ICLK/4) MHz. The
second filter allows a choice of decimation rates: 16× or ±2×.
Σ-Δ MODULATION AND DIGITAL FILTERING
The digital filtering on the AD7765 provides full-band filtering.
This means that its stop-band attenuation occurs at the Nyquist
frequency (ODR/2). This feature provides increased protection
against aliasing of sampled frequencies that lie above the
Nyquist rate (ODR/2). The filter gives maximum attenuation at
the Nyquist rate (see Figure 26). This means that it attenuates all
possible alias frequencies by 115 dB or greater. The frequency
response in Figure 26 occurs when the AD7765 is operated with
a 40 MHz MCLK in the decimate 128× mode. Note that the first
stop-band frequency occurs at Nyquist. The frequency response
of the filter scales with both the decimation rate chosen and the
MCLK frequency applied.
The input waveform applied to the modulator is sampled and
an equivalent digital word is output to the digital filter at a rate
equal to ICLK. By employing oversampling, the quantization
noise is spread across a wide bandwidth from 0 to fICLK, This
means that the noise energy contained in the signal band of
interest is reduced (see Figure 2±). To further reduce the
quantization noise, a high order modulator is employed to
shape the noise spectrum so that most of the noise energy is
shifted out of the signal band (see Figure 24).
The third filter has a fixed decimation rate of 2×. Table 6 shows
some characteristics of the digital filtering where ICLK =
MCLK /2. The group delay of the filter is defined to be the
delay to the center of the impulse response and is equal to the
computation plus the filter delays. The delay until valid data is
available (the FILTER-SETTLE status bit is set) is approximately
twice the filter delay plus the computation delay. This is listed in
terms of MCLK periods in Table 6.
QUANTIZATION NOISE
fICLK/2
BAND OF INTEREST
Figure 23. Σ-Δ ADC, Quantization Noise
NOISE SHAPING
0
PASS-BAND RIPPLE = 0.05dB
–0.1dB FREQUENCY = 125.1kHz
–3dB FREQUENCY = 128kHz
STOP BAND = 156.25kHz
fICLK/2
BAND OF INTEREST
–20
Figure 24. Σ-Δ ADC, Noise Shaping
–40
–60
DIGITAL FILTER CUTOFF FREQUENCY
–80
fICLK/2
–100
–120
–140
–160
BAND OF INTEREST
Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 25) while also
reducing the data rate from fICLK at the input of the filter to
fICLK/128 or less at the output of the filter, depending on the
decimation rate used.
0
50
100
150
200
250
300
FREQUENCY (kHz)
Figure 26. Filter Frequency Response (156.25 kHz ODR)
Table 6. Configuration with Default Filter
SYNC
ICLK
Frequency
Decimation
Rate
Computation
Delay
to
Pass-Band
Output Data Rate
Data State
Filter Delay
174 μs
346.8 μs
283.2 μs
564.5 μs
FILTER-SETTLE Bandwidth (ODR)
20 MHz
20 MHz
12.288 MHz
12.288 MHz
128×
256×
128×
256×
Fully filtered 3.1 μs
Fully filtered 4.65 μs
Fully filtered 5.05 μs
Fully filtered 7.57 μs
14217 x tMCLK
27895 x tMCLK
14217 x tMCLK
27895 x tMCLK
62.5 kHz
31.25 kHz
38.4 kHz
19.2 kHz
156.25 kHz
78.125 kHz
96 kHz
48 kHz
Rev. 0 | Page 15 of 32
AD7765
AD7765 INPUT STRUCTURE
The AD7765 requires a 4.096 V input to the reference pin
VREF+, supplied by a high precision reference, such as the
ADR444. Because the input to the device’s Σ-Δ modulator is
fully differential, the effective differential reference range is
8.192 V.
Modulator _ InputFULLSCALE = 8.192V ×0.8 = 6.55±6V
This means that a maximum of ±±.2768 V p-p can be applied to
each of the AD7765 modulator inputs (Pin 5 and Pin 6), with
the AD7765 being specified with an input −0.5 dB down from
full scale (−0.5 dBFS).
VREF +(Diff ) = 2 × 4.096 = 8.192V
The AD7765 modulator inputs must have a common-mode
input of 2.048 V. Figure 27 shows the relative scaling between
the differential voltages applied to the modulator pins and the
respective 24-bit twos complement digital outputs.
As is inherent in Σ-Δ modulators, only a certain portion of this
full reference may be used. In the case of the AD7765, 80% of
the full differential reference can be applied to the modulator’s
differential inputs.
TWOS COMPLEMENT
DIGITAL OUTPUT
INPUT VOLTAGE (V)
OVERRANGE REGION
+4.096V
+3.2768V = MODULATOR FULL-SCALE = 80% OF 4.096V
V
V
+ = 3.6855V
– = 0.4105V
IN
IN
0111 1111 1111 1111 1111 1111
0111 1000 1101 0110 1111 1101
–0.5dBFS INPUT
INPUT TO MODULATOR
PIN 5 AND PIN 6
DIGITAL OUTPUT
ON SDO PIN
0000 0000 0000 0000 0000 0001
0000 0000 0000 0000 0000 0000
1111 1111 1111 1111 1111 1111
V
V
+ = 2.048V
– = 2.048V
IN
IN
V
– AND V +
IN
IN
–0.5dBFS INPUT
1000 0111 0010 1001 0000 0010
1000 0000 0000 0000 0000 0000
V
V
+ = 0.4105V
– = 3.6855V
IN
IN
80% OF 4.096V = MODULATOR FULL-SCALE = –3.2768V
–4.096V
OVERRANGE REGION
Figure 27. AD7765 Scaling; Modulator Input Voltage vs. Digital Output Code
Rev. 0 | Page 16 of 32
AD7765
The common-mode input at each of the differential amplifier
inputs (Pin VINA and Pin VINA−) can range from−0.5 V dc to
2.2 V dc. The amplifier has a constant output common-mode
voltage of 2.048 V, that is, VREF/2, the requisite common-mode
voltage for the modulator input pins (VIN+ and VIN−).
ON-CHIP DIFFERENTIAL AMPLIFIER
The AD7765 contains an on-board differential amplifier that
is recommended to drive the modulator input pins. Pin 1, Pin 2,
Pin ±, and Pin 4 on the AD7765 are the differential input and
output pins of the amplifier. The external components, RIN, RFB,
CFB, CS, and RM, are placed around Pin 1 through Pin 6 to create
the recommended configuration. To achieve the specified
performance, the differential amplifier should be configured as
a first-order antialias filter, as shown in Figure 28 using the
component values listed in Table 7. The inputs to the
differential amplifier are then routed through this external
component network before being applied to the modulator
inputs VIN− and VIN+(Pin 5 and Pin 6). Using the optimal
values in the table as an example yields a 25 dB attenuation at
the first alias point of 19.84 MHz.
Figure 29 shows the signal conditioning that occurs using the
differential amplifier configuration detailed in Table 7 with a
±2.5 V input signal to the differential amplifier. The amplifier
in this example is biased around ground and is scaled to give
±±.168 V p-p (−0.5 dBFS) on each modulator input with a
2.048 V common mode.
+3.632V
+2.048V
+0.464V
+2.5V
V
+
IN
0V
A
C
FB
–2.5V
R
FB
V
A–
IN
V
A+
OUT
+2.5V
0V
+3.632V
+2.048V
+0.464V
R
R
IN
M
B
A
B
1
3
2
4
5
V
V
–
+
V
–
IN
IN
DIFF
AMP
C
S
C
M
6
IN
R
R
M
IN
R
FB
–2.5V
V
A+
V
A–
IN
OUT
Figure 29. Differential Amplifier Signal Conditioning
C
FB
To obtain maximum performance from the AD7765, it is advisable
to drive the ADC with differential signals. Figure ±0 shows how a
bipolar, single-ended signal biased around ground can drive the
AD7765 with the use of an external op amp, such as the AD8021.
Figure 28. Differential Amplifier Configuration
Table 7. On-Chip Differential Filter Component Values
RIN
RFB
RM
CS
CFB
CM
(pF)
(kΩ)
(kΩ)
(Ω)
(pF)
(pF)
C
FB
Optimal
4.75
3.01
43
8.2
47
33
Tolerance
2.37 to
5.76
2.4 to
4.87
36 to
47
0 to 10
20 to
100
39 to
56
R
2R
FB
Range1
2R
1 Values shown were the acceptable tolerances for each component when
altered relative to the optimal values used to achieve the stated
specifications of the device.
V
IN
R
R
R
IN
M
M
AD8021
V
–
+
IN
DIFF
AMP
C
S
C
M
R
The range of values that can be used for each of the listed
components in the differential amplifier configuration is also
listed in Table 7. When using the differential amplifier to gain
the input voltages to the required modulator input range, it is
advisable to implement the gain function by changing RIN,
leaving the RFB as the listed optimal value.
V
IN
R
R
IN
FB
C
FB
Figure 30. Single-Ended-to-Differential Conversion
Rev. 0 | Page 17 of 32
AD7765
MODULATOR INPUT STRUCTURE
Sampling Switches SS1 and SS± are driven by ICLK, whereas
ICLK
The AD7765 employs a double-sampling front end, as shown in
Figure ±1. For simplicity, only the equivalent input circuitry for
VIN+is shown. The equivalent circuitry for VIN− is the same.
Sampling Switches SS2 and SS4 are driven by
. When
ICLK is high, the analog input voltage is connected to CS1. On
the falling edge of ICLK, the SS1 and SS± switches open and the
analog input is sampled on CS1. Similarly, when ICLK is low,
the analog input voltage is connected to CS2. On the rising
edge of ICLK, the SS2 and SS4 switches open, and the analog
input is sampled on CS2.
V
+
IN
CS1
SS1
SH3
CPA
SS3
SH1
CPB1
ANALOG
Capacitors CPA, CPB1, and CPB2 represent parasitic capaci-
tances that include the junction capacitances associated with
the MOS switches.
MODULATOR
CS2
SS2
SH2
SH4
Table 8. Equivalent Component Values
SS4
CPB2
CS1
CS2
CPA
CPB1/2
13 pF
13 pF
13 pF
5 pF
Figure 31. Equivalent Input Circuit
Rev. 0 | Page 18 of 32
AD7765
AD7765 INTERFACE
READING DATA
READING STATUS AND OTHER REGISTERS
The AD7765 uses an SPI-compatible serial interface. The
timing diagram in Figure 2 shows how the AD7765 transmits
its conversion results.
The AD7765 features a gain correction register, an overrange
register, and a read-only status register. To read back the
contents of these registers, the user must first write to the
control register of the device and set the bit that corresponds
to the register to be read. The next read operation outputs the
contents of the selected register (on the SDO pin) instead of a
conversion result.
The data read from the AD7765 is clocked out using the serial
clock output (SCO). The SCO frequency is half that of the
MCLK input to the AD7765.
The conversion result output on the serial data output (SDO)
To ensure that the next read cycle contains the contents of the
register written to, the write operation to that register must be
line is framed by the frame synchronization output,
, which
FSO
is sent logic low for ±2 SCO cycles. Each bit of the new
FSO
completed a minimum of 8 × tSCO before the falling edge of
which indicates the start of the next read cycle. See Figure 4 for
further details.
,
conversion result is clocked onto the SDO line on the rising
SCO edge and is valid on the falling SCO edge. The ±2-bit result
consists of the 24 data bits followed by five status bits followed
further by three zeros. The five status bits are listed in Table 9
and described below the table.
The AD7765 Registers section provides more information on
the relevant bits in the control register.
WRITING TO THE AD7765
Table 9. Status Bits During Data Read
A write operation to the AD7765 is shown in Figure ±. The
serial writing operation is synchronous to the SCO signal. The
D7
D6
OVR
D5
LPWR
D4
D3
FILTER-SETTLE
DEC_RATE 1 Don’t Care
FSI
status of the frame synchronization input,
FSI
, is checked on the
•
The FILTER-SETTLE bit indicates whether the data output
from the AD7765 is valid. After resetting the device (using
falling edge of the SCO signal. If the
line is low, then the
first data bit on the serial data in (SDI) line is latched in on the
next SCO falling edge.
the
pin) or clearing the digital filter (using the
RESET
pin), the FILTER-SETTLE bit goes logic low to
SYNC
FSI
Set the active edge of the
the SCO signal is high or low to allow setup and hold times
FSI
signal to occur at a position when
indicate that the full settling time of the filter has not yet
passed and that the data is not yet valid. The FILTER-
SETTLE bit also goes to zero when the input to the part
has asserted the overrange alerts.
from the SCO falling edge to be met. The width of the
signal can be set to between 1 and ±2 SCO periods wide. A
second, or subsequent, falling edge that occurs before
±2 SCO periods have elapsed, is ignored.
•
•
The OVR (overrange) bit is described in the Overrange
Alerts section.
Figure ± details the format for the serial data being written to
the AD7765 through the SDI pin. Thirty-two bits are required
for a write operation. The first 16 bits are used to select the
register address for which the data being read is intended. The
second 16 bits contain the data for the selected register.
The LPWR bit is set to logic high when the AD7765 is
operating in low power mode. See the Power Modes
section for further details.
•
The DEC_RATE 1 and DEC_RATE 0 bits indicate the
decimation ratio used. Table 10 is a truth table for the
decimation rate bits.
Writing to the AD7765 is allowed at any time, even while
reading a conversion result. Note that after writing to the
devices, valid data is not output until after the settling time for
the filter has elapsed. The FILTER-SETTLE status bit is asserted
at this point to indicate that the filter has settled and that valid
data is available at the output.
Table 10. Truth Table
Decimate
DEC_RATE 1
128×
256×
1
0
Rev. 0 | Page 19 of 32
AD7765
AD7765 FUNCTIONALITY
changes at the output data rate. If the modulator has sampled a
voltage input that exceeded the overrange limit during the
process of gathering samples for a particular conversion result
output, then the OVR bit is set to logic high.
SYNCHRONIZATION
SYNC
The
input to the AD7765 provides a synchronization
function that allows the user to begin gathering samples of the
analog front-end input from a known point in time.
LOGIC
LEVEL
SYNC
The
function allows multiple AD7765 devices, operated
SYNC RESET
HI
LO
t
from the same master clock that use common
signals to be synchronized so that each ADC simultaneously
updates its output register.
and
OVERRANGE
LIMIT
OUTPUT FREQUENCY
OF FIR FILTER 1 = ICLK/4
SYNC
RESET
Connect common MCLK,
AD7765 devices in the system. On the falling edge of the
signal, the digital filter sequencer is reset to 0. The filter is held
SYNC
, and
signals to all
OBSOLUTE INPUT
TO AD7765
SYNC
[(V +) – (V –)]
IN
IN
OUTPUT DATA RATE (ODR)
(ICLK/DECIMATION RATE
in a reset state until a rising edge of the SCO senses
high.
pulse of
OVERRANGE
LIMIT
SYNC
Thus, to perform a synchronization of devices, a
LOGIC
LEVEL
a minimum of 2.5 ICLK cycles in length can be applied,
HI
synchronous to the falling edge of SCO. On the first rising edge
SYNC
LO
of SCO after
and the multiple parts gather input samples synchronously.
SYNC
goes logic high, the filter is taken out of reset,
t
Figure 32. OVERRANGE Pin and OVR Bit vs. Absolute Voltage
Applied to Modulator
Following a
, the digital filter needs time to settle before
valid data can be read from the AD7765. The user knows there
is valid data on the SDO line by checking the FILTER-SETTLE
status bit (see D7 in Table 9) that is output with each conversion
The output points from FIR Filter 1 in Figure ±2 are not drawn
to scale relative to the output data rate points. The FIR Filter 1
output is updated either 16× or ±2× faster than the output data
rate depending on the decimation rate in operation.
SYNC
result. The time from the rising edge of
until the FILTER-
SETTLE bit asserts depends on the filter configuration used.
See the Theory of Operation section and the values listed in
Table 6 for details on calculating the time until FILTER-
SETTLE asserts. Note that the FILTER-SETTLE bit is designed
as a reactionary flag to alert the user when the conversion data
output is valid.
POWER MODES
During power-up, the AD7765 defaults to operate in normal
power mode. There is no register write required.
The AD7765 also offers low power mode. To operate the device
in low power mode, the user sets the LPWR bit in the control
register to logic high (See Figure ±±). Operating the AD7765 in
low power mode has no impact on the output data rate or
available bandwidth.
OVERRANGE ALERTS
The AD7765 offers an overrange function in both a pin and
status bit output. The overrange alerts indicate when the voltage
applied to the AD7765 modulator input pins exceeds the limit
set in the overrange register, indicating that the voltage applied
is approaching an overrange level for the modulator. To set this
limit, the user must program the register. The default overrange
limit is set to 80% of the VREF voltage (see the AD7765 Registers
section).
SCO (O)
32 × tSCO
FSI (I)
SDI (I)
CONTROL REGISTER
ADDRESS 0x0001
LOW POWER MODE
DATA 0x0010
Figure 33. Write Scheme for Low Power Mode
The OVERRANGE pin outputs logic high to alert the user
that the modulator has sampled an input voltage greater in
magnitude than the overrange limit as set in the overrange
register. The OVERRANGE pin is set to logic high when the
modulator samples an input above the overrange limit. Once
the input returns below the limit, the OVERRANGE pin returns
to zero. The OVERRANGE pin is updated after the first FIR
filter stage. Its output changes at the ICLK/4 frequency.
RESET PWRDWN
input to this pin logic low places the AD7765 in power-down
mode. All internal circuitry is reset. To utilize the
functionality, pulse the input to this pin low for a minimum of
one MCLK period. This action resets the internal circuitry.
The AD7765 features a
/
pin. Holding the
RESET
RESET
When the AD7765 receives a logic high input on the
PWRDWN
/
pin, the device powers up.
The OVR status bit is output as Bit D6 on SDO during a data
conversion and can be checked in the AD7765 status register.
This bit is less dynamic than the OVERRANGE pin output. It is
updated on each conversion result output, that is, the bit
Rev. 0 | Page 20 of 32
AD7765
Table 11. DEC_RATE Pin Settings
DECIMATION RATE PIN
Decimate
DEC_RATE Pin Max Output Data Rate
The decimation rate of the AD7765 is selected using the
DEC_RATE pin. Table 11 shows the voltage input settings
required for each of the three decimation rates.
128×
256×
DVDD
GND
156.25 kHz
78.125 kHz
Rev. 0 | Page 21 of 32
AD7765
DAISY CHAINING
Daisy chaining devices allows numerous devices to use the
same digital interface lines. This feature is especially useful for
reducing component count and wiring connections, such as
in isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
from the devices AD7765 (B), AD7765 (C), and AD7765 (D),
respectively with all conversion results output in an MSB first
sequence. The signals output from the daisy chain are the
stream of conversion results from the SDO pin of AD7765 (A)
FSO
and the
signal output by the first device in the chain,
AD7765 (A).
The block diagram in Figure ±4 shows how to connect devices
to achieve daisy-chain functionality. Figure ±4 shows four
AD7765 devices daisy-chained together with a common
MCLK signal applied.
FSO
The falling edge of
signals the MSB of the first conversion
FSO
output in the chain.
stays logic low throughout the ±2 SCO
clock periods needed to output the AD7765 (A) result and then
goes logic high during the output of the conversion results from
the devices AD7765 (B), AD7765 (C), and AD7765 (D).
READING DATA IN DAISY-CHAIN MODE
The maximum number of devices that can be daisy-chained is
dependent on the decimation rate selected. Calculate the
maximum number of devices that can be daisy chained by
simply dividing the chosen decimation rate by ±2 (the number
of bits that must be clocked out for each conversion). Table 12
provides the maximum number of chained devices for each
decimation rate.
Referring to Figure ±4, note that the SDO line of AD7765 (A)
provides the output data from the chain of AD7765 converters.
Also, note that for the last device in the chain, AD7765 (D), the
SDI pin is connected to ground. All of the devices in the chain
SYNC
must use common MCLK and
signals.
To enable the daisy-chain conversion process, apply a common
SYNC
pulse to all devices (see the Synchronization section).
Table 12. Maximum Chain Length for all Decimation Rates
SYNC
After applying a
pulse to all devices, the filter settling
Decimation Rate
Maximum Chain Length
time must pass before the FILTER-SETTLE bit is asserted
indicating valid conversion data at the output of the chain of
devices. As shown in Figure ±5, the first conversion result is
output from the device labeled AD7765 (A). This ±2-bit
conversion result is then followed by the conversion results
256×
128×
8
4
FSI
AD7765
(D)
AD7765
(C)
AD7765
(B)
AD7765
(A)
FSI
FSI
FSI
FSI
FSO
SDI
SDO
SDI
SDO
SDI
SDO
SDI
SDO
SYNC
SYNC
MCLK
SYNC
SYNC
MCLK
MCLK
MCLK
SYNC
MCLK
Figure 34. Daisy-Chaining Four Devices in Decimate 128× Mode Using a 40 MHz MCLK Signal
32 × tSCO
32 × tSCO
32 × tSCO
32 × tSCO
SCO
AD7765 (A)
32-BIT OUTPUT
AD7765 (B)
32-BIT OUTPUT
AD7765 (C)
32-BIT OUTPUT
AD7765 (D)
32-BIT OUTPUT
AD7765 (A)
32-BIT OUTPUT
AD7765 (B)
32-BIT OUTPUT
SDO (A)
FSO (A)
AD7765 (B)
AD7765 (C)
AD7765 (D)
AD7765 (C)
AD7765 (D)
AD7765 (D)
AD7765 (B)
AD7765 (C)
AD7765 (D)
AD7765 (C)
AD7765 (D)
SDI (A) = SDO (B)
SDI (B) = SDO (C)
SDI (C) = SDO (D)
Figure 35. Daisy-Chain Mode, Data Read Timing Diagram
(for Daisy-Chain Configuration Shown in Figure 34)
Rev. 0 | Page 22 of 32
AD7765
FSI
and the rising edge of
must be between ±2 × (n−1) to ±2 × n
WRITING DATA IN DAISY-CHAIN MODE
SCO periods. For example, if three AD7765 devices are being
FSI
Writing to AD7765 devices in daisy-chain mode is similar to
writing to a single device. The serial writing operation is
synchronous to the SCO signal. The status of the frame synchro-
written to in daisy-chain mode,
is logic low for between
±2 × (±−1) to ±2 × ± SCO pulses. This means that the rising
edge of FSI must occur between the 64th and 96th SCO period.
FSI
nization input,
FSI
, is checked on the falling edge of the SCO
signal. If the
line is low, then the first data bit on the serial
The AD7765 devices can be written to at any time. The falling
FSI
data in the SDI line is latched in on the next SCO falling edge.
edge of
overrides all attempts to read data from the SDO
FSI
pin. In the case of a daisy chain, the
signal remaining logic
Writing data to the AD7765 in daisy-chain mode operates with
the same timing structure as writing to a single device (see
Figure ±). The difference between writing to a single device
and writing to a number of daisy-chained devices is in the
low for more than ±2 SCO periods indicates to the AD7765
device that there are more devices further on in the chain. This
means the AD7765 directs data that is input on the SDI pin to
its SDO pin. This ensures that data is passed to the next device
in the chain,
FSI
implementation of the
are in the daisy chain determines the period for which the
signal must remain logic low. To write to n number of devices
signal. The number of devices that
FSI
FSI
in the daisy chain, the period between the falling edge of
FSI
AD7765
(D)
AD7765
(C)
AD7765
(B)
AD7765
(A)
FSI
FSI
SDI
SYNC
MCLK
FSI
FSI
FSO
SDI
SDO
SDO
SDI
SDO
SDI
SDO
SDI
SYNC
SYNC
SYNC
MCLK
MCLK
MCLK
SYNC
MCLK
Figure 36. Writing to AD7765 Daisy-Chain Configuration
t10
FSI
32 × tSCO
32 × tSCO
32 × tSCO
31 × tSCO
SCO
SDI (D)
SDI (C) = SDO (D)
SDI (B) = SDO (C)
SDI (A) = SDO (B)
SDI (D)
SDI (C)
SDI (B)
SDI (A)
Figure 37. Daisy-Chain Write Timing Diagram. Writing to Four AD7765 Devices
Rev. 0 | Page 23 of 32
AD7765
CLOCKING THE AD7765
The AD7765 requires an external low jitter clock source. This
signal is applied to the MCLK pin. An internal clock signal
(ICLK) is derived from the MCLK input signal. The ICLK
controls the internal operation of the AD7765. The maximum
ICLK frequency is 20 MHz. To generate the ICLK
256
tj(rms)
=
= 470 ps
2× π×19.2×10± ×105.45
The input amplitude also has an effect on these jitter figures.
For example, if the input level is ± dB below full-scale, the
allowable jitter is increased by a factor of √2, increasing the first
example to 57.75 ps rms. This happens when the maximum
slew rate is decreased by a reduction in amplitude.
ICLK = MCLK/2
For output data rates equal to those used in audio systems, a
12.288 MHz ICLK frequency can be used. As shown in Table 6,
output data rates of 96 kHz and 48 kHz are achievable with this
ICLK frequency.
Figure ±8 and Figure ±9 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency, but
with different amplitudes.
1.0
MCLK JITTER REQUIREMENTS
The MCLK jitter requirements depend on a number of factors
and are given by
0.5
0
OSR
tj(rms)
=
SNR (dB)
2× π× fIN ×10
20
where:
OSR = oversampling ratio = fICLK/ODR.
fIN = maximum input frequency.
SNR(dB) = target SNR.
–0.5
–1.0
Example 1
Figure 38. Maximum Slew Rate of Sine Wave
with Amplitude of 2 V p-p
This example can be taken from Table 6, where:
ODR = 156.25 kHz.
fICLK = 20 MHz.
fIN (max) = 78.625 kHz.
SNR = 104 dB.
1.0
0.5
128
tj(rms)
=
= 102.29 ps
2× π×78.625×10± ×105.±5
0
This is the maximum allowable clock jitter for a full-scale,
78.625 kHz input tone with the given ICLK and output
data rate.
–0.5
–1.0
Example 2
Take a second example for Table 6, where:
ODR = 48 kHz.
Figure 39. Maximum Slew Rate of Same Frequency Sine Wave
with Amplitude of 1 V p-p
fICLK = 12.288 MHz.
fIN (max) = 19.2 kHz.
SNR = 109 dB.
Rev. 0 | Page 24 of 32
AD7765
DECOUPLING AND LAYOUT INFORMATION
SUPPLY DECOUPLING
ADR444
+VIN VOUT
200Ω
2
6
V
+
REF
PIN 27
7.5V
The decoupling of the supplies applied to the AD7765 is
important in achieving maximum performance. Each supply
pin must be decoupled to the correct ground pin with a 100 nF,
060± case size capacitor.
+
+
GND
4
10µF
100nF
100µF
100nF
Figure 41. Reference Connection
Pay particular attention to decoupling Pin 7 (AVDD2) directly to
the nearest ground pin (Pin 8). The digital ground pin, AGND2
(Pin 20) is routed directly to ground. Also, connect REFGND
(Pin 26) directly to ground.
DIFFERENTIAL AMPLIFIER COMPONENTS
The correct components for use around the on-chip differential
amplifier are detailed in Table 7. Matching the components on
both sides of the differential amplifier is important to minimize
distortion of the signal applied to the amplifier. A tolerance of
0.1% or better is required for these components. Symmetrical
routing of the tracks on both sides of the differential amplifier
also assists in achieving stated performance. Figure 42 shows a
typical layout for the components around the differential
amplifier. Note that the traces for both differential paths are
made as symmetrical as possible, and the feedback resistors and
capacitors are placed on the underside of the PCB to enable the
simplest routing.
The DVDD (Pin 17) and AVDD± (Pin 28) supplies should be
decoupled to the ground plane at a point away from the device.
It is advised to decouple the supplies that are connected to the
following supply pins through 060± size,100nF capacitors to a
star ground point linked to Pin 2± (AGND1)
•
•
•
•
VREF+ (Pin 27)
AVDD4 (Pin 25)
AVDD1 (Pin 24)
AVDD2 (Pin 21)
R
IN
R
FB
C
FB
A layout decoupling scheme for the these supplies, which
connect to the right hand side of the AD776, is shown in
Figure 40. Note the star-point ground created at Pin 2±.
V
V
A–
IN
A+
IN
AV
4
DD
(PIN 25)
R
GND
IN
AV 3 (PIN 28)
DD
Figure 42.Typical Layout Structure for Surrounding Components
PIN 23
STAR-POINT
GND
V
+ (PIN 27)
REF
LAYOUT CONSIDERATIONS
AV 1 (PIN 24)
DD
While using the correct components is essential to achieving
optimum performance, the correct layout is just as important.
The AD7765 product page on analog.com contains the Gerber
files for the AD7765 evaluation board. These files should be
downloaded and used as a reference when designing any system
using the AD7765.
AV 2 (PIN 21)
DD
GND
PIN 15
VIA TO GND
FROM PIN 20
Figure 40.AD7765 Supply Decoupling
REFERENCE VOLTAGE FILTERING
The use of ground planes should also be carefully considered.
To ensure that the return currents through the decoupling
capacitors are flowing to the correct ground pin, the ground
side of the capacitors should be as close to the ground pin
associated with that supply as recommended in the Supply
Decoupling section.
A low noise reference source, such as the ADR444 or ADR±4
(4.096 V), is suitable for use with the AD7765. The reference
voltage supplied to the AD7765 should be decoupled and
filtered, as shown in Figure 41.
The recommended scheme for the reference voltage supply
is a 200 Ω series resistor connected to a 100 μF tantalum
capacitor, followed by a 10 nF decoupling capacitor very close to
the VREF+ pin
Rev. 0 | Page 25 of 32
AD7765
Data can then be read from the device using the default gain
and overrange threshold values. The conversion data read is not
valid, however, until the settling time of the filter has elapsed.
Once this has occurred, the FILTER-SETTLE status bit is set,
indicating that the data is valid.
USING THE AD7765
The following is the recommended sequence for powering up
and using the AD7765:
1. Apply power to the device.
2. Start the clock oscillator while applying MCLK.
Values for gain and overrange thresholds can be written to or
read from the respective registers at this stage.
RESET
±. Take
low for a minimum of one MCLK cycle.
BIAS RESISTOR SELECTION
RESET
4. Wait a minimum of two MCLK cycles after
been released.
has
The AD7765 requires a resistor to be connected between the
R
BIAS and AGND pins. The resistor value should be selected to
SYNC
SYNC
5. If multiple parts are being synchronized, a
must be applied to the parts. Otherwise, no
required.
pulse
pulse is
give a current of 25 ꢀA through the resistor to ground. For a
4.096 V reference voltage, the correct resistor value is 160 kꢁ.
SYNC
When applying the
pulse
SYNC
•
The issue of a
pulse to the device must not
coincide with a write to the device.
SYNC
•
Ensure that the
pulse is taken low for a
minimum of 2.5 ICLK cycles.
Rev. 0 | Page 26 of 32
AD7765
AD7765 REGISTERS
The AD7765 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and
differential amplifier and provides an option to power down the AD7765. There are also digital gain and overrange threshold registers.
Writing to these registers involves writing the register address followed by a 16-bit data word. The register addresses, details of individual
bits, and default values are provided in this section.
CONTROL REGISTER
Table 13. Control Register (Address 0x0001, Default Value 0x0000)
MSB
LSB
D0
D15 D14
D13
D12 D11
D10 D9
SYNC
D8 D7
BYPASS
REF
D6 D5 D4 D3
D2
D1
0
RD
OVR
RD
GAIN
0
RD
0
0
0
0
0
PWR
LPWR REF BUF
OFF
AMP
OFF
STAT
DOWN
Table 14. Bit Descriptions of Control Register
Bit Mnemonic
14 RD OVR1, 2,
Comment
Read Overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register
instead of a conversion result.
Read Gain. If this bit is set, the next read operation outputs the contents of the digital gain register.
Read Status. If this bit is set, the next read operation outputs the contents of the status register.
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple
devices synchronizes all filters.
13 RD GAIN1, 2
11 RD STAT1, 2
9
SYNC1
7
3
2
1
0
BYPASS REF Bypass Reference. Setting this bit bypasses the reference buffer if the buffer is off.
PWR DOWN Power Down. A logic high powers the device down without resetting. Writing a 0 to this bit powers the device back up.
LPWR
REF BUF OFF Reference Buffer Off. Asserting this bit powers down the reference buffer.
AMP OFF Amplifier Off. Asserting this bit switches the differential amplifier off.
Low Power Mode. Set to Logic 1 when AD7765 is in low power mode.
1 Bit 14 to Bit 11 and Bit 9 are self-clearing bits.
2 Only one of the bits can be set in any write operation because it determines the contents of the next read operation.
STATUS REGISTER
Table 15. Status Register (Read Only)
MSB
LSB
D0
D15
D14 D13 D12 D11 D10
D9
D8
D7 D6 D5 D4
D3
D2
D1
PARTNO
1
0
0
0
FILTER-
SETTLE
0
OVR
0
1
0
REF BUF
ON
AMP
ON
LPWR DEC 1 DEC 0
Table 16. Bit Descriptions of Status Register
Bit
15
10
Mnemonic Comment
PARTNO
Part Number. This bit is set to one for the AD7765.
FILTER-
SETTLE
Filter Settling Bit. This bit corresponds to the FILTER-SETTLE bit in the status word output in the second 16-bit read
operation. It indicates when data is valid.
9
0
Zero. This bit is set to Logic 0.
8
OVR
Overrange. If the current analog input exceeds the current overrange threshold, this bit is set.
4
REF BUF ON Reference Buffer On. This bit is set when the reference buffer is in use.
3
2
AMP ON
LPWR
DEC[1:0]
Amplifier On. This bit is set when the input amplifier is in use.
Low Power Mode. This bit is set when operating in low power mode.
Decimation Rate. These bits correspond to decimation rate in use.
1 to 0
Rev. 0 | Page 27 of 32
AD7765
OVERRANGE REGISTER—ADDRESS 0x0005
Non-Bit-Mapped, Default Value 0xCCCC
GAIN REGISTER—ADDRESS 0x0004
Non-Bit-Mapped, Default Value 0xA000
The overrange register value is compared with the output of the
first decimation filter to obtain an overload indication with
minimum propagation delay. This is prior to any gain scaling or
offset adjustment. The default value is 0xCCCC, which corre-
sponds to 80% of VREF (the maximum permitted analog input
voltage). Assuming VREF = 4.096 V, the bit is then set when the
input voltage exceeds approximately 6.55 V p-p differential. The
overrange bit is set immediately if the analog input voltage
exceeds 100% of VREF for more than four consecutive samples at
the modulator rate.
The gain register is scaled such that 0x8000 corresponds to a
gain of 1.0. The default value of this register is 1.25 (0xA000).
This results in a full-scale digital output when the input is at
80% of VREF, tying in with the maximum analog input range of
±80% of VREF p-p.
Rev. 0 | Page 28 of 32
AD7765
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 43. 28-Lead Thin Shrink Small Outline [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7765BRUZ1
AD7765BRUZ-REEL71
EVAL-AD7765EBZ1
Temperature Range
Package Description
Package Option
RU-28
RU-28
–40°C to +85°C
–40°C to +85°C
28-Lead Thin Shrink Small Outline [TSSOP]
28-Lead Thin Shrink Small Outline [TSSOP]
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 29 of 32
AD7765
NOTES
Rev. 0 | Page 30 of 32
AD7765
NOTES
Rev. 0 | Page 31 of 32
AD7765
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06519-0-6/07(0)
Rev. 0 | Page 32 of 32
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1-CH 24-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16
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