AD7766BRUZ [ROCHESTER]
1-CH 24-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16;
| 型号： | AD7766BRUZ |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CH 24-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16 PC 光电二极管 转换器 |
| 文件： | 总25页 (文件大小：2644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24-Bit, 8.5 mW, 109 dB,
128 kSPS/64 kSPS/32 kSPS ADCs
AD7766
FEATURES
GENERAL DESCRIPTION
Oversampled successive approximation (SAR) architecture
High performance ac and dc accuracy, low power
115.5 dB dynamic range, 32 kSPS (AD7766-2)
112.5 dB dynamic range, 64 kSPS (AD7766-1)
109.5 dB dynamic range, 128 kSPS (AD7766)
−112 dB THD
The AD7766/AD7766-1/AD7766-2 are high performance,
24-bit, oversampled SAR analog-to-digital converters (ADCs).
The AD7766/AD7766-1/AD7766-2 combine the benefits of a
large dynamic range and input bandwidth, consuming 15 mW,
10.5 mW, and 8.5 mW power, respectively, and are contained in
a 16-lead TSSOP package.
Exceptionally low power
Ideal for ultralow power data acquisition (such as PCI- and USB-
based systems), the AD7766/AD7766-1/AD7766-2 provide 24-bit
resolution. The combination of exceptional SNR, wide dynamic
range, and outstanding dc accuracy make the AD7766/AD7766-1/
AD7766-2 ideally suited for measuring small signal changes over a
wide dynamic range. This is particularly suitable for applications
where small changes on the input are measured on larger ac or
dc signals. In such an application, the AD7766/AD7766-1/
AD7766-2 accurately gather both ac and dc information.
8.5 mW, 32 kSPS (AD7766-2)
10.5 mW, 64 kSPS (AD7766-1)
15 mW, 128 kSPS (AD7766)
High dc accuracy
24 bits, no missing codes (NMC)
INL: 6 ppm (typical), 15 ppm (maximum)
Low temperature drift
Zero error drift: 15 nV/°C
Gain error drift: 0.4 ppm/°C
The AD7766/AD7766-1/AD7766-2 include an on-board digital
filter (complete with linear phase response) that acts to elimi-
nate out-of-band noise by filtering the oversampled input voltage.
The oversampled architecture also reduces front-end antialias
requirements. Other features of the AD7766/AD7766-1/AD7766-2
On-chip low-pass FIR filter
Linear phase response
Pass-band ripple: 0.005 dB
Stop-band attenuation: 100 dB
2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options
Flexible interfacing options
SYNC PD
include a
/
(synchronization/power-down) pin, allowing
Synchronization of multiple devices
Daisy-chain capability
Power-down function
the synchronization of multiple AD7766/AD7766-1/AD7766-2
devices. The addition of an SDI pin provides the option of daisy
chaining multiple AD7766/AD7766-1/AD7766-2 devices.
Temperature range: −40°C to +105°C
The AD7766/AD7766-1/AD7766-2 operate from a 2.5 V supply
using a 5 V reference. The devices operate from −40°C to +105°C.
APPLICATIONS
Low power PCI/USB data acquisition systems
Low power wireless acquisition systems
Vibration analysis
Instrumentation
High precision medical acquisition
RELATED DEVICES
Table 1. 24-Bit ADCs
Part No.
Description
AD7760
2.5 MSPS, 100 dB dynamic range,1 on-board differential
amp and reference buffer, parallel, variable decimation
625 kSPS, 109 dB dynamic range,1 on-board differential
amp and reference buffer, parallel/serial, variable
decimation
AD7762/
AD7763
FUNCTIONAL BLOCK DIAGRAM
AV
AGND MCLK
DV
V
DGND
DD
DD
DRIVE
312 kSPS, 109 dB dynamic range,1 on-board differential
amp and reference buffer, variable decimation (pin)
156 kSPS, 112 dB dynamic range,1 on-board differential
amp and reference buffer, variable decimation (pin)
AD7764
AD7765
V
REF+
V
IN+
DIGITAL
FIR FILTER
SUCCESSIVE
APPROXIMATION
ADC
SYNC/PD
CS
128 kSPS, 109.5 dB,1 15 mW, 18-bit INL, serial interface
64 kSPS 112.5 dB,1 10.5 mW, 18-bit INL, serial interface
32 kSPS, 115.5 dB,1 8.5 mW, 18-bit INL, serial interface
V
AD7767
IN–
SERIAL INTERFACE
AND
CONTROL LOGIC
REFGND
AD7767-1
AD7767-2
AD7766/
AD7766-1/
AD7766-2
1 Dynamic range at maximum output data rate.
SCLK DRDY SDO SDI
Figure 1.
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD7766
TABLE OF CONTENTS
Features .............................................................................................. 1
Supply and Reference Voltages................................................. 16
AD7766/AD7766-1/AD77662-2 Interface.................................. 17
Initial Power-Up ......................................................................... 17
Reading Data............................................................................... 17
Power-Down, Reset, and Synchronization ............................. 17
Daisy Chaining ............................................................................... 18
Reading Data in Daisy-Chain Mode ....................................... 18
Choosing the SCLK Frequency ................................................ 18
Daisy-Chain Mode Configuration and Timing Diagrams ... 19
Driving the AD7766/AD7766-1/AD7766-2............................... 20
Differential Signal Source ......................................................... 20
Single-Ended Signal Source ...................................................... 20
Antialiasing ................................................................................. 21
Power Dissipation....................................................................... 21
VREF+ Input Signal ....................................................................... 22
Multiplexing Analog Input Channels...................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Related Devices................................................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
AD7766/AD7766-1/AD7766-2 Transfer Function................ 15
Converter Operation.................................................................. 15
Analog Input Structure.............................................................. 16
REVISION HISTORY
4/10—Rev. B to Rev. C
Changes to Pin 8 Description ......................................................... 9
Changes to Table 8.......................................................................... 20
3/09—Rev. A to Rev. B
Changes to tSETTLING Parameter, Table 3.......................................... 5
Changes to Table 7.......................................................................... 17
1/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Change to AD7766, Intermodulation Distortion (IMD)
Parameter and Integral Nonlinearity Parameter, Table 2....... 3
Change to Figure 21 and Figure 24 .............................................. 12
Changes to Supply and Reference Voltages Section................... 16
Changes to Choosing the SCLK Frequency Section.................. 18
Changes to Driving the AD7766 Section .................................... 20
Changes to Single-Ended Signal Source Section........................ 20
Changes to Figure 40 and Figure 41............................................. 20
Added Table 8; Renumbered Sequentially .................................. 20
Change to Figure 42 ....................................................................... 21
Changes to Antialiasing Section................................................... 21
Changes to Table 9.......................................................................... 21
Changes to VREF+ Input Signal Section......................................... 22
Changes to Figure 46...................................................................... 22
8/07—Revision 0: Initial Version
Rev. C | Page 2 of 24
AD7766
SPECIFICATIONS
AVDD = DVDD = 2.5 V 5ꢀ, VDRIVE = 1.8 V to 3.6 V, VREF+ = 5 V, MCLK = 1 MHz, common-mode input = VREF+/2, TA = −40°C to +105°C,
unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OUTPUT DATA RATE (ODR)
AD7766
AD7766-1
Decimate by 8
Decimate by 16
Decimate by 32
128
64
32
kHz
kHz
kHz
AD7766-2
ANALOG INPUT1
Differential Input Voltage
Absolute Input Voltage
VIN+ − VIN−
VIN+
VREF+
+VREF+ + 0.1
V p-p
V
−0.1
−0.1
VIN−
+VREF+ + 0.1
VREF+/2 + 5%
V
V
pF
Common-Mode Input Voltage
Input Capacitance
VREF+/2 − 5% VREF+/2
22
DYNAMIC PERFORMANCE
AD7766
Decimate by 8, ODR = 128 kHz
Shorted inputs
Full-scale input amplitude, 1 kHz tone
Dynamic Range2
108
107
109.5
108.5
−128
−112
dB
dB
dB
dB
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR)2 Full-scale input amplitude, 1 kHz tone
−116
−103
Total Harmonic Distortion (THD)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Full-scale input amplitude, 1 kHz tone
Tone A = 49.7 kHz, Tone B = 50.3 kHz
−133
−109
dB
dB
Third-Order Terms
AD7766-1
Decimate by 16, ODR = 64 kHz
Shorted inputs
Full-scale input amplitude, 1 kHz tone
Dynamic Range2
111
110
112.5
111.5
−128
−112
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR)2 Full-scale input amplitude, 1 kHz tone
−116
−103
Total Harmonic Distortion (THD)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Full-scale input amplitude, 1 kHz tone
Tone A = 24.7 kHz, Tone B = 25.3 kHz
−133
−108
Third-Order Terms
AD7766-2
Decimate by 32, ODR = 32 kHz
Shorted inputs
Full-scale input amplitude, 1 kHz tone
Dynamic Range2
114
112
115.5
113.5
−128
−112
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR)2 Full-scale input amplitude, 1 kHz tone
−116
−103
Total Harmonic Distortion (THD)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Full-scale input amplitude, 1 kHz tone
Tone A = 11.7 kHz, Tone B = 12.3 kHz
−137
−108
Third-Order Terms
DC ACCURACY1
For all devices
Resolution
No missing codes
24
Bits
Differential Nonlinearity2
Integral Nonlinearity2
Zero Error2
Guaranteed monotonic to 24 bits
16-bit linearity
6
20
0.0075
15
0.4
15
ppm
μV
% FS
nV/°C
ppm/°C
dB
Gain Error2
0.075
Zero Error Drift2
Gain Error Drift2
Common-Mode Rejection Ratio2
50 Hz tone
−110
Rev. C | Page 3 of 24
AD7766
Parameter
DIGITAL FILTER RESPONSE1
Test Conditions/Comments
Min
Typ
Max
Unit
Group Delay
37/ODR
74/ODR
ꢀs
ꢀs
Settling Time (Latency)
Pass-Band Ripple
Pass Band
−3 dB Bandwidth
Stop-Band Frequency
Stop-Band Attenuation
REFERENCE INPUT1
VREF+ Input Voltage
DIGITAL INPUTS (Logic Levels)1
VIL
Complete settling
0.005
dB
Hz
Hz
Hz
dB
0.453 × ODR
0.49 × ODR
0.547 × ODR
100
2.4
2 × AVDD
V
−0.3
0.7 × VDRIVE
+0.3 × VDRIVE
VDRIVE + 0.3
1
V
V
VIH
Input Leakage Current
Input Capacitance
Master Clock Rate
Serial Clock Rate
DIGITAL OUTPUTS1
Data Format
μA/pin
pF
MHz
Hz
5
1.024
1/t8
Serial 24 bits, twos complement
(MSB first)
VOL
VOH
ISINK = +500 μA
ISOURCE = −500 ꢀA
0.4
3.6
V
V
VDRIVE – 0.3
POWER REQUIREMENTS1
AVDD
DVDD
VDRIVE
5%
5%
2.5
2.5
2.5
V
V
V
1.7
CURRENT SPECIFICATIONS
MCLK = 1.024 MHz
AD7766 Operational Current
128 kHz output data rate
AIDD
DIDD
IREF
1.3
3.9
0.35
1.5
4.8
0.425
mA
mA
mA
AD7766-1 Operational Current
AIDD
DIDD
IREF
64 kHz output data rate
32 kHz output data rate
1.3
2.2
0.35
1.5
2.85
0.425
mA
mA
mA
AD7766-2 Operational Current
AIDD
DIDD
IREF
1.3
1.37
0.35
1.5
1.86
0.425
mA
mA
mA
Static Current with MCLK Stopped
AIDD
DIDD
Power-Down Mode Current
AIDD
For all devices
For all devices
0.9
1
1
93
mA
μA
0.1
1
6
93
μA
μA
DIDD
POWER DISSIPATION
AD7766 Operational Power
AD7766-1 Operational Power
AD7766-2 Operational Power
MCLK = 1.024 MHz
128 kHz output data rate
64 kHz output data rate
32 kHz output data rate
15
10.5
8.5
18
13
10.5
mW
mW
mW
1 Specifications are for all devices, AD7766, AD7766-1, and AD7766-2.
2 See the Terminology section.
Rev. C | Page 4 of 24
AD7766
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V 5ꢀ, VDRIVE = 1.7 V to 3.6 V, VREF+ = 5 V, common-mode input = VREF+/2, TA = −40°C (TMIN) to +105°C (TMAX),
unless otherwise noted.1
Table 3.
Parameter
Limit at tMIN, tMAX
Unit
Description
DRDY OPERATION
t1
510
100
900
265
128
71
ns typ
ns min
MCLK rising edge to DRDY falling edge
MCLK high pulse width
2
t2
t3
2
ns max MCLK low pulse width
t4
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
MCLK rising edge to DRDY rising edge (AD7766)
MCLK rising edge to DRDY rising edge (AD7766-1)
MCLK rising edge to DRDY rising edge (AD7766-2)
DRDY pulse width (AD7766)
t5
294
435
492
tDRDY − t5
DRDY pulse width (AD7766-1)
DRDY pulse width (AD7766-2)
3
tREAD
DRDY low period, read data during this period
3
tDRDY
n × 8 × tMCLK
ns typ
DRDY period
READ OPERATION
t6
t7
t8
0
ns min
DRDY falling edge to CS setup time
6
ns max CS falling edge to SDO tristate disabled
60
50
25
24
10
10
10
1/t8
6
ns max Data access time after SCLK falling edge (VDRIVE = 1.7 V)
ns max Data access time after SCLK falling edge (VDRIVE = 2.3 V)
ns max Data access time after SCLK falling edge (VDRIVE = 2.7 V)
ns max Data access time after SCLK falling edge (VDRIVE = 3.0 V)
ns min
ns min
ns min
t9
SCLK falling edge to data valid hold time (VDRIVE = 3.6 V)
SCLK high pulse width
SCLK low pulse width
t10
t11
tSCLK
t12
t13
sec min Minimum SCLK period
ns max Bus relinquish time after CS rising edge
0
ns min
CS rising edge to DRDY rising edge
READ OPERATION WITH CS LOW
t14
t15
0
0
ns min
DRDY falling edge to data valid setup time
ns max DRDY rising edge to data valid hold time
DAISY-CHAIN OPERATION
t16
t17
1
2
ns min
SDI valid to SCLK falling edge setup time
ns max SCLK falling edge to SDI valid hold time
SYNC/PD OPERATION
t18
t19
t20
t21
1
ns typ
ns typ
ns min
ns typ
tMCLK
SYNC/PD falling edge to MCLK rising edge
20
MCLK rising edge to DRDY rising edge going into SYNC/PD mode
SYNC/PD rising edge to MCLK rising edge
1
510
MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode
Filter settling time after a reset or power-down
3
tSETTLING
(592 × n) + 2
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V.
2 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum
MCLK frequency is 1.024 MHz.
3 n = 1 for AD7766, n = 2 for the AD7766-1, n = 4 for the AD7766-2.
Rev. C | Page 5 of 24
AD7766
TIMING DIAGRAMS
t2
1
8 × n
t4
1
8 × n
MCLK
t3
t1
t5
t5
tREAD
DRDY
tDRDY
DRDY
Figure 2.
vs. MCLK Timing Diagram, n = 1 for AD7766 (Decimate by 8), n = 2 for AD7766-1 (Decimate by 16), n = 4 for AD7766-2 (Decimate by 32)
tDRDY
tREAD
DRDY
t13
t6
CS
t10
1
23
SCLK
t11
t8
t9
t7
t12
SDO
MSB
D22
D21
D20
D1
LSB
CS
Figure 3. Serial Timing Diagram, Reading Data Using
CS = 0
DRDY
tDRDY
tREAD
t14
t10
1
23
24
SCLK
SDO
t11
t8
t9
t15
DATA
INVALID
DATA
INVALID
MSB
D22
D21
D20
D1
LSB
CS
Figure 4. Serial Timing Diagram, Reading Data Setting Logic Low
Rev. C | Page 6 of 24
AD7766
PART OUT OF POWER-DOWN
FILTER RESET
PART IN POWER-DOWN
A
BEGINS SAMPLING
MCLK (I)
B
C
D
t20
t18
SYNC/PD (I)
t21
t19
DRDY (O)
SDO (O)
tSETTLING
VALID DATA
INVALID DATA
VALID DATA
Figure 5. Reset, Synchronization, and Power-Down Timing (For More Information, See the Power-Down, Reset, and Synchronization Section)
Rev. C | Page 7 of 24
AD7766
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
AVDD to AGND
DVDD to DGND
AVDD to DVDD
VREF+ to REFGND
REFGND to AGND
VDRIVE to DGND
VIN+, VIN– to AGND
Digital Inputs to DGND
Digital Outputs to DGND
AGND to DGND
−0.3 V to +3 V
−0.3 V to +3 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +6 V
−0.3 V to VREF+ + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to +0.3 V
10 mA
ESD CAUTION
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
−40°C to +105°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
150.4°C/W
27.6°C/W
215°C
220°C
1 kV
ESD
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. C | Page 8 of 24
AD7766
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AV
CS
DD
SDI
V
REF+
AD7766/
AD766-1/
AD7766-2
TOP VIEW
(Not to Scale)
REFGND
MCLK
SCLK
DRDY
DGND
SDO
V
IN+
V
IN–
AGND
SYNC/PD
DV
V
DRIVE
DD
Figure 6. 16-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
AVDD
VREF+
+2.5 V Analog Power Supply.
Reference Input for the AD7766/AD7766-1/AD7766-2. An external reference must be applied to this input pin. The
VREF+ input can range from 2.4 V to 5 V. The reference voltage input is independent of the voltage magnitude
applied to the AVDD pin.
3
REFGND
Reference Ground. Ground connection for the reference voltage. The input reference voltage (VREF+) should be
decoupled to this pin.
4
5
6
7
VIN+
VIN−
AGND
SYNC/PD
Positive Input of the Differential Analog Input.
Negative Input of the Differential Analog Input.
Power Supply Ground for Analog Circuitry.
Synchronization and Power-Down Input Pin. This pin has dual functionality. It can be used to synchronize multiple
AD7766/AD7766-1/AD7766-2 devices and/or to put the AD7766/AD7766-1/AD7766-2 devices into power-down
mode. See the Power-Down, Reset, and Synchronization section for further details.
8
DVDD
VDRIVE
SDO
2.5 V Digital Power Supply Input. In cases where a logic voltage of 2.5 V for interfacing is used, (2.5 V applied to
VDRIVE pin), the DVDD and VDRIVE pins may be connected to the same voltage supply rail.
Logic Power Supply Input, 1.8 V to 3.6 V. The voltage supplied at this pin determines the operating voltage of the
digital logic interface.
Serial Data Output. The conversion result from the AD7766/AD7766-1/AD7766-2 is output on the SDO pin as a 24-bit,
twos complement, MSB first, serial data stream.
9
10
11
12
DGND
DRDY
Digital Logic Power Supply Ground.
Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data result is available in the
output register of the AD7766/AD7766-1/AD7766-2. See the AD7766/AD7766-1/AD77662-2 Interface section for
further details.
13
SCLK
Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the AD7766/AD7766-1/
AD7766-2 devices. See the AD7766/AD7766-1/AD77662-2 Interface section for further details.
14
15
MCLK
SDI
Master Clock Input. The sampling frequency of the AD7766/AD7766-1/AD7766-2 is equal to the MCLK frequency.
Serial Data Input. This is the daisy-chain input of the AD7766/AD7766-1/AD7766-2. See the Daisy Chaining section
for further details.
16
CS
Chip Select Input. The CS input selects a specific AD7766/AD7766-1/AD7766-2 device and acts as an enable on the
SDO pin. In cases where CS is used, the MSB of the conversion result is clocked onto the SDO line on the CS falling
edge. The CS input allows multiple AD7766/AD7766-1/AD7766-2 devices to share the same SDO line. This allows
the user to select the appropriate device by supplying it with a logic low CS signal, which enables the SDO pin of
the device concerned. See the AD7766/AD7766-1/AD77662-2 Interface section for further details.
Rev. C | Page 9 of 24
AD7766
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 2.5 V 5ꢀ, VDRIVE = 1.8 V to 3.6 V, VREF+ = 5 V, MCLK = 1 MHz, common-mode input = VREF+/2. TA = 25°C, unless
otherwise noted. All FFTs were generated using 8192 samples using a four-term Blackman-Harris window.
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
0
0
8k
16k
24k
32k
40k
48k
56k
64k
32k
16k
0
0
0
8k
16k
24k
32k
40k
48k
56k
64k
32k
16k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. AD7766 FFT, 1 kHz, −0.5 dB Input Tone
Figure 10. AD7766 FFT, 1 kHz, −6 dB Input Tone
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
4k
8k
12k
16k
20k
24k
28k
4k
8k
12k
16k
20k
24k
28k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. AD7766-1 FFT, 1 kHz, −0.5 dB Input Tone
Figure 11. AD7766-1 FFT, 1 kHz, −6 dB Input Tone
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
4k
8k
12k
4k
8k
12k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. AD7766-2 FFT, 1 kHz, −0.5 dB Input Tone
Figure 12. AD7766-2 FFT, 1 kHz, −6 dB Input Tone
Rev. C | Page 10 of 24
AD7766
0
–20
0
–20
TONE A = 49.7kHz
TONE B = 50.3kHz
SECOND-ORDER IMD = –133.71dB
THIRD-ORDER IMD = –109.05dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
0
0
8k
16k
24k
32k
40k
48k
56k
64k
32k
16k
0
8k
16k
24k
32k
40k
48k
56k
64k
32k
16k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. AD7766 FFT, 1 kHz, −60 dB Input Tone
Figure 16. AD7766 IMD FFT, 50 kHz Center Frequency
0
–20
0
–20
TONE A = 24.7kHz
TONE B = 25.3kHz
SECOND-ORDER IMD = –133.33dB
THIRD-ORDER IMD = –108.15dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
4k
8k
12k
16k
20k
24k
28k
0
4k
8k
12k
16k
20k
24k
28k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. AD7766-1 FFT, 1 kHz, −60 dB Input Tone
Figure 17. AD7766-1 IMD FFT, 25 kHz Center Frequency
0
–20
0
–20
TONE A = 11.7kHz
TONE B = 12.3kHz
SECOND-ORDER IMD = –137.96dB
THIRD-ORDER IMD = –108.1dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
4k
8k
12k
0
4k
8k
12k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. AD7766-2 FFT, 1 kHz, −60 dB Input Tone
Figure 18. AD7766-2 IMD FFT, 12 kHz Center Frequency
Rev. C | Page 11 of 24
AD7766
120
115
110
105
100
95
–104
–108
–112
–116
DYNAMIC RANGE
AD7766-2
AD7766-1
OPEN INPUTS
AD7766
–120
0
FULL-SCALE 921Hz
90
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
MCLK FREQUENCY (Hz)
0
10k
20k
30k
40k
50k
60k
fNOISE (Hz)
Figure 19. AD7766/AD7766-1/AD7766-2 THD vs. MCLK Frequency
Figure 22. AD7766 CMRR vs. Common-Mode Ripple Frequency (fNOISE
)
115
200
MAX = 8,388,637
MIN = 8,388,493
SPREAD = 145
180
160
140
120
100
80
114
AD7766-2
113
112
111
AD7766-1
110
60
109
AD7766
40
108
107
20
0
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
MCLK FREQUENCY (Hz)
CODES
Figure 20. AD7766/AD7766-1/AD7766-2 SNR vs. MCLK Frequency
Figure 23. AD7766 24-Bit Histogram
150
250
200
150
100
50
AV
DD
DV
MAX = 8,388,608
DD
MIN = 8,388,507
SPREAD = 102 CODES
140
130
120
110
100
V
DRIVE
0
0
10k
20k
30k
fNOISE (Hz)
40k
50k
60k
CODES
Figure 21. AD7766 Power Supply Sensitivity vs. Supply Ripple Frequency
(fNOISE) with Decoupling Capacitors
Figure 24. AD7766-1 24-Bit Histogram
Rev. C | Page 12 of 24
AD7766
15
12
9
MAX = 8,388,593
MIN = 8,388,526
SPREAD = 69 CODES
350
300
250
200
150
100
50
6
3
0
–3
–6
–9
–12
–15
0
0
4,194,304
2,097,152 6,291,456
24-BIT CODES
8,388,608
12,582,912
16,777,216
10,485,760
14,680,064
CODES
Figure 27. AD7766/AD7766-1/AD7766-2 24-Bit INL
Figure 25. AD7766-2 24-Bit Histogram
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4,194,304
2,097,152 6,291,456
24-BIT CODES
8,388,608
12,582,912
16,777,216
10,485,760
14,680,064
Figure 26. AD7766/AD7766-1/AD7766-2 24-Bit DNL
Rev. C | Page 13 of 24
AD7766
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in decibels.
SNR is the ratio of the actual input signal’s rms value to the rms
sum of all other spectral components below the Nyquist frequency,
excluding harmonics and dc. The value for SNR is expressed in
decibels.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
Total Harmonic Distortion (THD)
through the endpoints of the ADC transfer function.
THD is the ratio of the rms sum of harmonics to the fundamen-
tal. For the AD7766, it is defined as
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
V22 + V32 + V42 + V52 + V62
THD
where:
dB = 20 log
( )
Zero Error
V1
Zero error is the difference between the ideal midscale input
voltage (when both inputs are shorted together) and the actual
voltage producing the midscale output code.
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second to
the sixth harmonics.
Zero Error Drift
Zero error drift is the change in the actual zero error value due
to a temperature change of 1°C. It is expressed as a percentage
of full scale at room temperature.
Nonharmonic Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the rms signal amplitude to the rms value
of the peak spurious spectral component, excluding harmonics.
Gain Error
Dynamic Range
The first transition (from 100 … 000 to 100 … 001) should occur
½ LSB above the nominal negative full scale for an analog voltage.
The last transition (from 011 … 110 to 011 … 111) should occur
1½ LSB below the nominal full scale for an analog voltage. The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first transition,
from the difference between the ideal levels.
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for the dynamic range is expressed in decibels.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n is equal to 0. For example,
the second-order terms include (fa + fb) and (fa − fb), and the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
Gain Error Drift
Gain error drift is the change in the actual gain error value due
to a temperature change of 1°C. It is expressed as a percentage
of full scale at room temperature.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency f to the power of a 100 mV sine wave
applied to the common-mode voltage of the VIN+ and VIN−
inputs at frequency fS.
The AD7766 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, and the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
CMRR (dB) = 10 log(Pf/PfS)
where Pf is the power at the frequency f in the ADC output, and
PfS is the power at the frequency fS in the ADC output.
Rev. C | Page 14 of 24
AD7766
THEORY OF OPERATION
The AD7766/AD7766-1/AD7766-2 operate using a fully
differential analog input applied to a successive approximation
(SAR) core. The output of the oversampled SAR is filtered using
a linear-phase digital FIR filter. The fully filtered data is output
in a serial format, with the MSB being clocked out first.
The digital filtering that follows the converter output acts to
remove the out-of-band quantization noise (see Figure 30). This
also has the effect of reducing the data rate from fMCLK at the
input of the filter to fMCLK/8, fMCLK/16, or fMCLK/32 at the digital
output, depending on which model of the device is being used.
The digital filter consists of three separate filter blocks. Figure 31
shows the three constituent blocks of the filter. The order of
decimation of the first filter block is set as 2, 4, or 8. The
remaining sections each operate with a decimation of 2.
AD7766/AD7766-1/AD7766-2 TRANSFER
FUNCTION
The conversion results of the AD7766/AD7766-1/AD7766-2
are output in a twos complement, 24-bit serial format. The fully
differential inputs VIN+ and VIN− are scaled by the AD7766/
AD7766-1/AD7766-2 relative to the reference voltage input
(VREF+) as shown in Figure 28.
DIGITAL FILTER
STAGE 1
STAGE 2
STAGE 3
DATA
STREAM
SINC FILTER
FIR FILTER
FIR FILTER
SDO
24 BITS
TWOS
COMPLEMENT
DEC × (2 × n)
DEC × 2
DEC × 2
011 ... 111
011 ... 110
Figure 31. FIR Filter Stages
(n = 1 for AD7766, n = 2 for AD7766-1, n = 4 for AD7766-2)
000 ... 010
000 ... 001
Table 6 shows the three available models of the AD7766, listing
the change in output data rate relative to the order of decimation
rate implemented. This brings into focus the trade-off that exists
between extra filtering and reduction in bandwidth, whereby
using a filter option with a larger decimation rate increases the
noise performance while decreasing the usable input bandwidth.
000 ... 000
111 ... 111
111 ... 110
100 ... 001
100 ... 000
Table 6. AD7766 Models
Model
Decimation Rate
Output Data Rate (ODR)
V
= 0V
V
V
V
IN+
= V – 1LSB
REF+
IN+
REF+
2
REF+
V
V
=
=
AD7766
AD7766-1
AD7766-2
8
16
32
128 kHz
64 kHz
32 kHz
IN+
V
= V
REF+
– 1LSB
V
= 0V
IN–
IN–
IN–
2
Figure 28. AD7766/AD7766-1/AD7766-2 Transfer Function
CONVERTER OPERATION
Note that the output data rates shown in Table 6 are realized
when using the maximum MCLK input frequency of 1.024 MHz.
The output data rate scales linearly with the MCLK frequency,
as does the digital power dissipated in the device.
Internally, the input waveform applied to the SAR core is
converted and an equivalent digital word is output to the digital
filter at a rate equal to MCLK. By employing oversampling, the
quantization noise of the converter is spread across a wide
bandwidth from 0 to fMCLK. This means that the noise energy
contained in the signal band of interest is reduced (see
Figure 29).
The settling time of the filter implemented on the AD7766,
AD7766-1, and AD7766-2 is related to the length of the filter
employed. The response of the filter in the time domain sets the
filter settling time. Table 7 shows the filter settling times of the
AD7766/AD7766-1/AD7766-2.
The frequency responses of the digital filters on the AD7766,
AD7766-1, and AD7766-2 are shown in Figure 32, Figure 33,
and Figure 34, respectively. At the Nyquist frequency (output
data rate/2), the digital filter provides 6 dB of attenuation. In each
case, the filter provides stop-band attenuation of 100 dB and
pass-band ripple of 0.005 dB.
QUANTIZATION NOISE
fMCLK/2
BAND OF INTEREST
Figure 29. Quantization Noise
DIGITAL FILTER CUTOFF FREQUENCY
fMCLK/2
BAND OF INTEREST
Figure 30. Digital Filter Cutoff Frequency
Rev. C | Page 15 of 24
AD7766
0
ANALOG INPUT STRUCTURE
–20
The AD7766/AD7766-1/AD7766-2 are configured as a differential
input structure. A true differential signal is sampled between the
analog inputs VIN+ and VIN−, Pin 4 and Pin 5, respectively. Using
differential inputs provides rejection of signals that are common
to both the VIN+ and VIN− pins.
–40
–60
–80
Figure 35 shows the equivalent analog input circuit of the
AD7766/AD7766-1/AD7766-2. The two diodes on each of the
differential inputs provide ESD protection for the analog inputs.
–100
–120
–140
V
REF+
D
D
–160
0
C2
R
IN
16k
32k
48k
64k
80k
96k
112k
128k
V
IN+
FREQUENCY (Hz)
C1
Figure 32. AD7766 Digital Filter Frequency Response
GND
AGND
V
REF+
0
–20
D
C2
R
IN
V
IN–
C1
D
–40
GND
AGND
–60
Figure 35. Equivalent Analog Input Structure
–80
Take care to ensure that the analog input signal does not exceed
the reference supply voltage (VREF+) by more than 0.3 V, as specified
in the Absolute Maximum Ratings section. If the input voltage
exceeds this limit, the diodes become forward biased and start
to conduct current. The diodes can handle 130 mA maximum.
–100
–120
–140
–160
The impedance of the analog inputs can be modeled as a parallel
combination of C1 and the network formed by the series con-
nection of RIN, C1, and C2. The value of C1 is dominated by the
pin capacitance. RIN is typically 1.4 kΩ, the lumped component
of serial resistors and the RON of the switches. C2 is typically
22 pF, and its value is dominated by the sampling capacitor.
0
8k
16k
24k
32k
40k
48k
56k
64k
FREQUENCY (Hz)
Figure 33. AD7766-1 Digital Filter Frequency Response
0
–20
SUPPLY AND REFERENCE VOLTAGES
The AD7766/AD7766-1/AD7766-2 operate from a 2.5 V supply
applied to the DVDD and AVDD pins. The interface is specified to
operate between 1.7 V and 3.6 V. The AD7766/AD7766-1/
AD7766-2 operate from a reference input in the range of 2.2 V
to 2 × AVDD applied to the VREF+ pin. The nominal reference
supply voltage is 5 V, but a 2.5 V supply can also be used. When
using a 5 V reference, the recommended reference devices are
the ADR445, ADR435, or ADR425; when using 2.5 V, the ADR441,
ADR431, or ADR421 are recommended. The voltage applied to
the reference input (VREF+) operates both as a reference supply
and as a power supply to the AD7766/AD7766-1/AD7766-2
devices. Therefore, when using a 5 V reference input, the full-scale
differential input range of the AD7766/AD7766-1/AD7766-2 is
10 V. See the Driving the AD7766/AD7766-1/AD7766-2 section
for details on the maximum input voltage.
–40
–60
–80
–100
–120
–140
–160
0
4k
8k
12k
16k
20k
24k
28k
32k
FREQUENCY (Hz)
Figure 34. AD7766-2 Digital Filter Frequency Response
Rev. C | Page 16 of 24
AD7766
AD7766/AD7766-1/AD77662-2 INTERFACE
The AD7766/AD7766-1/AD7766-2 provide the user with a
flexible serial interface, enabling the user to implement the
most desirable interfacing scheme for their application. Each
AD7766/AD7766-1/AD7766-2 interface comprises seven
The AD7766/AD7766-1/AD7766-2 offer the option of using a
CS
CS
chip select input signal ( ) in a data read cycle. The
signal is
a gate for the SDO pin and allows many AD7766/AD7766-1/
AD7766-2 devices to share the same serial bus. It acts as an
instruction signal to each of these devices indicating permission
CS
different signals. Five of these signals are inputs: MCLK,
SYNC PD
,
CS
/
, SCLK, and SDI. The other two signals are outputs:
and SDO.
to use the bus. When
is logic high, the SDO line of the
DRDY
AD7766/AD7766-1/AD7766-2 is tristated.
There are two distinct patterns that can be initiated to read data
from the AD7766/AD7766-1/AD7766-2 devices: a pattern for
INITIAL POWER-UP
On initial power-up, apply a continuous MCLK signal. It is recom-
mended that the user reset the AD7766/AD7766-1/AD7766-2
to clear the filters and ensure correct operation. The reset is
completed as shown in Figure 5, with all events occurring relative
CS
when the
falling edge occurs after the
falling edge
DRDY
CS
CS
and a pattern for when the
falling edge occurs before the
is set to logic low).
falling edge (when
DRDY
to the rising edge of MCLK. A negative pulse on the
/
SYNC PD
CS
When the
falling edge occurs after the
falling edge,
DRDY
input initiates the reset, and the
output switches to logic
DRDY
the MSB of the conversion result is available on the SDO line on
CS
high and remains high until valid data is available. Following the
power-up of the AD7766/AD7766-1/AD7766-2 by transitioning
the
falling edge. The remaining bits of the conversion result
(MSB − 1, MSB − 2, and so on) are clocked onto the SDO line
by the falling edges of SCLK that follow the
Figure 3 details this interfacing scheme.
SYNC PD
the
/
pin to logic high, a settling time is required before
CS
falling edge.
valid data is output by the device. This settling time, tSETTLING
,
is a function of the MCLK frequency and the decimation rate.
Table 7 lists the settling time of each AD7766 model and should
be referenced when reviewing Figure 5.
CS
When
is tied low, the AD7766/AD7766-1/AD7766-2 serial
interfaces can operate in 3-wire mode as shown in Figure 4. In
this case, the MSB of the conversion result is available on the
SDO line on the falling edge of
the data conversion result (MSB − 1, MSB − 2, and so on) are
clocked onto the SDO line by the subsequent SCLK falling edges.
SYNC PD
Table 7. Filter Settling Time After
/
DRDY
. The remaining bits of
1
Model
Decimation Rate
tSETTLING
AD7766
AD7766-1
AD7766-2
8
16
32
(594 × tMCLK) + t21
(1186 × tMCLK) + t21
(2370 × tMCLK) + t21
POWER-DOWN, RESET, AND SYNCHRONIZATION
SYNC PD
pin allows the user to synchronize multiple
The
/
1 tSETTLING is measured from the first MCLK rising edge after the rising edge of
/
SYNC PD
AD7766/AD7766-1/AD7766-2 devices. This pin also allows the
user to reset and power down the AD7766/AD7766-1/AD7766-2
devices. These features are implemented relative to the rising edges
of MCLK and are shown in Figure 5, marked as A, B, C, and D.
to the falling edge of
.
DRDY
READING DATA
The AD7766/AD7766-1/AD7766-2 output data conversion
results in an MSB-first, twos complement, 24-bit format on the
serial data output (SDO) pin. MCLK is the master clock, which
controls all the AD7766/AD7766-1/AD7766-2 conversions. The
SCLK is the serial clock input for the device. All data transfers
take place with respect to the SCLK signal.
To power down, reset, or synchronize a device, the
/
SYNC PD
pin should be taken low. On the first rising edge of MCLK, the
AD7766/AD7766-1/AD7766-2 are powered down. The
DRDY
pin transitions to logic high, indicating that the data in the
output register is no longer valid. The status of the
/
SYNC PD
pin is checked on each subsequent rising edge of MCLK. On the
first rising edge of MCLK after the pin is taken high,
The
line is used as a status signal to indicate when the data
DRDY
is available to be read from the AD7766/AD7766-1/AD7766-2.
The falling edge of indicates that a new data-word is
/
SYNC PD
the AD7766/AD7766-1/AD7766-2 are taken out of power-down.
On the next rising edge, the filter of the AD7766/AD7766-1/
AD7766-2 is reset. On the following rising edge, the first new
sample is taken.
DRDY
available in the output register of the device.
stays low
DRDY
during the period that output data is permitted to be read from
the SDO pin. The signal returns to logic high to indicate
DRDY
A settling time, tSETTLING, from the filter reset must elapse before
valid data is output by the device (see Table 7). The
output goes logic low after tSETTLING to indicate when valid data is
available on SDO for readback.
when not to read from the device. Ensure that a data read is not
attempted during this period while the output register is being
updated.
DRDY
Rev. C | Page 17 of 24
AD7766
DAISY CHAINING
Daisy chaining devices allows numerous devices to use the same
digital interface lines by cascading the outputs of multiple ADCs
on a single data line. This feature is especially useful for reduc-
ing component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register where data is clocked on the falling edge of SCLK.
the devices labeled A, B, C, and D are clocked onto SDO (A)
DRDY
during the time between the falling edge of
DRDY
(A) and the
rising edge of
(A).
CHOOSING THE SCLK FREQUENCY
As shown in Figure 37, the number of SCLK falling edges that
DRDY
occurs during the period when
(A) is active low must
match the number of devices in the chain multiplied by 24 (the
number of bits that must be clocked through onto SDO (A) for
each device).
The block diagram in Figure 36 shows how devices must be
connected to achieve daisy-chain functionality. The scheme
shown operates by passing the output data of the SDO pin of an
AD7766 device to the SDI input of the next AD7766 device in
the chain. The data then continues through the chain until it is
clocked onto the SDO pin of the first device in the chain.
The period of SCLK (tSCLK) required for a known daisy-chain length
using a known common MCLK frequency must, therefore, be
established in advance. Note that the maximum SCLK frequency
is governed by t8 and is specified in Table 3 for different VDRIVE
voltages.
READING DATA IN DAISY-CHAIN MODE
An example of a daisy chain of four AD7766 devices is shown in
Figure 36 and Figure 37. In the case illustrated in Figure 36, the
output of the AD7766 labeled A is the output of the full daisy
chain. The last device in the chain (the AD7766 labeled D) has
its serial data input (SDI) pin connected to ground. All the
CS
In the case where
is tied logic low,
tREAD
⎡
⎤
tSCLK
≤
(1)
⎢
⎣
⎥
24 × K
⎦
where:
CS
devices in the chain must use common MCLK, SCLK, , and
K is the number of AD7766/AD7766-1/AD7766-2 devices in
the chain.
tSCLK is the period of the SCLK.
tREAD equals tDRDY − t5.
SYNC PD
/
signals.
To enable the daisy-chain conversion process, apply a common
SYNC PD
/
pulse to all devices, synchronizing all the devices in
the chain (see the Power-Down, Reset, and Synchronization
section).
CS
In the case where
is used in the daisy-chain interface,
t
)
−
t6 + t7 + t13
⎡
⎤
READ
SYNC PD
pulse to all the devices, there is a
After applying a
/
tSCLK
≤
(2)
⎢
⎣
⎥
⎦
24 × K
delay (as listed in Table 7) before valid conversion data appears
at the output of the chain of devices. As shown in Figure 37, the
first conversion result is output from the AD7766 device labeled
A. This 24-bit conversion result is followed by the conversion
results from the devices labeled B, C, and D, with all conversion
results output in an MSB-first sequence. The stream of conversion
results is clocked through each device in the chain and is eventually
clocked onto the SDO pin of the AD7766 device labeled A. The
conversion results of all the devices in the chain must be clocked
where:
K is the number of AD7766/AD7766-1/AD7766-2 devices in
the chain.
tSCLK is the period of the SCLK.
tREAD equals tDRDY − t5.
Note that the maximum value of SCLK is governed by t8 and is
specified in Table 3 for different VDRIVE voltages.
DRDY
onto the SDO pin of the final device in the chain while its
signal is active low. This is illustrated in the examples shown
(Figure 37 and Figure 38), where the conversion results from
Rev. C | Page 18 of 24
AD7766
DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS
SYNC/PD
CS
SYNC/PD
SYNC/PD
SYNC/PD
SYNC/PD
CS DRDY
CS
CS
CS
AD7766
(D)
AD7766
(C)
AD7766
(B)
AD7766
(A)
SDO
SDI
SDI
SDO
SDI
SDO
SDI
SDO
SDI
SCLK
SCLK
SCLK
SCLK
MCLK
MCLK
MCLK
MCLK
SCLK
MCLK
Figure 36. Daisy-Chain Configuration with Four AD7766 Devices
1
8 × n
MCLK
DRDY (A)
CS
24 × tSCLK
24 × tSCLK
24 × tSCLK
24 × tSCLK
SCLK
AD7766 (A)
AD7766 (B)
AD7766 (C)
AD7766 (D)
AD7766 (B)
AD7766 (C)
AD7766 (D)
AD7766 (C)
AD7766 (D)
AD7766 (D)
AD7766 (A)
AD7766 (B)
AD7766 (C)
AD7766 (D)
SDO (A)
SDI (A) = SDO (B)
SDI (B) = SDO (C)
SDI (C) = SDO (D)
Figure 37. Daisy-Chain Timing Diagram (n = 1 for AD7766, n = 2 for AD7766-1, n = 4 for AD7766-2) When Driving the AD7766
1
MCLK
DRDY (A)
CS
SDO (A)
SCLK
MSB (A)
LSB (A) MSB (B)
LSB (B) MSB (C)
LSB (C)
t16
t17
MSB (B)
LSB (B) MSB (C)
LSB (C) MSB (D)
LSB (D)
SDI (A) = SDO (B)
Figure 38. Daisy-Chain SDI Setup and Hold Timing
Rev. C | Page 19 of 24
AD7766
DRIVING THE AD7766/AD7766-1/AD7766-2
The AD7766/AD7766-1/AD7766-2 must be driven with fully
differential inputs. The common-mode voltage of the differential
inputs to the AD7766/AD7766-1/AD7766-2 devices, and therefore
the limits on the differential inputs, is set by the reference voltage
(VREF+) applied to the device. The common-mode voltage of the
AD7766/AD7766-1/AD7766-2 is VREF+/2. When the AD7766/
AD7766-1/AD7766-2 VREF+ pin has a 5 V supply (using ADR445,
ADR435, or ADR425), the common mode is at 2.5 V, meaning
that the maximum inputs that can be applied on the AD7766/
AD7766-1/AD7766-2 differential inputs are a 5 V p-p input
around 2.5 V.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF+). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. The ratio of R2 to R1 should be equal to the
ratio of REF to the peak-to-peak input voltage. For example, for
the 10 V range with a 4 kꢁ impedance, R2 = 1 kꢁ and R1 = 4 kꢁ.
R3 and R4 set the common mode on the VIN− input, and R5 and R6
set the common mode on the VIN+ input of the ADC. The common
mode, which is equal to the voltage present at VOFFSET1, should be
close to VREF+/2. The voltage present should roughly be set to the
ratio of VOFFSET1 to 1 + R2/R1.
V
REF
1kΩ
3.3nF
V
V
REF
2
IN+
ADP3330-2.5
2.5V
1kΩ
AIN+
15Ω
ADA4841-1
0V
2.2nF
1
V
1kΩ
AV
DD
4
REF
V
IN+
AD7766
3.3nF
V
IN–
V
5
V
IN–
REF+
V
REF
2
1kΩ
2
AIN–
2.2nF
15Ω
*
ADA4841-1
2.5V TO 5V
ADR4xx
1kΩ
1kΩ
REFERENCE
VOLTAGE
0V
Figure 39. Maximum Differential Inputs to the AD7766
An analog voltage of 2.5 V supplies the AD7766/AD7766-1/
AD7766-2 AVDD pin. However, the AD7766/AD7766-1/AD7766-2
allow the user to apply a reference voltage of up to 5 V. This
provides the user with an increased full-scale range, offering the
user the option of using the AD7766/AD7766-1/AD7766-2 with
a greater LSB voltage. Figure 39 shows the maximum inputs to
the AD7766.
*SEE V
INPUT SIGNAL SECTION FOR DETAILS.
REF+
Figure 40. Driving the AD7766 from a Fully Differential Source
V
IN
VOUT = 5V REF
0.1µF
ADR445
ADR425
0.1µF
ADP3330-2.5
V
OFFSET1 R6
R5
R3
2.5V
LDO
V
OFFSET2
R4
100µF
5.2V
DIFFERENTIAL SIGNAL SOURCE
100nF
100nF
REF
15Ω
15Ω
OUTN
OUTP
V
An example of recommended driving circuitry that can be used
in conjunction with the AD7766 is shown in Figure 40. Figure 40
shows how the ADA4841-1 device can be used to drive an input
to the AD7766 from a differential source. Each of the differential
paths is driven by an ADA4841-1 device.
REF+
AV
DD
V
V
IN+
2.2nF
2.2nF
AD7766
IN–
IN
AGND DGND
FB
ADA4941-1
–0.2V
R2
R1
SINGLE-ENDED SIGNAL SOURCE
V
IN
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-to-differential
driver creates a fully differential input to the AD7766. The
schematic is shown in Figure 41.
C
F
Figure 41. Driving the AD7766 from a Single-Ended Source
Table 8. Resistor Values Required When Using the Differential-to-Single-Ended Circuit with ADA4941 (See Figure 41)
VIN (V)
VOFFSET1 (V)
VOFFSET2 (V)
OUT+ (V)
−0.01, +4.96
0.01, 4.99
0.00, 5.00
OUT− (V)
5.01, 0.04
4.99, 0.01
5.00, 0.00
R1 (kΩ)
8.06
4.02
2
R2 (kΩ)
R4 (kΩ)
12.7
15
R3 = R5 = R6 (kΩ)
+20, −20
+10, −10
+5, −5
2.5
2.5
2.5
2.203
2.000
1.667
1
1
1
10
10
10
20
Rev. C | Page 20 of 24
AD7766
frequency applied divided by the decimation rate employed by
the device in use. For instance, operating the AD7766 device with
an MCLK of 800 kHz results in an output data rate of 100 kHz
due to the decimate-by-8 filtering.
ANTIALIASING
The AD7766/AD7766-1/AD7766-2 sample the analog input
at a maximum rate of 1.024 MHz. The on-board digital filter
provides up to 100 dB attenuation for any possible aliasing
frequency in the range from the beginning of the filter stop
band (0.547 × ODR) to where the image of the digital filter pass
band occurs. This occurs at fMCLK minus the filter stop band
(fMCLK − 0.547 × ODR), as shown in Figure 42.
4.5
4.0
3.5
DI
DD
3.0
2.5
2.0
1.5
fMCLK
DIGITAL FILTER
IMAGE AT fMCLK
DIGITAL FILTER 100dB
ANTIALIAS PROTECTION
AI
I
DD
1.0
0.5
0
fMCLK – (0.547 × ODR)
FIRST IMAGE POINT
REF
BAND OF INTEREST
Figure 42. AD7766/AD7766-1/AD7766 Spectrum
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k
FREQUENCY (Hz)
Table 9 shows the attenuation achieved by various orders of
front-end antialias filters prior to the signal entering the AD7766/
AD7766-1/AD7766-2 at the image of the digital filter stop band,
which is 1.024 MHz − 0.547 × ODR.
Figure 43. AD7766 Current vs. MCLK Frequency
2.5
2.0
1.5
1.0
0.5
0
Table 9. Antialias Filter Order
DI
DD
Attenuation at
1.024 MHz – 0.547 × ODR
Model
Filter Order
First
AD7766
27 dB
50 dB
70 dB
33 dB
62 dB
89 dB
38 dB
74 dB
110 dB
Second
Third
AI
DD
AD7766-1
AD7766-2
First
Second
Third
I
REF
First
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k
FREQUENCY (Hz)
Second
Third
Figure 44. AD7766-1 Current vs. MCLK Frequency
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
The AD7764 and AD7765 ∑-Δ devices are available to
DI
DD
customers that require extra antialias protection. These devices
sample the signal internally at a rate of 20 MHz to achieve up to
a maximum of 156 kHz or 312 kHz output data rate. This
means that the first alias point of these devices when run at the
maximum speeds is 19.921 MHz and 19.843 MHz, respectively.
AI
DD
POWER DISSIPATION
The AD7766/AD7766-1/AD7766-2 offer exceptional perform-
ance at ultralow power. Figure 43, Figure 44, and Figure 45
show how the current consumption of the AD7766, AD7766-1,
and AD7766-2 scales with the MCLK frequency applied to the
device. Both the digital and analog currents scale as the MCLK
frequency is reduced. The actual throughput equals the MCLK
I
REF
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k
FREQUENCY (Hz)
Figure 45. AD7766-2 Current vs. MCLK Frequency
Rev. C | Page 21 of 24
AD7766
VREF+ INPUT SIGNAL
MULTIPLEXING ANALOG INPUT CHANNELS
The AD7766/AD7766-1/AD7766-2 VREF + pin is supplied with a
voltage in the range of 2.4 V to 2 × AVDD (nominally 5 V). It is
recommended that the VREF+ input be generated by a low noise
voltage reference. Examples of such references are the ADR445,
ADR435, ADR425 (5 V output), and ADR421 (2.5 V output).
Typical reference supply circuits are shown in Figure 46.
The AD7766/AD7766-1/AD7766-2 can be used with a multi-
plexer configuration. As per any converter that uses a digital
filtering block, the maximum switching rate or the output data
rate per channel is a function of the digital filter settling time.
A user multiplexing the analog inputs to a converter that
employs a digital filter must wait the full digital filter settling
time before a valid conversion result can be achieved; after this
settling time, the channel can be switched. Then, the full
settling time must again be observed before a valid conversion
result is available and the input is switched once more.
The reference voltage input pin (VREF+) also acts as a power
supply to the AD7766/AD7766-1/AD7766-2 devices. For a 5 V
VREF+ input, a full-scale input of 5 V on both VIN+ and VIN− can
be applied while voltage supplies to pins AVDD remain at 2.5 V.
This configuration reduces the number of different supplies
required.
The AD7766 filter settling time equals 74 divided by the output
data rate in use. The maximum switching frequency in a multi-
plexed application is, therefore, 1/(74/ODR), where the output
data rate (ODR) is a function of the applied MCLK frequency
and the decimation rate employed by the device in question. For
example, applying a 1.024 MHz MCLK frequency to the AD7766
results in a maximum output data rate of 128 kHz, which in
turn allows a 1.729 kHz multiplexer switching rate.
The output of the low noise voltage reference does not require a
buffer; however, decoupling the output of the low noise reference is
important. Place a 0.1 μF capacitor at the output of the voltage
reference devices (ADR445, ADR435, ADR425, and ADR421)
and follow the decoupling advice provided for the reference
device chosen.
As mentioned, the nominal supply to the VREF+ pin is 5 V to
achieve the full dynamic range available. When a 2.5 V VREF+
input is used (that is, in low power applications), the signal-to-
noise ratio and dynamic range figures (generated using a 5 V
VREF+ input) quoted in the Specifications section decrease by
6 dB, a direct result of halving the available input range.
The AD7766-1 and the AD7766-2 employ digital filters with
longer settling time to achieve greater precision; thus, the
maximum switching frequency for these devices is 864 Hz and
432 Hz, respectively.
The AD7766/AD7766-1/AD7766-2 devices require a 100 μF
capacitor to ground, which acts as a decoupling capacitor and as
a reservoir of charge for the VREF+ pin. Place this capacitor as
close to the AD7766/AD7766-1/AD7766-2 devices as possible.
Reducing the value of this capacitor (C40 in Figure 46) to 10 μF
typically degrades noise performance by 1 dB. C40 can be an
electrolytic or tantalum capacitor.
REFERENCE
SUPPLY
V+
V
V
V
REF+
IN
OUT
C34
10µF
C35
0.1µF
C39
0.1µF
C40
100µF
ADR4xx
AD7766/
AD7766-1/
AD7766-2
Figure 46. AD7766/AD7766-1/AD7766-2 Reference Input Configuration
Rev. C | Page 22 of 24
AD7766
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
AD7766BRUZ
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
Evaluation Board
Evaluation Board
Converter Evaluation and Development Board
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
AD7766BRUZ-RL7
AD7766BRUZ-1
AD7766BRUZ-1-RL7
AD7766BRUZ-2
AD7766BRUZ-2-RL7
EVAL-AD7766EDZ
EVAL-AD7766-1EDZ
EVAL-AD7766-2EDZ
EVAL-CED1Z
1 Z = RoHS Compliant Part.
Rev. C | Page 23 of 24
AD7766
NOTES
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06449-0-4/10(C)
Rev. C | Page 24 of 24
相关型号：
AD7766BRUZ-1
1-CH 24-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16
ROCHESTER
AD7766BRUZ-RL7
1-CH 24-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16
ROCHESTER
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