AD7766_技术文档

24-Bit, 10mW, 125ksps Analog to Digital

Converter in 16 lead TSSOP

AD7766

Preliminary Technical Data

FEATURES

PRODUCT OVERVIEW

High performance 24-bit ADC

114dB SNR at 31.25 KHz output data rate

111dB SNR at 62.5 KHz output data rate

108dB SNR at 125 KHz output data rate

Max 20mW Power Consumption

10mW typ at 31.25 KHz output data rate

12mW typ at 62.5 KHz output data rate

15 mW typ at 125 KHz output data rate

High DC accuracy

24 Bits No Missing Codes (NMC)

Integral Non Linearity 15 ppm

Low temperature drift

Offset Drift 25 nV/°C

On Chip Low pass FIR filter

Linear Phase Response

Passband Ripple: 0.005dB

Stopband Attenuation: 100dB

2.5V Supply with 1.8V/2.5V/3V/3.6V logic interface

Flexible Interfacing options

Synchronization of multiple devices

Daisy Chain capability

Temp Range -40^oC to 105^oC

The AD7766 is high performance 24-bit over-sampled analog to

digital converter combining wide dynamic range and input

bandwidth with an on chip FIR filter while consuming only

20mW max power in a 16 pin TSSOP package.

Specifically designed for ultra low power data acquisition,

providing 24-bit resolution and high SNR makes the device

ideal for measuring small signal changes over a wide dynamic

range. This is particularly important in many data acquisition

applications where small changes are measured on larger AC or

DC signals. In addition the AD7766 provides excellent DC

accuracy and drift specifications making the device suitable

where DC data also needs to be acquired. The AD7766

improves SNR performance and simplifies anti aliasing

requirements through over-sampling which is important in

minimizing input signal distortion to the inputs of the ADC. A

high performance on-chip FIR filter subsequently filters the

over-sampled data and removes out of band noise. A

/

SYNC PD

(Synchronisation/Power down) pin is an added feature,

allowing for easy synchronization of multiple devices. The

device operates from -40^oC to 105^oC.

By combining wide dynamic range and high SNR at output data

rates up to 125ksps with ultra low power the AD7766 provides a

compact solution for low power data acquisition such as PCI or

USB based systems.

APPLICATIONS

Low-Power PCI/USB Data Acquisition Systems

Low-Power Wireless Acquisition Systems

Vibration Analysis

RELATED DEVICES

Table 1. 24 bit Analog to Digital Converters

Instrumentation

Part No

Speed

2.5MSPs 100dB Dynamic Range¹

On-board Diff Amp & Ref Buffer

Description

FUNCTIONAL BLOCK DIAGRAM

AD7760

AV

DD

DV

DD

V

DRIVE

AGND

MCLK

DGND

Parallel, Variable Decimation

625KSPs 109dB Dynamic Range¹

On-Board Diff Amp & Ref buffer

Parallel/Serial, Variable Decimation

312KSps 109dB Dynamic Range¹

On-board Diff Amp & Ref Buffer

Serial, Variable Decimation (pin)

156KSPs 112dB Dynamic Range¹

On-board Diff Amp & Ref Buffer

Serial,Variable Decimation (pin)

125KSPs 109dB Dynamic Range¹

10mW power dissipation

AD7762/3

AD7764

AD7765

AD7767

V

REF+

DIGITAL

FIR FILTER

V

IN

+

-

CONVERTER

V

IN

REFGND

SYNC/PD

CS

SERIAL INTERFACE

&

CONTROL LOGIC

AD7766/

AD7766-1/

AD7766-2

SCLK DRDY SDO SDI

Figure 1.

Serial interface

¹Dynamic Range at max output data rate.

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7766

Preliminary Technical Data

TABLE OF CONTENTS

PRODUCT OVERVIEW............................................................. 1

Initial Power-Up ......................................................................... 13

Reading Data............................................................................... 13

Power Down, Reset & Synchronization .................................. 13

Daisy Chaining ............................................................................... 14

Reading Data in Daisy chain Mode ......................................... 14

Choosing the SCLK frequency ................................................. 14

Daisy Chain Mode Configuration & Timing Diagrams ....... 15

Driving the AD7766....................................................................... 16

Differential Signal Source ......................................................... 16

Single-Ended signal source....................................................... 16

Digital Filtering............................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide............................................................................... 18

Revision History ............................................................................... 2

AD7766/AD7766-1/AD7766-2—Specifications .......................... 3

Timimg Diagrams............................................................................. 5

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

AD7766 Transfer Function ....................................................... 12

AD7766 Interface............................................................................ 13

REVISION HISTORY

Rev. PrD | Page 2 of 18

Preliminary Technical Data

AD7766

AD7766/AD7766-1/AD7766-2—SPECIFICATIONS

Table 2. AV_DD= DV_DD= 2.5 V 5%, V_DRIVE= 1.8 V to 3.6 V, V_REF= 5 V, MCLK = 1MHz, T_A= -40°C to +105°C, unless otherwise

noted

Parameter

Test Conditions/Comments

Specifcation

Unit

OUTPUT DATA RATE

AD7766

AD7766-1

Decimate × 8

Decimate × 16

Decimate × 32

125

62.5

31.25

KHz max

AD7766-2

ANALOG INPUT¹

Differential Input Voltage

Absolute Input Voltage

Vin(+) – Vin(-)

Vin(+)

Vin(-)

V_REF

V pk-pk

V min | max

-0.1 | +V_REF+ 0.1

V_REF/2 0.1

Common mode Input Voltage

Input Capacitance

V

pF typ

Ohms

Differential Input Impedance

DYNAMIC PERFORMANCE

AD7766

Decimate by 8, ODR = 125 ksps

Shorted inputs

Dynamic Range²

dB typ

Signal to Noise Ratio (SNR)²

Spurious Free Dynamic Range (SFDR)²

Total Harmonic Distortion (THD) ²

Intermodulation Distortion (IMD) ²

AD7766-1

108

TBD

-96

dB typ

dBFS typ

dB max

dB typ

TBD

Decimate by 16, ODR = 62.5 ksps

Shorted inputs

Dynamic Range²

dB typ

Signal to Noise Ratio (SNR)²

Spurious Free Dynamic Range²(SFDR)

Total Harmonic Distortion (THD) ²

Intermodulation Distortion (IMD) ²

AD7766-2

111

TBD

-96

dB typ

dBFS typ

dB max

dB typ

TBD

Decimate by 32, ODR = 31.25 ksps

Shorted inputs

Dynamic Range²

dB typ

Signal to Noise Ratio (SNR) ²

Spurious Free Dynamic Range (SFDR)²

Total Harmonic Distortion (THD) ²

Intermodulation Distortion (IMD) ²

DC ACCURACY¹

114

TBD

-96

dB typ

dBFS typ

dB max

dB typ

TBD

Resolution

No Missing Codes

24

Bits

Differential Nonlinearity²

Integral Nonlinearity²

Zero Error²

Guaranteed monotonic to 24 bits

16 bit linearity

15

ppm

% typ

nV/°C typ

ppm/°C typ

dB typ

dB

TBD

25

0.3

TBD

Gain Error²

Zero Error Drift²

Gain Error Drift²

Power Supply Rejection²

Common mode rejection²

DIGITAL FILTER RESPONSE¹

Group Delay

Settling time (latency)

Passband ripple

f = 50Hz, 60Hz

37/ODR

74/ODR

0.005

TBD

µs typ

dB max

Hz

Complete Settling

Passband

-3dB bandwidth

TBD

Hz

Stopband

TBD

Hz

Stopband Attenuation

100

dB min

Rev. PrD | Page 3 of 18

AD7766

Preliminary Technical Data

Parameter

REFERENCE INPUT¹

Test Conditions/Comments

Specifcation

Unit

V_REF+Input Voltage

+2.4

2 x AV_DD

TBD

V min

V max

Ohms

Reference Input Impedance

DIGITAL INPUTS (Logic Levels)¹

V_IL

-0.3

Vmin

0.3 x V_DRIVE

0.7 x V_DRIVE

V_DRIVE+ 0.3

TBD

Vmax

Vmin

Vmax

uA max

uA/pin max

pF max

MHz typ

MHz max

V_IH

Input Current

Input leakage

Input Capacitance

Master Clock rate

1

30

Serial Clock rate

DIGITAL OUTPUTS¹

Data Format

Serial 24 bits Two’s Complement (MSB 1^st)

I_SINK= +500 µA

V_OL

0.4

V max

V min

V_OH

V_DRIVE– 0.3

I_SOURCE= -500 µA

POWER REQUIREMENTS¹

AV_DD

DV_DD

V_DRIVE

+2.375/+2.625

+1.7/+3.6

V min/max

AD7766 Current Specifications

125 Khz Output Data Rate

AI_DD

DI_DD

I_REF

I_DRIVE

1.4

3.2

0.7

0.8

mA typ

V_DRIVE= 3.6V, Full-scale code output, TBD pF load.

62.5 Khz Output Data Rate

AD7766-1 Current Specifications

AI_DD

DI_DD

I_REF

I_DRIVE

1.4

1.8

0.7

0.8

mA typ

V_DRIVE= 3.6V, Full-scale code output, TBD pF load.

31.25 Khz Output Data Rate

AD7766-2 Current Specifications

AI_DD

DI_DD

I_REF

I_DRIVE

1.4

1.1

0.7

0.8

mA typ

V_DRIVE= 3.6V Full-scale code output, TBD pF load.

Power Dissapation

AD7766

AD7766-1

AD7766-2

Power Down ¹

125 KHz Output Data Rate (Dec × 8)

62.5 KHz Output Data Rate (Dec × 16)

31.25 KHz Output Data Rate (Dec × 32)

(All decimation rates)

15

12

10

mW typ

TBD

¹Specifications for all devices, AD7766, AD7766-1 and AD7766-2.

²See Terminology

Rev. PrD | Page 4 of 18

Preliminary Technical Data

TIMIMG DIAGRAMS

AD7766

t₂

1

8*n

1

8*n

MCLK

t₃

t₄

t₅

t₁

DRDY

t_READ

t_DRDY

DRDY

Figure 2.

versus MCLK TimingDiagram. For AD7766 n=1(Decimate by8), AD7766-1 n=2(Decimate by 16), AD7766-2 n = 4(Decimate by 32).

t_DRDY

DRDY

CS

t_READ

t₁₃

t₆

t₁₀

23

1

SCLK

SDO

t₁₁

t₈

t₁₂

t₇

t₉

D20

MSB

D1

LSB

D22

D21

CS

Figure 3.Serial timing diagram, reading data using

CS = 0

t_DRDY

t_READ

t₁₀

DRDY

SCLK

t₁₄

23

24

1

t₁₁

t₁₅

t₈

t₉

DATA

INVALID

DATA

INVALID

D1

SDO

MSB

D22

D21

D20

LSB

CS

Figure 4.Serial timing diagram, reading data setting logic low.

Rev. PrD | Page 5 of 18

AD7766

Preliminary Technical Data

Part out of Power down

Filter Reset

Begins Sampling

Part in Power down

B

D

A

C

MCLK (I)

t₂₀

t₁₈

SYNC/PD (I)

DRDY (O)

t₂₁

t₁₉

t

SETTLING

DOUT (O)

VALID DATA

INVALID DATA

VALID DATA

Figure 5.Reset and Synchronization and Power down timing diagram.

Rev. PrD | Page 6 of 18

Preliminary Technical Data

AD7766

TIMING SPECIFICATIONS

Table 3. AV_DD= DV_DD= 2.5 V 5%, V_DRIVE= 1.7 V to 3.6 V, V_REF= 5 V, T_A= -40°C to +105°C, unless otherwise noted¹

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DRDY Operation

t₁

t₂

t₃

t₄

t₅

TBD

ns

DRDY Falling edge to MCLK rising edge

MCLK High Pulsewidth

MCLK Low Pulsewidth

MCLK Rising edge to DRDYRising edge

DRDY Pulse width

TBD

2

t_READ

t_DRDY- t₅

DRDY low period. Read data during this period.

2

t_DRDY

n×8×t_MCLK

ns

DRDY Period.

Read Operation

t₆

0

ns

DRDY Falling Edge to CS Setup Time

CS Falling Edge to SDO three-state disabled

Data access time after SCLK falling edge

SCLK Falling Edge to Data Valid hold time

SCLK High Pulsewidth

SCLK Low Pulsewidth

Bus Relinquish Time after CS Rising Edge

CS Rising Edge to DRDY Rising Edge

t₇

TBD

0

t₈

t₉

t₁₀

t₁₁

t₁₂

t₁₃

Read Operation with CS low

t₁₄

TBD

0

ns

DRDY Falling Edge to Data valid Setup Time

DRDY Rising Edge to Data Valid hold time

t₁₅

Daisy Chain Operation

t₁₆

t₁₇

TBD

ns

SDI Valid to SCLK Falling Edge Setup Time

SCLK Falling Edge to SDI Valid Hold Time

Synchronise Operation

t₁₈

t₁₉

t₂₀

t₂₁

TBD

ns

SYNC/PD Falling edge to MCLK Rising Edge

MCLK Rising edge to DRDY Rising Edge

SYNC/PD Rising edge to MCLK Rising Edge

ns

TBD

ns

TBD

ns

MCLK Rising edge to DRDY Falling edge coming out of SYNC/PD

Filter Settling Time after a Reset or power down.

2

t_SETTLING

592×n +2

t_MCLK

¹Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV_DD) and timed from a voltage level of

1.6 V

²n = 1 for AD7766, n= 2 for the AD7766-1, n=4 for the AD7766-2.

Rev. PrD | Page 7 of 18

AD7766

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 4. T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameters

Rating

AV_DDto AGND

-0.3V to +3V

DV_DDto DGND

AV_DDto DV_DD

-0.3V to +3V

-0.3V to + 0.3V

-0.3V to +7V

V_REF+to V_REF-

V_REF-to AGND

-0.3V to + 0.3V

-0.3V to +6V

V_DRIVEto DGND

V_IN+,V_IN–to AGND

Digital inputs to DGND

Digital Outputs to DGND

AGND to DGND

-0.3V to V_REF+0.3V

-0.3V to V_DRIVE+ 0.3V

-0.3V to + 0.3V

10mA

Input current to any pin except

supplies¹

Operating temperature range

Storage temperature range

Junction temperature

TSSOP Package

−40°C to +105°

−65°C to +150°C

150°C

150.4°C/W

27.6°C/W

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead temperature, soldering

Vapor phase (60 secs)

Infrared (15 secs)

215°C

220°C

TBD kV

ESD

¹Transient currents of up to TBD mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrD | Page 8 of 18

Preliminary Technical Data

AD7766

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AV

1

2

3

4

5

6

7

8

16 CS

DD

AD7766/

AD7766-1/

AD7766-2

TOP VIEW

(Not to Scale)

V

15 SDI

REF+

14 MCLK

13 SCLK

12 DRDY

11 DGND

10 SDO

REFGND

V

IN+

V

IN-

AGND

SYNC/PD

DV

DD

9

V

DRIVE

Figure 6.16-Lead TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin Mnemonic

Description

Number

1

2

AV_DD

V_REF+

+2.5V Analog power supply.

Reference Input for the AD7766. An external reference must be applied to this input pin. The

VREF+ input can range from 2.4V to 5V. The reference voltage input is independent of the

voltage magnitude applied to the AV_DDpin.

3

REFGND

Reference Ground. Ground Connection for the reference voltage. The input reference voltage

(V_REF+) should be decoupled to this pin.

4

5

6

7

V_IN+

V_IN-

AGND

SYNC/PD

Positive input of the Differential Analog input.

Negative input of the Differential Analog input.

Power supply ground for Analog circuitry.

Synchronisation and Power Down Input pin. This pin has dual functionality. It can be used to

synchronise multiple AD7766 devices and/or put the AD7766 device into power down mode.

See the Power Down, Reset & Synchronization section for further details.

8

9

DVDD

V_DRIVE

Digital Power Supply input. This pin can be connected directly to V_DRIVE.

Logic power supply input, +1.8V to +3.6V. The voltage supplied at this pin will determine the

operating voltage of the digital logic interface.

10

SDO

Serial Data Output (SDO). The conversion result from the AD7766 is output on the SDO pin as a

24 bit, two’s complement, MSB first, serial data stream.

11

12

DGND

DRDY

Digital logic power supply ground

Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data

result is available in the output register of the AD7766. See the AD7766 Interface section for

further details.

13

14

15

SCLK

MCLK

SDI

Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the

AD7766 device. See the AD7766 Interface Section for further details.

Master Clock Input. The AD7766 sampling frequency is directly proportional to the MCLK

frequency.

Serial Data Input. This is the Daisy-Chain input of the AD7766. See the

Daisy Chaining section for further details.

16

CS

Chip Select Input. The CS input selects the AD7766 device, and acts as an enable on the SDO

pin. In cases where CS is used, the MSB of the conversion result is clocked onto the SDO line on

the CS falling edge. The CS input allows multiple AD7766 devices to share the same SDO line.

This allows the user to select the appropriate device by supplying it with a logic low CS signal,

which enables the SDO pin of the device concerned. See the AD7766 Interface section for

further details.

Rev. PrD | Page 9 of 18

AD7766

Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Rev. PrD | Page 10 of 18

Preliminary Technical Data

TERMINOLOGY

AD7766

Signal-to-Noise Ratio (SNR)

Integral Nonlinearity (INL)

SNR is the ratio of the rms value of the actual input signal to the

ms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

INL is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal

1 LSB change between any two adjacent codes in the ADC.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the fundamental.

For the AD7766, it is defined as

Zero Error

Zero error is the difference between the ideal midscale input

voltage (when both inputs are shorted together) and the actual

voltage producing the midscale output code.

V₂²+ V₃²+ V₄²+ V₅²+ V₆²

THD

where:

dB = 20 log

( )

V₁

Zero Error Drift

Zero error drift is the change in the actual zero error value due

to a temperature change of 1°C. It is expressed as a percentage

of full scale at room temperature.

V₁is the rms amplitude of the fundamental.

V₂, V₃, V₄, V₅, and V₆are the rms amplitudes of the second to

the sixth harmonics.

Gain Error

Nonharmonic Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the rms signal amplitude to the rms value

of the peak spurious spectral component, excluding harmonics.

The first transition (from 100 … 000 to 100 … 001) should

occur for an analog voltage ½ LSB above the nominal negative

full scale. The last transition (from 011 … 110 to 011 … 111)

should occur for an analog voltage 1½ LSB below the nominal

full scale. The gain error is the deviation of the difference

between the actual level of the last transition and the actual

level of the first transition, from the difference between the

ideal levels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to

the rms noise measured with the inputs shorted together. The

value for the dynamic range is expressed in decibels.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion products

at sum and difference frequencies of mfa nfb, where m, n = 0,

1, 2, 3, and so on. Intermodulation distortion terms are those

for which neither m nor n are equal to 0. For example, the second-

order terms include (fa + fb) and (fa − fb), and the third-order

terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

Gain Error Drift

Gain error drift is the change in the actual gain error value due

to a temperature change of 1°C. It is expressed as a percentage

of full scale at room temperature.

The AD7766 is tested using the CCIF standard, where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, and the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification, where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in decibels.

Rev. PrD | Page 11 of 18

AD7766

Preliminary Technical Data

AD7766 TRANSFER FUNCTION

THEORY OF OPERATION

The AD7766 outputs its conversion results in a 2’s complement,

24-bit serial format. The fully differential inputs VIN+ and

VIN- are scaled by the AD7766 relative to the reference voltage

input (VREF+) as shown in Figure 12.

The AD7766 is high performance 24-bit over-sampled analog to

digital converter combining wide dynamic range and input

bandwidth with an on chip FIR filter while consuming only

20mW max power in a 16 pin TSSOP package. The AD7766 is

available with 3 preset decimation rates, 8, 16 and 32. Table 6

shows the three available models of the AD7766. The three

models differ in the preset decimation rate employed. The

output data rates of the AD7766, AD7766-1 and the AD7766-2

are relative to each of their preset decimation rates.

24-Bits

2’s Complement

011…111

011…110

000…010

Table 6. AD7766 Models.

000…001

AD7766

Decimation Rate Output Data Rate (ODR)

000…000

24-Bit

Output

AD7766

AD7766-1

AD7766-2

8

125 KHz

62.5 KHz

31.25 KHz

111…111

111…110

16

32

100…001

100…000

In decimate × 8 mode the output will be updated every 8 MCLK

periods, offering a maximum output data rate of 125KHz for

the AD7766 device. The AD7766-1 model is set in decimate ×

16 mode, and the AD7766-2 is preset to decimate × 32. The

decimation ratio of each model indicates the level of filtering

employed in the on-board digital FIR filter. The higher filter

decimation rates provide the user with increased dynamic

specifications; however, there is a trade-off on throughput as the

filter delay increases as higher decimation rates are introduced.

V

+ = V

V

+

= 0V

V

+ = V

- 1LSB

IN

REF

2

IN

REF

V

-

= V

REF

-1LSB

V

-

= V

V

-

= 0V

IN

REF

2

IN

Figure 12.AD7766 TransferFunction

.

Rev. PrD | Page 12 of 18

Preliminary Technical Data

AD7766 INTERFACE

AD7766

CS

devices indicating permission to use the bus. When

high, the SDO line of the AD7766 is is tri-stated.

logic

The AD7766 provides the user with a flexible serial interface

enabling the user to implement the most desireable interfacing

scheme for their application. The AD7766 interface is

There are two distinct patterns that can be initiated to read data

CS

from the AD7766 device, these are for the cases when

falling

edge occurs after the DRDY falling edge and for the case when

comprised of seven different signals. Five of these signals are

CS

the

CS

falling edge occurs before the DRDY falling edge (when

is set to logic low.

CS SYNC PD

inputs : MCLK

output signals,

,

/

, SCLK, and SDI. There are two

DRDY

and SDO.

When the CS falling edge occurs after DRDY falling edge the

MSB of the conversion result is becomes available on the SDO

line on this CS falling edge. The remaining bits of the

conversion result (MSB-1, MSB-2 ..etc) are clocked onto the

SDO line by the falling edges of SCLK which follow the CS

falling edge. Figure 3 details this interfacing scheme.

INITIAL POWER-UP

On initial power up, apply a continuous MCLK signal. Iit is

recommended that the user reset the AD7766 to clear the filters

and ensure correct operation. The reset is completed as

described in Figure 5, with all events occurring relative to the

rising edge of MCLK. A negative pulse on the

/

input

SYNC PD

initiates the reset and the

output will switch to logic high

DRDY

and will remain high until valid data is available.. Following the

SYNC PD

When CS is tied low the AD7766 serial interface can operate in

3-wire mode as shown in Figure 4. In this case the MSB of the

conversion result is available on the SDO line on the falling

power up of the AD7766 by transitioning the

/

pin to

DRDY

edge of

. The remaining bits of the data conversion result

logic high, a settling time is required before valid data is output

by the device. This settling time, t_SETTLING, is a function of the

MCLK frequency and the decimation rate. Table 7 lists the

settling time of each of the AD7766 models, and should be

referenced to Figure 5..

(MSB-1, MSB-2 etc..) are clocked onto the SDO line by the

subsequent SCLK falling edges.

POWER DOWN, RESET & SYNCHRONIZATION

SYNC PD

Decimation Rate

Table 7. Filter settling time after

/

1

t_SETTLING

The AD7766’s

/

pin allows the user to synchronise

SYNC PD

multiple AD7766 devices. This pin also allows the user to reset

and power down the AD7766 device. These features are

implemented relative to the rising edges of MCLK and are

shown in Figure 5

AD7766

AD7766-1

AD7766-2

8

594 × t_MCLK+ t₂₁

1,186 × t_MCLK+ t₂₁

2,370 × t_MCLK+ t₂₁

16

32

¹t_SETTLINGis measured from the first MCLK rising edge after the rising edge of

SYNC PD

To power down, reset or synchronise a device the AD7766

DRDY

.

/

to the falling edge of

/

pin should be taken low. On the first rising edge of

SYNC PD

MCLK the AD7766 is powered down. The

DRDY

transitions to logic high indicating that the data in the output

register is no longer valid. The status of the pin is

READING DATA

The AD7766 outputs its data conversion results in an MSB first,

2’s complement 24-bit format on the Serial Data Output Pin

(SDO). MCLK is the master clock, which controls all the

AD7766 conversions. The SCLK is the serial clock input for the

device. All data transfers take place with respect to the SCLK

signal

/

SYNC PD

checked on each subsequent rising edge of MCLK. On the first

rising edge of MCLK after the pin is taken high the

/

SYNC PD

AD7766 is taken out of power down. On the next rising edge,

the filter of the AD7766 is reset. On the following rising edge,

the first new sample is taken.

The

line is used as a status signal to indicate when the

DRDY

data is available to be read from the AD7766. The falling edge of

indicates that a new data word is available in the output

A settling time, t_SETTLING, from the filter reset, must pass before

valid data is output by the device (as listed in Table 7). The

DRDY

register of the device.

DRDY

output goes logic low after t_SETTLINGto indicate when

valid data is available on SDO for readback.

stays low during the period that

DRDY

output data is permitted to be read from the SDO pin. The

signal returns to logic high to indicate when not to read

DRDY

from the device. Ensure that a data read is not attempted during

this period as the output register is being updated

The AD7766 offers the user the option of using a chip select

CS

input signal ( ) in its data read cycle. The

signal is a gate

for the SDO pin and allows many AD7766 devices to share the

same serial bus acting as an instruction signal to each of these

AD7766

Preliminary Technical Data

The period of SCLK (t_SCLK) required for a known daisy chain

length using a known common MCLK frequency must

DAISY CHAINING

Daisy chaining devices allows numerous devices to use the same

digital interface lines by cascading the outputs of multiple

ADC’s on a single data line. This feature is especially useful for

reducing component count and wiring connections, e.g. in

isolated multi-converter applications or for systems with a

limited interfacing capacity. Data read-back is analogous to

clocking a shift register where data is clocked on the falling edge

of SCLK.

CS

therefore be established in advance. In the case where

logic low:

is tied

Equation 1

t_SCLK

=

{n x 8 x t_MCLK} - {t_{DRDY Hi}}

]

24 x K

The block diagram in Figure 13 shows the way in which devices

must be connected in order to achieve daisy chain functionality.

This scheme operates by passing the output data of the SDO pin

of an AD7766 device to the SDI input of the next AD7766

device in the chain. The data then continues through the chain

until it is clocked onto the SDO pin of the first device on the

chain.

Where K = Number of AD7766 devices in the chain

n is the AD7766 model number being used, where for

AD7766 n= 1, AD7766-1 n= 2, AD7766-2 n= 4.

t_MCLKis the period of the MCLK.

DRDY

t_{DRDY Hi}~ Where

results.

is logic high between conversion

READING DATA IN DAISY CHAIN MODE

CS

In the case where

Equation 2

is used in the daisy chain interface:

An example of a daisy chain of four AD7766 devices is shown in

Figure 13 and Figure 14. In the case illustrated in Figure 13 the

output of AD7766 (A) is the output of the full daisy chain. The

last device in the chain (AD7764(D)) will have its Serial Data In

(SDI) pin connected to ground. All the devices in the chain

t_SCLK

=

{n x 8 x t_MCLK} - { t₆+ t₇+ t₁₃+ t_{DRDY Hi}}

]

24 x K

CS

SYNC PD

must use common MCLK, SCLK,

and

/ signals.

K = Number of AD7766 devices in the chain

n = AD7766 model number being used,

{AD7766 n= 1, AD7766-1 n= 2, AD7766-2 n= 4}

t_MCLKis the period of the MCLK.

To enable the daisy chain conversion process, apply a common

SYNC PD

/

pulse to all devices synchronizing all the devices in

the chain (see Power Down, Reset & Synchronization section).

SYNC PD

pulse to all the devices there is a

After applying a

/

CS

is logic low (SDO is active).

t

_CS= Time when

delay (as listed in Table 7) before valid conversion data appears

at the output of the chain of devices. As shown in Figure 14 the

first conversion result is output from the device labeled

AD7766(A). This 24-bit conversion result is then followed by

the conversion results from the devices B, C and D respectively

with all conversion results output in an MSB first sequence. The

stream of conversion results are clocked through each device in

the chain and are eventually clocked onto the SDO pin of the

AD7766 (A) device. The conversion results of the all the devices

in the chain must be clocked onto the SDO pin of the final

If it is the case that the SCLK frequency is chosen firstly then it

is the SCLK for any given MCLK, which determines the limit of

the number of AD7766 devices that can be successfully daisy-

chained.

Table 8 SCLK Frequency required for a given number of

daisy-chained devices using a 1MCLK frequency.

No. Of Devices MCLK (MHz)

SCLK Frequency

(MHz)¹

DRDY

device in the chain while its

signal is active low. This is

2

4

1

TBD/(n)

illustrated in the example shown where the conversion results

from devices A, B, C, & D are be clocked onto SDO (A) in the

DRDY

time between the falling edge of

DRDY

(A) and the rising edge

8

of

(A).

16

CHOOSING THE SCLK FREQUENCY

¹n = 1 for AD7766, n= 2 for the AD7766-1, n=4 for the AD7766-2.

As shown in Figure 13 the number of SCLK falling edges that

DRDY

occur during the period when

(A) is active low must

match the number of devices in the chain multiplied by 24 (the

number of bits that must be clocked through onto SDO (A) for

each device).

Rev. PrD | Page 14 of 18

Preliminary Technical Data

AD7766

DAISY CHAIN MODE CONFIGURATION & TIMING DIAGRAMS

SYNC/PD

CS

SYNC/PD

CS

DRDY

SDO

SDI

AD7766

(D)

AD7766

(B)

AD7766

(C)

AD7766

(A)

SDI

SDO

SDI

SDO

SDI

SDO

SDI

SCLK

MCLK

SCLK

MCLK

Figure 13 AD7766 Daisy chain configuration with 4 ×AD7766 devices..

8*n

1

DRDY(A)

CS

24 x t

SCLK

24 x t

SCLK

24 x t

SCLK

SDO (A)

AD7766 (A)

AD7766 (B)

AD7766 (C)

AD7766 (D)

AD7766 (B)

AD7766 (C)

AD7766 (D)

AD7766 (C)

AD7766 (D)

AD7766 (A)

AD7766 (B)

AD7766 (C)

AD7766 (D)

SDI (A) = SDO (B)

SDI (B) = SDO (C)

SDI (C) = SDO (D)

Figure 14 AD7766 Daisy chain Timing diagram. For AD7766 n=1, AD7766-1 n =2, AD7766-2 n= 4. Driving the AD7766

1

MCLK

DRDY(A)

CS

SDO (A)

MSB (A)

LSB (A)

MSB (B)

LSB (B) MSB (C)

LSB (C)

t₁₆

t₁₇

MSB (B)

LSB (B)

MSB (C)

LSB (C) MSB (D)

LSB (D)

SDI (A) = SDO (B)

Figure 15 AD7766 Daisychain SDI Set-up and hold timing .

AD7766

Preliminary Technical Data

DRIVING THE AD7766

The AD7766 must be driven with fully differential inputs. The

common mode voltage of the differential inputs to the AD7766

device and thus the limits on the differential inputs are set by

the reference voltage V_REFapplied to the device. The common

mode voltage of the AD7766 is V_REF/2. Where the AD7766 V_REF

pin is supplied with a 5V supply (the ADR435 is

DIFFERENTIAL SIGNAL SOURCE

An example of some recommended driving circuitry that can be

employed in conjunction with the AD7766 is shown in Figure

17. Figure 17 shows how the ADA4841 device can be used to

drive an input to the AD7766 from a differential source. Each of

the differential is driven by an ADA4841 device.

reccommended) the common mode is at 2.5V. This means that

the max inputs that can be applied on the AD7766 differential

inputs are a 5V pk-pk input around 2.5V.

499R

3.3nF

2.5V

499R

A

IN+

V

3R3

REF

ADA4841

1

V

+

IN

V

AV_DD

REF

2

4

5

V

IN+

499R

10nF

AD7766

3.3nF

V

IN-

V_REF+

2

0V

499R

1K

A

IN-

3R3

V

ADA4841

REF

2x V

CM

1K

ADR425

V

–

REF

2

IN

Figure 17. Driving the AD7766 from a fully differential source

0V

Figure 16 Maximum differential inputs to the AD7766

SINGLE-ENDED SIGNAL SOURCE

An analog voltage of 2.5V supplies the AD7766 AV_DDpin.

However, the AD7766 allows the user to apply a reference

voltage of up to 5V. This provides the user with an increased

full-scale range, offering the user the option of using the

AD7766 with a larger LSB voltage size Figure 16 shows the

maximum and minimum inputs to the AD7766.

In the case where the AD7766 is being supplied from a single-

ended source the following application circuit can be used to

drive the AD7766 device. Figure 18 shows how the ADA4941

single to differential amplifier can be used to create a fully

differential input to the AD7766. The single-ended signal input

is applied to the positive input of the ADA4941 device

Vss -

R1

2.5V

Ain +

C1

R1

IN

DIS

V-

OUT-

R3

1

AV

4

5

DD

V

IN+

C2

AD7766

ADA4941

V

IN-

V_REF+

2

FB

REF

R2

V+

OUT+

R4

ADR425

V_offset

R5

C3

2 xV_CM

R2

Vss +

R_FB

C_FB

Figure 18. Driving the AD7766 from a single- ended source.

Rev. PrD | Page 16 of 18

Preliminary Technical Data

DIGITAL FILTERING

AD7766

The response of the digital filter on board the AD7766 is shown

in Figure 20.. The filter provides stop-band attenuation of

100dB and passband ripple of 0.005dB.

The AD7766 has an on-board digital FIR filter. The FIR filter’s

decimation rate is preset for each AD7766 model (See Table 6

for details). The digital filter consists of three separate filter

blocks. Figure 19 shows the three constituent blocks of the filter.

The order of decimation of the first filter block is either set as

either 2, 4 or 8. The remaining sections have a decimation rate

of 2. The settling time of the filter implemented on the AD7766,

AD7766-1 and AD7766-2 is related to the amount of

decimation employed, the filter settling time of each device is

shown in Table 7.

0

-20

-40

( dB )

-60

-80

Digital Filter

Stage 1

Stage 2

FIR Filter

Dec x 2

Stage 3

FIR Filter

Dec x 2

-100

Data

Stream

7th Order

Sinc Filter

SDO

10³

10⁴

10⁵

Dec x (2 x n)

(Hz)

Figure 20.AD7766 Filter Response for AD7766 (MCLK =1Mhz, ODR = 125Khz)

Figure 19.FIR filter stages

(n = 1 for AD7766, n= 2 for AD7766-1, n = 4 for AD7766-2)

AD7766

Preliminary Technical Data

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 21 16-Lead Thin Shrink Small Outline Package

ORDERING GUIDE

Model

Temperature Range

−40°C to +105°

Package Description

Package Option

RU-16

AD7766BRUZ¹

AD7766BRUZ-1¹

AD7766BRUZ-2¹

16-Lead Thin Shrink Small Outline Package

RU-16

¹Z = Pb-free part.

registered trademarks are the property of their respective owners.

PR06449-0-11/06(PrD)

Rev. PrD | Page 18 of 18


型号：	AD7766
厂家：	ADI
描述：	24-Bit, 10mW, 125ksps Analog to Digital Converter in 16 lead TSSOP 24位， 10毫瓦， 125ksps采样率模拟到数字转换器， 16引脚TSSOP 转换器
文件：	总18页 (文件大小：632K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7766 [ADI]

相关型号：

AD7766-1

AD7766-2

AD7766BRUZ

AD7766BRUZ

AD7766BRUZ-1

AD7766BRUZ-1

AD7766BRUZ-1-RL7

AD7766BRUZ-2

AD7766BRUZ-2-RL7

AD7766BRUZ-RL7

AD7766BRUZ-RL7

AD7766_17