AD775 [ADI]
8-Bit 20 MSPS, 60 mW Sampling A/D Converter; 8位20 MSPS ， 60 mW的采样A / D转换器
| 型号： | AD775 |
| 厂家： | 
ADI |
| 描述： | 8-Bit 20 MSPS, 60 mW Sampling A/D Converter |
| 文件： | 总12页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit 20 MSPS, 60 mW
Sampling A/D Converter
a
AD775
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
V
AV
IN
CMOS 8-Bit 20 MSPS Sam pling A/ D Converter
Low Pow er Dissipation: 60 m W
+5 V Single Supply Operation
Differential Nonlinearity: 0.3 LSB
Differential Gain: 1%
DD
DV
DD
19
18 14 15
11
13
AV
DD
AD775
10
D7 (MSB)
9
8
7
15
4
16
17
COARSE
COMPARATORS
V
RTS
Differential Phase: 0.5 Degrees
Three-State Outputs
V
RT
8
6
5
FINE COMPARATORS
On-Chip Reference Bias Resistors
Adjustable Reference Input
Video Industry Standard Pinout
Sm all Packages:
24-Pin 300 Mil SOIC Surface Mount
24-Pin 400 Mil Plastic DIP
BANK A
5
4
3
255
23
22
V
FINE COMPARATORS
BANK B
RB
D0 (LSB)
OE
V
RBS
1
CLOCK LOGIC
AV
SS
2
24
20
AV
21
SS
12
CLK
DV
SS
P RO D UCT H IGH LIGH TS
P RO D UCT D ESCRIP TIO N
Low Power: T he AD775 has a typical supply current of 12 mA,
for a power consumption of 60 mW. Reference ladder current
is also low: 6.6 mA typical, minimizing the reference power
consumption.
T he AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling
analog-to-digital converter (ADC). T he AD775 features a built-
in sampling function and on-chip reference bias resistors to pro-
vide a complete 8-bit ADC solution. T he AD775 utilizes a
pipelined/ping pong two-step flash architecture to provide high
sampling rates (up to 35 MH z) while maintaining very low
power consumption (60 mW).
Complete Solution: T he AD775’s switched capacitor design
features an inherent sample/hold function: no external SHA is
required. On-chip reference bias resistors are included to allow
a supply-based reference to be generated without any external
resistors.
Its combination of excellent DNL, fast sampling rate, low dif-
ferential gain and phase errors, extremely low power dissipation,
and single +5 V supply operation make it ideally suited for a
variety of video and image acquisition applications, including
portable equipment. T he AD775’s reference ladder may be con-
nected in a variety of configurations to accommodate different
input ranges. The low input capacitance (11 pF typical) provides
an easy-to-drive input load compared to conventional flash
converters.
Excellent Differential Nonlinearity: T he AD775 features a
typical DNL of 0.3 LSBs, with a maximum limit of 0.5 LSBs.
No missing codes is guaranteed.
Single +5 V Supply Operation: T he AD775 is designed to oper-
ate on a single +5 V supply, and the reference ladder may be
configured to accommodate analog inputs inclusive of ground.
Low Input Capacitance: T he 11 pF input capacitance of the
AD775 can significantly decrease the cost and complexity of
input driving circuitry, compared with conventional 8-bit flash
ADCs.
T he AD775 is offered in both 300 mil SOIC and 400 mil DIP
plastic packages, and is designed to operate over an extended
commercial temperature range (–20°C to +75°C).
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(T = +25؇C with AV , DV = +5 V, AV , DV = 0 V, V = 2.6 V, V = +0.6 V,
A
DD
DD
SS
SS
RT
RB
AD775–SPECIFICATIONS CLOCK = 20 MHz unless otherwise noted)
AD 775J
P aram eter
Min
Typ
Max
Units
RESOLUT ION
8
Bits
DC ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
+0.5
±0.3
GUARANT EED
1.3
±0.5
LSB
LSB
Offset
T o T op of Ladder VRT
T o Bottom of Ladder VRB
–10
0
–35
+15
–60
+45
mV
mV
VIDEO ACCURACY1
Differential Gain Error
Differential Phase Error
1.0
0.5
%
Degrees
ANALOG INPUT
Input Range (VRT –VRB
Input Capacitance
)
2.0
11
V p-p
pF
AC SPECIFICAT IONS2
Signal-to-Noise and Distortion (S/(N + D))
fIN = 1 MHz
47
41
dB
dB
fIN = 5 MHz
T otal Harmonic Distortion (T HD)
fIN = 1 MHz
fIN = 5 MHz
–51
–42
dB
dB
REFERENCE INPUT
Reference Input Resistance (RREF
Case 1: VRT = VRT S, VRB = VRBS
)
230
300
450
Ω
Reference Bottom Voltage (VRB
Reference Span (VRT –VRB
Reference Ladder Current (IREF
Case 2: VRT = VRT S, VRB = AVSS
Reference Span (VRT –VRB
)
0.60
1.96
4.4
0.64
2.09
7.0
0.68
2.21
9.6
V
V
mA
)
)
)
2.25
5
2.39
8
2.53
11
V
mA
Reference Ladder Current (IREF
)
POWER SUPPLIES
Operating Voltages
AVDD
+4.75
+4.75
+5.25
+5.25
Volts
Volts
DVDD
Operating Current
IAVDD
IDVDD
9.5
2.5
12
mA
mA
mA
IAVDD + IDVDD
17
85
POWER CONSUMPT ION
60
mW
T EMPERAT URE RANGE
Operating
–20
+75
°C
NOT ES
1NST C 40 IRE modulation ramp, CLOCK = 14.3 MSPS.
2fIN amplitude = 0.3 dB full scale.
Specifications subject to change without notice. See Definition of Specifications for additional information.
–2–
REV. 0
AD775
DIGITAL SPECIFICATIONS (T = +25؇C with AV , DV = +5 V, AV , DV = 0 V, V = 2.6 V, V = +0.6 V,
CLOCK = 20 MHz unless otherwise noted)
A
DD
DD
SS
SS
RT
RB
AD 775J
Typ
P aram eter
Sym bol
D VD D
Min
Max
Units
LOGIC INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
VIH
VIL
5.0
5.0
4.0
V
V
1.0
5
(VIH = DVDD
)
IIH
5.25
5.25
µA
Low Level Input Current
(VIL = 0 V)
IIL
–5
µA
Logic Input Capacitance
CIN
5
pF
LOGIC OUT PUT S
High Level Output Current
OE = DVSS, VOH = DVDD–0.5 V
OE = DVDD, VOH = DVDD
Low Level Output Current
OE = DVSS, VOL = 0.4 V
OE = DVDD, VOL = 0 V
IOH
IOZ
4.75
5.25
–1.1
16
mA
µA
IOL
IOZ
4.75
5.25
3.7
mA
µA
16
TIMING SPECIFICATIONS
Sym bol
Min
Typ
Max
Units
Maximum Conversion Rate
Clock Period
Clock High
Clock Low
Output Delay
20
50
25
25
35
MHz
ns
ns
ns
tC
tCH
tCL
tOD
18
30
ns
Pipeline Delay (Latency)
Sampling Delay
Aperture Jitter
2.5
Clock Cycles
ns
ps
tDS
4
30
Specifications subject to change without notice.
SAMPLE N+2
SAMPLE N+1
SAMPLE N
VIN
tDS
tCL
tCH
CLK
OUT
tC
tOD
DATA N-3
DATA N-2
DATA N-1
DATA N
Figure 1. AD775 Tim ing Diagram
REV. 0
–3–
AD775
P IN D ESCRIP TIO N
P in No.
Sym bol
Type Nam e and Function
1
OE
DI
OE = Low
Normal Operating Mode.
Digital Ground. Note: DVSS and AVSS pins should share a common ground plane on the circuit board.
OE = High
High Impedance Outputs.
2, 24
3
DVSS
P
D0 (LSB) DO Least Significant Bit, Data Bit 0.
D1–D6 DO Data Bits 1 T hrough 6.
D7 (MSB) DO Most Significant Bit, Data Bit 7.
4–9
10
11, 13
12
DVDD
CLK
VRT S
VRT
P
+5 V Digital Supply. Note: DVDD and AVDD pins should share a common supply on the circuit board.
DI
AI
AI
AI
AI
P
Clock Input.
16
Reference T op Bias. Short to VRT for Self-Bias.
Reference Ladder T op.
17
23
VRB
Reference Ladder Bottom.
22
VRBS
Reference Bottom Bias. Short to VRB for Self-Bias.
14, 15, 18 AVDD
+5 V Analog Supply. Note: DVDD and AVDD pins should share a common supply within 0.5 inches
of the AD775.
19
VIN
AI
P
Analog Input. Input Span = VRT –VRB.
20, 21
AVSS
Analog Ground. Note: DVSS and AVSS pins should share a common ground within 0.5 inches of the
AD775.
NOT E
T ype: AI = Analog Input; DI = Digital Input; DO = Digital Output; P = Power.
P IN CO NFIGURATIO N
(D IP and SO IC)
MAXIMUM RATINGS*
Supply Voltage (AVDD, DVDD
)
. . . . . . . . . . . . . . . . . . . . 7 V
. . . . . . . . . . . . . . . . . . 0 V
Ground Difference (AVSS–DVSS) . . . . . . . . . . . . . . . . . . . 0 V
Reference Voltage (VRT , VRB . . . . . . . . . . . . . . . . VDD to VSS
Analog Input Voltage (VIN . . . . . . . . . . . . . . . . . . VDD to VSS
Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . VDD to VSS
Digital Output Voltage (VOH , VOL . . . . . . . . . . . . VDD to VSS
Supply Difference (AVDD–DVDD
)
)
)
)
Storage T emperature . . . . . . . . . . . . . . . . . . –55°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
AD775JN –20°C to +75°C 24-Pin 400 Mil Plastic DIP N-24B
AD775JR –20°C to +75°C 24-Pin 300 Mil SOIC R-24A
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD775 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD775
54
48
42
36
30
24
18
12
6
–30
–36
–42
–48
–54
0
0.1
1
10
0.1
1
10
f
IN
– MHz
f
– MHz
IN
Figure 2. S/(N + D) vs. Input Frequency at 20 MSPS Clock
Rate (VIN = –0.3 dB)
Figure 5. THD vs. Input Frequency at 20 MSPS Clock Rate
(VIN = –0.3 dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0
FREQUENCY – MHz
FREQUENCY – MHz
Figure 3. Typical FFT at 1 MHz Input, 20 MSPS Clock Rate
(VIN = –0.5 dB)
Figure 6. Typical FFT at 5 MHz Input, 20 MSPS Clock Rate
(VIN = –0.5 dB)
+0.4
+0.3
+0.2
+0.1
0
+1
0
–0.1
–0.2
–0.3
–0.4
–1
–FULLSCALE
+FULLSCALE
–FULLSCALE
+FULLSCALE
Figure 4. Typical Differential Nonlinearity (DNL)
Figure 7. Typical Integral Nonlinearity (INL)
REV. 0
–5–
AD775
D EFINITIO NS O F SP ECIFICATIO NS
D iffer ential P hase
Integr al Nonlinear ity (INL)
T he difference in the output phase of a small high frequency
sine wave at two stated levels of a low frequency signal on which
it is superimposed.
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” T he
point used as “zero” occurs 1/2 LSB before the first code tran-
sition. “Full scale” is defined as a level 1 1/2 LSB beyond the
last code transition. T he deviation is measured from the center
of each particular code to the true straight line.
P ipeline D elay (Latency)
T he number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
D iffer ential Nonlinear ity (D NL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) is guaranteed.
Signal-to-Noise P lus D istor tion Ratio (S/N+D )
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components including har-
monics but excluding dc. T he value for S/N+D is expressed in
decibels.
O ffset Er r or
Total H ar m onic D istor tion (TH D )
T he first code transition should occur at a level 1/2 LSB above
nominal negative full scale. Offset referred to the Bottom of
Ladder VRB is defined as the deviation from this ideal. T he last
code transition should occur 1 1/2 LSB below the nominal
positive full scale. Offset referred to the T op of Ladder VRT is
defined as the deviation from this ideal.
T HD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is ex-
pressed as a percentage or in decibels.
D iffer ential Gain
T he percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low fre-
quency signal on which it is superimposed.
TH EO RY O F O P ERATIO N
AP P LYING TH E AD 775
T he AD775 uses a pipelined two-step (subranging) flash archi-
tecture to achieve significantly lower power and lower input
capacitance than conventional full flash converters while still
maintaining high throughput. T he analog input is sampled by
the switched capacitor comparators on the falling edge of the
input clock: no external sample and hold is required. T he coarse
comparators determine the top four bits (MSBs), and select the
appropriate reference ladder taps for the fine comparators. With
the next falling edge of the clock, the fine comparators determine
the bottom four bits (LSBs). Since the LSB comparators require
a full clock cycle between their sampling instant and their deci-
sion, the converter alternates between two sets of fine compara-
tors in a “ping-pong” fashion. T his multiplexing allows a new
input sample to be taken on every falling clock edge, thereby
providing 20 MSPS operation. T he data is accumulated in the
correction logic and output through a three-state output latch
on the rising edge of the clock. T he latency between input sam-
pling and the corresponding converted output is 2.5 clock cycles.
REFERENCE INP UT
T he AD775 features a resistive reference ladder similar to that
found in most conventional flash converters. T he analog input
range of the converter falls between the top (VRT ) and bottom
(VRB) voltages of this ladder. T he nominal resistance of the lad-
der is 300 ohms, though this may vary from 230 ohms to 450
ohms. T he minimum recommended voltage for VRB is 0 V; the
linearity performance of the converter may deteriorate for input
spans (VRB–VRB) below 1.8 V. While 2.8 V is the recommended
maximum ladder top voltage (VRT ), the top of the ladder may be
as high as the positive supply voltage (AVDD) with minimal lin-
earity degradation.
AV
DD
325Ω
AD775
16
17
0.1µF
All three comparator banks utilize the same resistive ladder for
their reference input. T he analog input range is determined by
the voltages applied to the bottom and top of the ladder, and
the AD775 can digitize inputs down to 0 V using a single sup-
ply. On-chip application resistors are provided to allow the
ladder to be conveniently biased by the supply voltage.
300Ω
*VALUES FOR
RESISTANCE
ARE TYPICAL
23
22
T he AD775 uses switched capacitor autozeroing techniques to
cancel the comparators’ offsets and achieve excellent differential
nonlinearity performance: typically ±0.3 LSB. T he integral
nonlinearity is determined by the linearity of the reference lad-
der and is typically +0.5 LSB.
0.1µF
90Ω
AV
SS
Figure 8. Reference Configuration: 0.64 V to 2.73 V
T o simplify biasing of the AD775, on-chip reference bias resis-
tors are provided on Pins 16 and 22. T he two recommended
configurations for these resistors are shown in Figures 8 and 9.
–6–
REV. 0
AD775
In the topology shown in Figure 8, the top of the ladder (VRT
)
NC
16
17
VRTS
VRT
is shorted to the top bias resistor (VRT S) (Pin 17 shorted to Pin
16), while the bottom of the ladder (VRB) is shorted to the bot-
tom bias resistor (VRBS) (Pin 23 shorted to Pin 22). T his creates
a resistive path (nominally 725 ohms) between AVDD and AVSS
For nominal supply voltages (5 V and 0 V respectively), this
creates an input range of 0.64 V to 2.73 V.
10kΩ
10kΩ
+5V
0.1µF
AD680
500pF
AD775
3
VIN
VOUT
2
.
2
3
GND
1
20Ω
422Ω
0.1µF
1
AD822
0.1µF
22
23
NC
VRBS
VRB
10kΩ
Both top and bottom of the reference ladder should be de-
500pF
0.1µF
coupled, preferably with a chip capacitor to ground to minimize
reference noise.
NC = NO CONNECT
422Ω
10kΩ
6
5
20Ω
7
AD822
T he topology shown in Figure 9 provides a ground-inclusive
input range. T he bottom of the ladder (VRB) is shorted to AVSS
(0 V), while the top of the ladder (VRT ) is connected to the on-
.
140Ω
board bias resistor (VRT S). T his provides a nominal input range
of 0 V to +2.4 V for AVDD of 5 V. T he VRBS pin may be left
floating, or shorted to AVSS
.
Figure 11. Reference Configuration: 0.7 V to 3.2 V
ANALO G INP UT
AV
DD
T he impedance looking into the analog input is essentially
capacitive, as shown in the equivalent circuit of Figure 12, typi-
cally totalling around 11 pF. A portion of this capacitance is
parasitic; the remainder is part of the switched capacitor struc-
ture of the comparator arrays. T he switches close on the rising
edge of the clock, acquire the input voltage, and open on the
clock’s falling edge (the sampling instant). T he charge that must
be moved onto the capacitors during acquisition will be a func-
tion of the converter’s previous two samples, but there should be
no sample-to-sample crosstalk so long as ample driving imped-
ance and acquisition time are provided.
325Ω
AD775
16
17
0.1µF
300Ω
*VALUES FOR
RESISTANCE
ARE TYPICAL
23
22
AV
SS
90Ω
AV
SS
SWITCHES EACH
CLOCK CYCLE
Figure 9. Reference Configuration: 0 V to +2.4 V
AV
DD
More elaborate topologies can be used for those wishing to
provide an input span based on an external reference voltage.
T he circuit in Figure 10 uses the AD780 2.5 V reference to
drive the top of the ladder (VRT ), with the bottom (VRB) of the
ladder grounded to provide an input span of 0 V to +2.5 V. This is
modified in Figure 11 to shift the 2.5 V span up 700 mV.
C2
V
IN
SWITCHES ON ALTERNATE
C1
CLOCK CYCLES
C3
+5V
AV
SS
AD780
AD775
1
2
3
4
8
7
6
5
C1 + C2 + C3 ≈ 11pF
NC
NC
NC
NC
16
17
NC
Figure 12. Equivalent Analog Input Circuit (VIN)
0.1µF
0.1µF
NC
AD775
For example, to ensure accurate acquisition (to 1/4 bit accuracy)
of a full-scale input step in less than 20 ns, a source impedance
of less than 100 ohms is recommended. Figure 13 shows one
option of input buffer circuitry using the AD817. T he AD817
acts as both an inverting buffer and level shifting circuit. In
order to level shift the ground-based input signal to the dc level
required by the input of the AD775, the supply voltage is resis-
tively divided to produce the appropriate voltage at the nonin-
verting input of the AD817. For most applications, the AD817
provides a low cost, high performance level shifter. T he AD811
is recommended for systems which require faster settling times.
22
23
NC
NC = NO CONNECT
Figure 10. Reference Configuration: 0 V to 2.5 V
T he AD775 can accommodate dynamic changes in the reference
voltage for gain or offset adjustment. However, conversions that
are in progress, including those in the converter pipeline, while
the reference voltages are changing will be invalid.
REV. 0
–7–
AD775
1kΩ
100
90
80
70
60
50
40
30
1kΩ
AD775
0VDC
+5V
1.5VDC
AIN
19
AD817
5.6kΩ
10µF
1kΩ
Figure 13. Level Shifting Input Buffer
T he analog input range is set by the voltage at the top and bot-
tom of the reference ladder. In general, the larger the span
(VRT –VRB), the better the differential nonlinearity (DNL) of the
converter; a 1.8 V span is suggested as a minimum to realize
good linearity performance. AS the input voltage exceeds 2.8 V
(for AVDD = 4.75 V), the input circuitry may start to slightly
degrade the acquisition performance.
0
10
20
30
40
CLOCK FREQUENCY – MHz
Figure 15. Power Dissipation vs. Clock Frequency
In applications sensitive to aperture jitter, the clock signal
should have a fall time of less than 3 ns. High speed CMOS
logic families (HC/HCT ) are recommended for their symmetri-
cal swing and fast rise/fall times. Care should be taken to mini-
mize the fanout and capacitive loading of the clock input line.
CLO CK INP UT
T he AD775’s internal control circuitry makes use of both clock
edges to generate on-chip timing signals. T o ensure proper
settling and linearity performance, both tCH and tCL times
should be 25 ns or greater. For sampling frequencies at or near
20 MSPS, a 50% duty cycle clock is recommended. For slower
sampling applications, the AD775 can accommodate a wider
range of duty cycles, provided each clock phase is as least 25 ns.
D IGITAL INP UTS AND O UTP UTS
T he AD775’s digital interface uses standard CMOS, with logic
thresholds roughly midway between the supplies (DVSS, DVDD).
T he digital output is presented in straight binary format, with
full scale (1111 1111) corresponding to VIN = VRT , and zero
(0000 0000) corresponding to VIN = VRB. Excessive capacitive
loading of the digital output lines will increase the dynamic
power dissipation as well as the on-chip digital noise. Logic
fanout and parasitic capacitance on these lines should be mini-
mized for optimum noise performance.
Under certain conditions, the AD775 can be operated at sam-
pling rates above 20 MSPS. Figure 14 shows the signal-to-noise
plus distortion (S/(N+D)) performance of a typical AD775
versus clock frequency. It is extremely important to note that the
maximum clock rate will be a strong function of both temperature and
supply voltage. In general, the part slows down with increasing
temperature and decreasing supply voltage.
T he data output lines may be placed in a high output impedance
state by bringing OE (Pin 1) to a logic high. Figure 16 indicates
typical timing for access and float delay times (tH L and tDD
respectively). Note that even when the outputs are in a high
impedance state, activity on the digital bus can couple back to
the sensitive analog portions of the AD775 and corrupt conver-
sions in progress.
50
40
30
20
10
0
OE
tDD
tHL
DATA
OUTPUT
DATA ACTIVE
THREE-STATE
(HIGH IMPEDANCE)
t
DD = 18ns TYPICAL
tHL = 12ns TYPICAL
0.1
1
10
100
CLOCK FREQUENCY – MHz
Figure 16. High Im pedance Output Tim ing
Figure 14. S(N + D) vs. Clock Frequency (Tem perature
= +25°C)
A significant portion of the AD775’s power dissipation is pro-
portional to the clock frequency: Figure 15 illustrates this
tradeoff for a typical part.
–8–
REV. 0
AD775
P O WER SUP P LY CO NNECTIO NS AND D ECO UP LING
T he analog and digital supplies of the AD775 have been sepa-
rate to prevent the typically large transients associated with the
on-chip digital circuitry from coupling into the analog supplies
(AVDD, AVSS). However, in order to avoid possible latch-up
conditions, AVDD and DVDD must share a common supply
external to the part, preferably a common source somewhere on
the PC board.
AP P LICATIO NS
AD 775 EVALUATIO N BO ARD
Figures 17 through 22 show the schematic and printed circuit
board (PCB) layout for the AD775 evaluation board. Referring
to Figure 17, the input signal is buffered by U3, an AD817 op
amp configured as a unity-gain follower. T he signal is then ac-
coupled and dc-biased by adjusting potentiometer R14. Video
and imaging applications would typically use a dc-restoration
circuit instead of the manual potentiometer adjustment. Q1, an
emitter-follower, buffers the input signal and provides ample
current to drive a simple low-pass filter. T he filtering is included
to limit wideband noise and highlight the fact that the AD775
can be driven from a nonzero source impedance.
Each supply should be decoupled by a 0.1 µF capacitor located
as close to the device pin as possible. Surface-mount capacitors,
by virtue of their low parasitic inductance, are preferable to
through-hole types. A larger capacitor (10 µF electrolytic)
should be located somewhere on the board to help decouple
large, low frequency supply noise. For specific layout informa-
tion, refer to the AD775 Evaluation Board section of the data
sheet.
T he reference circuit is similar to the one shown in Figure 11
with the exception that R1 and R2 allow precise adjustment of
J8
+5VA
+5VA
CLOCK
TP10
(
)
R15
5
6
9
8
CR1
1N4148
499
A
R14
500
R16
49.9
1/6
U7
TP9
1/6
U7
V
CC
D
U3
R13
20
TP5
IN
J1
ANALOG
INPUT
2
3
V
TP2
R4
Q1
6
AD817
4
2N3904
7
C8
22µF
TP1
R11
75
TP13
C7
10pF
49.9
+5VA
+5V
R12
4.99k
ENABLE
C6
C5
EE
P2-40 PIN IDC
1
A
C15
D
C18
A
A
V
V
V
EE
CC
+5V
D
AD775
74ALS541
C22
D
D
13
DV
CLK 12
DD
DD
DD
1
2
3
20
19
18
17
16
15
14
13
12
11
J10
14 AV
15 AV
DV
DD
G1
A1
A2
V
CC
11
10
9
D
TP4
D7
G2
Y1
Y2
Y3
V
RT
R8
10k
R9
10k
16
17
V
V
D6
D5
D4
D3
D2
D1
D0
RTS
J3
J6
4
5
U5
8
A3
A4
A5
A6
A7
A8
RT
U6
C4
390pF
C13
18 AV
7
A
DD
+5VA
3
U1
AD680
6
7
A
19
20
21
22
23
24
6
V
Y4
Y5
IN
1/2 U2
R10
20
C14
2
2
3
AV
AV
V
5
SS
SS
V
V
IN
OUT
8
1
AD822
8
4
Y6
Y7
Y8
GND
C12
9
C9
A
C2
1
A
J4
3
2
1
RBS
RB
J5
D
10
A
GND
V
DV
A
SS
+5VA
R3
499
J2
DV
OE
SS
J9
TP3
D
C1
A
VRB
C3
390pF
R6
10k
R2
D
R7
R5
20
500
10k
1/2 U2
7
6
5
AD822
A
R1
500
4
TP12
TP6
A
+5V
A
J7
NOTES
40
D
= 47µF ELECTROLYTIC CAPACITOR
78M05
U4
C21
V
CC
UNLESS OTHERWISE NOTED
+5VA
D
TP7
V
2
CC
= 0.1µF CERAMIC CAPACITOR
1
3
5
V
V
IN
OUT
UNLESS OTHERWISE NOTED
GND
C16
C11
TP8
4
6
A
C19
C20
TP11
V
EE
V
EE
Figure 17. AD775 Evaluation Board Schem atic
–9–
REV. 0
AD775
portant aspect is the power and ground distribution. While the
AD775 has separate analog and digital power and ground pins,
the AD775 should be treated as an entirely analog component.
T he ground plane is joined close to the ADC in order to main-
tain a low potential difference across the analog and digital
ground pins. Because the power and grounds are derived from a
common point, a slit in the ground plane is used to minimize
any interaction between the analog and digital return currents.
VRT and VRB. Note that the VRT and VRB traces (see Figures 19
and 20) are run in parallel and in the same proximity. Any noise
coupling is likely to be common mode to both signals and would
result in an offset error but not a gain error. T he entire reference
circuit is powered by a single +5 V supply. T he minimum volt-
age for VRB is determined by the impedance of the AD822 out-
put stage and the amount of current flowing through the
internal resistor ladder of the AD775.
T he power for the AD775, AVDD and DVDD, are derived from
the same supply. Separate traces are run to AVDD and DVDD
and joined together at the source. While not used on the evalua-
tion board, a ferrite bead or inductor can effectively isolate noise
generated by digital circuitry such as the output buffers. In cases
where only a single supply is available, the inductor should not
be placed between AVDD and DVDD. Instead, both supplies of
the AD775 should be connected together and isolated from
entirely digital components.
T he sampling clock is buffered by U7, a 74HC04 inverter. It is
recommended that the output loading of the inverter is mini-
mized in order to maintain fast transition times on the clock. An
additional inverter is used to provide a buffered clock signal
whose rising edges indicate that data is valid. A 74ALS541
buffers the eight digital data outputs of the AD775 to improve
the load driving capability.
T he multilayer PCB board layout shows some of the important
design guidelines recommended for the AD775. T he most im-
Table I. Com ponents List
D escription
Reference D esignator
Quantity
R1, R2, R14
R3, R15
R4, R13, R16
R5, R10
R6–R9
R11
R12
CR1
Potentiometer
3
2
3
2
4
1
1
1
Resistor, 1%, 499 Ω
Resistor, 1%, 49.9 Ω
Resistor, 1%, 20 Ω
Resistor, 1%, 10 kΩ
Resistor, 1%, 75 Ω
Resistor, 1%, 4.99 kΩ
Diode, 1N4148
C1, C2, C5, C6, C9, C12–C15, C18
C20, C22, C23
C3, C4
C7
C8
C11, C16, C19, C21
Q1
U1
U2
U3
U4
U5
U6
U7
J1, J8
Ceramic Cap, Z5U, 0.1 µF
Capacitor, Mica, 390 pF
Capacitor, Mica, 10 pF
Capacitor, T antalum, 22 µF, 16 V
Capacitor, Alum. Electrolytic, 47 µF, 16 V
T ransistor, 2N3904
AD680JT
AD822AN
AD817AN
78M05
AD775
13
2
1
1
4
1
1
1
1
1
1
1
1
2
74ALS541N
74HC04N
BNC Jack
–10–
REV. 0
AD775
Figure 20. Solder Side PCB Layout (Not to Scale)
Figure 18. Silkscreen Layer (Not to Scale)
Figure 19. Com ponent Side PCB Layout (Not to Scale)
Figure 21. Ground Plane PCB Layout (Not to Scale)
REV. 0
–11–
AD775
Figure 22. Power Plane PCB Layout (Not to Scale)
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic D IP (N-24B)
SO IC (R-24A)
24
1
13
12
24
1
0.346 (8.80)
0.330 (8.40)
13
PIN 1
0.221 (5.6)
0.205 (5.2)
PIN 1
12
0.327 (8.3)
0.295 (7.5)
1.205 (30.60)
1.185 (30.10)
0.020
(0.50)
MIN
0.400 (10.16)
0.089 (2.25)
0.200 (5.05)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.606 (15.4)
0.586 (14.9)
0.067 (1.70)
0.272 (6.9)
0.118 (3.00)
MIN
15
°
0.014 (0.35)
0.008 (0.20)
0°
0.024 (0.60)
0.016 (0.40)
0.053 (1.35) SEATING
0.100
(2.54)
BSC
0.012 (0.12)
0.002 (0.05)
PLANE
0.022 (0.55)
0.014 (0.35)
0.028 (0.7)
0.012 (0.3)
0.041 (1.05)
0.050 (1.27)
BSC
0.012 (0.30)
0.006 (0.15)
–12–
REV. 0
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