AD7750 [ADI]
Product-to-Frequency Converter; 产品 - 频率转换器
| 型号： | AD7750 |
| 厂家： | 
ADI |
| 描述： | Product-to-Frequency Converter |
| 文件： | 总16页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product-to-Frequency
Converter
a
AD7750
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Tw o Differential Analog Input Channels
Product of Tw o Channels
G1
VDD ACDC
Voltage-to-Frequency Conversion on a Single Channel
Real Pow er Measurem ent Capability
< 0.2% Error Over the Range 400% Ibasic to 2% Ibasic
Tw o or Four Quadrant Operation (Positive and
Negative Pow er)
Gain Select of 1 or 16 on the Current Channel (Channel 1)
Choice of On-Chip or External Reference
Choice of Output Pulse Frequencies Available
(Pins F1 and F2)
ADC1
REVP
V
V
1+
2ND ORDER
MODULATOR
x16
DELAY
CLKOUT
CLKIN
1–
HPF
ADC2
MULT
V
V
2+
2–
2ND ORDER
MODULATOR
x2
F1
F2
DTF
High Frequency Pulse Output for Calibration Purposes
2.5V
BAND GAP
REFERENCE
LPF
(FOUT
)
HPF on Current Channel for Offset Rem oval
Single 5 V Supply and Low Pow er
F
DTF
OUT
AD7750
AGND REFOUT
REFIN
FS S1 S2 DGND
GENERAL D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD7750 is a Product-to-Frequency Converter (PFC)
that can be configured for power measurement or voltage-to-
frequency conversion. T he part contains the equivalent of two
channels of A/D conversion, a multiplier, a digital-to-frequency
converter, a reference and other conditioning circuitry. Channel 1
has a differential gain amplifier with selectable gains of 1 or 16.
Channel 2 has a differential gain amplifier with a gain of 2. A high-
pass filter can be switched into the signal path of Channel 1 to
remove any offsets.
1. T he part can be configured for power measurement or
voltage-to-frequency conversion.
2. T he output format and maximum frequency is selectable;
from low-frequency outputs, suitable for driving stepper
motors, to higher frequency outputs, suitable for calibration
and test.
3. T here is a reverse polarity indicator output that becomes
active when negative power is detected in the Magnitude
Only Mode.
T he outputs F1 and F2 are fixed width (275 ms) logic low going
pulse streams for output frequencies less than 1.8 Hz. A range
of output frequencies is available and the frequency of F1 and
F2 is proportional to the product of V1 and V2. T hese outputs
are suitable for directly driving an electromechanical pulse
counter or full stepping two phase stepper motors. T he outputs
can be configured to represent the result of four-quadrant multi-
plication (i.e., Sign and Magnitude) or to represent the result of
a two quadrant multiplication (i.e., Magnitude Only). In this
configuration the outputs are always positive regardless of the
input polarities. In addition, there is a reverse polarity indicator
output that becomes active when negative power is detected in
the Magnitude Only Mode, see Reverse Polarity Indicator.
4. Error as a % of reading over a dynamic range of 1000:1 is
< 0.3%.
T he error as a percent (%) of reading is less than 0.3% over a
dynamic range of 1000:1.
T he AD7750 is fabricated on 0.6 µ CMOS technology; a pro-
cess that combines low power and low cost.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(V = 5 V ؎ 5%, AGND = 0 V, DGND = 0 V, REFIN = +2.5 V, CLKIN = 3.58 MHz
DD
T
MIN to TMAX = –40؇C to +85؇C, ACDC = Logic High)
AD7750–SPECIFICATIONS
A Version
–40؇C to
+85؇C
P aram eter
Units
Test Conditions/Com m ents
ACCURACY
Measurement Error1
Gain = 1
Channel 2 with Full-Scale Signal
0.2
0.3
0.2
0.4
% Reading max
% Reading max
% Reading max
% Reading max
Measured Over a Dynamic Range on Channel 1 of 500:1
Measured Over a Dynamic Range on Channel 1 of 1000:1
Measured Over a Dynamic Range on Channel 1 of 500:1
Measured Over a Dynamic Range on Channel 1 of 1000:1
CLKIN = 3.58 MHz, Line Frequency = 50 Hz
HPF Filter On, ACDC = 1
Gain = 16
Phase Error Between Channels
Phase Lead 40° (PF = +0.8)
Phase Lag 60° (PF = –0.5)
±0.2
±0.2
Degrees (°) max
Degrees (°) max
HPF Filter On, ACDC = 1
Feedthrough Between Channels
Output Frequency Variation (FOUT
Power Supply Rejection
HPF Filter On, ACDC = 1, Mode 3, Channel 1 = 0 V
% Full-Scale max Channel 2 = 500 mV rms at 50 Hz
HPF Filter On, ACDC = 1, Mode 3, Channel 1 = 0 V
% Full-Scale max Channel 2 = 500 mV rms, Power Supply Ripple
250 mV at 50 Hz. See Figures 1 and 3.
)
)
0.0005
0.03
Output Frequency Variation (FOUT
ANALOG INPUT S
Maximum Signal Levels
Input Impedance (DC)
Bandwidth
±1
400
3.5
V max
kΩ min
kHz typ
On Any Input, V1+, V1–, V2+ and V2–. See Analog Inputs.
CLKIN = 3.58 MHz
CLKIN = 3.58 MHz, CLKIN/1024
Offset Error
Gain Error
Gain Error Match
±10
±4
±0.3
mV typ
% Full-Scale typ
% Full-Scale typ
REFERENCE INPUT
REFIN Input Voltage Range
2.7
2.3
50
V max
V min
kΩ min
2.5 V + 8%
2.5 V – 8%
Input Impedance
ON-CHIP REFERENCE
Reference Error
Nominal 2.5 V
±200
mV max
T emperature Coefficient
55
ppm/°C typ
CLKIN
Input Clock Frequency
4.5
2
MHz max
MHz min
LOGIC INPUT S
FS, S1, S2, ACDC and G1
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
CLKIN
2.4
0.8
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
T ypically 10 nA, VIN = 0 V to VDD
V max
µA max
pF max
Input High Voltage, VINH
Input Low Voltage, VINL
4
0.4
V min
V max
LOGIC OUT PUT S2
F1 and F2
Output High Voltage, VOH
ISOURCE = 8 mA
VDD = 5 V
ISINK = 8 mA
VDD = 5 V
4.3
0.5
V min
V max
Output Low Voltage, VOL
FOUT and REVP
Output High Voltage, VOH
ISOURCE = 1 mA
VDD = 5 V ± 5%
ISINK = 200 µA
VDD = 5 V ± 5%
4
V min
Output Low Voltage, VOL
0.4
±10
15
V max
µA max
pF max
High Impedance Leakage Current
High Impedance Capacitance
–2–
REV. 0
AD7750
A Version
–40؇C to
+85؇C
P aram eter
Units
Test Conditions/Com m ents
POWER SUPPLY
For Specified Performance, Digital Input @ AGND
or VDD
VDD
IDD
4.75
5.25
5.5
V min
V max
mA max
5 V – 5%
5 V + 5%
T ypically 3.5 mA
NOT ES
1See plots in T ypical Performance Graphs.
2External current amplification/drive should be used if higher current source and sink capabilities are required, e.g., bipolar transistor.
All specifications subject to change without notice.
(V = 5 V, AGND = 0 V, DVDD = 0 V, REFIN = REFOUT. All specifications TMIN to T
unless otherwise noted.)
DD
MAX
1, 2
TIMING CHARACTERISTICS
P aram eter
A Version
Units
Test Conditions/Com m ents
3
t1
t2
t3
t4
t5
t6
275
See T able I
t2/2
ms
s
s
ms
s
s
F1 and F2 Pulsewidth (Logic Low)
Output Pulse Period. See T able I to Determine the Output Frequency
T ime Between F1 Falling Edge and F2 Falling Edge
FOUT Pulsewidth (Logic High)
FOUT Pulse Period. See T able I to Determine the Output Frequency
Minimum T ime Between F1 and F2 Pulse
3
90
See T able I
CLKIN/4
NOT ES
1Sample tested during initial release and after any redesign or process change that may affect this parameter.
2See Figure 18.
3T he pulsewidths of F1, F2 and F OUT are not fixed for higher output frequencies. See the Digital-to-Frequency Converter (DT F) section for an explanation.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
20-Lead SOIC Package, Power Dissipation . . . . . . . . 450 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
20-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead T emperature, Soldering
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
V1+, V1–, V2+ and V2– . . . . . . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
O RD ERING GUID E
P ackage
Tem perature
Range
P ackage
O ptions
Model
D escription
AD7750AN
AD7750AR
–40°C to +85°C
–40°C to +85°C
20-Lead Plastic DIP
20-Lead Wide Body SOIC
N-20
R-20
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7750 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD7750
P IN FUNCTIO N D ESCRIP TIO NS
P in
No.
Mnem onic
D escriptions
1
VDD
G1
Power Supply Pin, 5 V nominal ± 5% for specifications.
2
Gain Select, Digital Input. T his input selects the gain for the Channel 1 differential input. When G1 is
low, the gain is 1 and when G1 is high, the gain is 16. See Analog Inputs section.
3, 4
5
V
1(+), V1(–)
Channel 1 Differential Inputs. See the Analog Inputs section for an explanation of the maximum input
signal ranges. Channel 1 has selectable gains of 1 and 16. T he absolute maximum rating is ±6 V for each
pin. T he recommended clamp voltage for external protection circuitry is ±5 V.
AGND
T he Analog Ground reference level for Channels 1 and 2 differential input voltages. Absolute voltage
range relative to DGND pin is –20 mV to +20 mV. T he Analog Ground of the PCB should be connected
to digital ground by connecting the AGND pin and DGND pin together at the DGND pin.
6, 7
V
2(+), V2(–)
Channel 2 Differential Inputs. See the Analog Inputs section for an explanation of the maximum input
signal ranges. Channel 2 has a fixed gain of 2. T he absolute maximum rating is ±6 V for each pin. T he
recommended clamp voltage for external protection circuitry is ±5 V.
8
9
REFOUT
REFIN
Internal Reference Output. T he AD7750 can use either its own internal 2.5 V reference or an external
reference. For operation with the internal reference this pin should be connected to the REFIN pin.
Reference Input. T he AD7750 can use either its own internal 2.5 V reference or an external reference.
For operation with an external reference, a 2.5 V ± 8%, reference should be applied at this pin. For op-
eration with an internal reference, the REFOUT pin should be connected to this input. For both internal
or external reference connections, an input filtering capacitor should be connected between the REFIN
pin and Analog Ground.
10
11
DGND
FS
T he Ground and Substrate Supply Pin, 0 V. T his is the reference ground for the digital inputs and out-
puts. T hese pins should have their own ground return on the PCB, which is joined to the Analog Ground
reference at one point, i.e., the DGND pin.
Frequency Select, Digital Input. T his input, along with S1 and S2, selects the operating mode of the
AD7750—see T able I.
13, 12 S1, S2
Mode Selection, Digital Inputs. T hese pins, along with FS, select the operating mode of the AD7750—
see T able I.
14
ACDC
High-Pass Filter Control Digital Input. When this pin is high, the high-pass filter is switched into the
signal path of Channel 1. When this pin is low, the high-pass filter is removed. Note when the filter is off
there is a fixed time delay between channels; this is explained in the Functional Description section.
15
16
17
CLKIN
CLKOUT
REVP
An external clock can be provided at this pin. Alternatively, a crystal can be connected across CLKIN
and CLKOUT for the clock source. T he clock frequency is 3.58 MHz for specified operation.
When using a crystal, it must be connected across CLKIN and CLKOUT . T he CLKOUT can drive
only one CMOS load when CLKIN is driven externally.
Reverse Polarity, Digital Output. T his output becomes active high when the polarity of the signal on
Channel 1 is reversed. T his output is reset to zero at power-up. T his output becomes active only when
there is a pulse output on F1 or F2. See Reverse Polarity Indicator section.
18
FOUT
High-Speed Frequency Output. T his is also a fixed-width pulse stream that is synchronized to the
AD7750 CLKIN. T he frequency is proportional to the product of Channel 1 and Channel 2 or the signal
on either channel, depending on the operating mode—see T able I. T he output format is an active high
pulse approximately 90 ms wide—see Digital-to-Frequency Conversion section.
20, 19 F1, F2
Frequency Outputs. F1 and F2 provide fixed-width pulse streams that are synchronized to the AD7750
CLKIN. T he frequency is proportional to the product of Channel 1 and Channel 2—see T able I. T he
output format is an active low pulse approximately 275 ms wide—see Digital-to-Frequency Conver-
sion section.
–4–
REV. 0
AD7750
P IN CO NFIGURATIO N
SO IC and D IP
V
1
2
3
4
5
6
7
8
9
20
F1
DD
G1
19 F2
V
18
17
16
15
14
13
12
11
F
OUT
1+
1–
V
REVP
CLKOUT
CLKIN
ACDC
S1
AD7750
AGND
TOP VIEW
(Not to Scale)
V
2+
V
2–
REFOUT
REFIN
S2
FS
DGND 10
Typical Performance Characteristics
120
100
80
140
AS PER DATA SHEET
CONDITIONS WITH
GAIN = 16
120
AS PER DATA SHEET
CONDITIONS WITH
GAIN = 1
100
80
60
40
20
0
60
40
20
0
0
0.01
0.02 0.03 0.04 0.05 0.06
50Hz RIPPLE – V rms
0.07 0.08 0.09
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
50Hz RIPPLE – V rms
Figure 3. PSR as a Function of VDD 50 Hz Ripple
Figure 1. PSR as a Function of VDD 50 Hz Ripple
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
45
46
47
48
49
50
51
52
53
54
55
LINE FREQUENCY – Hz
Figure 2. Phase Error as a Function of Line Frequency
REV. 0
–5–
AD7750
0.1
0.6
0.05
0.4
0.2
V
= 5.25V
DD
0
–0.05
–0.1
0
V
= 5.00V
DD
–0.15
–0.2
V
= 5V
–0.2
DD
V2 = FULL SCALE
–0.4
–0.6
–0.25
V
= 4.75V
DD
–0.3
0.001
0
1
2
3
0.01
0.1
V1 AMPLITUDE – mV rms
1.0
10
10
10
10
10
V1 AMPLITUDE – mV rms
Figure 4. Error as a Percentage (%) of Reading Over a
Dynam ic Range of 1000, Gain = 1
Figure 6. Measurem ent Error vs. Input Signal Level and
Varying VDD with Channel 1, Gain = 1
0
–0.05
–0.1
0.8
0.6
0.4
0.2
–0.15
–0.2
V
= 5.00V
= 5.25V
= 4.75V
DD
–0.25
–0.3
0
V
–0.2
DD
V
= 5V
DD
–0.35
–0.4
V2 = FULL SCALE
–0.4
–0.6
V
DD
–0.45
–0.5
–2
–1
0
1
2
0.0001
0.001
V1 AMPLITUDE – mV rms
0.01
0.1
10
10
10
V1 AMPLITUDE – mV rms
10
10
Figure 5. Error as a Percentage (%) of Reading Over a
Dynam ic Range of 1000, Gain = 16
Figure 7. Measurem ent Error vs. Input Signal Level and
Varying VDD with Channel 1, Gain = 16
–6–
REV. 0
AD7750
In Figure 12, Channel 1 has a peak voltage on V1+ and V1– of
±1 V. These signals are not gained (G1 = 0) and so the
differential signal presented to the modulator is ±2 V.
However, Channel 2 has an associated gain of two and so
care must be taken to ensure the modulator input does not
exceed ±2 V. T herefore, the maximum signal voltage that
can appear on V2+ and V2– is ±0.5 V.
ANALO G INP UTS
T he analog inputs of the AD7750 are high impedance bipolar
voltage inputs. T he four voltage inputs make up two truly
differential voltage input channels called V1 and V2. As with
any ADC, an antialiasing filter or low-pass filter is required on
the analog input. T he AD7750 is designed with a unique
switched capacitor architecture that allows a bipolar analog
input with a single 5 V power supply. T he four analog inputs
(V1+, V1–, V2+, V2–) each have a voltage range from –1.0 V to
+1.0 V. T his is an absolute voltage range and is relative to the
ground (AGND) pin. T his ground is nominally at a potential of
0 V relative to the board level ground. Figure 8 shows a very
simplified diagram of the analog input structure. When the ana-
log input voltage is sampled, the switch is closed and a very
small sampling capacitor is charged up to the input voltage. T he
resistor in the diagram can be thought of as a lumped compo-
nent made up of the on resistance of various switches.
T he difference between single-ended and complementary
differential input schemes is shown in the diagram below,
Figure 9. For a single-ended input scheme the V– input is
held at the same potential as the AGND Pin. T he maxi-
mum voltages can then be applied to the V+ input are
shown in Figures 10 and 11. An example of this input
scheme uses a shunt resistor to convert the line current to a
voltage that is then applied to the V1+ input of the AD7750.
An example of the complementary differential input scheme
uses a current transformer to convert the line current to a
voltage that is then applied to V1+ and V1–. With this
scheme the voltage on the V+ input is always equal to, but
of opposite polarity to the voltage on V–. T he maximum
voltage that can be applied to the inputs of the AD7750
using this scheme is shown in Figures 12 and 13.
R
1.4k⍀
V
IN
SAMPLING
CAPACITOR
C
2pF
Figure 8. Equivalent Analog Input Circuit
Analog Inputs P r otection Cir cuitr y
Note that the common mode of the analog inputs must
be driven. T he output terminals of the CT are, therefore,
referenced to ground.
T he analog input section also has protection circuitry. Since the
power supply rails are 0 V to 5 V, the analog inputs can no
longer be clamped to the supply rails by diodes. T hus, the inter-
nal protection circuitry monitors the current paths during a fault
condition and protects the device from continuous overvoltage,
continuous undervoltage and ESD events. T he maximum over-
voltage the AD7750 analog inputs can withstand without caus-
ing irreversible damage is ±6 V relative to AGND pin.
V+
A CURRENT TRANSFORMER
PROVIDES COMPLEMENTARY
DIFFERENTIAL INPUTS TO THE
AD7750
V–
In the case of continuous overvoltage and undervoltage the
series resistance of the antialiasing filter can be used to limit
input current. T he total input current in the case of a fault
should be limited to 10 mA.
V+
A CURRENT SENSE RESISTOR
PROVIDES A SINGLE-ENDED
INPUT TO THE AD7750
SHUNT
RESISTOR
V–
For normal operation of the AD7750 there are two further re-
strictions on the signal levels presented to the analog inputs.
1. T he voltage on any input relative to the AGND pin must not
Figure 9. Exam ples of Com plem entary and Single-
Ended Input Schem es
exceed ±1 V.
2. T he differential voltage presented to the ADC (Analog
Modulator) must not exceed ±2 V.
REV. 0
–7–
AD7750
؎1V MAX
؎1V
V
= ؎1V MAX
1+
ADC
X1
V
= AGND
1–
F
OUT
DTF
F1
F2
؎2V MAX
؎2V
V
= ؎1V MAX
2+
X2
ADC
V
= AGND
2–
Figure 10. Maxim um Input Signals with Respect to AGND for a Single-Ended Input Schem e, G1 = 0
؎2V MAX
V
= ؎125mV MAX
1+
ADC
؎2V
X16
V
= AGND
1–
F
OUT
DTF
F1
F2
؎2V MAX
؎2V
V
= ؎1V MAX
2+
X2
ADC
V
= AGND
2–
Figure 11. Maxim um Input Signals with Respect to AGND for a Single-Ended Input Schem e, G1 = 1
؎1V MAX
V+ = ؎1V MAX
ADC
؎2V
X1
V– = ؎1V MAX
F
OUT
؎1V MAX
DTF
F1
F2
؎1V MAX
؎2V
V+ = ؎0.5V MAX
V– = ؎0.5V MAX
X2
ADC
؎1V MAX
Figure 12. Maxim um Input Signals for a Com plem entary Input Schem e, G1 = 0
؎1V MAX
V+ = ؎62.5V MAX
ADC
X16
؎2V
V– = ؎62.5V MAX
F
OUT
؎1V MAX
؎1V MAX
DTF
F1
F2
V+ = ؎0.5V MAX
V– = ؎0.5V MAX
X2
؎2V
ADC
؎1V MAX
Figure 13. Maxim um Input Signals for a Com plem entary Input Schem e, G1 = 1
–8–
REV. 0
AD7750
D ETERMINING TH E O UTP UT FREQ UENCIES O F TH E
AD 7750
FOUT, F1 and F2 are the frequency outputs of the AD7750. T he
output frequencies of the AD7750 are a multiple of a binary
fraction of the master clock frequency CLKIN. T his binary
fraction of the master clock is referred to as FMAX in this data
sheet. FMAX can have one of two values, FMAX1 and FMAX2,
depending on which mode of operation the AD7750 is in. T he
operating modes of the AD7750 are selected by the logic inputs
FS, S2 and S1. T he table below outlines the FMAX frequencies
and the transfer functions for the various operating modes of the
AD7750.
Table I. O perating Mode
Mode
FS
S2
S1
Mode D escription
F1, F21 (H z)
FO UT1 (H z)
FMAX
0
0
0
0
Power Measurement Mode.
Four Quandrant Multiplication
(Sign and Magnitude Output).
FMAX1 ± k.FMAX1
16.[FMAX1 ± k.FMAX1
]
FMAX1 = CLKIN/219
FMAX1 = 6.8 Hz
1
2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Power Measurement Mode.
Two Quandrant Multiplication
(Magnitude Only).
0 to k.FMAX1
0 to k.FMAX1
8.[0 to k.FMAX1
]
FMAX1 = CLKIN/219
FMAX1 = 6.8 Hz
Power Measurement Mode.
Two Quandrant Multiplication
(Magnitude Only).
16.[0 to k.FMAX1
]
FMAX1 = CLKIN/219
FMAX1 = 6.8 Hz
32
4
V1 Channel Monitor Mode on FOUT. FMAX1 ± k.FMAX1
Power Measurement Mode on F1,
F2 (Sign and Magnitude Output).
32.[FMAX1 ± k2.FMAX1
]
FMAX1 = CLKIN/219
FMAX1 = 6.8 Hz
Power Measurement Mode.
Four Quandrant Multiplication
(Sign and Magnitude Output).
FMAX2 ± k.FMAX2
16.[FMAX2 ± k.FMAX2
]
FMAX2 = CLKIN/218
FMAX2 = 13.6 Hz
5
Power Measurement Mode.
Two Quandrant Multiplication
(Magnitude Only).
0 to k.FMAX2
16.[0 to k.FMAX2
]
]
FMAX2 = CLKIN/218
FMAX2 = 13.6 Hz
6
Power Measurement Mode.
Two Quandrant Multiplication
(Magnitude Only).
0 to k.FMAX2
32.[0 to k.FMAX2
FMAX2 = CLKIN/218
FMAX2 = 13.6 Hz
72
V2 Channel Monitor Mode on FOUT. FMAX2 ± k.FMAX2
Power Measurement Mode on F1,
16.[FMAX2 ± k2.FMAX2
]
FMAX2 = CLKIN/218
FMAX2 = 13.6 Hz
F2 (Sign and Magnitude Output).
NOT ES
1T he variable k is proportional to the product of the rms differential input voltages on Channel 1 and Channel 2 (V 1 and V2).
2
k = (1.32 × V1 × V2 × Gain)/VREF
2Applies to F OUT only. T he variable k is proportional to the instantaneous differential input voltage on Channel 1 (FS = 0, S1 = 1, S0 = 1) or the instantaneous differ-
ential voltage on Channel 2 (FS = 1, S1 = 1, S0 = 1), i.e., Channel Monitor Mode.
k = (0.81 × V)/VREF
V = V1 × Gain or
V = V2 × 2
NOT E: V1 and V2 here refer to the instantaneous differential voltage on Channel 1 or Channel 2, not the rms value.
Mode D escr iption (Table I)
quadrant multiplication the magnitude information is included
in the output frequency variation (k.FMAX). However, in this
mode the zero power frequency is 0 Hz, so the output frequency
variation is from 0 Hz to (k.FMAX) Hz. Also note that a no-load
threshold and the reverse polarity indicator are implemented in
these modes see No Load T hreshold and Reverse Polarity
Indicator sections. T hese modes are the most suitable for a
Class 1 meter implementation.
T he section of T able I labeled Mode Description summarizes
the functional modes of the AD7750. T he AD7750 has two
basic modes of operation, i.e., four and two quadrant multiplica-
tion. T he diagram in Figure 14 is a graphical representation of
the transfer functions for two and four quadrant multiplication.
Four Q uadr ant Multiplication (Modes 0, 3, 4 and 7)
When the AD7750 is operating in its four quadrant multiplica-
tion mode the output pulse frequency on F1, F2 and FOUT
contains both sign and magnitude information. T he magni-
tude information is indicated by the output frequency variation
(k.FMAX) from a center frequency (FMAX). T he sign informa-
tion is indicated by the sign of the frequency variation around
FMAX. For example if the output frequency is equal to FMAX
k.FMAX then the magnitude of the product is given by k.FMAX
and it has a negative sign.
Channel Monitor Modes (Modes 3 and 7)
In this mode of operation the FOUT pulse frequency does not
give product information. When FS = 0, the FOUT output fre-
quency gives sign and magnitude information about the volt-
age on Channel 1. When FS = 1 the FOUT output frequency
gives sign and magnitude information about the voltage on
Channel 2.
–
Note the F1, F2 pulse outputs still continue to give power
information.
Two Q uadr ant Multiplication (Modes 1, 2, 5 and 6)
When operating in this mode the output pulse frequency only
contains magnitude information. Again as in the case of four
REV. 0
–9–
AD7750
FOUR QUADRANT MULTIPLICATION
(SIGN AND MAGNITUDE)
TWO QUADRANT MULTIPLICATION
( MAGNITUDE ONLY)
V2(+)
V2(+)
F
– k
؋
F F
+ k
؋
F MAX
k
؋
F MAX
k
؋
F MAX
MAX
MAX
MAX
(–)
(+)
(+)
(+)
0
V1(–)
V1(+)
V1(–)
V1(+)
k
؋
F MAX
k
؋
F MAX
F
+ k
؋
F F
_ k
؋
F MAX
MAX
MAX
MAX
(+)
(+)
(+)
(–)
V2(–)
V2(–)
(1.32
؋
V1 ؋
V2 ؋
GAIN) K =
2
V
REF
Figure 14. Transfer Functions (Four and Two Quadrant Multiplication)
Maxim um O utput Fr equencies
reason great care must be taken when interfacing the analog
inputs of the AD7750 to the transducer. T his is discussed in the
Applications section.
T able II shows the maximum output frequencies of FOUT and
F1, F2 for the various operating modes of the AD7750. T he
table shows the maximum output frequencies for dc and ac
input signals on V1 and V2. When an ac signal (sinusoidal) is
applied to V1 and V2 the AD7750 produces an output frequency
which is proportional to the product of the rms value of these
inputs. If two ac signals with peak differential values of V1MAX
and V2MAX are applied to Channels 1 and 2, respectively, then
the output frequency is proportional to V1MAX/sqrt(2) × V2MAX
sqrt(2) = (V1MAX × V2MAX)/2. If V1MAX and V2MAX are also the
maximum dc input voltages then the maximum output frequen-
cies for ac signals will always be half that of dc input signals.
Example calculation of F1, F2 max for Mode 2 and Gain = 1.
H P F in Channel 1
T o remove any dc offset that may be present at the output
modulator 1, a user selectable high-pass IIR filter (Pin ACDC)
can be introduced into the signal path. T his HPF is necessary
when carrying out power measurements. However, this HPF
has an associated phase lead given by 90°–tan–1(f/2.25). Figure
16 shows the transfer function of the HPF in Channel 1. T he
Phase lead is 2.58° at 50 Hz. In order to equalize the phase
difference between the two channels a fixed time delay is intro-
duced. T he time delay is set at 143 µs, which is equivalent to a
phase lag of –2.58° at 50 Hz. T hus the cumulative phase shift
through Channel 1 is 0°.
/
T he maximum input voltage (dc) on Channel 1 is 2 V (V1+
+1 V, V1– = –1 V)—see Analog Inputs section. T he maximum
input voltage on Channel 2 is 1 V. Using the transfer function:
=
Because the time delay is fixed, external phase compensation
circuitry will be required if the line frequency differs from
50 Hz. For example with a line frequency of 60 Hz the phase
lead due to the HPF is 2.148° and the phase lag due to the fixed
time delay is 3.1°. T his means there is a net phase lag in Chan-
nel 1 of 0.952°. T his phase lag in Channel 1 can be compen-
sated for by using a phase lag compensation circuit like the
one shown in Figure 17. The phase lag compensation is placed
on Channel 2 (voltage channel) to equalize the channels. T he
antialiasing filter associated with Channel 1 (see Applications
section) produces a phase lag of 0.6° at 50 Hz; therefore, to
equalize the channels, a net phase lag of (0.6° + 0.952°) 1.552°
should be in place on Channel 2. T he gain trim resistor VR1
(100 Ω) produces a phase lag variation of 1.4° to 1.5° with VR2
= 0 Ω. VR2 can add an additional 0.1° phase lag (VR2 = 200 Ω).
2
k = (1.32 × V1 × V2 × Gain)/VREF
k = 0.4224
F1, F2 = k.6.8 Hz = 2.9 Hz
FUNCTIO NAL D ESCRIP TIO N
T he AD7750 combines two analog-to-digital converters, a digi-
tal multiplier, digital filters and a digital-to-frequency (DT F)
converter onto one low cost integrated circuit. T he AD7750 is
fabricated on a double poly CMOS process (0.6 µ) and retains
its high accuracy by performing all multiplications and manipu-
lations in the digital domain. T he schematic in Figure 15 shows
an equivalent circuit for the AD7750 signal processing chain.
T he first thing to notice is that the analog signals are first con-
verted to digital signals by the two second-order sigma-delta
modulators. All subsequent signal processing is carried out in
the digital domain. T he main source of errors in an application
is therefore in the analog-to-digital conversion process. For this
–10–
REV. 0
AD7750
Table II. Maxim um O utput Frequencies
F1, F2 (H z) FOUT (H z) F1, F2 (H z) FOUT (H z)
Mode
FS S2 S1 (D C)
(D C)
(AC)
(AC)
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.8 ± 2.9
0 to 2.9
0 to 2.9
6.8 ± 2.9
13.6 ± 5.8
0 to 5.8
109 ± 46
0 to 23
0 to 46
218 ± 142
218 ± 92
0 to 92
0 to 184
218 ± 142
6.8 ± 1.45
0 to 1.45
0 to 1.45
6.8 ± 1.45
13.6 ± 2.9
0 to 2.9
109 ± 23
0 to 11.5
0 to 23
218 ± 142
218 ± 46
0 to 46
0 to 5.8
13.6 ± 5.8
0 to 2.9
13.6 ± 2.9
0 to 92
218 ± 142
ACDC
TIME DELAY 143s
G1
(CLKIN = 3.5795MHz)
2.58؇C AT 50Hz
HPF
DIGITAL-TO-FREQUENCY BLOCK
COUNTER/ACCUMULATOR
V
V
1+
PGA
τ
ADC 1
CLKIN
1–
F
LPF
OUT
PHASE LEAD OF
2.58؇C AT 50Hz
DTF
F1
F2
DIGITAL
MULTIPLIER
V
V
2+
FS
S2
S1
X2
ADC 2
2–
Figure 15. Equivalent AD7750 Signal Processing Chain
sRC
D igital-to-Fr equency Conver ter (D TF)
H(s) =
1 + sRC
After they have been filtered, the outputs of the two sigma-delta
modulators are fed into a digital multiplier. T he output of the
multiplier is then low-pass filtered to obtain the real power
information. The output of the LPF enters a digital-to-frequency
converter whose output frequency is now proportional to the
real power. T he DT F offers a range of output frequencies to
suit most power measurement applications. T here is also a high
frequency output called FOUT , which can be used for calibra-
tion purposes. T he output frequencies are determined by the
logic inputs FS, S2 and S1. T his is explained in the section of
this data sheet called Determining the Output Frequencies of
the AD7750.
C
R = 1M⍀
C = 0.0707F
R
Figure 16. HPF in Channel 1
VR2
200⍀
R1
1M⍀
PIN 7
C1
47nF
VR1
100⍀
C2
33nF
R2
33k⍀
R3
1.1k⍀
860:1 ATTENUTATION
Figure 18 shows the waveforms of the various frequency out-
puts. T he outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or electrome-
chanical pulse counter. T he F1 and F2 outputs provide two
alternating low going pulses. T he pulsewidth is set at 275 ms
and the time between the falling edges of F1 and F2 is ap-
proximately half the period of F1. If, however, the period of
F1 and F2 falls below 550 ms (1.81 H z) the pulsewidth of F1
and F2 is set to half the period. For example in Mode 3,
where F1 and F2 vary around 6.8 Hz, the pulsewidth would vary
from 1/2.(6.8+1.45) seconds to 1/2.(6.8–1.45) seconds—see
T able II.
R4
1.1k⍀
PIN 6
C3
33F
Figure 17. Phase Lag Com pensation on Channel 1 for
60 Hz Line Frequency
REV. 0
–11–
AD7750
T he high frequency FOUT output is intended to be used for
communications (via IR LED) and calibration purposes. FOUT
produces a 90 ms wide pulse at a frequency that is proportional
to the product of Channel 1 and Channel 2 or the instanta-
neous voltage on Channel 1 or Channel 2. T he output fre-
quencies are given in T able I in the Determining the Output
Frequencies of the AD7750 section of this data sheet. As in
the case of F1 and F2, if the period of FOUT falls below 180 ms,
the FOUT pulsewidth is set to half the period. For example, if the
FOUT frequency is 20 Hz, the FOUT pulsewidth is 25 ms.
meter accuracy with small load currents. Hence an error of less
than 1% from 4% Ib to 400% Ib will be easier to achieve.
We will assume the design of a Class 1 meter. T he specification
(IEC1036) requires that the meter have an error of no greater
than 1% over the range 4% Ib to 400% Ib (IMAX), where Ib is
the basic current1. In addition, we will design a meter that ac-
commodates signals with a crest factor of 2. T he crest factor is
the ratio of VPEAK/V rms. A pure sinusoidal waveform has a crest
of sqrt(2) = 1.414 and an undistorted triangular waveform has a
crest factor of sqrt(3) = 1.73. Using a gain of 1 on Channel 1
the maximum differential signal which can be applied to Chan-
nel 1 is ±2 V—See Analog Input Ranges section. With a crest
factor of 2 the maximum rms signal on Channel 1 is, therefore,
1 V rms (equivalent to IMAX). T he smallest signal (4% Ib) ap-
pearing on Channel 1 is therefore 10 mV rms.
t1
V
DD
F1
t6
0V
t2
V
DD
Load Current
4% Ib
Ib
Channel 1
10 mV rms
250 mV rms
1 V rms
F2
t3
0V
t5
t4
V
DD
400 Ib
F
OUT
0V
2
1
Figure 18. Tim ing Diagram for Frequency Outputs
400% Ib
VO LTAGE REFERENCE
T he AD7750 has an on-chip temperature compensated band-
gap voltage reference of 2.5 V with a tolerance of ±250 mV.
0. 2
The temperature drift for the reference is specified at 50 ppm/°C.
It should be noted that this reference variation will cause a
frequency output variation from device to device for a given set
of input signals. T his should not be a problem in most applica-
tions since it is a straight gain error that can easily be removed
at the calibration stage.
0. 02
4% Ib
0.01
REVERSE P O LARITY IND ICATO R
0. 002
When the AD7750 is operated in a Magnitude Only mode of
operation (i.e., Modes 1, 2, 5 and 6), and the polarity of the
power changes, the logic output REVP will go high. However,
the REVP pin is only activated when the there is pulse output
on F1 or F2. Therefore, if the power being measured is low, it may
be some time before the REVP pin goes logic high even though the
polarity of the power is reversed. Once activated the REVP output
will remain high until the AD7750 is powered down.
Figure 19. Use the Upper End of the Dynam ic Range of
Channel 1 (Current)
Calculations for a 100 P P KWH R Meter
T he AD7750 offers a range of maximum output frequencies—
see T able I and T able II. In the Magnitude Only modes of
operation the two maximum output frequencies are 1.45 Hz
and 2.9 Hz. T he signal on the voltage channel (Channel 2) is
scaled to achieve the correct output pulse frequency for a given
load (e.g., 100 PPKWHR). T he relationship between the input
signals and the output frequency is given by the equation:
AP P LICATIO NS INFO RMATIO N
D esigning a Single P hase Class 1 Ener gy Meter (IEC 1036)
T he AD7750 Product-to-Frequency Converter is designed for
use in a wide range of power metering applications. In a typical
power meter two parameters are measured (i.e., line voltage and
current) and their product obtained. T he real power is then
obtained by low-pass filtering this product result. T he line
voltage can be measured through a resistor divider or voltage
transformer, and the current can be sensed and converted to
a voltage through a shunt resistor, current transformer or hall
effect device.
Freq = k × FMAX
2
where k = (1.32 × V1 × V2 × Gain)/VREF
FMAX = 6.8 Hz or 13.6 Hz depending on the mode—see T able
I, Gain is the gain of Channel 1, V1 and V2 are the differential
voltages on Channels 1 and 2 and VREF is the reference voltage
(2.5 V ± 8%).
T o design a 100 PPKWHR meter with Ib = 15 A rms and a line
voltage of 220 V rms the output pulse frequency with a load
current of Ib is 0.0916 Hz (See Calculation 1 below).
T he design methodology used in the following example is to use
the upper end of the current channel dynamic range, i.e., Chan-
nel 1 of the AD7750. T he assumption here is that the signal on
the voltage channel will remain relatively constant while the
signal on the current channel will vary with load. Using the
upper end of the dynamic range of Channel 1 will improve the
T herefore, 0.0916 Hz = k × 6.8 Hz (Mode 2) or k = 0.01347.
With a load current of Ib the signal on Channel 1 (V1) is equal
to 0.25 V rms (remember 400% Ib = 1 V rms) and, therefore,
the signal on Channel 2 (V2) is equal to 0.255 V rms (See Calcula-
tion 2). This means that the nominal line voltage (220 V rms)
needs to be attenuated by approximately 860, i.e., 220/0.255.
1See IEC 1036 2nd Edition 1996-09 Section 3.5.1.1.
–12–
REV. 0
AD7750
For 100 PPKWHR V2 is equal to 0.255 V rms or the line volt-
age attenuated by a factor of 860.
Antialiasing Com ponents Channels 1 and 2
T he AD7750 is basically two ADCs and a digital multiplier. As
with any ADC, a LPF (Low-Pass Filter) should be used on the
analog inputs to avoid out of band signal being aliased into the
band of interest. In the case of a Class 1 meter the band of
interest lies in the range 48 Hz to 1 kHz approximately. T he
components R3, R4, R6, R7, C5, C6, C9 and C10 make up the
LPFs on each of the four analog inputs. Note that although
Channel 2 is used single ended a LPF is still required on V2–.
Ca lcula tion 1
100 PPKWHR = 0.02777 Hz/kW.
Ib of 15 A rms and line voltage of 220 V = 3.3 kΩ. Hence, the
output frequency is given by 3.3 × 0.02777 Hz = 0.0916 Hz.
Ca lcula tion 2
k = (1.32 × V1 × V2 × Gain)/VREF
2
.
0.01347 = (1.32 × 0.25 × V2 × 1)/6.25.
V2 = 0.255.
P ower Supply Cir cuit
T he AD7750 operates from a single power supply of 5 V ± 5%
but still accommodates input signals in the range ±1 V. Because
the AD7750 doesn’t require dual supplies the number of exter-
nal components for the power supply is reduced. One of the
most important design goals for the power supply is to ensure
that the ripple on the output is as low as possible. Every analog
or mixed signal IC is to a greater or lesser extent susceptible to
power supply variations. Power supply variations or ripple, if
large enough, may affect the accuracy of the device when mea-
suring small signals. T he plot in Figure 20 shows the ripple
associated with the circuit in Figure 21. T he ripple is in the
region of 10 mV peak to peak.
Figure 21 below shows how the design equations from the previ-
ous page are implemented.
Measur ing the Load Cur r ent
T he load current is converted to a voltage signal for Channel 1
using a CT (Current T ransformer). A 15 A rms load should
produce a 250 mV rms signal on Channel 1. A CT with a turns
ratio of 120 and a shunt resistor of 2 Ω. will carry out the neces-
sary current to voltage conversion. T he CT and its shunt resis-
tance should be placed as close as possible to the AD7750. T his
will improve the accuracy of the meter at very small load cur-
rents. At small load currents the voltage levels on Channel 1 are
in the order of 10 mV and the meter is more prone to error due
to stray signal “pick up.” When measuring power the HPF in
the current channel must be switched on. T his is done by con-
5.065
5.060
5.055
necting the ACDC pin to VDD
.
NOT E: T he voltage signals on V1+ and V1– must be referenced
to ground. T his can be achieved as shown in Figure 21 below,
i.e., by referencing 1/2 RCT to ground or by connecting a
centertap on the CT secondary to ground.
Measur ing the Line Voltage
When the AD7750 is biased around the live wire as shown in
Figure 21, the task of measuring the line voltage is greatly
simplified. A resistor divider attenuates the line voltage and
provides a single-ended input for Channel 2. T he component
values of the divider are chosen to give the correct rating (e.g.,
100 PPKWHR) for the meter. See the design equations on the
previous page. For this design an attenuation ratio of 860:1 is
required.
5.050
600 620 640 660 680 700 720 740 760 780 800
TIME ؊ ms
Figure 20. Power Supply Ripple
V
DD
R4
LOAD
1/2 R
CT
20
19
18
17
16
15
14
13
12
11
1
2
C5
1⍀
M
PULSE COUNTER
C8
C7
R8
R9
1/2 R
CT
D4
D3
D5
IR DIODE FOR
CALIBRATION
3
CT
120:1
1⍀
C6
R3
4
REVERSE POLARITY
INDICATOR
C4
5
AD7750
TOP VIEW
(Not to Scale)
R5
XTAL 3.57954MHz
6
C3
V
R7
C9
VR1
R6
7
DD
C10
8
9
V
MODE2
DD
C12
C11
*
10
D1
D2
C1
R1
R2
C2
V
DD
Z1
MOV
SOURCE
*BIASING AROUND THE LIVE WIRE PATENTED BY SCHLUMBERGER.
Figure 21. Suggested Class 1 Meter Im plem entation
–13–
REV. 0
AD7750
Register ing the P ower O utput
T his is equivalent to a line current of:
T he low frequency pulse outputs (F1 and F2) of the AD7750
provide the frequency output from the product-to-frequency
conversion. T hese outputs can be used to drive a stepper motor
or impulse counter.
(37.95 µV/2 Ω ) × 120 = 2.27 mA rms or 0.5 W
or
(2.27 mA/15 A) × 100% = 0.015% of Ib.
A high frequency output is available at the pin FOUT . T his high
frequency output is used for calibration purposes. In Mode 2
the output frequency is 16 × F1(2). With a load current of Ib
the frequency at FOUT will be 1.4656 Hz (0.0916 Hz × 16 from
calculations). If a higher frequency output is required, the FS
pin can be set to VDD 5 V for calibration. In this case the output
frequency is equal to 64 × F1 or 5.8624 Hz at Ib—see T able I.
NOT E: T he no load threshold as a percentage of Ib will be
different for each value of Ib since the no load in watts is fixed:
FS = 0, the no load threshold is (FMAX = 6.8 Hz)
0.5 Watts for a 100 PPKWHR meter
5 Watts for a 10 PPKWHR meter
FS = 1, the no load threshold is (FMAX = 13.6 Hz)
1 Watt for a 100 PPKWHR meter
10 Watts for a 10 PPKWHR meter
NO LO AD TH RESH O LD O F TH E AD 7750
T he AD7750 will detect when the power drops below a certain
level. When the power (current) drops below a predefined
threshold the AD7750 will cease to generate an output drive for
the stepper motor (F1, F2). T his feature of the AD7750 is
intended to reproduce the behavior of Ferraris meters. A
Ferraris meter will have friction associated with the wheel rota-
tion, therefore the wheel will not rotate below a certain power
level. T he no load threshold is only implemented in the Magni-
tude Only modes (Modes 1, 2, 5 and 6—see T able I). T he
IEC1036 specification includes a test for this effect by requiring
no output pulses during some predetermined time period. T his
time period is calculated as:
Ca lcula tion 3
FMIN = 1.32 × V1 × V2 × Gain × 6.8 Hz) VREF
1.39 × 10–5 Hz = V1 × 0.2555 × 1 × 6.8)/6.25
V1 = 37.95 µV
2
EXTERNAL LEAD /LAG CO MP ENSATIO N
External phase compensation is often required in a power meter
design to eliminate the phase errors introduced by transducers
and external components. T he design restriction on any external
compensating network is that the network must have an overall
low-pass response with a 3 dB point located somewhere between
5 kHz and 6 kHz. T he corner frequency of this LPF(s) is much
higher than the band of interest. T he reason for this is to mini-
mize its effect on phase variation at 50 Hz due to component
tolerances.
time period = 60,000/pulses-per-minute
If a meter is calibrated to 100 PPKWHR with a FOUT running
16 times faster than F1 and F2, this time period is 37.5 minutes
(60,000/1,600). T he IEC1036 specifications state that the no
load threshold must be less than the start up current level. T his
is specified as 0.4% of Ib.
With the antialiasing filters on all channels having the same
corner (–3 dB) frequency, the main contribution to phase error
will be due to the CT . A phase lead in a channel is compensated
by lowering the corner frequency of the antialiasing filter to
increase its associated lag and therefore cancel the lead. A phase
lag in a channel should be compensated by introducing extra lag
in the other channel. T his can be done as previously described,
i.e., moving the corner frequency of the antialiasing filters. T he
result in this case is that the signal on both channels has the
same amount of phase lag and is therefore in phase at the analog
inputs to the AD7750. T he recommended RC values for the
antialiasing filters on the voltage and current channels (see
Antialiasing Components Channels 1 and 2) are R = 1 kΩ,
C = 33 nF and R = 100 Ω, C = 330 nF respectively. T hese
values produce a phase lag of 0.6° through the filters. Varying R
in the antialiasing network from 80 Ω to 100 Ω or 800 Ω to 1 kΩ
produces a phase variation from 0.475° to 0.6° at 50 Hz. T his
allows the user to vary the lag by 0.125°.
T he threshold level for a given design can be easily calculated
given that the minimum output frequency of the AD7750 is
0.00048% of the maximum output frequency for a full-scale
differential dc input. For example if FS = 0, the maximum
output frequency for a full-scale dc input is 2.9 Hz (see Table II)
and the minimum output frequency is, therefore, 1.39 × 10–5 Hz.
Calculating the Thr eshold P ower (Cur r ent)
T he meter used in this example is calibrated to 100 PPKWHR,
has an Ib (basic current) of 15 A rms, the line voltage is 220 V
rms and the turns ratio of the CT on Channel 1 is 120:1 with an
2 Ω shunt resistor.
T he nominal voltage on Channel 2 of the AD7750 is 255 mV
rms. An FMAX of 6.8 Hz is selected by setting FS = 0. A Magni-
tude Only Mode (Mode 2) is selected to enable the no load thresh-
old. The gain on Channel 1 is set to 1. The threshold power or
current can be found by using the transfer function in T able I.
2
F1, F2 = (1.32 × V1 × V2 × Gain × FMAX)/VREF
From the transfer function V1 is calculated as 37.95 µV rms—
see Calculation 3.
–14–
REV. 0
AD7750
Table III. Com ponents for Suggested Class 1 Meter Im plem entation in Figure 21
Schem atic
D esignator
D escription
Com m ents
R1
R2
470 Ω, 5%, 1 W
1 kΩ, 5%, 1/2 W
R3, R4,
R7
100 Ω, 10%, 1/2 W
1 kΩ, 10%, 1/2 W
T hese registers are required to form part of the antialiasing filtering on the analog inputs;
they do not perform a voltage-to-current conversion.
R5
1 MΩ, 5%, 2 W
T he choice of R5 determines the attenuation on the voltage channels and hence the meter
rating, e.g., 100 PPKWHR.
R6
1.1 kΩ, 5%, 1/2 W
500 Ω, 10%, 1/2 W
100 Ω, 10/15 T urn
Forms part of the Gain Calibration network with R5 and VR1.
R8, R9
VR1
T his potentiometer is used to perform the Gain Calibration of the meter. Attenuation of
830 to 900—see Applications section.
C1
470 nF, 250 V ac
100 µF, 24 V dc
33 pF
C2
C3, C4
C5, C6,
C9, C10
330 nF
33 nF
Forms part of the antialiasing filters on the analog inputs.
C7, C11
C8, C12
Z1
10 µF, 10 V
10 nF
1N750
D1, D2
D3
1N4007
LED
D4, D5
XT AL
MOV
IR LEDS
3.579545 MHz
V250PA40A
Metal Oxide Varistor–Harris Semiconductor.
REV. 0
–15–
AD7750
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-Lead P lastic D IP
(N-20)
1.060 (26.90)
0.925 (23.50)
20
1
11
0.280 (7.11)
0.240 (6.10)
10
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
20-Lead Wide Body SO IC
(R-20)
0.5118 (13.00)
0.4961 (12.60)
20
11
1
10
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
–16–
REV. 0
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