AD7327TRU-EP-RL7_技术文档

500 kSPS, 8-Channel, Software-Selectable,

True Bipolar Input, 12-Bit Plus Sign ADC

Enhanced Product

AD7327-EP

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

REFIN/OUT

V

CC

DD

12-bit plus sign SAR ADC

AD7327-EP

True bipolar input ranges

Software-selectable input ranges

10 V, 5 V, 2.5 V, 0 V to +10 V

Military temperature range: −55°C to +125°C

500 kSPS throughput rate

8 analog input channels with channel sequencer

Single-ended, true differential, and pseudo differential

analog input capability

V

0

1

2

3

4

5

6

7

IN

2.5V

VREF

13-BIT

I/P

MUX

SUCCESSIVE

APPROXIMATION

ADC

T/H

TEMPERATURE

INDICATOR

DOUT

SCLK

CS

High analog input impedance

Low power: 18 mW

Temperature indicator

CONTROL LOGIC

AND REGISTERS

CHANNEL

SEQUENCER

DIN

Full power signal bandwidth: 22 MHz

Internal 2.5 V reference

V

DRIVE

AGND

V

DGND

High speed serial interface

SS

Power-down modes

Figure 1.

Controlled manufacturing baseline

Single assembly/test site

20-lead TSSOP package

iCMOS process technology

Qualification data available on request

the AD7327-EP can be programmed to be single-ended, true

differential, or pseudo differential.

ENHANCED PRODUCT FEATURES

The ADC contains a 2.5 V internal reference. The AD7327-EP

also allows external reference operation. If a 3 V reference is

applied to the REFIN/OUT pin, the AD7327-EP can accept a

true bipolar 12 V analog input. Minimum 12 V V_DDand V_SS

supplies are required for the 12 V input range. The ADC has a

high speed serial interface that can operate at throughput rates up

to 500 kSPS.

Supports defense and aerospace applications (AQEC standard)

Military temperature range: −55°C to +105°C

Controlled manufacturing baseline

One assembly/test site

One fabrication site

Enhanced product change notification

Qualification data available on request

The AD7327-EP is housed in a 20-lead TSSOP with operation

specified from −55°C to +125°C. Additional application and

technical information can be found in the AD7327 data sheet.

GENERAL DESCRIPTION

The AD7327-EP¹is an 8-channel, 12-bit plus sign successive

approximation ADC designed on the iCMOS™ (industrial CMOS)

process. It enables the development of a wide range of high

performance analog ICs capable of 33 V operation in a footprint

that no previous generation of high voltage devices achieved.

Unlike analog ICs using conventional CMOS processes, iCMOS

components can accept bipolar input signals while providing

increased performance, dramatically reduced power consumption,

and reduced package size.

PRODUCT HIGHLIGHTS

1. The AD7327-EP can accept true bipolar analog input

signals, 10 V, 5 V, 2.5 V, and 0 V to +10 V (unipolar).

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential inputs, four pseudo

differential inputs, or seven pseudo differential inputs.

3. 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 18 mW, at a maximum throughput rate of

500 kSPS.

5. Channel sequencer.

The AD7327-EP can accept true bipolar analog input signals,

software-selectable from 10 V, 5 V, 2.5 V, and 0 V to +10 V.

Each analog input channel can be independently programmed

to one of the four input ranges. The analog input channels on

¹Protected by U.S. Patent No. 6,731,232.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD7327-EP

Enhanced Product

TABLE OF CONTENTS

Features .............................................................................................. 1

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configuration and Function Descriptions..............................9

Typical Performance Characteristics ........................................... 10

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 7

REVISION HISTORY

9/15—Rev. A to Rev. B

Added Enhanced Product Features Section.................................. 1

10/14—Rev. 0 to Rev. A

Changes to Operating Temperature Range, Table 3 .................... 8

9/14—Revision 0: Initial Version

Rev. B | Page 2 of 14

Enhanced Product

SPECIFICATIONS

AD7327-EP

V_DD= 12 V to 16.5 V, V_SS= −12 V to −16.5 V, V_CC= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, V_REF= 2.5 V to 3.0 V internal/external,

f_SCLK= 10 MHz, f_S= 500 kSPS, T_A= T_MAXto T_MIN, unless otherwise noted.

Table 1.

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

f_IN= 50 kHz sine wave

Differential mode, V_CC= 4.75 V to 5.25 V

Differential mode, V_CC< 4.75 V

Single-ended/pseudo differential mode; 10 V,

2.5 V and 5 V ranges, V_CC= 4.75 V to 5.25 V

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)²

76

75.5

72

dB

71.7

75

dB

Single-ended/pseudo differential mode; 0 V to 10 V

V_CC= 4.75 V to 5.25 V and all ranges at V_CC< 4.75 V

Differential mode; 2.5 V and 5 V ranges

Signal-to-Noise + Distortion

(SINAD)²

74

Differential mode; 0 V to 10 V

Differential mode; 10 V range

Single-ended/pseudo differential mode; 2.5 V and

5 V ranges

76

dB

70.7

72.5

dB

Single-ended/pseudo differential mode; 0 V to +10 V

and 10 V ranges

Total Harmonic Distortion (THD)²

−79.3

−78.8

dB

Differential mode; 2.5 V and 5 V ranges

Differential mode; 0 V to 10 V ranges

Differential mode; 10 V range

Single-ended/pseudo differential mode; 5 V range

Single-ended/pseudo differential mode; 2.5 V range

Single-ended/pseudo differential mode; 0 V to +10 V

and 10 V ranges

−82

−80

−76

−77.3

Peak Harmonic or Spurious

Noise (SFDR)²

−80

dB

Differential mode; 2.5 V and 5 V ranges

dB

Differential mode; 0 V to 10 V ranges

Differential mode; 10 V ranges

Single-ended/pseudo differential mode; 5 V range

Single-ended/pseudo differential mode; 2.5 V range

Single-ended/pseudo differential mode; 0 V to +10 V

and 10 V ranges

−82

−79

−77.2

−78.9

dB

Intermodulation Distortion

(IMD)²

f_A= 50 kHz, f_B= 30 kHz

Second-Order Terms

Third-Order Terms

Aperture Delay³

Aperture Jitter³

−88

−90

7

50

−79

dB

ns

ps

dB

Common-Mode Rejection

Up to 100 kHz ripple frequency; see Figure 17

(CMRR)²

Channel-to-Channel Isolation²

Full Power Bandwidth

−72

22

5

dB

MHz

f_INon unselected channels up to 100 kHz; see Figure 14

At 3 dB

At 0.1 dB

Rev. B | Page 3 of 14

AD7327-EP

Enhanced Product

B Version

Typ

Parameter¹

DC ACCURACY⁴

Min

Max

Unit

Test Conditions/Comments

Single-ended/pseudo differential mode 1 LSB =

FSR/4096, unless otherwise noted; differential mode

1 LSB = FSR/8192, unless otherwise noted

Resolution

No Missing Codes

13

12-bit

Bits

Differential mode

plus sign

(13 bits)

11-bit

Bits

Single-ended/pseudo differential mode

plus sign

(12 bits)

Integral Nonlinearity²

1.25

1.2

LSB

Differential mode; V_CC= 3 V to 5.25 V, typical for V_CC

2.7 V

Single-ended/pseudo differential mode, V_CC= 3 V to

5.25 V, typical for V_CC= 2.7 V

Single-ended/pseudo differential mode

(LSB = FSR/8192)

=

−0.7/+1.2

−0.7/+1

Differential Nonlinearity²

−0.99/+1.2 LSB

Differential mode; guaranteed no missing codes to

13 bits

Single-ended mode; guaranteed no missing codes to

12 bits

Single-ended/pseudo differential mode

(LSB = FSR/8192)

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

0.99

LSB

Offset Error^{2, 5}

−6/+10

−7/+11

0.8

0.5

8

LSB

Offset Error Match^{2, 5}

Gain Error^{2, 5}

15

Gain Error Match^{2, 5}

0.5

4

Positive Full-Scale Error^{2, 6}

Positive Full-Scale Error Match^{2, 6}

Bipolar Zero Error^{2, 6}

8

0.5

9

8

Bipolar Zero Error Match^{2, 6}

Negative Full-Scale Error^{2, 6}

Negative Full-Scale Error Match^{2, 6}

0.5

4

7

0.5

Single-ended/pseudo differential mode

Differential mode

ANALOG INPUT

Input Voltage Ranges²

Reference = 2.5 V

(Programmed via Range

Registers)

10

V

V_DD= +10 V min, V_SS= −10 V min, V_CC= +2.7 V to +5.25 V

5

2.5

0 to 10

V

V_DD= +5 V min, V_SS= −5 V min, V_CC= +2.7 V to +5.25 V

V_DD= +10 V min, V_SS= AGND min, V_CC= +2.7 V to +5.25 V

Rev. B | Page 4 of 14

Enhanced Product

AD7327-EP

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

Pseudo Differential V_IN(−)

Input Range²

V_DD= +16.5 V, V_SS= −16.5 V, V_CC= +5 V

3.5

6

5

V

nA

pF

Reference = 2.5 V; range = 10 V

Reference = 2.5 V; range = 5 V

Reference = 2.5 V; range = 2.5 V

Reference = 2.5 V; range = 0 V to +10 V

V_IN= V_DDor V_SS

Per input channel, V_IN= V_DDor V_SS

When in track, 10 V range

When in track, 5 V and 0 V to +10 V ranges

When in track, 2.5 V range

+3/−5

DC Leakage Current

Input Capacitance³

80

3

13.5

16.5

21.5

3

When in hold, all ranges

REFERENCE INPUT/OUTPUT

Input Voltage Range

Input DC Leakage Current

Input Capacitance

2.5

3

1

V

µA

pF

V

10

2.5

Reference Output Voltage

Reference Output Voltage Error

at 25°C

Reference Output Voltage

5

10

25

mV

T_MINto T_MAX

Reference Temperature

Coefficient

ppm/°C

3

7

ppm/°C

Ω

Reference Output Impedance

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

2.4

V

µA

pF

0.8

0.4

1

V_CC= 4.75 V to 5.25 V

V_CC= 2.7 to 3.6 V

V_IN= 0 V or V_DRIVE

Input Current, I_IN

3

Input Capacitance, C_IN

10

LOGIC OUTPUTS

Output High Voltage, V_OH

V_DRIVE

0.2 V

−

V

I_SOURCE= 200 µA

I_SINK= 200 µA

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output

Capacitance³

0.4

1

V

µA

pF

5

Output Coding

Straight natural binary

Twos complement

Coding bit set to 1 in control register

Coding bit set to 0 in control register

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition

Time^{2, 3}

1.6

305

µs

ns

16 SCLK cycles with SCLK = 10 MHz

Full-scale step input

Throughput Rate

500

kSPS

POWER REQUIREMENTS

V_DD

Digital inputs = 0 V or V_DRIVE

2

12

16.5

−16.5

5.25

V

2

V_SS

−12

2.7

2

V_CC

V_DRIVE

Normal Mode (Static)

0.9

mA

V_DD/V_SS= 16.5 V, V_CC/V_DRIVE= 5.25 V

Rev. B | Page 5 of 14

AD7327-EP

Enhanced Product

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

Normal Mode (Operational)

I_DD

I_SS

I_CCand I_DRIVE

Autostandby Mode (Dynamic)

I_DD

I_SS

I_CCand I_DRIVE

Autoshutdown Mode (Static)

I_DD

I_SS

I_CCand I_DRIVE

Full Shutdown Mode

I_DD

f_SAMPLE= 500 kSPS

V_DD= 16.5 V

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

f_SAMPLE= 250 kSPS

V_DD= 16.5 V

195

215

2.3

µA

mA

100

110

0.87

µA

mA

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

SCLK on or off

V_DD= 16.5 V

1

µA

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

SCLK on or off

V_DD= 16.5 V

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

1

µA

I_SS

I_CCand I_DRIVE

POWER DISSIPATION

Normal Mode (Operational)

Full Shutdown Mode

19

38.25

mW

µW

V_DD= +16.5 V, V_SS= −16.5 V, V_CC= +5.25 V

¹Temperature range is −55°C to +125°C.

²See the terminology section of the AD7327 data sheet.

³Sample tested during initial release to ensure compliance.

⁴For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless

otherwise noted.

⁵Unipolar 0 V to 10 V range with straight binary output coding.

⁶Bipolar range with twos complement output coding.

Rev. B | Page 6 of 14

Enhanced Product

AD7327-EP

TIMING SPECIFICATIONS

V_DD= 12 V to 16.5 V, V_SS= −12 V to −16.5 V, V_CC= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, V_REF= 2.5 V to 3.0 V internal/external,

T_A= T_MAXto T_MIN. Timing specifications apply with a 32 pF load, unless otherwise noted.¹

Table 2.

Limit at T_MIN, T_MAX

Description

V_DRIVE≤ V_CC

Parameter V_CC< 4.75 V V_CC= 4.75 V to 5.25 V Unit

f_SCLK

50

10

16 × t_SCLK

75

50

10

16 × t_SCLK

60

kHz min

MHz max

ns max

ns min

ns max

ns min

ns max

ns min

ns max

μs max

μs typ

t_CONVERT

t_QUIET

t₁

t_SCLK= 1/f_SCLK

Minimum time between end of serial read and next falling edge of CS

Minimum CS pulse width

12

5

2

t₂

25

20

CS to SCLK set-up time; bipolar input ranges ( 10 V, 5 V, 2.5 V)

Unipolar input range (0 V to 10 V)

Delay from CS until DOUT three-state disabled

Data access time after SCLK falling edge

SCLK low pulse width

SCLK high pulse width

SCLK to data valid hold time

SCLK falling edge to DOUT high impedance

DIN set-up time prior to SCLK falling edge

DIN hold time after SCLK falling edge

45

26

35

14

t₃

t₄

t₅

t₆

t₇

t₈

57

0.4 × t_SCLK

13

40

10

4

43

0.4 × t_SCLK

8

22

9

4

t₉

t₁₀

t_POWER-UP

2

750

500

25

750

500

25

Power-up from autostandby

Power-up from full shutdown/autoshutdown mode, internal reference

Power-up from full shutdown/autoshutdown mode, external reference

¹Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DRIVE) and timed from a voltage level of 1.6 V.

²When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t₂at 20 ns, the mark space ratio needs to be limited to 50:50.

t₁

CS

t_CONVERT

t₂

t₆

1

2

3

4

5

13

14

t₅

15

16

SCLK

DOUT

3 IDENTIFICATION BITS

t₃

t₇

DB10

t₈

t₄

t_QUIET

ADD1

ADD0

SIGN

DB11

DB2

DB1

DB0

THREE-

STATE

ADD2

THREE-STATE

t₁₀

t₉

DON’T

CARE

REG

SEL1

REG

SEL2

WRITE

MSB

LSB

DIN

Figure 2. Serial Interface Timing Diagram

Rev. B | Page 7 of 14

AD7327-EP

Enhanced Product

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 3.

Parameter

Rating

V_DDto AGND, DGND

V_SSto AGND, DGND

V_DDto V_CC

V_CCto AGND, DGND

V_DRIVEto AGND, DGND

AGND to DGND

Analog Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to GND

REFIN to AGND

Input Current to Any Pin

Except Supplies¹

−0.3 V to +16.5 V

+0.3 V to −16.5 V

V_CC− 0.3 V to 16.5 V

−0.3 V to +7 V

−0.3 V to +0.3 V

V_SS− 0.3 V to V_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to V_CC+ 0.3 V

10 mA

ESD CAUTION

Operating Temperature Range

Storage Temperature Range

Junction Temperature

TSSOP Package

−55°C to +125°C

−65°C to +150°C

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Pb-Free Temperature, Soldering

Reflow

143°C/W

45°C/W

260(0)°C

2.5 kV

ESD

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. B | Page 8 of 14

Enhanced Product

AD7327-EP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

20

19

18

17

16

15

14

13

12

11

CS

SCLK

DGND

DOUT

2

DIN

3

DGND

AD7327-EP

4

AGND

V

TOP VIEW

DRIVE

(Not to Scale)

5

REFIN/OUT

V

CC

DD

6

V

SS

7

V

0

1

4

5

2

IN

8

V

3

6

7

9

10

Figure 3. TSSOP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

1

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7327-EP and frames the serial data transfer.

2

DIN

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the

AD7327-EP on the falling edge of SCLK (see the Registers section of AD7327 data sheet).

3, 19

DGND

Digital Ground. Ground reference point for all digital circuitry on the AD7327-EP. The DGND and AGND

voltages, ideally, share the same potential and must not be more than 0.3 V apart, even on a transient

basis.

4

5

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7327-EP. Refer all analog input

signals and any external reference signal to this AGND voltage. The AGND and DGND voltages, ideally,

share the same potential and must not be more than 0.3 V apart, even on a transient basis.

REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the

AD7327-EP. The nominal internal reference voltage is 2.5 V, which appears at this pin. Place a 680 nF

capacitor on the reference pin (see the Reference section of the AD7327 data sheet). Alternatively, the

internal reference can be disabled and an external reference applied to this input. On power-up, the

external reference mode is the default condition.

6

V_SS

Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

7, 8, 14, 13, 9,

10, 12, 11

V_IN0 to V_IN7 Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.

The analog input channel for conversion is selected by programming the channel address Bit ADD2

through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs,

four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.

The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and

Bit Mode 0, in the control register. The input range on each input channel is controlled by program-

ming the range registers. Input ranges of 10 V, 5 V, 2.5 V, and 0 V to +10 V can be selected on each

analog input channel when a +2.5 V reference voltage is used (see the Registers section of AD7327

data sheet).

15

16

V_DD

V_CC

Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7327-EP.

Decouple this supply to AGND.

17

18

V_DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface

operates. Decouple this pin to DGND. The voltage at this pin may be different to that at V_CC, but it must

not exceed V_CCby more than 0.3 V.

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The

data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data.

The data is provided MSB first (see the Serial Interface section of AD7327 data sheet).

DOUT

20

SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

AD7327-EP. This clock is also used as the clock source for the conversion process.

Rev. B | Page 9 of 14

AD7327-EP

Enhanced Product

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0

V

= V

= 25°C

= 5V INT/EXT 2.5V REFERENCE

4096 POINT FFT

CC

DRIVE

T

±10V RANGE

+INL = +0.55LSB

–INL = –0.68LSB

A

V

= V

= 5V

CC

DRIVE

V

, V = ±15V

–20

–40

DD SS

, V = ±15V

DD SS

0.6

T

= 25°C

A

INT/EXT 2.5V REFERENCE

±10V RANGE

0.4

F

= 50kHz

IN

0.2

SNR = 77.30dB

SINAD = 76.85dB

THD = –86.96dB

SFDR = –88.22dB

–60

0

–80

–0.2

–0.4

–0.6

–0.8

–1.0

–100

–120

–140

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

0

50

100

150

200

250

512 1536

2560

4608

5632

6656

7680

FREQUENCY (kHz)

Figure 7. Typical INL True Differential Mode

Figure 4. FFT True Differential Mode

1.0

0.8

0

4096 POINT FFT

V

= V

= 5V

CC

DRIVE

–20

–40

, V = ±15V

DD SS

0.6

T

= 25°C

A

INT/EXT 2.5V REFERENCE

±10V RANGE

0.4

F

= 50kHz

IN

0.2

SNR = 74.67dB

SINAD = 74.03dB

THD = –82.68dB

SFDR = –85.40dB

–60

0

–80

–0.2

–0.4

–0.6

–0.8

–1.0

–100

–120

–140

V

= V

= 5V

±10V RANGE

CC

DRIVE

T

V

= 25°C

+DNL = +0.79LSB

–DNL = –0.38LSB

A

, V = ±15V

DD SS

INT/EXT 2.5V REFERENCE

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

0

50

100

150

200

250

512 1536

2560

4608

5632

6656

7680

FREQUENCY (kHz)

Figure 8. Typical DNL Single-Ended Mode

Figure 5. FFT Single-Ended Mode

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

V

T

= V

= 25°C

= 5V

CC

DRIVE

V

T

V

= V

= 25°C

= 5V

CC

DRIVE

A

V

, V = ±15V

A

DD SS

, V = ±15V

INT/EXT 2.5V REFERENCE

±10V RANGE

+INL = +0.87LSB

–INL = –0.49LSB

DD SS

INT/EXT 2.5V REFERENCE

±10V RANGE

+DNL = +0.72LSB

–DNL = –0.22LSB

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

512 1536

2560

4608

5632

6656

7680

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

512 1536

2560

4608

5632

6656

7680

Figure 9. Typical INL Single-Ended Mode

Figure 6. Typical DNL True Differential Mode

Rev. B | Page 10 of 14

Enhanced Product

AD7327-EP

–50

80

75

70

65

60

55

50

V

= V

= 3V

±5V DIFF

±2.5V DIFF

CC

DRIVE

/V = ±12V

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

DD SS

T

f

= 25°C

= 500kSPS

A

±5V SE

S

0V TO +10V SE

INTERNAL REFERENCE

±2.5V SE

±10V DIFF

±10V SE

±10V DIFF

0V TO +10V DIFF

0V TO +10V SE

±10V SE

0V TO +10V DIFF

±5V SE

±5V DIFF

±2.5V DIFF

V

= V

= 5V

CC

DRIVE

/V = ±12V

DD SS

T

= 25°C

A

±2.5V SE

f

= 500kSPS

S

INTERNAL REFERENCE

10

100

1000

10

100

1000

ANALOG INPUT FREQUENCY (kHz)

Figure 10. THD vs. Analog Input Frequency

for Single-Ended (SE) and True Differential Mode (Diff) at 3 V V_CC

Figure 13. SINAD vs. Analog Input Frequency

for Single-Ended (SE) and True Differential Mode (Diff) at 5 V V_CC

–50

–55

–50

V

= V

= 5V

CC

DRIVE

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

/V = ±12V

DD SS

T

= 25°C

= 500kSPS

A

0V TO +10V SE

f

S

V

= 3V

–60

–65

–70

–75

–80

–85

–90

–95

CC

INTERNAL REFERENCE

V

= 5V

CC

±10V SE

±10V DIFF

0V TO +10V DIFF

±5V SE

V

/V = ±12V

DD SS

±5V DIFF

SINGLE-ENDED MODE

f

= 500kSPS

S

±2.5V SE

T

= 25°C

A

50kHz ON SELECTED CHANNEL

±2.5V DIFF

0

100

200

300

400

500

600

10

100

1000

FREQUENCY OF INPUT NOISE (kHz)

ANALOG INPUT FREQUENCY (kHz)

Figure 14. Channel-to-Channel Isolation

Figure 11. THD vs. Analog Input Frequency

for Single-Ended (SE) and True Differential Mode (Diff) at 5 V V_CC

80

10k

9k

8k

7k

6k

5k

4k

3k

2k

1k

0

9469

V

= 5V

±5V DIFF

±2.5V DIFF

CC

/V = ±12V

DD SS

RANGE = ±10V

10k SAMPLES

75

±5V SE

±2.5V SE

T

= 25°C

A

0V TO +10V DIFF

70

±10V DIFF

±10V SE

0V TO +10V SE

65

60

V

= V

= 3V

CC

DRIVE

/V = ±12V

DD SS

55

50

T

f

= 25°C

= 500kSPS

A

S

228

–1

303

1

INTERNAL REFERENCE

0

2

10

100

1000

–2

0

ANALOG INPUT FREQUENCY (kHz)

CODE

Figure 12. SINAD vs. Analog Input Frequency

Figure 15. Histogram of Codes, True Differential Mode

for Single-Ended (SE) and True Differential Mode (Diff) at 3 V V_CC

Rev. B | Page 11 of 14

AD7327-EP

Enhanced Product

2.0

1.5

8k

7k

6k

5k

4k

3k

2k

1k

7600

V

= 5V

CC

/V = ±12V

DD SS

RANGE = ±10V

10k SAMPLES

1.0

T

= 25°C

A

0.5

INL = 500kSPS

0

–0.5

–1.0

–1.5

–2.0

±5V RANGE

= V

1201

–1

1165

1

V

= 5V

DRIVE

CC

INTERNAL REFERENCE

SINGLE-ENDED MODE

0

23

–2

11

2

0

3

0

5

7

9

11

13

15

17

19

–3

0

±V /V SUPPLY VOLTAGE (V)

CODE

DD SS

Figure 16. Histogram of Codes, Single-Ended Mode

Figure 19. INL Error vs. Supply Voltage at 500 kSPS

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

100mV p-p SINE WAVE ON EACH SUPPLY

NO DECOUPLING

SINGLE-ENDED MODE

f

= 500kSPS

S

V

= 5V

CC

V

= 3V

CC

V

= 5V

CC

V

= 12V

DD

V

= 3V

CC

DIFFERENTIAL MODE

V

= –12V

SS

F

= 50kHz

IN

V

/V = ±12V

DD SS

f

T

= 500kSPS

= 25°C

S

A

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

RIPPLE FREQUENCY (kHz)

SUPPLY RIPPLE FREQUENCY (kHz)

Figure 17. CMRR vs. Common-Mode Ripple Frequency

Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

2.0

–50

V

= V

= 5V

CC

DRIVE

/V = ±12V

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

DD SS

1.5

1.0

T

= 25°C

A

±10V RANGE

INTERNAL REF

RANGE = ±10V AND ±2.5V

R

= 4000Ω

= 3000Ω

= 2000Ω

= 1000Ω

= 100Ω

= 12Ω

IN

f

= 500kSPS

S

DIFFERENTIAL MODE

0.5

DNL = 500kSPS

0

±2.5V RANGE

R

= 9000Ω

= 5500Ω

= 2000Ω

= 100Ω

= 12Ω

–0.5

–1.0

–1.5

–2.0

IN

±5V RANGE

= V

INTERNAL REFERENCE

SINGLE-ENDED MODE

V

= 5V

DRIVE

CC

5

7

9

11

13

15

17

19

10

100

INPUT FREQUENCY (kHz)

1000

±V /V SUPPLY VOLTAGE (V)

DD SS

Figure 18. DNL Error vs. Supply Voltage at 500 kSPS

Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,

True Differential Mode

Rev. B | Page 12 of 14

Enhanced Product

AD7327-EP

–50

V

= V

= 5V

CC

DRIVE

/V = ±12V

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

DD SS

T

= 25°C

A

±10V RANGE

INTERNAL REF

RANGE = ±10V AND ±2.5V

R

= 4000Ω

= 2000Ω

= 1000Ω

= 100Ω

= 50Ω

IN

f

= 500kSPS

S

SINGLE-ENDED MODE

±2.5V RANGE

R

= 4700Ω

= 3000Ω

= 1000Ω

= 100Ω

= 50Ω

IN

10

100

INPUT FREQUENCY (kHz)

1000

Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,

Single-Ended Mode

Rev. B | Page 13 of 14

AD7327-EP

Enhanced Product

OUTLINE DIMENSIONS

6.60

6.50

6.40

20

11

10

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

COPLANARITY

0.10

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 23. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions show in millimeters

ORDERING GUIDE

Model¹

AD7327TRU-EP

AD7327TRU-EP-RL7

EVAL-AD7327SDZ

EVAL-SDP-CB1Z

Temperature Range

−55°C to +125°C

Package Description

20-Lead [TSSOP]

Evaluation Board

Controller Board

Package Option

RU-20

¹Z = RoHS Compliant Part

registered trademarks are the property of their respective owners.

D12481-0-9/15(B)

Rev. B | Page 14 of 14


型号：	AD7327TRU-EP-RL7
厂家：	ADI
描述：	8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20, MO-153AC, TSSOP-20 光电二极管
文件：	总14页 (文件大小：377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7327TRU-EP-RL7 [ADI]

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