AD7329BRUZ-REEL [ADI]
1 MSPS , 8-Channel, Software Selectable True Bipolar Input, 12-Bit Plus Sign A/D Converter;
| 型号： | AD7329BRUZ-REEL |
| 厂家： | 
ADI |
| 描述： | 1 MSPS , 8-Channel, Software Selectable True Bipolar Input, 12-Bit Plus Sign A/D Converter 光电二极管 转换器 |
| 文件： | 总39页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 MSPS, 8-Channel, Software-Selectable,
True Bipolar Input, 12-Bit Plus Sign ADC
Data Sheet
AD7329
FEATURES
FUNCTIONAL BLOCK DIAGRAM
MUX
+
MUX
–
OUT
REF /REF
IN OUT
ADC
–
ADC
+
V
V
CC
OUT
IN
IN
DD
12-bit plus sign SAR ADC
True bipolar input ranges
2.5V
VREF
Software-selectable input ranges
10 V, 5 V, 2.5 V, 0 V to +10 V
1 MSPS throughput rate
8 analog input channels with channel sequencer
Single-ended true differential and pseudo differential
analog input capability
V
V
V
V
V
V
0
1
2
3
4
5
IN
IN
IN
13-BIT SUCCESSIVE
APPROXIMATION
ADC
I/P
MUX
T/H
IN
IN
IN
V
V
6
7
IN
IN
DOUT
SCLK
High analog input impedance
MUXOUT and ADCIN pins allow separate access to mux and ADC
Low power: 21 mW
CONTROL
LOGIC AND
REGISTERS
CHANNEL
SEQUENCER
CS
DIN
AD7329
Temperature indicator
V
AGND
V
DRIVE
SS
Full power signal bandwidth: 20 MHz
Internal 2.5 V reference
Figure 1.
High speed serial interface
iCMOS process technology
24-lead TSSOP package
Power-down modes
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD73291 is an 8-channel, 12-bit plus sign successive
approximation ADC designed on the iCMOS™ (industrial
CMOS) process. iCMOS is a process combining high voltage
CMOS and low voltage CMOS. It enables the development of
a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no previous generation of high
voltage parts could achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can accept bipolar input
signals while providing increased performance, dramatically
reduced power consumption, and reduced package size.
1. The AD7329 can accept true bipolar analog input signals,
± 1 ꢀ V, ± ± V, ± 2 . ± V, a n d ꢀ V to + 1 ꢀ V u n ip o l ar s i g n a l s .
2. The eight analog inputs can be configured as eight single-
ended inputs, four true differential input pairs, four pseudo
differential inputs, or seven pseudo differential inputs.
3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-
compatible interface.
4. Low power, 21 mW, at 1 MSPS.
±. The MUXOUT± and ADCIN± pins allow for signal conditioning
of the mux output prior to entering the ADC.
The AD7329 can accept true bipolar analog input signals. The
AD7329 has four software-selectable input ranges: ±1ꢀ V, ±± V,
±2.± V, and ꢀ V to +1ꢀ V. Each analog input channel can be
independently programmed to one of the four input ranges.
The analog input channels on the AD7329 can be programmed
to be single-ended, true differential, or pseudo differential.
Table 1. Similar Devices
Device
Number
AD7328
AD7327
AD7324
AD7323
AD7322
AD7321
Throughput Rate
1000 kSPS
500 kSPS
Number of Channels
8
8
4
4
2
2
1000 kSPS
500 kSPS
The ADC contains a 2.± V internal reference. The AD7329 also
allows for external reference operation. If a 3 V reference is
applied to the REFIN/REFOUT pin, the AD7329 can accept a true
bipolar ±12 V analog input. The ADC has a high speed serial
interface that can operate at throughput rates up to 1 MSPS.
1000 kSPS
500 kSPS
1 Protected by U.S. Patent No. 6,731,232.
Rev. C
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AD7329* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
• AD7329 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD7329 Evaluation Board
DOCUMENTATION
Application Notes
DISCUSSIONS
View all AD7329 EngineerZone Discussions.
• AN-0972: How the AD7329 Helps Reduce Costs
Data Sheet
SAMPLE AND BUY
• AD7329: 1 MSPS, 8-Channel, Software-Selectable, True
Visit the product page to see pricing options.
Bipolar Input, 12-Bit Plus Sign ADC Data Sheet
User Guides
TECHNICAL SUPPORT
• UG-526: Evaluating the AD7329 1 MSPS, 12-Bit Plus Sign
ADC
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number.
REFERENCE MATERIALS
DOCUMENT FEEDBACK
Technical Articles
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• Maximizing Eight-Channel Data-Acquisition System
Performance Using a Single ADC Driver
• MS-2210: Designing Power Supplies for High Speed ADC
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AD7329
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Addressing Registers.................................................................. 25
Control Register ......................................................................... 26
Sequence Register....................................................................... 28
Range Registers........................................................................... 28
Sequencer Operation ..................................................................... 29
Reference ..................................................................................... 31
VDRIVE ............................................................................................ 31
Temperature Indicator............................................................... 31
Modes of Operation ....................................................................... 32
Normal Mode (PM1 = PM0 = 0) ............................................. 32
Full Shutdown Mode (PM1 = PM0 = 1) ................................. 32
Autoshutdown Mode (PM1 = 1, PM0 = 0)............................. 33
Autostandby Mode (PM1 = 0, PM0 =1) ................................. 33
Power vs. Throughput Rate....................................................... 34
Serial Interface ................................................................................ 35
Microprocessor Interfacing........................................................... 36
AD7329 to ADSP-21xx.............................................................. 36
AD7329 to ADSP-BF53x........................................................... 36
Applications Information.............................................................. 37
Layout and Grounding .............................................................. 37
Power Supply Configuration .................................................... 37
Outline Dimensions....................................................................... 38
Ordering Guide .......................................................................... 38
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 17
Circuit Information.................................................................... 17
Converter Operation.................................................................. 17
Output Coding............................................................................ 18
Transfer Functions...................................................................... 18
Analog Input Structure.............................................................. 18
Track-and-Hold Section............................................................ 19
Typical Connection Diagram ................................................... 20
Analog Input ............................................................................... 20
Driver Amplifier Choice............................................................ 23
Registers........................................................................................... 25
REVISION HISTORY
12/14—Rev. B to Rev. C
2/10—Rev. 0 to Rev. A
Change to Specifications Section.................................................... 3
Change to Timing Specifications Section...................................... 7
Changes to Table 5.......................................................................... 10
Changes to Pseudo Differential Inputs Section.......................... 22
Changes to DC Accuracy Parameter, Test Conditions/
Comments, Table 2............................................................................4
Change to Normal Mode (Operational) ICC and IDRIVE
Parameter and to Power Dissipation Normal Mode
Parameter, Table 2 .............................................................................6
Changes to Table 16 and Table 17 ................................................ 36
Added Applications Information Section, Figure 60,
and Table 18 .................................................................................... 37
Changes to Ordering Guide.......................................................... 38
1/14—Rev. A to Rev. B
Changes to Circuit Information Section and Table 6 ................ 17
Changes to Addressing Registers Section.................................... 25
Changes to Power Supply Configuration Section ...................... 37
Changes to Ordering Guide .......................................................... 38
4/06—Revision 0: Initial Version
Rev. C | Page 2 of 38
Data Sheet
AD7329
SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, fSCLK = 20 MHz,
fS = 1 MSPS, TA = TMAX to TMIN, unless otherwise noted. MUXOUT+ is connected directly to ADCIN+ and MUXOUT− is connected directly to
ADCIN−, which is connected to AGND for single-ended mode.
Table 2.
B Version
Typ
Parameter1
Min
Max
Unit
Test Conditions/Comments
fIN = 50 kHz sine wave
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
76
72.5
75
77
74
76.5
dB
dB
dB
Differential mode
Single-ended/pseudo differential mode
Differential mode; 2.5 V and 5 V ranges
Signal-to-Noise and Distortion
(SINAD)2
76.5
73.5
dB
dB
Differential mode; 0 V to +10 V and 10 V ranges
Single-ended/pseudo differential mode; 2.5 V and
5 V ranges
72
73.5
dB
Single-ended/pseudo differential mode; 0 V to +10 V
and 10 V ranges
Total Harmonic Distortion (THD)2
−87
−85
−82
−80
−77
dB
dB
dB
Differential mode; 2.5 V and 5 V ranges
Differential mode; 0 V to +10 V and 10 V ranges
Single-ended/pseudo differential mode; 2.5 V and
5 V ranges
−80
−88
dB
dB
Single-ended/pseudo differential mode; 0 V to +10 V
and 10 V ranges
Differential mode; 2.5 V and 5 V ranges
Peak Harmonic or Spurious
Noise (SFDR)2
−80
−78
−86
−84
dB
dB
Differential mode; 0 V to +10 V and 10 V ranges
Single-ended/pseudo differential mode; 2.5 V and
5 V ranges
−82
dB
Single-ended/pseudo differential mode; 0 V to +10 V
and 10 V ranges
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
fa = 50 kHz, fb = 30 kHz
−88
−90
7
50
−79
dB
dB
ns
ps
dB
Aperture Delay3
Aperture Jitter3
Common-Mode Rejection
Up to 100 kHz ripple frequency; see Figure 17
(CMRR)2
Channel-to-Channel Isolation2
Full Power Bandwidth
−75
dB
fIN on unselected channels up to 100 kHz;
see Figure 14
At 3 dB
20
1.5
MHz
MHz
At 0.1 dB
Rev. C | Page 3 of 38
AD7329
Data Sheet
B Version
Typ
Parameter1
DC ACCURACY4
Min
Max
Unit
Test Conditions/Comments
All dc accuracy specifications are typical for 0 V to 10 V
mode
Single-ended/pseudo differential mode 1 LSB =
FSR/4096, unless otherwise noted
Differential mode 1 LSB = FSR/8192, unless otherwise
noted
Resolution
No Missing Codes
13
12-bit
Bits
Bits
Differential mode
plus sign
(13 bits)
11-bit
Bits
Single-ended/pseudo differential mode
plus sign
(12 bits)
Integral Nonlinearity2
1.1
1
LSB
LSB
LSB
Differential mode
Single-ended/pseudo differential mode
Single-ended/pseudo differential mode
(LSB = FSR/8192)
−0.7/+1.2
−0.7/+1
Differential Nonlinearity2
−0.9/+1.5 LSB
Differential mode; guaranteed no missing codes to
13 bits
Single-ended mode; guaranteed no missing codes to
12 bits
Single-ended/pseudo differential mode
(LSB = FSR/8192)
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
0.9
LSB
LSB
Offset Error2, 5
−4/+9
−7/+10
0.6
0.5
8.0
14
0.5
0.5
4
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Offset Error Match2, 5
Gain Error2, 5
Gain Error Match2, 5
Positive Full-Scale Error2, 6
Positive Full-Scale Error Match2, 6
Bipolar Zero Code Error2, 6
Bipolar Zero Code Error Match2, 6
Negative Full-Scale Error2, 6
Negative Full-Scale Error Match2, 6
7
0.5
0.5
8.5
7.5
0.5
0.5
4
6
0.5
0.5
Single-ended/pseudo differential mode
Differential mode
Rev. C | Page 4 of 38
Data Sheet
AD7329
B Version
Typ
Parameter1
Min
Max
Unit
Test Conditions/Comments
ANALOG INPUT
Input Voltage Ranges
Reference = 2.5 V; see Table 6
(Programmed via Range
Register)
10
V
VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V
5
2.5
0 to 10
V
V
V
VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V
VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V
VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V
Pseudo Differential VIN−
Input Range
VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 43 and
Figure 44
3.5
6
5
V
V
V
V
Reference = 2.5 V; range = 10 V
Reference = 2.5 V; range = 5 V
Reference = 2.5 V; range = 2.5 V
Reference = 2.5 V; range = 0 V to +10 V
VIN = VDD or VSS
+3/−5
DC Leakage Current
100
nA
nA
pF
pF
pF
pF
pF
pF
pF
pF
3
Per channel, VIN = VDD or VSS
Input Capacitance3
ADCIN Capacitance3
16
7
When in track, all ranges, single ended
When in track, 10 V range, single ended
When in track, 5 V range, single ended
When in track, 2.5 V range, single ended
When in track, 0 V to +10 V range, single ended
When in hold, all ranges, single ended
All ranges, single ended
10
14.5
10.5
4.0
7.5
13
MUXOUT− Capacitance3
MUXOUT+ Capacitance3
REFERENCE INPUT/OUTPUT
Input Voltage Range
Input DC Leakage Current
Input Capacitance
All ranges, single ended
2.5
3
1
V
µA
pF
V
10
2.5
Reference Output Voltage
Reference Output Voltage Error
at 25°C
Reference Output Voltage
5
10
25
mV
mV
TMIN to TMAX
Reference Temperature
Coefficient
ppm/°C
3
7
ppm/°C
Ω
Reference Output Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
V
V
V
µA
pF
0.8
0.4
1
VCC = 4.75 V to 5.25 V
VCC = 2.7 to 3.6 V
VIN = 0 V or VDRIVE
Input Current, IIN
3
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
VDRIVE
0.2 V
−
V
ISOURCE = 200 µA
ISINK = 200 µA
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output
Capacitance3
0.4
1
V
µA
pF
5
Output Coding
Straight natural binary
Twos complement
Coding bit set to 1 in control register
Coding bit set to 0 in control register
Rev. C | Page 5 of 38
AD7329
Data Sheet
B Version
Typ
Parameter1
Min
Max
Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition
Time2, 3
800
300
ns
ns
16 SCLK cycles with SCLK = 20 MHz
Full-scale step input; see the Terminology section
Throughput Rate
1
770
MSPS
kSPS
VCC = 4.75 V to 5.25 V; see the Serial Interface section
VCC < 4.75 V
POWER REQUIREMENTS
VDD
VSS
VCC
Digital inputs = 0 V or VDRIVE
See Table 6
See Table 6
12
16.5
−16.5
5.25
5.25
V
V
V
V
−12
2.7
2.7
See Table 6; typical specifications for VCC < 4.75 V
VDRIVE
Normal Mode (Static)
Normal Mode (Operational)
0.9
mA
VDD= 16.5, VSS = −16.5 V, VCC = VDRIVE = 5.25 V
fS = 1 MSPS
IDD
ISS
360
410
3.4
µA
µA
mA
VDD = 16.5 V
VSS = −16.5 V
VCC = VDRIVE = 5.25 V
fS = 250 kSPS
ICC and IDRIVE
Autostandby Mode (Dynamic)
IDD
ISS
200
210
1.3
µA
µA
mA
VDD = 16.5 V
VSS = −16.5 V
VCC = VDRIVE = 5.25 V
SCLK on or off
ICC and IDRIVE
Autoshutdown Mode (Static)
IDD
ISS
1
1
1
µA
µA
µA
VDD = 16.5 V
VSS = −16.5 V
VCC = VDRIVE = 5.25 V
SCLK on or off
VDD = 16.5 V
ICC and IDRIVE
Full Shutdown Mode
IDD
1
1
1
µA
µA
µA
ISS
VSS = −16.5 V
VCC = VDRIVE = 5.25 V
ICC and IDRIVE
POWER DISSIPATION
Normal Mode (Operational)
31
mW
mW
µW
VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
VDD = 12 V, VSS = −12 V, VCC = 5 V
VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
21
Full Shutdown Mode
38.25
1 Temperature range is −40°C to +85°C.
2 See the Terminology section.
3 Sample tested during initial release to ensure compliance.
4 For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless
otherwise noted.
5 Unipolar 0 V to 10 V range with straight binary output coding.
6 Bipolar range with twos complement output coding.
Rev. C | Page 6 of 38
Data Sheet
AD7329
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMAX to
MIN. Timing specifications apply with a 32 pF load, unless otherwise noted. MUXOUT+ is connected directly to ADCIN+ and MUXOUT− is
T
connected directly to ADCIN−, which is connected to AGND for single-ended mode.
Table 3.
Limit at TMIN, TMAX
Description
VDRIVE ≤ VCC
Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit
fSCLK
50
14
16 × tSCLK
75
50
20
16 × tSCLK
60
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
µs max
tCONVERT
tQUIET
t1
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
12
5
1
t2
25
20
CS to SCLK setup time; bipolar input ranges ( 10 V, 5 V, 2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
45
26
35
14
t3
t4
t5
t6
t7
t8
57
0.4 × tSCLK
0.4 × tSCLK
13
40
10
4
2
750
500
43
0.4 × tSCLK
0.4 × tSCLK
8
22
9
4
2
750
500
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power-up from autostandby
t9
t10
tPOWER-UP
Power-up from full shutdown/autoshutdown mode, internal
reference
25
25
µs typ
Power-up from full shutdown/autoshutdown mode, external
reference
1 When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark-space ratio must be limited to 50:50.
t1
CS
tCONVERT
t2
t6
1
2
3
4
5
13
14
t5
15
16
SCLK
DOUT
3 IDENTIFICATION BITS
t3
t7
t8
t4
tQUIET
ADD1
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
ADD2
THREE-STATE
t10
t9
REG
SEL1
REG
SEL2
WRITE
MSB
LSB
0
DIN
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 7 of 38
AD7329
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameter
Rating
VDD to AGND, DGND
VSS to AGND, DGND
VDD to VCC
VCC to AGND, DGND
VDRIVE to AGND, DGND
AGND to DGND
Analog Input Voltage to AGND1
Digital Input Voltage to DGND
Digital Output Voltage to GND
REFIN to AGND
Input Current to Any Pin
Except Supplies2
−0.3 V to +16.5 V
+0.3 V to −16.5 V
VCC − 0.3 V to +16.5 V
−0.3 V to +7 V
ESD CAUTION
−0.3 V to +7 V
−0.3 V to +0.3 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VCC + 0.3 V
10 mA
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
−40°C to +85°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Pb-Free Temperature, Soldering
Reflow
128°C/W
42°C/W
260(0)°C
2.5 kV
ESD
1 If the analog inputs are driven from alternative VDD and VSS supply circuitry,
Schottky diodes should be placed in series with the VDD and VSS supplies of
the AD7329 (see the Power Supply Configuration section).
2 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. C | Page 8 of 38
Data Sheet
AD7329
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
24
23
22
21
20
19
18
17
16
15
14
13
CS
SCLK
DGND
DOUT
2
DIN
3
DGND
AGND
4
V
V
V
DRIVE
CC
AD7329
TOP VIEW
(Not to Scale)
5
REF /REF
IN
OUT
6
V
SS
DD
7
ADC
+
+
ADC
MUX
–
IN
IN
8
MUX
–
OUT
OUT
9
V
V
V
V
0
1
4
5
V
V
V
V
2
3
6
7
IN
IN
IN
IN
IN
IN
IN
IN
10
11
12
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Descriptions
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7329 and frames the serial data transfer.
2
DIN
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register
on the falling edge of SCLK (see the Registers section).
3, 23
4
DGND
AGND
Digital Ground. Ground reference point for all digital circuitry on the AD7329. Ideally, the DGND and AGND
voltages are at the same potential and must not be more than 0.3 V apart, even on a transient basis.
Analog Ground. Ground reference point for all analog circuitry on the AD7329. All analog input signals and
any external reference signal must be referred to this AGND voltage. Ideally, the AGND and DGND voltages
are at the same potential and must not be more than 0.3 V apart, even on a transient basis.
5
REFIN/REFOUT Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7329.
The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor must be placed
on the reference pin. Alternatively, the internal reference can be disabled and an external reference can be
applied to this input. On power-up, the external reference mode is the default condition (see the Reference
section).
6
7
VSS
ADCIN+
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
Positive ADC Input. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still
a high voltage signal ( 10 V, 5 V, 2.5 V, or 0 V to +10 V).
8
MUXOUT
+
Positive Multiplexer Output. The output of the multiplexer appears at this pin. The voltage at this pin is still a
high voltage signal equivalent to the voltage applied to the VIN+ input channel, as selected in the control
register or sequence register. If no external filtering or buffering is required, tie this pin to the ADCIN+ pin.
9, 10, 16, 15, VIN0 to VIN7
11, 12, 14, 13
Analog Input 0 Through Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the channel address bits, ADD2
through ADD0, in the control register. The inputs can be configured as eight single-ended inputs, four true
differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration
of the analog inputs is selected by programming the mode bits, Mode 1 and Mode 0, in the control register.
The input range on each input channel is controlled by programming the range registers. Input ranges of
10 V, 5 V, 2.5 V, or 0 V to +10 V can be selected on each analog input channel (see the Range Registers
section). On power-up, VIN0 is automatically selected and the voltage on this pin appears on MUXOUT+.
17
18
MUXOUT
−
Negative Multiplexer Output. This pin allows access to the on-chip track-and-hold. The voltage applied to this
pin is still a high voltage signal when the AD7329 is in differential mode. In single-ended mode, this pin can
either be left floating or tied to AGND. When the AD7329 is in pseudo differential mode, a small dc voltage
appears at this pin, and this pin is tied to the ADCIN− pin.
Negative ADC Input. This pin allows access to the track-and-hold. When the AD7329 is in single-ended mode,
tie this pin to AGND. When the AD7329 is in pseudo differential mode, connect this pin to MUXOUT−. When
the AD7329 is in true differential mode, the voltage applied to this pin is a high voltage signal ( 10 V, 5 V,
2.5 V, or 0 V to +10 V).
ADCIN−
19
20
VDD
VCC
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7329. Decouple
this supply to AGND.
Rev. C | Page 9 of 38
AD7329
Data Sheet
Pin No.
Mnemonic
Descriptions
21
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Decouple this pin to DGND. The voltage at this pin can be different than that at VCC but must not exceed VCC
by more than 0.3 V.
22
24
DOUT
SCLK
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data
stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is
provided MSB first (see the Serial Interface section).
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7329.
This clock is also used as the clock source for the conversion process.
Rev. C | Page 10 of 38
Data Sheet
AD7329
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0
V
= V
DRIVE
= 5V
INT/EXT 2.5V REFERENCE
±10V RANGE
CC
= 25°C
4096 POINT FFT
T
A
V
V
= V = 5V
= 15V, V = –15V
SS
= 25°C
CC
DRIVE
V
= 15V, V = –15V +INL = +0.55LSB
DD
SS
–20
–40
DD
–INL = –0.68LSB
0.6
T
A
INT/EXT 2.5V REFERENCE
±10V RANGE
0.4
fIN = 50kHz
SNR = 77.30dB
0.2
–60
SINAD = 76.85dB
THD = –86.96dB
SFDR = –88.22dB
0
–80
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–120
–140
0
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
0
0
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
512 1536
2560
4608
5632
6656
7680
Figure 7. Typical INL for True Differential Mode
Figure 4. FFT for True Differential Mode
1.0
0.8
0
–20
4096 POINT FFT
V
V
= V = 5V
= 15V, V = –15V
SS
CC
DRIVE
DD
0.6
T
= 25°C
A
INT/EXT 2.5V REFERENCE
±10V RANGE
fIN = 50kHz
SNR = 74.67dB
SINAD = 74.03dB
THD = –82.68dB
SFDR = –85.40dB
0.4
–40
0.2
–60
0
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–100
–120
–140
V
T
V
= V
DRIVE
= 5V
±10V RANGE
+DNL = +0.79LSB
–DNL = –0.38LSB
CC
= 25°C
A
= 15V, V = –15V
DD
INT/EXT 2.5V REFERENCE
SS
0
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
512 1536
2560
4608
5632
6656
7680
Figure 8. Typical DNL for Single-Ended Mode
Figure 5. FFT for Single-Ended Mode
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
V
T
= V = 5V
DRIVE
V
T
= V = 5V
DRIVE
CC
= 25°C
CC
= 25°C
A
A
V
= 15V, V = –15V
V
= 15V, V = –15V
DD
SS
DD
SS
INT/EXT 2.5V REFERENCE
±10V RANGE
+INL = +0.87LSB
–INL = –0.49LSB
INT/EXT 2.5V REFERENCE
±10V RANGE
+DNL = +0.72LSB
–DNL = –0.22LSB
0
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
7680
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
512 1536
2560
4608
5632
6656
512
1536 2560
4608
5632
6656
7680
Figure 9. Typical INL for Single-Ended Mode
Figure 6. Typical DNL for True Differential Mode
Rev. C | Page 11 of 38
AD7329
Data Sheet
–50
80
75
70
65
60
55
50
V
V
T
= V = 5V
DRIVE
CC
DD
= 12V, V = –12V
SS
–55
–60
–65
–70
–75
–80
–85
–90
–95
= 25°C
fSA= 1MSPS
±2.5V RANGE
±5V RANGE
INTERNAL REFERENCE
AD8021 BETWEEN MUX
OUT+
±10V RANGE
AND ADC
PINS
IN+
±10V RANGE
±5V RANGE
0V TO +10V RANGE
0V TO +10V RANGE
V
V
T
= V = 5V
DRIVE
CC
DD
= 12V, V = –12V
SS
= 25°C
fSA= 1MSPS
±2.5V RANGE
INTERNAL REFERENCE
AD8021 BETWEEN MUX
OUT
AND ADC PINS
IN
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
Figure 10. THD vs. Analog Input Frequency for Single-Ended Mode at 5 V VCC
Figure 13. SINAD vs. Analog Input Frequency for True Differential Mode at 5 V VCC
–50
–50
–55
V
V
T
= V = 5V
DRIVE
CC
DD
= 12V, V = –12V
SS
±10V RANGE
±5V RANGE
–55
–60
–65
–70
–75
–80
–85
–90
–95
= 25°C
fSA= 1MSPS
WIRE LINK
–60
INTERNAL REFERENCE
AD8021 BETWEEN MUX
AND ADC PINS
OUT
–65
–70
–75
–80
–85
–90
–95
–100
WITH AD8021
IN
0V TO +10V RANGE
±2.5V RANGE
V
V
= 12V, V = –12V
SS
DD
CC
= V
= 5V
DRIVE
SINGLE-ENDED MODE
50kHz ON SELECTED CHANNEL
fS = 1MSPS
T
= 25°C
A
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
0
100
200
300
400
500
600
FREQUENCY OF INPUT NOISE (kHz)
Figure 11. THD vs. Analog Input Frequency for True Differential Mode at 5 V VCC
Figure 14. Channel-to-Channel Isolation with and Without AD8021 Between
the MUXOUT+ and ADCIN+ Pins
74
10k
9469
V
V
= 5V
CC
9k
8k
7k
6k
5k
4k
3k
2k
1k
0
= 12V, V = –12V
DD
SS
73
RANGE = ±10V
10k SAMPLES
±2.5V RANGE
±5V RANGE
72
71
70
69
68
67
66
T
= 25°C
A
0V TO +10V RANGE
±10V RANGE
V
V
T
= V = 5V
DRIVE
CC
DD
= 12V, V = –12V
SS
= 25°C
fSA= 1MSPS
INTERNAL REFERENCE
AD8021 BETWEEN MUX
OUT+
228
–1
303
1
0
0
2
AND ADC
PINS
IN+
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
–2
0
CODE
Figure 12. SINAD vs. Analog Input Frequency for Single-Ended Mode at 5 V VCC
Figure 15. Histogram of Codes, True Differential Mode
Rev. C | Page 12 of 38
Data Sheet
AD7329
2.0
1.5
8k
7k
6k
5k
4k
3k
2k
1k
7600
V
V
= 5V
CC
DD
= 12V, V = –12V
SS
INL = 1MSPS
RANGE = ±10V
10k SAMPLES
1.0
T
= 25°C
A
0.5
INL = 500kSPS
INL = 500kSPS
0
–0.5
–1.0
–1.5
–2.0
INL = 1MSPS
±5V RANGE
= V
V
= 5V
DRIVE
CC
INTERNAL REFERENCE
SINGLE-ENDED MODE
AD8021 BETWEEN MUX
1201
–1
1165
1
+
OUT
AND ADC + PINS
IN
0
23
–2
11
2
0
3
0
±5
±7
±9
±11
±13
±15
±17
±19
–3
0
SUPPLY VOLTAGE (V) (V = +, V = –)
DD SS
CODE
Figure 19. INL Error vs. Supply Voltage at 500 kSPS and 1 MSPS
Figure 16. Histogram of Codes, Single-Ended Mode
–50
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
100mV p-p SINE WAVE ON EACH SUPPLY
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
NO DECOUPLING
SINGLE-ENDED MODE
f
= 1MSPS
S
V
= 5V
CC
V
V
= 3V
CC
V
= 5V
CC
= 12V
DD
V
= 3V
CC
DIFFERENTIAL MODE
fIN = 50kHz
V
= –12V
SS
V
= 12V, V = –12V
SS
fSD=D 1MSPS
T
= 25°C
A
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
SUPPLY RIPPLE FREQUENCY (kHz)
RIPPLE FREQUENCY (kHz)
Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
Figure 17. CMRR vs. Common-Mode Ripple Frequency
2.0
1.5
–50
DIFFERENTIAL MODE
V
V
= 12V, V = –12V
DD
CC
SS
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
= V
DRIVE
= 5V
INTERNAL REFERENCE
AD8021 BETWEEN MUX
±10V RANGE
DNL = 500kSPS
OUT
1.0
R
R
R
R
R
= 2000Ω
= 1000Ω
= 600Ω
= 100Ω
= 50Ω
IN
IN
IN
IN
IN
AND ADC PINS
IN
0.5
DNL = 1MSPS
DNL = 1MSPS
0
–0.5
–1.0
–1.5
–2.0
±2.5V RANGE
R
R
R
R
R
= 4000Ω
= 1000Ω
= 600Ω
= 100Ω
= 50Ω
±5V RANGE
IN
IN
IN
IN
IN
DNL = 500kSPS
V
= V = 5V
CC
DRIVE
INTERNAL REFERENCE
SINGLE-ENDED MODE
AD8021 BETWEEN MUX
+
OUT
AND ADC + PINS
IN
±5
±7
±9
±11
±13
±15
±17
±19
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
SUPPLY VOLTAGE (V) (V = +, V = –)
DD SS
Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,
True Differential Mode
Figure 18. DNL Error vs. Supply Voltage at 500 kSPS and 1 MSPS
Rev. C | Page 13 of 38
AD7329
Data Sheet
–76
–78
–80
–82
–84
–86
–88
–50
±5V RANGE
= V
INTERNAL REFERENCE
SINGLE-ENDED MODE
AD8021 BETWEEN MUX
SINGLE-ENDED MODE
V
= 5V
DRIVE
CC
V
V
= 12V, V = –12V
= V = 5V
DRIVE
DD
CC
SS
–55
–60
–65
–70
–75
–80
–85
–90
INTERNAL REFERENCE
AD8021 BETWEEN MUX
+
OUT
±10V RANGE
+
OUT
AND ADC + PINS
IN
AND ADC + PINS
R
R
R
R
R
= 2000Ω
IN
IN
IN
IN
IN
IN
= 1000Ω
= 600Ω
= 100Ω
= 50Ω
30kHz/500kSPS
30kHz/1MSPS
10kHz/1MSPS
±2.5V RANGE
R
R
R
R
R
= 2000Ω
= 1000Ω
= 600Ω
= 100Ω
= 50Ω
IN
IN
IN
IN
IN
10kHz/500kSPS
±7
±5
±9
±11
±13
±15
±17
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
SUPPLY VOLTAGE (V) (V = +, V = –)
DD SS
Figure 23. THD vs. Supply Voltage at 500 kSPS and 1 MSPS
with 10 kHz and 30 kHz Input Tone
Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,
Single-Ended Mode
Rev. C | Page 14 of 38
Data Sheet
AD7329
TERMINOLOGY
Negative Full-Scale Error
Differential Nonlinearity
This applies when using twos complement output coding and
any of the bipolar analog input ranges. This is the deviation of
the first code transition (10 … 000) to (10 … 001) from the ideal
(that is, −4 × VREF + 1 LSB, −2 × VREF + 1 LSB, −VREF + 1 LSB)
after adjusting for the bipolar zero code error.
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB
above the last code transition).
Negative Full-Scale Error Match
This is the difference in negative full-scale error between any
two input channels.
Track-and-Hold Acquisition Time
Offset Error
The track-and-hold amplifier returns to track mode after the
14th SCLK rising edge. Track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ½ LSB, after the end of a conversion.
This applies to straight binary output coding. It is the deviation
of the first code transition (00 ... 000) to (00 ... 001) from the
ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two input
channels.
Signal-to-Noise-and-Distortion Ratio
This is the measured ratio of signal to (noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process. The more levels, the smaller the quantization noise.
Theoretically, the signal-to-noise-and-distortion ratio for an
ideal N-bit converter with a sine wave input is given by
Gain Error
This applies to straight binary output coding. It is the deviation
of the last code transition (111 ... 110) to (111 ... 111) from the
ideal (that is, 4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB)
after adjusting for the offset error.
Gain Error Match
This is the difference in gain error between any two input
channels.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
For a 13-bit converter, this is 80.02 dB.
Bipolar Zero Code Error
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7329, it is defined as
This applies when using twos complement output coding and a
bipolar analog input. It is the deviation of the midscale transition
(all 1s to all 0s) from the ideal input voltage, that is, AGND − 1 LSB.
2
2
2
2
2
Bipolar Zero Code Error Match
This refers to the difference in bipolar zero code error between
any two input channels.
V2 + V3 + V4 + V5 + V6
THD (dB) = 20 log
V1
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Positive Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. It is the deviation of the
last code transition (011 … 110) to (011 … 111) from the ideal
(that is, 4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after
adjusting for the bipolar zero code error.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, the
largest harmonic could be a noise peak.
Positive Full-Scale Error Match
This is the difference in positive full-scale error between any
two input channels.
Rev. C | Page 15 of 38
AD7329
Data Sheet
Channel-to-Channel Isolation
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
per the THD specification, where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of
the sum of the fundamentals expressed in decibels.
Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale,
100 kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a 50 kHz signal. Figure 14 shows the
worst case across all eight channels for the AD7329. The analog
input range is programmed to be 2.5 V on the selected channel
and 10 V on all other channels.
Power Supply Rejection (PSR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value (see the
Typical Performance Characteristics section).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to 0. For example,
the second-order terms include (fa + fb) and (fa − fb), whereas
the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb),
and (fa − 2fb).
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV sine wave
applied to the common-mode voltage of the VIN+ and VIN−
frequency, fS, as
CMRR (dB) = 10 log (Pf/PfS)
The AD7329 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, whereas the third-order
where Pf is the power at frequency f in the ADC output, and PfS
is the power at frequency fS in the ADC output (see Figure 17).
Rev. C | Page 16 of 38
Data Sheet
AD7329
THEORY OF OPERATION
The analog inputs can be configured as eight single-ended inputs,
four true differential input pairs, four pseudo differential inputs, or
seven pseudo differential inputs. Selection can be made by program-
ming the mode bits, Mode 0 and Mode 1, in the control register.
CIRCUIT INFORMATION
The AD7329 is a fast, 8-channel, 12-bit plus sign, bipolar input,
serial ADC. The AD7329 can accept bipolar input ranges that
include 10 V, 5 V, and 2.5 V; it can also accept a 0 V to +10 V
unipolar input range. A different analog input range can be
programmed on each analog input channel via the on-chip
registers. The AD7329 has a high speed serial interface that
can operate at throughput rates up to 1 MSPS.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
AD7329 has an on-chip 2.5 V reference. However, the AD7329
can also work with an external reference. On power-up, the
external reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal
reference operation.
The AD7329 requires VDD and VSS dual supplies for the high
voltage analog input structures. These supplies must be equal to
or greater than the analog input range. See Table 6 for the
requirements of these supplies for each analog input range. The
AD7329 requires a low voltage 2.7 V to 5.25 V VCC supply to
power the ADC core.
The AD7329 also features power-down options to allow power
savings between conversions. The power-down modes are
selected by programming the on-chip control register as
described in the Modes of Operation section.
Table 6. Reference and Supply Requirements for Each
Analog Input Range
Selected
CONVERTER OPERATION
The AD7329 is a successive approximation analog-to-digital
converter built around two capacitive DACs. Figure 24 and
Figure 25 show simplified schematics of the ADC in single-
ended mode during the acquisition and conversion phases,
respectively. Figure 26 and Figure 27 show simplified
schematics of the ADC in differential mode during acquisition
and conversion phases, respectively. In both examples, the
MUXOUT+ pin is connected to the ADCIN+ pin, and the
MUXOUT− pin is connected to the ADCIN− pin. The ADC is
composed of control logic, a SAR, and capacitive DACs. In
Figure 24 (the acquisition phase), SW2 is closed and SW1 is in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor array acquires the signal on the input.
Analog
Input
Full-Scale
Input
Reference
Minimum
VDD/VSS (V)1
Range (V) Voltage (V) Range (V) VCC (V)
10
5
2.5
3.0
2.5
3.0
2.5
3.0
2.5
3.0
10
12
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
10
12
5
6
5
6
2.5
2.5
3
5
5
0 to +10
0 to +10
0 to +12
+10/AGND
+12/AGND
1 Guaranteed performance for VDD = 12 V to 16.5 V and VSS = −12 V to −16.5 V.
The performance specifications are guaranteed for VDD = 12 V
to 16.5 V and VSS = −12 V to −16.5 V. With VDD and VSS supplies
outside this range, the AD7329 is fully functional but performance
is not guaranteed. When the AD7329 is configured with the
minimum VDD and VSS supplies for a chosen analog input range,
the throughput rate should be decreased from the maximum
throughput range (see the Typical Performance Characteristics
section). Figure 18 and Figure 19 show the change in INL and
DNL as the VDD and VSS voltages are varied. When operating at
the maximum throughput rate, as the VDD and VSS supply voltages
are reduced, the INL and DNL error increases. However, as the
throughput rate is reduced with the minimum VDD and VSS
supplies, the INL and DNL error is reduced.
CAPACITIVE
DAC
COMPARATOR
C
S
B
A
V
0
IN
CONTROL
LOGIC
SW1
SW2
AGND
Figure 24. ADC Configuration During Acquisition Phase, Single-Ended Mode
When the ADC starts a conversion (Figure 25), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 23 shows the change in THD as the VDD and VSS supplies
are reduced. At the maximum throughput rate, the THD degrades
significantly as VDD and VSS are reduced. It is therefore necessary to
reduce the throughput rate when using minimum VDD and VSS
supplies so that there is less degradation of THD and the specified
performance can be maintained. The degradation is due to an
increase in the on resistance of the input multiplexer when the
CAPACITIVE
DAC
COMPARATOR
C
S
B
A
V
0
IN
CONTROL
LOGIC
SW1
SW2
V
DD and VSS supplies are reduced.
AGND
Figure 25. ADC Configuration During Conversion Phase, Single-Ended Mode
Rev. C | Page 17 of 38
AD7329
Data Sheet
Figure 26 shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (see Figure 27). The output
impedances of the source driving the VIN+ and VIN− pins must
match; otherwise, the two inputs have different settling times,
resulting in errors.
The ideal transfer characteristic for the AD7329 when twos
complement coding is selected is shown in Figure 28. The ideal
transfer characteristic for the AD7329 when straight binary
coding is selected is shown in Figure 29.
011 ... 111
011 ... 110
CAPACITIVE
DAC
COMPARATOR
000 ... 001
000 ... 000
111 ... 111
C
S
B
V
V
+
IN
A
A
SW1
SW2
CONTROL
LOGIC
SW3
–
IN
B
C
S
100 ... 010
100 ... 001
100 ... 000
AGND – 1LSB
V
REF
CAPACITIVE
DAC
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
Figure 26. ADC Configuration During Acquisition Phase, Differential Mode
ANALOG INPUT
Figure 28. Twos Complement Transfer Characteristic, Bipolar Ranges
CAPACITIVE
DAC
111 ... 111
111 ... 110
COMPARATOR
C
S
B
V
V
+
IN
A
A
SW1
SW2
CONTROL
LOGIC
SW3
111 ... 000
011 ... 111
–
IN
B
C
S
V
REF
CAPACITIVE
DAC
000 ... 010
000 ... 001
000 ... 000
Figure 27. ADC Configuration During Conversion Phase, Differential Mode
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
OUTPUT CODING
ANALOG INPUT
The AD7329 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When
operating in sequence mode, the output coding for each
channel in the sequence is the value written to the coding bit
during the last write to the control register.
Figure 29. Straight Binary Transfer Characteristic, Bipolar Ranges
ANALOG INPUT STRUCTURE
The analog inputs of the AD7329 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits, as shown in Table 12. The AD7329 can accept
true bipolar input signals. On power-up, the analog inputs operate
as eight single-ended analog input channels. If true differential
or pseudo differential is required, a write to the control register
is necessary after power-up to change this configuration.
TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
Figure 30 shows the equivalent analog input circuit of the
AD7329 in single-ended mode. Figure 31 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
Table 7. LSB Sizes for Each Analog Input Range
Input Range
Full-Scale Range/8192 Codes
LSB Size
2.441 mV
1.22 mV
ꢀ.61 mV
1.22 mV
±1ꢀ V
±± V
±2.± V
ꢀ V to +1ꢀ V
2ꢀ V
1ꢀ V
± V
V
DD
MUX
+
ADC +
IN
OUT
D
C2
R1
V
0
IN
1ꢀ V
C1
C3
C4
D
V
SS
Figure 30. Equivalent Analog Input Circuit, Single-Ended Mode
Rev. C | Page 18 of 38
Data Sheet
AD7329
V
DD
For the AD7329, the value of R includes the on resistance of the
input multiplexer and is typically 300 Ω. RSOURCE should include
any extra source impedance on the analog input.
The AD7329 enters track mode on the 14th SCLK rising edge.
When the AD7329 is run at a throughput rate of 1 MSPS with
a 20 MHz SCLK signal, the ADC has approximately 1.5 SCLK
periods plus t8 and the quiet time, tQUIET, to acquire the analog
MUX
+
ADC
+
IN
OUT
D
C2
R1
V
+
IN
C1
C3
C4
D
V
SS
V
DD
MUX
–
ADC
–
IN
OUT
D
C2
R1
CS
input signal. The ADC goes back into hold mode on the
falling edge.
V
–
IN
C1
C3
C4
D
The current required to drive the ADC is extremely small when
using the external op amp between the MUXOUT and ADCIN
pins. This is due to the high input impedance of the op amp
placed between the MUXOUT and ADCIN pins. This can be seen
in Figure 32, where the current required to drive the AD7329
input is <0.2 μA when AD8021 is placed between the MUXOUT
and ADCIN pins.
V
SS
Figure 31. Equivalent Analog Input Circuit, Differential Mode
Care should be taken to ensure that the analog input does not
exceed the VDD and VSS supply rails by more than 300 mV.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the VDD supply rail or
the VSS supply rail. These diodes can conduct up to 10 mA
without causing irreversible damage to the part.
0.20
0.19
0.18
0.17
In Figure 30 and Figure 31, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
V
V
= 12V, V = –12V
SS
DD
CC
0.16
0.15
0.14
= V
= 5V
DRIVE
SINGLE-ENDED MODE
50kHz ON SELECTED CHANNEL
fIN = 50kHz
TRACK-AND-HOLD SECTION
The track-and-hold on the analog input of the AD7329 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The
AD7329 can handle frequencies up to 20 MHz.
T
= 25°C
A
AD8021 BETWEEN MUX
OUT
AND ADC PINS
IN
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT RATE (kSPS)
Figure 32. Input Current vs. Throughput Rate
with AD8021 Between MUXOUT and ADCIN
The ADCIN pins connect directly to the input stage of the track-
and-hold circuit. This is a high impedance input. Connecting
the MUXOUT pins directly to the ADCIN pins connects the
multiplexer output to the track-and-hold circuit. The input
voltage range on the ADCIN pins is determined by the range
register bits for the input channel selected. The user must
ensure that the input voltage to the ADCIN pins is within the
selected voltage range.
35
30
25
20
15
10
5
V
V
= 12V, V = –12V
SS
The track-and-hold enters its tracking mode on the 14th SCLK
DD
= V
= 5V
CC
DRIVE
SINGLE-ENDED MODE
50kHz ON SELECTED CHANNEL
fIN = 50kHz
CS
rising edge after the
falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 300 ns is
sufficient to acquire the signal to the 13-bit level.
T
= 25°C
A
WIRE LINK BETWEEN MUX
AND ADC PINS
IN
OUT
0
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT RATE (kSPS)
The acquisition time required is calculated using the following
formula:
Figure 33. Input Current vs. Throughput Rate
with a Wire Link Between MUXOUT and ADCIN
tACQ = 10 × ((RSOURCE + R)C)
where C is the sampling capacitance, and R is the resistance
seen by the track-and-hold amplifier looking at the input.
Rev. C | Page 19 of 38
AD7329
Data Sheet
TYPICAL CONNECTION DIAGRAM
ANALOG INPUT
Single-Ended Inputs
Figure 34 shows a typical connection diagram for the AD7329.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7329 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7329 can operate
with either an internal or external reference. In Figure 34, the
AD7329 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The AD7329 has a total of eight analog inputs when operating
in single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 36 shows the configuration of the AD7329 in single-
ended mode.
V+
5V
AGND
The VCC pin can be connected to either a 3 V or a 5 V supply
voltage. The VDD and VSS are the dual supplies for the high
voltage analog input structures. The voltage on these pins must
be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6 for more
information). The VDRIVE pin is connected to the supply voltage
of the microprocessor. The voltage applied to the VDRIVE input
controls the voltage of the serial interface.
V
+
IN
V
V
CC
DD
AD73291
V
SS
V–
ADDITIONAL PINS OMITTED FOR CLARITY.
1
FILTERING/BUFFERING
Figure 36. Single-Ended Mode Typical Connection Diagram
+15V
V
+2.7V TO +5.25V
CC
+
10µF
+
True Differential Mode
0.1µF
10µF
0.1µF
The AD7329 can have four true differential analog input pairs.
Differential signals have some benefits over single-ended
signals, including better noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 37 defines the configuration of the true
differential analog inputs of the AD7329.
1
+
+
ADC
IN
V
MUX
V
CC
DD
OUT
+3V SUPPLY
V
DRIVE
+
10µF
0.1µF
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
IN
IN
IN
IN
IN
IN
IN
IN
AD7329
CS
DOUT
SCLK
DIN
µC/µP
ANALOG INPUTS:
±10V, ±5V, ±2.5V,
0V TO +10V
V
+
IN
DGND
SERIAL
INTERFACE
REF /REF
IN
AD73291
OUT
680nF
0.1µF
1
–
–
ADC
MUX
V
OUT
IN AGND
SS
V
–
IN
–15V
10µF
1
+
MINIMUM V AND V SUPPLY VOLTAGES
DD SS
DEPEND ON THE HIGHEST ANALOG INPUT
1
ADDITIONAL PINS OMITTED FOR CLARITY.
RANGE SELECTED.
Figure 37. True Differential Inputs
Figure 34. Typical Connection Diagram, Single-Ended Mode
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in
each differential pair (VIN+ − VIN−). VIN+ and VIN− should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180° out of
phase. Assuming the 4 ꢀ VREF mode, the amplitude of the
differential signal is −20 V to +20 V p-p (2 ꢀ 4 ꢀ VREF),
regardless of the common mode.
FILTERING/BUFFERING
+15V
V
+2.7V TO +5.25V
CC
+
+
0.1µF
10µF
10µF
0.1µF
1
V
V
CC
DD
+3V SUPPLY
V
DRIVE
+
10µF
0.1µF
V
V
V
V
V
V
V
V
0
IN
IN
IN
IN
IN
IN
IN
IN
CS
1
AD7329
2
3
4
5
6
7
DOUT
SCLK
DIN
µC/µP
ANALOG INPUTS:
±10V, ±5V, ±2.5V,
0V TO +10V
The common mode is the average of the two signals
(VIN+ + VIN−)/2
DGND
AGND
SERIAL
INTERFACE
REF /REF
IN
OUT
and is therefore the voltage on which the two input signals are
centered.
680nF
0.1µF
1
V
SS
–15V
10µF
1
+
MINIMUM V AND V SUPPLY VOLTAGES
DD SS
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
Figure 35. Typical Connection Diagram, Differential Mode
Rev. C | Page 20 of 38
Data Sheet
AD7329
6
4
This voltage is set up externally, and its range varies with reference
voltage. As the reference voltage increases, the common-mode
range decreases. When the differential inputs are driven with an
amplifier, the actual common-mode range is determined by the
amplifier’s output swing. If the differential inputs are not driven
from an amplifier, the common-mode range is determined by
the supply voltage on the VDD supply pin and the VSS supply pin.
±5V RANGE
±5V RANGE
2
0
–2
–4
–6
–8
±2.5V
±10V
RANGE RANGE
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude −2 × (4 × VREF) to +2 ×
(4 × VREF), corresponding to Digital Codes −4096 to +4095.
5
±10V
±2.5V
RANGE
RANGE
V
V
= 3V
CC
= 2.5V
REF
±5V RANGE
4
±16.5V V /V
DD SS
±12V V /V
DD SS
±5V RANGE
3
2
±2.5V
RANGE
Figure 40. Common-Mode Range for VCC = 3 V and REFIN/REFOUT = 2.5 V
8
1
±5V RANGE
±2.5V
±10V
0
6
4
RANGE
RANGE
±10V
–1
–2
–3
–4
–5
–6
RANGE
±2.5V
RANGE
±10V
±10V
RANGE
2
RANGE
0
V
V
= 3V
CC
= 3V
REF
–2
–4
–6
–8
±16.5V V /V
DD SS
±12V V /V
DD SS
±5V RANGE
Figure 38. Common-Mode Range for VCC = 3 V and REFIN/REFOUT = 3 V
±2.5V
V
V
= 5V
8
CC
RANGE
= 2.5V
REF
±5V RANGE
±5V RANGE
±16.5V V /V
DD SS
±12V V /V
DD SS
6
4
Figure 41. Common-Mode Range for VCC = 5 V and REFIN/REFOUT = 2.5 V
±2.5V
RANGE
±2.5V
RANGE
±10V
RANGE
2
±10V
RANGE
0
–2
–4
V
V
= 5V
CC
= 3V
REF
±16.5V V /V
DD SS
±12V V /V
DD SS
Figure 39. Common-Mode Range for VCC = 5 V and REFIN/REFOUT = 3 V
Rev. C | Page 21 of 38
AD7329
Data Sheet
8
6
Pseudo Differential Inputs
±5V RANGE
±2.5V
RANGE
±5V RANGE
The AD7329 can have four pseudo differential pairs or seven
pseudo differential inputs referenced to a common VIN− pin.
The VIN+ inputs are coupled to the signal source and must have
an amplitude within the selected range for that channel, as
programmed in the range register. A dc input is applied to the
VIN− pin. The voltage applied to this input provides an offset for
the VIN+ input from ground or pseudo ground. Pseudo differential
inputs separate the analog input signal ground from the ADC
ground, allowing cancellation of dc common-mode voltages.
Figure 42 shows the configuration of the AD7329 in pseudo
differential mode.
±2.5V
RANGE
±10V
RANGE
4
2
0
–2
–4
–6
–8
±10V
RANGE
0V TO +10V
RANGE
0V TO +10V
RANGE
V
V
= 5V
CC
= 2.5V
REF
±16.5V V /V
DD SS
±12V V /V
DD SS
See Figure 28 and Figure 29 for the output transfer
characteristic when a conversion takes place.
Figure 43. Pseudo Differential Input Range with VCC = 5 V
4
2
V+
5V
±5V RANGE
±5V RANGE
±2.5V
RANGE
V
+
IN
V
V
CC
DD
0
AD73291
V
V
–
SS
IN
–2
–4
–6
–8
±10V
RANGE
±2.5V
RANGE
±10V
RANGE
V–
0V TO +10V
RANGE
0V TO +10V
RANGE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
V
V
= 3V
CC
= 2.5V
Figure 42. Pseudo Differential Inputs
REF
±16.5V V /V
DD SS
±12V V /V
DD SS
Figure 43 and Figure 44 show the typical voltage range on the
VIN− pin for various analog input ranges when configured in
the pseudo differential mode.
Figure 44. Pseudo Differential Input Range with VCC = 3 V
For example, when the AD7329 is configured to operate in
pseudo differential mode and the 5 V range is selected with
16.5 V VDD, −16.5 V VSS, and 5 V VCC, the voltage on the VIN−
pin can vary from −6.5 V to +6.5 V.
Rev. C | Page 22 of 38
Data Sheet
AD7329
DRIVER AMPLIFIER CHOICE
Table 8. Typical AC Performance Using Different Op Amps
in Single-Ended Mode, 10 V Input Range
In applications where the harmonic distortion and signal-to-
noise ratio are critical specifications, the analog input of the
AD7329 should be driven from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC and can necessitate the use of an input buffer amplifier.
Parameter
No Buffer
AD845
AD8021
AD8610
SNR (dB)
74.24
74.03
73.78
73.88
SNRD (dB)
THD (dB)
72.42
−77.05
74.88
−75.95
72.11
−77.04
71.98
−76.47
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 21 and Figure 22
show graphs of the THD vs. the analog input frequency for
various source impedances. Depending on the input range and
analog input configuration selected, the AD7329 can handle
source impedances of up to 4 kΩ before the THD starts to
degrade.
Table 9. Typical AC Performance Using Different Op Amps
in Differential Mode, 10 V Input Range
Parameter
No Buffer
AD845
AD8021
AD8610
SNR (dB)
77.16
76.81
76.95
76.76
SNRD (dB)
THD (dB)
76.50
−84.91
76.02
−83.74
76.78
−90.55
75.89
−83.24
Differential operation requires that VIN+ and VIN− be simulta-
neously driven with two signals of equal amplitude that are 180°
out of phase. The common mode must be set up externally to the
AD7329. The common-mode range is determined by the REFIN/
REFOUT voltage, the VCC supply voltage, and the particular amplifier
used to drive the analog inputs. Differential mode with either an ac
input or a dc input provides the best THD performance over a
wide frequency range. Because not all applications have a signal
preconditioned for differential operation, there is often a need
to perform a single-ended-to-differential conversion.
Due to the programmable nature of the analog inputs on the
AD7329, the choice of op amp used to drive the inputs is a
function of the particular application and depends on the input
configuration and the analog input voltage ranges selected.
The driver amplifier must be able to settle for a full-scale step to
a 13-bit level, within 0.0122%, in less than the specified acquisition
time of the AD7329. An op amp such as the AD8021 meets this
requirement when operating in single-ended mode. The AD8021
needs an external compensating NPO type of capacitor. The
AD8022 can also be used in high frequency applications where
a dual version is required. For lower frequency applications, op
amps such as the AD797, AD845, and AD8610 can be used with
the AD7329 in single-ended mode configuration.
This single-ended-to-differential conversion can be performed
using an op amp pair. Typical connection diagrams for an op
amp pair are shown in Figure 45 and Figure 46. In Figure 45,
the common-mode signal is applied to the noninverting input
of the second amplifier.
Rev. C | Page 23 of 38
AD7329
Data Sheet
1.5kΩ
2kΩ
V
DD
V
IN
V+
100nF
1.5kΩ
1.5kΩ
1.5kΩ
1.5kΩ
7
3
2
MUX
+
OUT
AD8021
6
ADC
+
IN
5
4
V–
10pF
100nF
10kΩ
V
SS
Figure 45. Single-Ended-to-Differential Configuration with the AD845
for Bipolar Operation
Figure 47. AD8021 Configuration Used Between MUXOUT and ADCIN Pins
442Ω
442Ω
AD8021
V
IN
V+
442Ω
442Ω
442Ω
442Ω
V–
AD8021
100Ω
Figure 46. Single-Ended-to-Differential Configuration with the AD8021
Rev. C | Page 24 of 38
Data Sheet
REGISTERS
AD7329
The AD7329 has four programmable registers: the control register, sequence register, Range Register 1, and Range Register 2.
These registers are write-only registers.
ADDRESSING REGISTERS
A serial transfer on the AD7329 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to
determine which register is addressed. The three MSBs consist of the write bit, the Register Select 1 bit, and the Register Select 2 bit. The
register select bits are used to determine which of the four on-board registers is selected. The write bit determines if the data on the DIN
line following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the
register select bits. If the write bit is 0, the data on the DIN line does not load into any register.
Combinations of the write bit, the Register Select 1 bit, and the Register Select 2 bit other than those specified in Table 10 access registers
that are for Analog Devices internal use only. Do not access these registers, as doing so may lead to unspecified operation of the device.
Table 10. Decoding Register Select Bits and Write Bit
Write Register Select 1
Register Select 2
Description
0
1
0
0
0
0
Data on the DIN line during this serial transfer is ignored.
This combination selects the control register. The subsequent 12 bits are loaded into
the control register.
1
1
1
0
1
1
1
0
1
This combination selects Range Register 1. The subsequent 8 bits are loaded into
Range Register 1.
This combination selects Range Register 2. The subsequent 8 bits are loaded into
Range Register 2.
This combination selects the sequence register. The subsequent 8 bits are loaded into
the sequence register.
Rev. C | Page 25 of 38
AD7329
Data Sheet
CONTROL REGISTER
The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The
control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7329 configuration for the next
conversion. If the sequence register is being used, data should be loaded into the control register after the range registers and the sequence
register have been initialized. The bit functions of the control register are described in Table 11 (the power-up status of all bits is 0).
MSB
15
LSB
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Write Register Register ADD2 ADD1 ADD0 Mode 1 Mode 0 PM1 PM0 Coding REF SEQ1 SEQ2 Weak/
0
Select 1 Select 2
Three-State
Table 11. Control Register Details
Bit
Mnemonic
Description
12, 11, 10 ADD2, ADD1,
ADD0
These three channel address bits are used to select the analog input channel for the next conversion if the
sequencer is not being used. If the sequencer is being used, the three channel address bits are used to
select the final channel in a consecutive sequence.
9, 8
Mode 1, Mode 0
These two mode bits are used to select the configuration of the eight analog input pins, VIN0 to VIN7. These
pins are used in conjunction with the channel address bits. On the AD7329, the analog inputs can be
configured as eight single-ended inputs, four fully differential input pairs, four pseudo differential inputs,
or seven pseudo differential inputs (see Table 12).
7, 6
5
PM1, PM0
Coding
The power management bits are used to select different power mode options on the AD7329 (see Table 13).
This bit is used to select the type of output coding that the AD7329 uses for the next conversion result.
If coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary.
When operating in sequence mode, the output coding for each channel is the value written to the coding
bit during the last write to the control register.
4
REF
The reference bit is used to enable or disable the internal reference. If REF = 0, the external reference is
enabled and used for the next conversion and the internal reference is disabled. If REF = 1, the internal ref-
erence is used for the next conversion. When operating in sequence mode, the reference used for each
channel is the value written to the REF bit during the last write to the control register.
3, 2
1
SEQ1/SEQ2
The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 14).
Weak/Three-State This bit selects the state of the DOUT line at the end of the current serial transfer. If the bit is set to 1, the
DOUT line is weakly driven to Channel Address Bit ADD2 of the following conversion. If this bit is set to 0,
DOUT returns to three-state at the end of the serial transfer (see the Serial Interface section).
The eight analog input channels can be configured as seven pseudo differential analog inputs, four pseudo differential inputs, four true
differential input pairs, or eight single-ended analog inputs.
Table 12. Analog Input Configuration Selection
7 Pseudo Differential I/Ps 4 Fully Differential I/Ps 4 Pseudo Differential I/Ps
8 Single-Ended I/Ps
Channel Address Bits
ADD2 ADD1 ADD0 VIN+
(Mode 1 = 1, Mode 0 = 1) (Mode 1 = 1, Mode 0 = 0) (Mode 1 = 0, Mode 0 =1) (Mode 1 = 0, Mode 0 = 0)
VIN−
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
VIN+
VIN0
VIN0
VIN2
VIN2
VIN4
VIN4
VIN6
VIN6
VIN−
VIN1
VIN1
VIN3
VIN3
VIN5
VIN5
VIN7
VIN7
VIN+
VIN0
VIN0
VIN2
VIN2
VIN4
VIN4
VIN6
VIN6
VIN−
VIN1
VIN1
VIN3
VIN3
VIN5
VIN5
VIN7
VIN7
VIN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN−
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
Temperature indicator
Rev. C | Page 26 of 38
Data Sheet
AD7329
Table 13. Power Mode Selection
PM1
PM0
Description
1
1
Full shutdown mode. In this mode, all internal circuitry on the AD7329 is powered down. Information in the control register
is retained when the AD7329 is in full shutdown mode.
1
0
0
0
1
0
Autoshutdown mode. The AD7329 enters autoshutdown on the 15th SCLK rising edge when the control register is updated.
All internal circuitry is powered down in autoshutdown.
Autostandby mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7329
enters autostandby mode on the 15th SCLK rising edge after the control register is updated.
Normal mode. All internal circuitry is powered up at all times.
Table 14. Sequencer Selection
SEQ1
SEQ2
Description
0
0
The channel sequencer is not used. The analog channel, selected by programming the ADD2 to ADD0 bits in the control
register, selects the next channel for conversion.
0
1
1
1
0
1
Uses the sequence of channels that were previously programmed in the sequence register for conversion. The AD7329
starts converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted,
the AD7329 keeps converting the sequence. The range for each channel defaults to the range previously written into the
corresponding range register.
This configuration is used in conjunction with the channel address bits in the control register. This allows continuous
conversions on a consecutive sequence of channels, from Channel 0 through a final channel selected by the channel
address bits in the control register. The range for each channel defaults to the range previously written into the
corresponding range register.
The channel sequencer is not used. The analog channel, selected by programming the ADD2 bit to ADD0 bit in the control
register, selects the next channel for conversion.
Rev. C | Page 27 of 38
AD7329
Data Sheet
SEQUENCE REGISTER
The sequence register on the AD7329 is an 8-bit, write-only register. Each of the eight analog input channels has one corresponding bit in
the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.
MSB
16
LSB
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Write
Register Select 1
Register Select 2
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
0
0
0
0
0
RANGE REGISTERS
The range registers are used to select one analog input range per analog input channel. Range Register 1 is used to set the ranges for Channel 0 to
Channel 3. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 0 to Channel 3.
There are four analog input ranges, 10 V, 5 V, 2.5 V, and 0 V to +10 V. A write to Range Register 1 is selected by setting the write bit to 1
and the range select bits to 0 and 1, respectively. After the initial write to Range Register 1 occurs, each time an analog input is selected,
the AD7329 automatically configures the analog input to the appropriate range, as indicated by Range Register 1. The 10 V input range
is selected by default on each analog input channel (see Table 15).
MSB
16
LSB
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Write Register Select 1
Register Select 2
VIN0A VIN0B VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B
0
0
0
0
0
Range Register 2 is used to set the ranges for Channel 4 to Channel 7. It is an 8-bit, write-only register with two dedicated range bits for
each of the analog input channels from Channel 4 to Channel 7. There are four analog input ranges, 10 V, 5 V, 2.5 V, and 0 V to +10 V.
After the initial write to Range Register 2 occurs, each time an analog input is selected, the AD7329 automatically configures the analog
input to the appropriate range, as indicated by Range Register 2. The 10 V input range is selected by default on each analog input
channel (see Table 15).
MSB
16
LSB
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Write Register Select 1
Register Select 2
VIN4A VIN4B VIN5A VIN5B VIN6A VIN6B VIN7A VIN7B
0
0
0
0
0
Table 15. Range Selection
VINxA
VINxB
Description
0
0
1
1
0
1
0
1
This combination selects the 10 V input range on VINx.
This combination selects the 5 V input range on VINx.
This combination selects the 2.5 V input range on VINx.
This combination selects the 0 V to +10 V input range on VINx.
Rev. C | Page 28 of 38
Data Sheet
AD7329
SEQUENCER OPERATION
POWER ON.
CS
DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE
FOR EACH ANALOG INPUT CHANNEL.
DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE
FOR EACH ANALOG INPUT CHANNEL.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER 1.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
ANALOG INPUT CHANNELS TO BE INCLUDED IN
THE SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER 1.
CS
DIN: WRITE TO CONTROL REGISTER TO START THE
SEQUENCE, SEQ1 = 0, SEQ2 = 1.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER 1.
CS
DIN: TIE DIN LOW/WRITE BIT = 0 TO CONTINUE TO CONVERT
THROUGH THE SEQUENCE OF CHANNELS.
CS
DOUT: CONVERSION RESULT FROM FIRST CHANNEL IN
THE SEQUENCE.
DIN TIED LOW/WRITE BIT = 0.
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, SEQ1 = 0, SEQ2 = 0.
CONTINUOUSLY CONVERT
STOP
ON THE SELECTED SEQUENCE
A SEQUENCE.
OF CHANNELS.
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
SELECT A NEW SEQUENCE.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
NEW SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL X IN
THE FIRST SEQUENCE.
Figure 48. Programmable Sequence Flowchart
The AD7329 can be configured to automatically cycle through
a number of selected channels using the on-chip sequence
register with the SEQ1 bit and the SEQ2 bit in the control
register. Figure 48 shows how to program the AD7329 register
to operate in sequence mode.
These two initial serial transfers are required only if input ranges
other than the default ranges are required. After the analog input
ranges are configured, a write to the sequence register is necessary
to select the channels to be included in the sequence. After the
channels for the sequence have been selected, the sequence can
be initiated by writing to the control register and setting SEQ1
to 0 and SEQ2 to 1. The AD7329 continues to convert the selected
sequence without interruption if the sequence register remains
unchanged and SEQ1 = 0 and SEQ2 = 1 in the control register.
After power-up, the four on-chip registers contain default
values. Each analog input has a default input range of 10 V. If
different analog input ranges are required, a write to the range
registers is necessary. This is shown in the first two serial
transfers of Figure 48.
Rev. C | Page 29 of 38
AD7329
Data Sheet
If a change to one of the range registers is required during a
sequence, it is necessary to first stop the sequence by writing to
the control register and setting SEQ1 to 0 and SEQ2 to 0. Next,
write to the range register to change the required range. The
previously selected sequence should then be initiated again by
writing to the control register and setting SEQ1 to 0 and SEQ2
to 1. The ADC converts the first channel in the sequence.
SEQ2 to 0 in the control register, and then select the final channel
in the sequence by programming Bit ADD2 to Bit ADD0 in the
control register.
After the control register is configured to operate the AD7329
in this mode, the DIN line can be held low or the write bit can
be set to 0. To return to traditional multichannel operation, a
write to the control register to set SEQ1 to 0 and SEQ2 to 0 is
necessary.
The AD7329 can be configured to convert a sequence of
consecutive channels (see Figure 49). This sequence begins by
converting on Channel 0 and ends with a final channel as
selected by Bit ADD2 to Bit ADD0 in the control register. In
this configuration, there is no need for a write to the sequence
register. To operate the AD7329 in this mode, set SEQ1 to 1 and
When SEQ1 and SEQ2 are both set to 0 or to 1, the AD7329 is
configured to operate in traditional multichannel mode, where
a write to Channel Address Bit ADD2 to Bit ADD0 in the control
register selects the next channel for conversion.
POWER ON.
CS
DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE
FOR ANALOG INPUT CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE
FOR ANALOG INPUT CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER 1,
SINGLE-ENDED MODE.
CS
DIN: WRITE TO CONTROL REGISTER TO SELECT THE FINAL
CHANNEL IN THE CONSECUTIVE SEQUENCE, SET SEQ1 = 1
AND SEQ2 = 0. SELECT OUTPUT CODING FOR SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER 1,
SINGLE-ENDED MODE.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE
TO CONVERT THROUGH THE SEQUENCE OF
CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER 1.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE
THROUGH SEQUENCE OF CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 1,
RANGE SELECTED IN RANGE REGISTER 1.
DIN TIED LOW/WRITE BIT = 0.
CONTINUOUSLY CONVERT
ON CONSECUTIVE SEQUENCE
OF CHANNELS.
STOP
A SEQUENCE.
CS
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, SEQ1 = 0, SEQ2 = 0.
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
Figure 49. Flowchart for Consecutive Sequence of Channels
Rev. C | Page 30 of 38
Data Sheet
AD7329
REFERENCE
TEMPERATURE INDICATOR
The AD7329 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The internal reference
is selected by setting the REF bit in the control register to 1. On
power-up, the REF bit is 0, which selects the external reference for
the AD7329 conversion. Suitable reference sources for the AD7329
include AD780, AD1582, ADR431, REF193, and ADR391.
The AD7329 has an on-chip temperature indicator. The tem-
perature indicator can be used to provide local temperature
measurements on the AD7329. To access the temperature indicator,
the ADC should be configured in pseudo differential mode,
Mode 1 = Mode 0 = 1, which sets Channel Bits ADD2, ADD1,
and ADD0 to 1. VIN7 must be tied to AGND or to a small dc
voltage within the specified pseudo differential input range for
the selected analog input range. When a conversion is initiated in
this configuration, the output code represents the temperature
(see Figure 50 and Figure 51). When using the temperature
indicator on the AD7329, the part should be operated at low
throughput rates, such as approximately 30 kSPS for the 2.5 V
range. The throughput rate is reduced for the temperature indicator
mode because the AD7329 requires more acquisition time for
this mode.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7329 in
internal reference mode, the 2.5 V internal reference is available
at the REFIN/REFOUT pin, which should be decoupled to AGND
using a 680 nF capacitor. It is recommended that the internal
reference be buffered before applying it elsewhere in the system.
The internal reference is capable of sourcing up to 90 μA.
On power-up, if the internal reference operation is required for
the ADC conversion, a write to the control register is necessary
to set the REF bit to 1. During the control register write, the
conversion result from the first initial conversion is invalid. The
reference buffer requires 500 µs to power up and charge the
680 nF decoupling capacitor during the power-up time.
5450
V
V
= V = 5V
DRIVE
CC
= 12V, V = –12V
DD
SS
5400
5350
5300
5250
5200
5150
5100
5050
±2.5V RANGE
INTERNAL REFERENCE
30kSPS
The AD7329 is specified for a 2.5 V to 3 V reference range.
When a 3 V reference is selected, the ranges are 12 V, 6 V,
3 V, and 0 V to +12 V. For these ranges, the VDD and VSS supply
must be equal to or greater than the maximum analog input
range selected.
VDRIVE
The AD7329 has a VDRIVE feature to control the voltage at which
the serial interface operates. VDRIVE allows the ADC to easily
interface to both 3 V and 5 V processors. For example, if the
AD7329 is operated with a VCC of 5 V, the V DRIVE pin can be
powered from a 3 V supply. This allows the AD7329 to accept
large bipolar input signals with low voltage digital processing.
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 50. ADC Output Code vs. Temperature for 2.5 V Range
4420
V
V
= V
= 5V
CC
DRIVE
/V = ±12V
DD SS
4410
4400
4390
4380
4370
4360
4350
4340
50kSPS
±10V RANGE, INT REF
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 51. ADC Output Code vs. Temperature for 10 V Range
Rev. C | Page 31 of 38
AD7329
Data Sheet
MODES OF OPERATION
The AD7329 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7329 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 13. The default mode is normal mode, where all internal
circuitry is fully powered up.
The AD7329 remains fully powered up at the end of the
conversion if both PM1 and PM0 contain 0 in the control
register.
To complete the conversion and access the conversion result,
16 serial clock cycles are required. At the end of the conversion,
CS
can idle either high or low until the next conversion.
After the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
NORMAL MODE
(PM1 = PM0 = 0)
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate
performance with the AD7329 being fully powered up at all
times. Figure 52 shows the general operation of the AD7329
in normal mode.
In this mode, all internal circuitry on the AD7329 is powered
down. The part retains information in the registers during full
shutdown. The AD7329 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the
control register are changed.
CS
The conversion is initiated on the falling edge of , and the
track-and-hold section enters hold mode, as described in the
Serial Interface section. The data on the DIN line during the
16 SCLK transfer is loaded into one of the on-chip registers if
the write bit is set. The register is selected by programming the
register select bits (see Table 10).
A write to the control register with PM1 = PM0 = 1 places the
part into full shutdown mode. The AD7329 enters full shutdown
mode on the 15th SCLK rising edge when the control register is
updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up on
the 15th SCLK rising edge when the control register is updated.
Figure 53 shows how the AD7329 is configured to exit full
shutdown mode. To ensure that the AD7329 is fully powered
CS
1
16
SCLK
DOUT
DIN
3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RESULT
DATA INTO CONTROL/SEQUENCE/RANGE1/RANGE2
REGISTER
CS
up, tPOWER-UP should elapse before the next
falling edge.
Figure 52. Normal Mode
THE PART IS FULLY POWERED UP
ONCE tPOWER-UP HAS ELAPSED
THE PART BEGINS TO POWER UP ON THE
15TH SCLK RISING EDGE AS PM1 = PM0 = 0
PART IS IN FULL
SHUTDOWN
tPOWER-UP
CS
1
16
1
16
SCLK
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL/SHADOW REGISTER
SDATA
DIN
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS.
PM1 = PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
Figure 53. Exiting Full Shutdown Mode
Rev. C | Page 32 of 38
Data Sheet
AD7329
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
When the autoshutdown mode is selected, the AD7329
automatically enters shutdown on the 15th SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down.
The AD7329 retains information in the registers during
autoshutdown. The track-and-hold section is in hold mode
In autostandby mode, portions of the AD7329 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to
autoshutdown but allows the AD7329 to power up much faster,
which allows faster throughput rates.
CS
during autoshutdown. On the rising
edge, the track-and-
hold section, which was in hold during shutdown, returns to
track as the AD7329 begins to power up. The time to power up
from autoshutdown is 500 µs.
As is the case with autoshutdown mode, the AD7329 enters
standby on the 15th SCLK rising edge when the control register
is updated (see Figure 54). The part retains information in the
registers during standby. The AD7329 remains in standby until
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15th SCLK rising edge.
Figure 54 shows the part entering autoshutdown mode. The
CS
it receives a
rising edge. The ADC begins to power up on the
CS
CS
rising edge, the track-and-hold,
rising edge. On the
CS
AD7329 automatically begins to power up on the
edge. The tPOWER-UP is required before a valid conversion, initiated
CS
rising
which was in hold mode while the part was in standby, returns
to track.
by bringing the
signal low, can take place. After this valid
conversion is complete, the AD7329 powers down again on the
The power-up time from standby is 750 ns. The user should
CS
ensure that 750 ns have elapsed before bringing
low to
th
CS
15 SCLK rising edge. The
signal must remain low again to
attempt a valid conversion. After this valid conversion is
complete, the AD7329 again returns to standby on the 15th
keep the part in autoshutdown mode.
CS
SCLK rising edge. The
part in standby mode.
signal must remain low to keep the
Figure 54 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby
mode. In Figure 54, the power management bits are configured
for autoshutdown. For autostandby mode, the power
management bits, PM1 and PM0, should be set to 0 and 1,
respectively.
PART BEGINS TO POWER
UP ON CS RISING EDGE
THE PART IS FULLY POWERED UP
ONCE tPOWER-UP HAS ELAPSED
PART ENTERS SHUTDOWN MODE
tPOWER-UP
TH
ON THE 15 RISING SCLK EDGE
IF PM1 = 1, PM0 = 0
CS
1
15 16
1
15 16
SCLK
SDATA
DIN
VALID DATA
VALID DATA
DATA INTO CONTROL REGISTER
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS
PM1 = 1, PM0 = 0
Figure 54. Entering Autoshutdown/Autostandby Mode
Rev. C | Page 33 of 38
AD7329
Data Sheet
20
18
16
14
12
10
8
POWER VS. THROUGHPUT RATE
The power consumption of the AD7329 varies with throughput
rate. The static power consumed by the AD7329 is very low, and
significant power savings can be achieved as the throughput rate is
reduced. Figure 55 and Figure 56 show the power vs. throughput
rate for the AD7329 at a VCC of 3 V and 5 V, respectively. Both
plots clearly show that the average power consumed by the AD7329
is greatly reduced as the sample frequency is reduced. This is true
whether a fixed SCLK value is used or if the SCLK value is scaled
with the sampling frequency. Figure 55 and Figure 56 show the
power consumption when operating the device in normal mode
for a fixed 20 MHz SCLK and a variable SCLK that scales with
the sampling frequency.
VARIABLE SCLK
20MHz SCLK
6
4
V
V
T
= 5V
CC
DD
= 12V, V = –12V
= 25°C
SS
2
A
INTERNAL REFERENCE
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT RATE (kHz)
0
0
12
Figure 56. Power vs. Throughput Rate with 5 V VCC
10
20MHz SCLK
8
VARIABLE SCLK
6
4
V
V
= 3V
CC
DD
2
0
= 12V, V = –12V
= 25°C
SS
T
A
INTERNAL REFERENCE
100 200 300 400 500 600 700 800 900 1000 1100
THROUGHPUT RATE (kSPS)
0
Figure 55. Power vs. Throughput Rate with 3 V VCC
Rev. C | Page 34 of 38
Data Sheet
AD7329
SERIAL INTERFACE
Figure 57 shows the timing diagram for the serial interface of
the AD7329. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7329 during a conversion.
Conversion data is clocked out of the AD7329 on each SCLK
falling edge. Data on the DOUT line consists of three channel
identifier bits, a sign bit, and a 12-bit conversion result. The
channel identifier bits are used to indicate which channel
corresponds to the conversion result.
CS
The
signal initiates the data transfer and the conversion
CS
Three-State
If the Weak/
bit is set in the control register, rather
process. The falling edge of
puts the track-and-hold section
than returning to true three-state upon the 16th SCLK falling
edge, the DOUT line is pulled weakly to the logic level
corresponding to ADD3 of the next serial transfer. This is done
to ensure that the MSB of the next serial transfer is set up in
into hold mode and takes the bus out of three-state. The analog
input signal is then sampled. Once the conversion is initiated,
16 SCLK cycles are required for the conversion to complete.
The track-and-hold section goes back into track mode on the
14th SCLK rising edge. On the 16th SCLK falling edge, the
DOUT line returns to three-state. If the rising edge of
before 16 SCLK cycles have elapsed, the conversion is
CS
time for the first SCLK falling edge after the
falling edge. If
Three-State
the Weak/
bit is set to 0 and the DOUT line returns
CS
occurs
to true three-state between conversions, then depending on the
particular processor interfacing to the AD7329, the ADD3 bit
may be valid in time for the processor to clock it in successfully.
terminated and the DOUT line returns to three-state. Depending
CS
on where the
may update.
signal is brought high, the addressed register
Three-State
If the Weak/
bit is set to 1, then although the DOUT
line has been driven to ADD3 since the previous conversion, it
is nevertheless so weakly driven that another device could take
control of the bus. This will not lead to a bus contention issue
because, for example, a 10 kΩ pull-up or pull-down resister is
sufficient to overdrive the logic level of ADD3. When the
Data is clocked into the AD7329 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is addressed. The control register is a 12-bit register. If the
control register is addressed by the three MSBs, the data on the
DIN line is loaded into the control on the 15th SCLK rising edge.
If the sequence register or either of the range registers is
addressed, the data on the DIN line is loaded into the addressed
register on the 11th SCLK falling edge.
Three-State
Weak/
bit is set to 1, the ADD3 is typically valid 9 ns
CS
after the
falling edge, compared with 14 ns when the DOUT
line returns to three-state at the end of the conversion.
t1
CS
tCONVERT
t2
t6
1
2
3
4
5
13
14
t5
15
16
SCLK
DOUT
3 IDENTIFICATION BITS
t3
t7
t8
t4
tQUIET
ADD1
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
ADD2
THREE-STATE
t10
t9
REG
SEL1
REG
SEL2
WRITE
MSB
LSB
0
DIN
Figure 57. Serial Interface Timing Diagram (Control Register Write)
Rev. C | Page 35 of 38
AD7329
Data Sheet
MICROPROCESSOR INTERFACING
The serial interface on the AD7329 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7329 with some of the most
common microcontroller and DSP serial interface protocols.
The frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given (AX0 =
TX0), the state of the serial clock is checked. The DSP waits
until the SCLK has gone high, low, and high again before
starting the transmission. If the timer and SCLK are chosen so
that the instruction to transmit occurs on or near the rising
edge of SCLK, data can be transmitted immediately or at the
next clock edge.
AD7329 TO ADSP-21xx
The ADSP-21xx family of DSPs interfaces directly to the AD7329
without requiring glue logic. The VDRIVE pin of the AD7329 takes
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial
interface. The SPORT0 on the ADSP-21xx should be configured
as shown in Table 16.
For example, if the ADSP-21xx has a master clock frequency of
16 MHz and the SCLKDIV register is loaded with the value 3,
an SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every one SCLK period. If the timer registers are
loaded with the value 803, 100.5 SCLKs occur between
interrupts and, subsequently, between transmit instructions.
This situation leads to nonequidistant sampling because the
transmit instruction occurs on an SCLK edge. If the number of
SCLKs between interrupts is an integer of N, equidistant
sampling is implemented by the DSP.
Table 16. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
Alternative framing
Active low frame signal
Right justify data
16-bit data-word
Internal serial clock
Frame every word
AD7329 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7329 without requiring glue logic, as shown in Figure 59.
The SPORT0 Receive Configuration 1 register should be set up
as outlined in Table 17.
Internal receive frame sync
Internal transmit frame sync
The connection diagram is shown in Figure 58. The ADSP-21xx
has TFS0 and RFS0 tied together. TFS0 is set as an output, and
RFS0 is set as an input. The DSP operates in alternative framing
mode, and the SPORT0 control register is set up as described in
Table 16. The frame synchronization signal generated on TFS is
1
AD73291
ADSP-BF53x
SCLK
RSCLK0
RFS0
DT0
CS
CS
tied to
and, as with all signal processing applications, requires
DIN
equidistant sampling. However, as in this example, the timer
interrupt is used to control the sampling rate of the ADC, and
under certain conditions equidistant sampling cannot be achieved.
DR0
DOUT
V
DRIVE
1
AD73291
ADSP-21xx
V
DD
SCLK
SCLK0
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 59. Interfacing the AD7329 to the ADSP-BF53x
TFS0
RFS0
CS
Table 17. SPORT0 Receive Configuration 1 Register
DIN
DT0
DR0
Setting
Description
DOUT
RCKFE = 1
LRFS = 1
RFSR = 1
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
V
DRIVE
IRFS = 1
Internal RFS used
V
DD
1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
Receive MSB first
Zero fill
Internal receive clock
Receive enable
16-bit data-word
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 58. Interfacing the AD7329 to the ADSP-21xx
The timer registers are loaded with a value that provides an
interrupt at the required sampling interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, hence, the
reading of data.
Transmit and receive frame sync
Rev. C | Page 36 of 38
Data Sheet
AD7329
APPLICATIONS INFORMATION
These low ESR, low ESI capacitors provide a low impedance
path to ground at high frequencies to handle transient currents
due to internal logic switching.
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7329 should be
designed so that the analog and digital sections are confined to
certain areas of the board. This design facilitates the use of ground
planes that can be easily separated.
POWER SUPPLY CONFIGURATION
It is recommended that Schottky diodes be placed in series with
the AD7329 VDD and VSS supply signals. Figure 60 shows this
Schottky diode configuration. BAT43 Schottky diodes are used.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins on the AD7329
should be connected to the AGND plane. Digital and analog
ground pins should be joined in only one place. If the AD7329
is in a system where multiple devices require an AGND and
DGND connection, the connection should still be made at only
one point. A star point should be established as close as possible
to the ground pins on the AD7329.
V+
3V/5V
V
V
CC
DD
CS
SCLK
DOUT
DIN
AD73291
V
V
0
7
IN
IN
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
V
SS
V–
Avoid running digital lines under the AD7329 device because
this couples noise onto the die. However, the analog ground
plane should be allowed to run under the AD7329 to avoid
noise coupling. The power supply lines to the AD7329 device
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 60. Schottky Diode Connection
In an application where nonsymmetrical VDD and VSS supplies
are used, adhere to the guidelines provided in Table 18, which
outlines the VSS supply range that can be used for various VDD
voltages when nonsymmetrical supplies are required. When
operating the AD7329 with low VDD and VSS voltages, it is
recommended that these supplies be symmetrical.
To avoid radiating noise to other sections of the board, com-
ponents, such as clocks, with fast switching signals should be
shielded with digital ground and never run near the analog inputs.
Avoid crossover of digital and analog signals. To reduce the effects
of feedthrough within the board, traces should be run at right
angles to each other. A microstrip technique is the best method,
but its use may not be possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes, and signals are placed on the other side.
Table 18. Nonsymmetrical VDD and VSS Requirements
VDD
Typical VSS Range
−5 V to −5.5 V
−5 V to −8.5 V
−5 V to −11.5 V
−5 V to −15 V
5 V
6 V
7 V
8 V
9 V
−5 V to −16.5 V
−5 V to −16.5 V
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 µF capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is typical
of common ceramic and surface-mount types of capacitors.
10 V to 16.5 V
For the 0 V to 4 × VREF range, VSS can be tied to AGND as per
the minimum supply recommendations outlined in Table 6.
Rev. C | Page 37 of 38
AD7329
Data Sheet
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 61. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
RU-24
RU-24
AD7329BRUZ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
AD7329BRUZ-REEL
AD7329BRUZ-REEL7
EVAL-AD7329SDZ
EVAL-SDP-CBZ1
RU-24
Controller Board
1 Z = RoHS Compliant Part.
©2006–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05402-0-12/14(C)
Rev. C | Page 38 of 38
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